project_euler.gprj

<?xml version="1" encoding="UTF-8"?>
<!DOCTYPE gowin-fpga-project>
<Project>
    <Template>FPGA</Template>
    <Version>5</Version>
    <Device name="GW1NSR-4C" pn="GW1NSR-LV4CQN48PC6/I5">gw1nsr4c-000</Device>
    <FileList>
        <File path="src/is_prime.v" type="file.verilog" enable="1"/>
        <File path="src/p0001.v" type="file.verilog" enable="1"/>
        <File path="src/p0002.v" type="file.verilog" enable="1"/>
        <File path="src/p0003.v" type="file.verilog" enable="1"/>
        <File path="src/p0004.v" type="file.verilog" enable="1"/>
        <File path="src/p0005.v" type="file.verilog" enable="1"/>
    </FileList>
</Project>