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5E problem 11 solved · karaketir16/project-euler-verilog@72db6a0 · GitHub
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problem 11 solved
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‎README.md

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@@ -24,7 +24,8 @@ As a computer engineer learning digital design, I wanted a fun and practical way
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| Problem 7 | Solved | Verified in simulation |
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| Problem 8 | Solved | Verified in simulation |
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| Problem 9 | Solved | Verified in simulation |
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| Problem 10 | Solved | Verified in simulation |
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| Problem 10 | Solved | Verified in simulation |
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| Problem 11 | Solved | Verified in simulation |
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---
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‎dsim/p0011.mem

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‎dsim/project_euler.dpf

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@@ -27,6 +27,10 @@ simulations:
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options: '-top work.p0009_tb +acc+b -waves waves_p0009.mxd'
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- name: p0010
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options: '-top work.p0010_tb +acc+b -waves waves_p0010.mxd'
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- name: p0011
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options: '-top work.p0011_tb +acc+b -waves waves_p0011.mxd'
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- name: p0011_v2
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options: '-top work.p0011_v2_tb +acc+b -waves waves_p0011_v2.mxd'
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source_files:
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- language: verilog
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path: ..\filelist.txt

‎dsim/waves_p0011.mxd

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‎dsim/waves_p0011_v2.mxd

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‎filelist.txt

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@@ -11,6 +11,8 @@ src/p0007.v
1111
src/p0008.v
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src/p0009.v
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src/p0010.v
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src/p0011.v
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src/p0011_v2.v
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1517
tb/p0001_tb.v
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tb/p0002_tb.v
@@ -21,4 +23,6 @@ tb/p0006_tb.v
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tb/p0007_tb.v
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tb/p0008_tb.v
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tb/p0009_tb.v
24-
tb/p0010_tb.v
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tb/p0010_tb.v
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tb/p0011_tb.v
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tb/p0011_v2_tb.v

‎src/p0011.v

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module p0011(
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input clk,
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output reg [31:0] result = 0,
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output reg done = 0,
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output reg error = 0
6+
);
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localparam LEN = 20;
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reg [7:0] rom [0:LEN*LEN - 1];
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initial $readmemh("p0011.mem", rom);
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14+
function [7:0] rom_index;
15+
input integer i;
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input integer j;
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begin
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if (i < 0 || i >= LEN || j < 0 || j >= LEN) begin
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rom_index = 0;
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end
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else begin
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rom_index = rom[i*LEN + j];
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end
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end
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endfunction
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integer i = 0;
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integer j = 0;
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localparam state_down = 3'd0;
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localparam state_right = 3'd1;
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localparam state_diag = 3'd2;
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localparam state_diag_2 = 3'd3;
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reg [2:0] state = state_down;
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reg [2:0] inner_state = 3'd0;
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reg [31:0] tmp = 1;
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wire [31:0] debug_reg;
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assign debug_reg = rom_index(i + inner_state, j);
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always @(posedge clk) begin
43+
if ( done )begin
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end
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else begin
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if (i < LEN - 3) begin
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if (j < LEN - 3) begin
48+
case (state)
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state_down: begin
50+
if (inner_state < 4) begin
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tmp <= tmp * rom_index(i + inner_state, j);
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inner_state <= inner_state + 1;
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end
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else begin
55+
result <= result > tmp ? result : tmp;
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inner_state <= 0;
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tmp <= 1;
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state <= state_right;
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end
60+
end
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state_right: begin
62+
if (inner_state < 4) begin
63+
tmp <= tmp * rom_index(i, j + inner_state);
64+
inner_state <= inner_state + 1;
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end
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else begin
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result <= result > tmp ? result : tmp;
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inner_state <= 0;
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tmp <= 1;
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state <= state_diag_2;
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end
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end
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state_diag_2: begin
74+
if (inner_state < 4) begin
75+
tmp <= tmp * rom_index(i + inner_state, j - inner_state);
76+
inner_state <= inner_state + 1;
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end
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else begin
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result <= result > tmp ? result : tmp;
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inner_state <= 0;
81+
tmp <= 1;
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state <= state_diag;
83+
end
84+
end
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state_diag: begin
86+
if (inner_state < 4) begin
87+
tmp <= tmp * rom_index(i + inner_state, j + inner_state);
88+
inner_state <= inner_state + 1;
89+
end
90+
else begin
91+
result <= result > tmp ? result : tmp;
92+
inner_state <= 0;
93+
tmp <= 1;
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state <= state_down;
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j <= j + 1;
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end
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end
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default: begin
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error <= 1;
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done <= 1;
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end
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endcase
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end
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else begin
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i <= i + 1;
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j <= 0;
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end
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end
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else begin
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done <= 1;
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end
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end
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end
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endmodule

‎src/p0011_v2.v

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module p0011_v2(
2+
input clk,
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output reg [31:0] result = 0,
4+
output reg done = 0,
5+
output reg error = 0
6+
);
7+
8+
localparam LEN = 20;
9+
10+
reg [7:0] rom [0:LEN*LEN - 1];
11+
12+
initial $readmemh("p0011.mem", rom);
13+
14+
15+
function [7:0] rom_index;
16+
input integer i;
17+
input integer j;
18+
begin
19+
if (i < 0 || i >= LEN || j < 0 || j >= LEN) begin
20+
rom_index = 0;
21+
end
22+
else begin
23+
rom_index = rom[i*LEN + j];
24+
end
25+
end
26+
endfunction
27+
28+
function [31:0] get_down;
29+
input integer i;
30+
input integer j;
31+
begin
32+
get_down = rom_index(i, j) * rom_index(i + 1, j) * rom_index(i + 2, j) * rom_index(i + 3, j);
33+
end
34+
endfunction
35+
36+
function [31:0] get_right;
37+
input integer i;
38+
input integer j;
39+
begin
40+
get_right = rom_index(i, j) * rom_index(i, j + 1) * rom_index(i, j + 2) * rom_index(i, j + 3);
41+
end
42+
endfunction
43+
44+
function [31:0] get_diag_down_right;
45+
input integer i;
46+
input integer j;
47+
begin
48+
get_diag_down_right = rom_index(i, j) * rom_index(i + 1, j + 1) * rom_index(i + 2, j + 2) * rom_index(i + 3, j + 3);
49+
end
50+
endfunction
51+
52+
function [31:0] get_diag_down_left;
53+
input integer i;
54+
input integer j;
55+
begin
56+
get_diag_down_left = rom_index(i, j) * rom_index(i + 1, j - 1) * rom_index(i + 2, j - 2) * rom_index(i + 3, j - 3);
57+
end
58+
endfunction
59+
60+
function [31:0] max_5;
61+
input reg [31:0] a;
62+
input reg [31:0] b;
63+
input reg [31:0] c;
64+
input reg [31:0] d;
65+
input reg [31:0] e;
66+
begin
67+
max_5 = a > b ? a : b;
68+
max_5 = max_5 > c ? max_5 : c;
69+
max_5 = max_5 > d ? max_5 : d;
70+
max_5 = max_5 > e ? max_5 : e;
71+
end
72+
endfunction
73+
74+
integer index_i = 0;
75+
integer index_j = 0;
76+
77+
78+
wire [31:0] down;
79+
wire [31:0] right;
80+
wire [31:0] diag_right;
81+
wire [31:0] diag_left;
82+
83+
assign down = get_down(index_i, index_j);
84+
assign right = get_right(index_i, index_j);
85+
assign diag_right = get_diag_down_right(index_i, index_j);
86+
assign diag_left = get_diag_down_left(index_i, index_j);
87+
88+
always @(posedge clk) begin
89+
if ( done )begin
90+
end
91+
else begin
92+
if (index_i < LEN - 3) begin
93+
if (index_j < LEN - 3) begin
94+
result <= max_5(down, right, diag_right, diag_left, result);
95+
index_j <= index_j + 1;
96+
end
97+
else begin
98+
index_i <= index_i + 1;
99+
index_j <= 0;
100+
end
101+
end
102+
else begin
103+
done <= 1;
104+
end
105+
end
106+
end
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108+
endmodule

‎tb/p0011_tb.v

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`timescale 1ns/1ps
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3+
module p0011_tb();
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reg clk = 0;
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wire [31:0] out;
7+
wire done;
8+
wire error;
9+
10+
always #0.5 clk=~clk;
11+
12+
p0011 u_p0011(
13+
.clk(clk),
14+
.result(out),
15+
.done(done),
16+
.error(error)
17+
);
18+
19+
initial begin
20+
@(posedge done or posedge error);
21+
#5;
22+
$display("out = %d", out);
23+
$display("done = %d", done);
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$display("error = %d", error);
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$stop;
26+
end
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endmodule

‎tb/p0011_v2_tb.v

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`timescale 1ns/1ps
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module p0011_v2_tb();
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reg clk = 0;
6+
wire [31:0] out;
7+
wire done;
8+
wire error;
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always #0.5 clk=~clk;
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p0011_v2 u_p0011_v2(
13+
.clk(clk),
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.result(out),
15+
.done(done),
16+
.error(error)
17+
);
18+
19+
initial begin
20+
@(posedge done or posedge error);
21+
#5;
22+
$display("out = %d", out);
23+
$display("done = %d", done);
24+
$display("error = %d", error);
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$stop;
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end
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endmodule

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