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20 Lower neon_vqshrn_n_v · llvm/clangir@d125844 · GitHub
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Lower neon_vqshrn_n_v
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‎clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3416,7 +3416,14 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned BuiltinID, const CallExpr *E,
34163416
SInt32Ty},
34173417
Ops, "aarch64.neon.sqrshrun", ty, getLoc(E->getExprLoc()));
34183418
case NEON::BI__builtin_neon_vqshrn_n_v:
3419-
llvm_unreachable("NEON::BI__builtin_neon_vqshrn_n_v NYI");
3419+
return emitNeonCall(
3420+
builder,
3421+
{builder.getExtendedOrTruncatedElementVectorType(
3422+
vTy, true /* extend */,
3423+
mlir::cast<cir::IntType>(vTy.getEltType()).isSigned()),
3424+
SInt32Ty},
3425+
Ops, usgn ? "aarch64.neon.uqshrn" : "aarch64.neon.sqshrn", ty,
3426+
getLoc(E->getExprLoc()));
34203427
case NEON::BI__builtin_neon_vrshrn_n_v:
34213428
return emitNeonCall(
34223429
builder,

‎clang/test/CIR/CodeGen/AArch64/neon.c

Lines changed: 78 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -6935,59 +6935,89 @@ uint32x2_t test_vqrshrun_n_s64(int64x2_t a) {
69356935
// return vqrshrun_high_n_s64(a, b, 19);
69366936
// }
69376937

6938-
// NYI-LABEL: @test_vqshrn_n_s16(
6939-
// NYI: [[TMP0:%.*]] = bitcast <8 x i16> %a to <16 x i8>
6940-
// NYI: [[VQSHRN_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
6941-
// NYI: [[VQSHRN_N1:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqshrn.v8i8(<8 x i16> [[VQSHRN_N]], i32 3)
6942-
// NYI: ret <8 x i8> [[VQSHRN_N1]]
6943-
// int8x8_t test_vqshrn_n_s16(int16x8_t a) {
6944-
// return vqshrn_n_s16(a, 3);
6945-
// }
6938+
int8x8_t test_vqshrn_n_s16(int16x8_t a) {
6939+
return vqshrn_n_s16(a, 3);
69466940

6947-
// NYI-LABEL: @test_vqshrn_n_s32(
6948-
// NYI: [[TMP0:%.*]] = bitcast <4 x i32> %a to <16 x i8>
6949-
// NYI: [[VQSHRN_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
6950-
// NYI: [[VQSHRN_N1:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqshrn.v4i16(<4 x i32> [[VQSHRN_N]], i32 19)
6951-
// NYI: ret <4 x i16> [[VQSHRN_N1]]
6952-
// int16x4_t test_vqshrn_n_s32(int32x4_t a) {
6953-
// return vqshrn_n_s32(a, 9);
6954-
// }
6941+
// CIR-LABEL: vqshrn_n_s16
6942+
// CIR: cir.llvm.intrinsic "aarch64.neon.sqshrn" {{%.*}}, {{%.*}} :
6943+
// CIR-SAME: (!cir.vector<!s16i x 8>, !s32i) -> !cir.vector<!s8i x 8>
69556944

6956-
// NYI-LABEL: @test_vqshrn_n_s64(
6957-
// NYI: [[TMP0:%.*]] = bitcast <2 x i64> %a to <16 x i8>
6958-
// NYI: [[VQSHRN_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
6959-
// NYI: [[VQSHRN_N1:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqshrn.v2i32(<2 x i64> [[VQSHRN_N]], i32 19)
6960-
// NYI: ret <2 x i32> [[VQSHRN_N1]]
6961-
// int32x2_t test_vqshrn_n_s64(int64x2_t a) {
6962-
// return vqshrn_n_s64(a, 19);
6963-
// }
6945+
// LLVM:{{.*}}test_vqshrn_n_s16(<8 x i16>{{.*}}[[A:%.*]])
6946+
// LLVM: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>
6947+
// LLVM: [[VQSHRN_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
6948+
// LLVM: [[VQSHRN_N1:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqshrn.v8i8(<8 x i16> [[VQSHRN_N]], i32 3)
6949+
// LLVM: ret <8 x i8> [[VQSHRN_N1]]
6950+
}
69646951

6965-
// NYI-LABEL: @test_vqshrn_n_u16(
6966-
// NYI: [[TMP0:%.*]] = bitcast <8 x i16> %a to <16 x i8>
6967-
// NYI: [[VQSHRN_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
6968-
// NYI: [[VQSHRN_N1:%.*]] = call <8 x i8> @llvm.aarch64.neon.uqshrn.v8i8(<8 x i16> [[VQSHRN_N]], i32 3)
6969-
// NYI: ret <8 x i8> [[VQSHRN_N1]]
6970-
// uint8x8_t test_vqshrn_n_u16(uint16x8_t a) {
6971-
// return vqshrn_n_u16(a, 3);
6972-
// }
6952+
int16x4_t test_vqshrn_n_s32(int32x4_t a) {
6953+
return vqshrn_n_s32(a, 9);
69736954

6974-
// NYI-LABEL: @test_vqshrn_n_u32(
6975-
// NYI: [[TMP0:%.*]] = bitcast <4 x i32> %a to <16 x i8>
6976-
// NYI: [[VQSHRN_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
6977-
// NYI: [[VQSHRN_N1:%.*]] = call <4 x i16> @llvm.aarch64.neon.uqshrn.v4i16(<4 x i32> [[VQSHRN_N]], i32 9)
6978-
// NYI: ret <4 x i16> [[VQSHRN_N1]]
6979-
// uint16x4_t test_vqshrn_n_u32(uint32x4_t a) {
6980-
// return vqshrn_n_u32(a, 9);
6981-
// }
6955+
// CIR-LABEL: vqshrn_n_s32
6956+
// CIR: cir.llvm.intrinsic "aarch64.neon.sqshrn" {{%.*}}, {{%.*}} :
6957+
// CIR-SAME: (!cir.vector<!s32i x 4>, !s32i) -> !cir.vector<!s16i x 4>
69826958

6983-
// NYI-LABEL: @test_vqshrn_n_u64(
6984-
// NYI: [[TMP0:%.*]] = bitcast <2 x i64> %a to <16 x i8>
6985-
// NYI: [[VQSHRN_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
6986-
// NYI: [[VQSHRN_N1:%.*]] = call <2 x i32> @llvm.aarch64.neon.uqshrn.v2i32(<2 x i64> [[VQSHRN_N]], i32 19)
6987-
// NYI: ret <2 x i32> [[VQSHRN_N1]]
6988-
// uint32x2_t test_vqshrn_n_u64(uint64x2_t a) {
6989-
// return vqshrn_n_u64(a, 19);
6990-
// }
6959+
// LLVM:{{.*}}test_vqshrn_n_s32(<4 x i32>{{.*}}[[A:%.*]])
6960+
// LLVM: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>
6961+
// LLVM: [[VQSHRN_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
6962+
// LLVM: [[VQSHRN_N1:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqshrn.v4i16(<4 x i32> [[VQSHRN_N]], i32 9)
6963+
// LLVM: ret <4 x i16> [[VQSHRN_N1]]
6964+
}
6965+
6966+
int32x2_t test_vqshrn_n_s64(int64x2_t a) {
6967+
return vqshrn_n_s64(a, 19);
6968+
6969+
// CIR-LABEL: vqshrn_n_s64
6970+
// CIR: cir.llvm.intrinsic "aarch64.neon.sqshrn" {{%.*}}, {{%.*}} :
6971+
// CIR-SAME: (!cir.vector<!s64i x 2>, !s32i) -> !cir.vector<!s32i x 2>
6972+
6973+
// LLVM:{{.*}}test_vqshrn_n_s64(<2 x i64>{{.*}}[[A:%.*]])
6974+
// LLVM: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>
6975+
// LLVM: [[VQSHRN_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
6976+
// LLVM: [[VQSHRN_N1:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqshrn.v2i32(<2 x i64> [[VQSHRN_N]], i32 19)
6977+
// LLVM: ret <2 x i32> [[VQSHRN_N1]]
6978+
}
6979+
6980+
uint8x8_t test_vqshrn_n_u16(uint16x8_t a) {
6981+
return vqshrn_n_u16(a, 3);
6982+
6983+
// CIR-LABEL: vqshrn_n_u16
6984+
// CIR: cir.llvm.intrinsic "aarch64.neon.uqshrn" {{%.*}}, {{%.*}} :
6985+
// CIR-SAME: (!cir.vector<!u16i x 8>, !s32i) -> !cir.vector<!u8i x 8>
6986+
6987+
// LLVM:{{.*}}test_vqshrn_n_u16(<8 x i16>{{.*}}[[A:%.*]])
6988+
// LLVM: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>
6989+
// LLVM: [[VQSHRN_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
6990+
// LLVM: [[VQSHRN_N1:%.*]] = call <8 x i8> @llvm.aarch64.neon.uqshrn.v8i8(<8 x i16> [[VQSHRN_N]], i32 3)
6991+
// LLVM: ret <8 x i8> [[VQSHRN_N1]]
6992+
}
6993+
6994+
uint16x4_t test_vqshrn_n_u32(uint32x4_t a) {
6995+
return vqshrn_n_u32(a, 9);
6996+
6997+
// CIR-LABEL: vqshrn_n_u32
6998+
// CIR: cir.llvm.intrinsic "aarch64.neon.uqshrn" {{%.*}}, {{%.*}} :
6999+
// CIR-SAME: (!cir.vector<!u32i x 4>, !s32i) -> !cir.vector<!u16i x 4>
7000+
7001+
// LLVM:{{.*}}test_vqshrn_n_u32(<4 x i32>{{.*}}[[A:%.*]])
7002+
// LLVM: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>
7003+
// LLVM: [[VQSHRN_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
7004+
// LLVM: [[VQSHRN_N1:%.*]] = call <4 x i16> @llvm.aarch64.neon.uqshrn.v4i16(<4 x i32> [[VQSHRN_N]], i32 9)
7005+
// LLVM: ret <4 x i16> [[VQSHRN_N1]]
7006+
}
7007+
7008+
uint32x2_t test_vqshrn_n_u64(uint64x2_t a) {
7009+
return vqshrn_n_u64(a, 19);
7010+
7011+
// CIR-LABEL: vqshrn_n_u64
7012+
// CIR: cir.llvm.intrinsic "aarch64.neon.uqshrn" {{%.*}}, {{%.*}} :
7013+
// CIR-SAME: (!cir.vector<!u64i x 2>, !s32i) -> !cir.vector<!u32i x 2>
7014+
7015+
// LLVM:{{.*}}test_vqshrn_n_u64(<2 x i64>{{.*}}[[A:%.*]])
7016+
// LLVM: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>
7017+
// LLVM: [[VQSHRN_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
7018+
// LLVM: [[VQSHRN_N1:%.*]] = call <2 x i32> @llvm.aarch64.neon.uqshrn.v2i32(<2 x i64> [[VQSHRN_N]], i32 19)
7019+
// LLVM: ret <2 x i32> [[VQSHRN_N1]]
7020+
}
69917021

69927022
// NYI-LABEL: @test_vqshrn_high_n_s16(
69937023
// NYI: [[TMP0:%.*]] = bitcast <8 x i16> %b to <16 x i8>

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