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45 Fix bit shift in AHB1 register for CRC enable/reset/sleep-mode bits, STM32L4x3.svd patch by cyrusmetcalf · Pull Request #517 · stm32-rs/stm32-rs · GitHub
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Fix bit shift in AHB1 register for CRC enable/reset/sleep-mode bits, STM32L4x3.svd patch #517

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Merged
merged 4 commits into from
Mar 28, 2021
Merged

Fix bit shift in AHB1 register for CRC enable/reset/sleep-mode bits, STM32L4x3.svd patch #517

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e3106c8
Fix bit shift in AHB1 register for CRC enable/reset/sleep-mode bits
cyrusmetcalf Mar 17, 2021
3aca3ef
Update devices/stm32l4x3.yaml
cyrusmetcalf Mar 24, 2021
2f5b0e5
Update devices/stm32l4x3.yaml
cyrusmetcalf Mar 28, 2021
0dfef36
Merge branch 'master' into merge_branch
cyrusmetcalf Mar 28, 2021
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Update devices/stm32l4x3.yaml 
Co-authored-by: Adam Greig <adam@adamgreig.com>
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@cyrusmetcalf @adamgreig
cyrusmetcalf and adamgreig authored Mar 24, 2021
commit 3aca3ef434541de0f888e205e9f99a30b420742a
3 changes: 1 addition & 2 deletions devices/stm32l4x3.yaml
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Expand Up @@ -12,8 +12,7 @@ RCC:
name: USBFSEN
description: USB FS clock enable

# SVD incorrectly shifts CRCEN/CRCRST/CRCSMEN 11 bits instead of 12
RCC:
# SVD incorrectly shifts CRCEN/CRCRST/CRCSMEN 11 bits instead of 12
AHB1ENR:
_modify:
CRCEN:
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