Content-Length: 19663 | pFad | http://github.com/stm32-rs/stm32-rs/pull/659.patch

thub.com From fa959e18bb85ebf2f0ad4c470356c3bc9e7c693b Mon Sep 17 00:00:00 2001 From: James Waples Date: Sun, 14 Nov 2021 21:10:32 +0000 Subject: [PATCH 1/3] Add entire TIM21/TIM22 config into l0xx --- peripherals/tim/tim_l0.yaml | 161 +++++++++++++++++++++++++++++++++++- 1 file changed, 157 insertions(+), 4 deletions(-) diff --git a/peripherals/tim/tim_l0.yaml b/peripherals/tim/tim_l0.yaml index e73808e51..000035dbd 100644 --- a/peripherals/tim/tim_l0.yaml +++ b/peripherals/tim/tim_l0.yaml @@ -30,8 +30,161 @@ LSE: [5, "TIM2 ETR input is connected to LSE"] HSI: [3, "TIM2 ETR input is connected to HSI16 when HSI16OUTEN bit is set"] -"TIM21": +"TIM2?": + CR1: + CMS: + EdgeAligned: [0, "The counter counts up or down depending on the direction bit"] + CenterAligned1: [1, "The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down."] + CenterAligned2: [2, "The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up."] + CenterAligned3: [3, "The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down."] + DIR: + Up: [0, "Counter used as upcounter"] + Down: [1, "Counter used as downcounter"] + OPM: + NotStopped: [0, "Counter is not stopped on the update event"] + Stopped: [1, "Counter stops counting on the next update event (clearing the CEN bit)"] + CR2: + MMS: + Reset: [0, "Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO)"] + Enable: [1, "Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO)"] + Update: [2, "Update - The update event is selected as trigger output (TRGO)"] + ComparePulse: [3, "Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred"] + OC1REF: [4, "OC1REF signal is used as trigger output (TRGO)"] + OC2REF: [5, "OC2REF signal is used as trigger output (TRGO)"] + SMCR: + ETP: + RisingEdge: [0, "ETR is non-inverted, active at high level or rising edge"] + FallingEdge: [1, "ETR is inverted, active at low level or falling edge"] + ECE: + Disabled: [0, "External clock mode 2 disabled"] + Enabled: [1, "External clock mode 2 enabled"] + ETPS: + Div1: [0, "Prescaler OFF"] + Div2: [1, "ETRP frequency divided by 2"] + Div4: [2, "ETRP frequency divided by 4"] + Div8: [3, "ETRP frequency divided by 8"] + ETF: + NoFilter: [0, "No filter, sampling is done at fDTS"] + FCK_INT_N2: [1, "fSAMPLING=fCK_INT, N=2"] + FCK_INT_N4: [2, "fSAMPLING=fCK_INT, N=4"] + FCK_INT_N8: [3, "fSAMPLING=fCK_INT, N=8"] + FDTS_Div2_N6: [4, "fSAMPLING=fDTS/2, N=6"] + FDTS_Div2_N8: [5, "fSAMPLING=fDTS/2, N=8"] + FDTS_Div4_N6: [6, "fSAMPLING=fDTS/4, N=6"] + FDTS_Div4_N8: [7, "fSAMPLING=fDTS/4, N=8"] + FDTS_Div8_N6: [8, "fSAMPLING=fDTS/8, N=6"] + FDTS_Div8_N8: [9, "fSAMPLING=fDTS/8, N=8"] + FDTS_Div16_N5: [10, "fSAMPLING=fDTS/16, N=5"] + FDTS_Div16_N6: [11, "fSAMPLING=fDTS/16, N=6"] + FDTS_Div16_N8: [12, "fSAMPLING=fDTS/16, N=8"] + FDTS_Div32_N5: [13, "fSAMPLING=fDTS/32, N=5"] + FDTS_Div32_N6: [14, "fSAMPLING=fDTS/32, N=6"] + FDTS_Div32_N8: [15, "fSAMPLING=fDTS/32, N=8"] + MSM: + NoSync: [0, "No action"] + Sync: [1, "The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event."] + TS: + ITR0: [0, "Internal Trigger 0 (ITR0)"] + ITR1: [1, "Internal Trigger 1 (ITR1)"] + ITR2: [2, "Internal Trigger 2 (ITR2)"] + TI1F_ED: [4, "TI1 Edge Detector (TI1F_ED)"] + TI1FP1: [5, "Filtered Timer Input 1 (TI1FP1)"] + TI2FP2: [6, "Filtered Timer Input 2 (TI2FP2)"] + ETRF: [7, "External Trigger input (ETRF)"] + SMS: + Disabled: [0, "Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock."] + Encoder_Mode_1: [1, "Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level."] + Encoder_Mode_2: [2, "Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level."] + Encoder_Mode_3: [3, "Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input."] + Reset_Mode: [4, "Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers."] + Gated_Mode: [5, "Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled."] + Trigger_Mode: [6, "Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled."] + Ext_Clock_Mode: [7, "External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter."] + DIER: + TIE: + Disabled: [0, "Trigger interrupt disabled"] + Enabled: [1, "Trigger interrupt enabled"] + "CC?IE": + Disabled: [0, "CCx interrupt disabled"] + Enabled: [1, "CCx interrupt enabled"] + SR: + "CC?OF": + _read: + Overcapture: [1, "The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set"] + _write: + Clear: [0, "Clear flag"] + TIF: + _read: + NoTrigger: [0, "No trigger event occurred"] + Trigger: [1, "Trigger interrupt pending"] + _write: + Clear: [0, "Clear flag"] + "CC?IF": + _read: + Match: [1, "If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register."] + _write: + Clear: [0, "Clear flag"] + EGR: + TG: + _write: + Trigger: [1, "The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled."] + "CC?G": + _write: + Trigger: [1, "If CCx is an output: CCxIF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CCx is an input: The current value of the counter is captured in TIMx_CCR1 register."] + CCMR?_Input: + IC?F: + NoFilter: [0, "No filter, sampling is done at fDTS"] + FCK_INT_N2: [1, "fSAMPLING=fCK_INT, N=2"] + FCK_INT_N4: [2, "fSAMPLING=fCK_INT, N=4"] + FCK_INT_N8: [3, "fSAMPLING=fCK_INT, N=8"] + FDTS_Div2_N6: [4, "fSAMPLING=fDTS/2, N=6"] + FDTS_Div2_N8: [5, "fSAMPLING=fDTS/2, N=8"] + FDTS_Div4_N6: [6, "fSAMPLING=fDTS/4, N=6"] + FDTS_Div4_N8: [7, "fSAMPLING=fDTS/4, N=8"] + FDTS_Div8_N6: [8, "fSAMPLING=fDTS/8, N=6"] + FDTS_Div8_N8: [9, "fSAMPLING=fDTS/8, N=8"] + FDTS_Div16_N5: [10, "fSAMPLING=fDTS/16, N=5"] + FDTS_Div16_N6: [11, "fSAMPLING=fDTS/16, N=6"] + FDTS_Div16_N8: [12, "fSAMPLING=fDTS/16, N=8"] + FDTS_Div32_N5: [13, "fSAMPLING=fDTS/32, N=5"] + FDTS_Div32_N6: [14, "fSAMPLING=fDTS/32, N=6"] + FDTS_Div32_N8: [15, "fSAMPLING=fDTS/32, N=8"] + IC?PSC: [0, 3] + CC?S: + Output: [0, "CCx channel is configured as output"] + TI1: [1, "CCx channel is configured as input, ICx is mapped on TI1"] + TI2: [2, "CCx channel is configured as input, ICx is mapped on TI2"] + TRC: [3, "CCx channel is configured as input, ICx is mapped on TRC"] + CCMR?_Output: + OC?PE: + Disabled: [0, "Preload register on CCRx disabled. New values written to CCRx are taken into account immediately"] + Enabled: [1, "Preload register on CCRx enabled. Preload value is loaded into active register on each update event"] + CC?S: + Output: [0, "CCx channel is configured as output"] + CCER: + "CC?NP": + Negative: [0, "Negative polarity"] + Positive: [1, "Positive polarity"] + "CC?P": + RisingEdge: [0, "Noninverted/rising edge"] + FallingEdge: [1, "Inverted/falling edge"] + "CC?E": + Disabled: [0, "Capture disabled"] + Enabled: [1, "Capture enabled"] + CNT: + CNT: [0, 65535] + ARR: + ARR: [0, 65535] + "CCR?": + "CCR?": [0, 65535] OR: - TI2_RMP: - GPIO: [0, "TIM2x TI2 input connected to GPIO"] - COMP2_OUT: [1, "TIM2x TI2 input connected to COMP2_OUT"] \ No newline at end of file + TI1_RMP: + GPIO: [0, "TIM2x TI1 input connected to GPIO"] + COMP2_OUT: [1, "TIM2x TI1 input connected to COMP2_OUT"] + COMP1_OUT: [2, "TIM2x TI1 input connected to COMP1_OUT"] + ETR_RMP: + GPIO: [0, "TIM2x ETR input connected to GPIO"] + COMP2_OUT: [1, "TIM2x ETR input connected to COMP2_OUT"] + COMP1_OUT: [2, "TIM2x ETR input connected to COMP1_OUT"] + LSE: [3, "TIM2x ETR input connected to LSE clock"] + From 639fcd5c18402e9b1220a4db417e4f68d2c66cfb Mon Sep 17 00:00:00 2001 From: James Waples Date: Wed, 8 Dec 2021 13:50:07 +0000 Subject: [PATCH 2/3] Remove copypasta, use tim21.yaml directly This also removes the CKD from tim21.yaml - this is already included in tim_basic.yaml --- peripherals/tim/tim21.yaml | 4 - peripherals/tim/tim_l0.yaml | 160 +----------------------------------- 2 files changed, 2 insertions(+), 162 deletions(-) diff --git a/peripherals/tim/tim21.yaml b/peripherals/tim/tim21.yaml index 6a28fbe33..363ddfa26 100644 --- a/peripherals/tim/tim21.yaml +++ b/peripherals/tim/tim21.yaml @@ -2,10 +2,6 @@ "TIM2?": CR1: - CKD: - Div1: [0, "t_DTS = t_CK_INT"] - Div2: [1, "t_DTS = 2 × t_CK_INT"] - Div4: [2, "t_DTS = 4 × t_CK_INT"] CMS: EdgeAligned: [0, "The counter counts up or down depending on the direction bit"] CenterAligned1: [1, "The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down."] diff --git a/peripherals/tim/tim_l0.yaml b/peripherals/tim/tim_l0.yaml index 000035dbd..e533510d3 100644 --- a/peripherals/tim/tim_l0.yaml +++ b/peripherals/tim/tim_l0.yaml @@ -30,161 +30,5 @@ LSE: [5, "TIM2 ETR input is connected to LSE"] HSI: [3, "TIM2 ETR input is connected to HSI16 when HSI16OUTEN bit is set"] -"TIM2?": - CR1: - CMS: - EdgeAligned: [0, "The counter counts up or down depending on the direction bit"] - CenterAligned1: [1, "The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down."] - CenterAligned2: [2, "The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up."] - CenterAligned3: [3, "The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down."] - DIR: - Up: [0, "Counter used as upcounter"] - Down: [1, "Counter used as downcounter"] - OPM: - NotStopped: [0, "Counter is not stopped on the update event"] - Stopped: [1, "Counter stops counting on the next update event (clearing the CEN bit)"] - CR2: - MMS: - Reset: [0, "Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO)"] - Enable: [1, "Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO)"] - Update: [2, "Update - The update event is selected as trigger output (TRGO)"] - ComparePulse: [3, "Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred"] - OC1REF: [4, "OC1REF signal is used as trigger output (TRGO)"] - OC2REF: [5, "OC2REF signal is used as trigger output (TRGO)"] - SMCR: - ETP: - RisingEdge: [0, "ETR is non-inverted, active at high level or rising edge"] - FallingEdge: [1, "ETR is inverted, active at low level or falling edge"] - ECE: - Disabled: [0, "External clock mode 2 disabled"] - Enabled: [1, "External clock mode 2 enabled"] - ETPS: - Div1: [0, "Prescaler OFF"] - Div2: [1, "ETRP frequency divided by 2"] - Div4: [2, "ETRP frequency divided by 4"] - Div8: [3, "ETRP frequency divided by 8"] - ETF: - NoFilter: [0, "No filter, sampling is done at fDTS"] - FCK_INT_N2: [1, "fSAMPLING=fCK_INT, N=2"] - FCK_INT_N4: [2, "fSAMPLING=fCK_INT, N=4"] - FCK_INT_N8: [3, "fSAMPLING=fCK_INT, N=8"] - FDTS_Div2_N6: [4, "fSAMPLING=fDTS/2, N=6"] - FDTS_Div2_N8: [5, "fSAMPLING=fDTS/2, N=8"] - FDTS_Div4_N6: [6, "fSAMPLING=fDTS/4, N=6"] - FDTS_Div4_N8: [7, "fSAMPLING=fDTS/4, N=8"] - FDTS_Div8_N6: [8, "fSAMPLING=fDTS/8, N=6"] - FDTS_Div8_N8: [9, "fSAMPLING=fDTS/8, N=8"] - FDTS_Div16_N5: [10, "fSAMPLING=fDTS/16, N=5"] - FDTS_Div16_N6: [11, "fSAMPLING=fDTS/16, N=6"] - FDTS_Div16_N8: [12, "fSAMPLING=fDTS/16, N=8"] - FDTS_Div32_N5: [13, "fSAMPLING=fDTS/32, N=5"] - FDTS_Div32_N6: [14, "fSAMPLING=fDTS/32, N=6"] - FDTS_Div32_N8: [15, "fSAMPLING=fDTS/32, N=8"] - MSM: - NoSync: [0, "No action"] - Sync: [1, "The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event."] - TS: - ITR0: [0, "Internal Trigger 0 (ITR0)"] - ITR1: [1, "Internal Trigger 1 (ITR1)"] - ITR2: [2, "Internal Trigger 2 (ITR2)"] - TI1F_ED: [4, "TI1 Edge Detector (TI1F_ED)"] - TI1FP1: [5, "Filtered Timer Input 1 (TI1FP1)"] - TI2FP2: [6, "Filtered Timer Input 2 (TI2FP2)"] - ETRF: [7, "External Trigger input (ETRF)"] - SMS: - Disabled: [0, "Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock."] - Encoder_Mode_1: [1, "Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level."] - Encoder_Mode_2: [2, "Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level."] - Encoder_Mode_3: [3, "Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input."] - Reset_Mode: [4, "Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers."] - Gated_Mode: [5, "Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled."] - Trigger_Mode: [6, "Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled."] - Ext_Clock_Mode: [7, "External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter."] - DIER: - TIE: - Disabled: [0, "Trigger interrupt disabled"] - Enabled: [1, "Trigger interrupt enabled"] - "CC?IE": - Disabled: [0, "CCx interrupt disabled"] - Enabled: [1, "CCx interrupt enabled"] - SR: - "CC?OF": - _read: - Overcapture: [1, "The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set"] - _write: - Clear: [0, "Clear flag"] - TIF: - _read: - NoTrigger: [0, "No trigger event occurred"] - Trigger: [1, "Trigger interrupt pending"] - _write: - Clear: [0, "Clear flag"] - "CC?IF": - _read: - Match: [1, "If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register."] - _write: - Clear: [0, "Clear flag"] - EGR: - TG: - _write: - Trigger: [1, "The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled."] - "CC?G": - _write: - Trigger: [1, "If CCx is an output: CCxIF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CCx is an input: The current value of the counter is captured in TIMx_CCR1 register."] - CCMR?_Input: - IC?F: - NoFilter: [0, "No filter, sampling is done at fDTS"] - FCK_INT_N2: [1, "fSAMPLING=fCK_INT, N=2"] - FCK_INT_N4: [2, "fSAMPLING=fCK_INT, N=4"] - FCK_INT_N8: [3, "fSAMPLING=fCK_INT, N=8"] - FDTS_Div2_N6: [4, "fSAMPLING=fDTS/2, N=6"] - FDTS_Div2_N8: [5, "fSAMPLING=fDTS/2, N=8"] - FDTS_Div4_N6: [6, "fSAMPLING=fDTS/4, N=6"] - FDTS_Div4_N8: [7, "fSAMPLING=fDTS/4, N=8"] - FDTS_Div8_N6: [8, "fSAMPLING=fDTS/8, N=6"] - FDTS_Div8_N8: [9, "fSAMPLING=fDTS/8, N=8"] - FDTS_Div16_N5: [10, "fSAMPLING=fDTS/16, N=5"] - FDTS_Div16_N6: [11, "fSAMPLING=fDTS/16, N=6"] - FDTS_Div16_N8: [12, "fSAMPLING=fDTS/16, N=8"] - FDTS_Div32_N5: [13, "fSAMPLING=fDTS/32, N=5"] - FDTS_Div32_N6: [14, "fSAMPLING=fDTS/32, N=6"] - FDTS_Div32_N8: [15, "fSAMPLING=fDTS/32, N=8"] - IC?PSC: [0, 3] - CC?S: - Output: [0, "CCx channel is configured as output"] - TI1: [1, "CCx channel is configured as input, ICx is mapped on TI1"] - TI2: [2, "CCx channel is configured as input, ICx is mapped on TI2"] - TRC: [3, "CCx channel is configured as input, ICx is mapped on TRC"] - CCMR?_Output: - OC?PE: - Disabled: [0, "Preload register on CCRx disabled. New values written to CCRx are taken into account immediately"] - Enabled: [1, "Preload register on CCRx enabled. Preload value is loaded into active register on each update event"] - CC?S: - Output: [0, "CCx channel is configured as output"] - CCER: - "CC?NP": - Negative: [0, "Negative polarity"] - Positive: [1, "Positive polarity"] - "CC?P": - RisingEdge: [0, "Noninverted/rising edge"] - FallingEdge: [1, "Inverted/falling edge"] - "CC?E": - Disabled: [0, "Capture disabled"] - Enabled: [1, "Capture enabled"] - CNT: - CNT: [0, 65535] - ARR: - ARR: [0, 65535] - "CCR?": - "CCR?": [0, 65535] - OR: - TI1_RMP: - GPIO: [0, "TIM2x TI1 input connected to GPIO"] - COMP2_OUT: [1, "TIM2x TI1 input connected to COMP2_OUT"] - COMP1_OUT: [2, "TIM2x TI1 input connected to COMP1_OUT"] - ETR_RMP: - GPIO: [0, "TIM2x ETR input connected to GPIO"] - COMP2_OUT: [1, "TIM2x ETR input connected to COMP2_OUT"] - COMP1_OUT: [2, "TIM2x ETR input connected to COMP1_OUT"] - LSE: [3, "TIM2x ETR input connected to LSE clock"] - +_include: + - ./tim21.yaml From f7e638cb5b080b0d70102a2fe40753e22d8b0bbe Mon Sep 17 00:00:00 2001 From: James Waples Date: Tue, 14 Dec 2021 09:30:55 +0000 Subject: [PATCH 3/3] Add TI2_RMP back in --- peripherals/tim/tim21.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/peripherals/tim/tim21.yaml b/peripherals/tim/tim21.yaml index 363ddfa26..647b1f107 100644 --- a/peripherals/tim/tim21.yaml +++ b/peripherals/tim/tim21.yaml @@ -158,3 +158,9 @@ COMP1_OUT: [2, "TIM2x ETR input connected to COMP1_OUT"] LSE: [3, "TIM2x ETR input connected to LSE clock"] +# TI2_RMP is only available on TIM21 +TIM21: + OR: + TI2_RMP: + GPIO: [0, "TIM2x TI2 input connected to GPIO"] + COMP2_OUT: [1, "TIM2x TI2 input connected to COMP2_OUT"] \ No newline at end of file

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