DAC smal rename DAC1 -> DAC for all l4x types opamp added description

stm32-rs · bors · Jul 3, 2022 · Dec 27, 2021 · Dec 28, 2021 · Jan 4, 2022
commit dfd1f12d6a78194d15e90938883f80904ed63ca3
diff --git a/devices/common_patches/dac/dac_rename_stm32l4xx.yaml b/devices/common_patches/dac/dac_rename_stm32l4xx.yaml
@@ -0,0 +1,4 @@
+_modify:
+  # Fix DAC peripherals to match other devices
+  DAC1:
+    name: DAC
diff --git a/devices/stm32l4x1.yaml b/devices/stm32l4x1.yaml
@@ -140,3 +140,6 @@ _include:
  - ../peripherals/spi/spi_l4.yaml
  - ./common_patches/comp/l4xx_comp_reg_rename.yaml
  - ../peripherals/comp/comp_l4x1.yaml
+ - ./common_patches/dac/dac_rename_stm32l4xx.yaml
+ - ../peripherals/dac/dac_l4xx.yaml
+ - ../peripherals/opamp/opamp_l4.yaml
diff --git a/devices/stm32l4x2.yaml b/devices/stm32l4x2.yaml
@@ -3,6 +3,7 @@ _svd: ../svd/stm32l4x2.svd
 MPU:
   _strip:
     - "MPU_"
+
 
 # Most of the patches and includes for this device are shared with the L412,
 # so update the common patch file below instead.
@@ -15,3 +16,6 @@ _include:
  - ../peripherals/rcc/rcc_l4_uart4.yaml
  - ./common_patches/comp/l4xx_comp_reg_rename.yaml
  - ../peripherals/comp/comp_l4x1.yaml
+ - ./common_patches/dac/dac_rename_stm32l4xx.yaml
+ - ../peripherals/dac/dac_l4xx.yaml
+ - ../peripherals/opamp/opamp_l4.yaml
diff --git a/devices/stm32l4x3.yaml b/devices/stm32l4x3.yaml
@@ -170,3 +170,6 @@ _include:
  - ./common_patches/l4_lcd_segment.yaml
  - ./common_patches/comp/l4xx_comp_reg_rename.yaml
  - ../peripherals/comp/comp_l4x6.yaml
+ - ./common_patches/dac/dac_rename_stm32l4xx.yaml
+ - ../peripherals/dac/dac_l4xx.yaml
+ - ../peripherals/opamp/opamp_l4.yaml
diff --git a/devices/stm32l4x6.yaml b/devices/stm32l4x6.yaml
@@ -96,3 +96,6 @@ _include:
  - common_patches/adc_common_group_name.yaml
  - ./common_patches/comp/l4xx_comp_reg_rename.yaml
  - ../peripherals/comp/comp_l4x6.yaml
+ - ../peripherals/dac/dac_l4xx.yaml
+ - ../peripherals/opamp/opamp_l4.yaml
+
diff --git a/peripherals/dac/dac_l4xx.yaml b/peripherals/dac/dac_l4xx.yaml
@@ -0,0 +1,95 @@
+DAC,DAC?:
+  "CR,CR?":
+    "CEN?":
+      Normal: [0, 'DAC Channel X Normal operating mode']
+      Calibration: [1, 'DAC Channel X calibration mode']
+    "DMAUDRIE?":
+      Disabled: [0, "DAC Channel X  DMA Underrun Interrupt disabled"]
+      Enabled: [1, "DAC Channel X DMA Underrun Interrupt enabled"]
+    "DMAEN?":
+      Disabled: [0, "DAC Channel X DMA mode disabled"]
+      Enabled: [1, "DAC Channel X DMA mode enabled"]
+    "MAMP?":
+      Amp1: [0b0000, 'Unmask bit0 of LFSR/ triangle amplitude equal to 1']
+      Amp3: [0b0001, 'Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3']
+      Amp7: [0b0010, 'Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7']
+      Amp15: [0b0011, 'Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15']
+      Amp31: [0b0100, 'Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31']
+      Amp63: [0b0101, 'Unmask bits[5:0] of LFSR/ triangle amplitude equal 63']
+      Amp127: [0b0110, 'Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127']
+      Amp255: [0b0111, 'Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255']
+      Amp511: [0b1000, 'Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511']
+      Amp1023: [0b1001, 'Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023']
+      Amp2047: [0b1010, 'Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047']
+      Amp4095: [0b1011, 'Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095']
+    "WAVE?":
+      Disabled: [0, 'Wave generation disabled']
+      Noise: [1, 'Noise wave generation enabled']
+      Triangle: [2, 'Triangle wave generation enabled']
+    "TSEL?":
+      TIM6_TRGO: [0, 'TIM6_TRGO event trigger for DAC conversion, if TEN is enabled']
+      TIM8_TRGO: [1, 'TIM8_TRGO']
+      TIM7_TRGO: [2, 'TIM7_TRGO  (Note: Reserved on STM32L45xxx and STM32L46xxx devices)']
+      TIM5_TRGO: [3, 'TIM5_TRGO']
+      TIM2_TRGO: [4, 'TIM2_TRGO']
+      TIM4_TRGO: [5, 'TIM4_TRGO']
+      EXTI9: [6, 'External pin']
+      SWTRIG: [7, 'Software triger']
+    "TEN?":
+      Disabled: [0, "DAC Channel X trigger disabled"]
+      Enabled: [1, "DAC Channel X trigger enabled"]
+    "EN?":
+      Disabled: [0, "DAC Channel X disabled"]
+      Enabled: [1, "DAC Channel X enabled"]
+
+  SWTRIGR:
+    "SWTRIG?":
+      NoTrigger: [0, 'No trigger']
+      Trigger: [1, 'Trigger']
+
+  "DOR?":
+    "DACC?DOR": [0, 4095]
+
+  SR:
+    "BWST?":
+      Idle: [0, 'There is no write operation of DAC_SHSR1 ongoing: DAC_SHSR1 can be written']
+      Busy: [1, 'There is a write operation of DAC_SHSR1 ongoing: DAC_SHSR1 cannot be written']
+    "CAL_FLAG?":
+      Lower: [0, 'Calibration trimming value is lower than the offset correction value']
+      Equal_Higher: [1, 'Calibration trimming value is equal or greater than the offset correction value']
+    "DMAUDR?":
+      NoError: [0, 'No DMA underrun error condition occurred for DAC channel x']
+      Error: [1, 'DMA underrun error condition occurred for DAC channel x (the currently selected trigger is driving DAC channel1 conversion at a frequency higher than the DMA service capability rate)']
+
+  CCR:
+    "OTRIM?": [0, 31]
+
+  MCR:
+    "MODE?":
+      NormalPinBuffer: [0b000, 'Normal mode - DAC channelx is connected to external pin with Buffer enabled']
+      NormalPinChipBuffer: [0b001, 'Normal mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled']
+      NormalPinNoBuffer: [0b010, 'Normal mode - DAC channelx is connected to external pin with Buffer disabled']
+      NormalChipNoBuffer: [0b011, 'Normal mode - DAC channelx is connected to on chip peripherals with Buffer disabled']
+      SHPinBuffer: [0b100, 'S&H mode - DAC channelx is connected to external pin with Buffer enabled']
+      SHPinChipBuffer: [0b101, 'S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled']
+      SHPinNoBuffer: [0b110, 'S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer disabled']
+      SHChipNoBuffer: [0b111, 'S&H mode - DAC channelx is connected to on chip peripherals with Buffer disabled']
+
+  "SHSR?":
+    "TSAMPLE?": [0, 1023]
+
+  SHHR:
+    "THOLD?": [0, 1023]
+
+  SHRR:
+    "TREFRESH?": [0, 255]
+
+  "DHR12R?":
+    "DACC?DHR": [0, 4095]
+
+  "DHR12L?":
+    "DACC?DHR": [0, 4095]
+
+  "DHR8R?":
+    "DACC?DHR": [0, 256]
+
diff --git a/peripherals/opamp/opamp_l4.yaml b/peripherals/opamp/opamp_l4.yaml
@@ -0,0 +1,47 @@
+
+OPAMP:
+  OPAMP?_CSR:
+    CALOUT:       [0, 1]
+    PGA_GAIN:
+      Gain2:      [0, "Gain 2"]
+      Gain4:      [1, "Gain 4"]
+      Gain8:      [2, "Gain 8"]
+      Gain16:     [3, "Gain 16"]
+    CALSEL:
+      NMOS:    [0, "0.2V applied to OPAMP inputs during calibration"]
+      PMOS:        [1, VDDA-0.2V applied to OPAMP inputs during calibration"]
+    CALON:
+      Disabled:    [0, "Normal mode"]
+      Enabled:     [1, "Calibration mode"]
+    VP_SEL:
+      GPIO:        [0, "GPIO connectet to VINP"]
+      DAC:         [1, "DAC connected to VPINP"]
+    VM_SEL:
+      GPIO:        [0, "GPIO connectet to VINM"]
+      LOW_LEAKAGE: [1, "Low leakage inputs connecte (only available in certen BGA cases"]
+      PGA_MODE:    [2, "OPAMP in PGA mode"]
+    USERTRIM:
+      Factory:     [0, "Factory trim used"]
+      User:        [1, "User trim used"]
+    OPAMODE:
+      PGA_DISABLED: [0, "internal PGA diabled"]
+      PGA_ENABLED:  [2, "internal PGA enabled, gain programmed in PGA_GAIN"]
+      FOLLOWER:     [3, "internal follower"]
+    OPALPM:
+      NORMAL:       [0, OpAmp in normal mode]
+      LOW:          [1, OpAmp in low power mode]
+    OPAEN:
+      Disabled:     [0, "OpAmp disabled"]
+      Enabled:      [1, "OpAmp enabled"]
+  OPAMP?_OTR:
+    TRIMOFFSETN:    [0, 31]
+    TRIMOFFSETP:    [0, 31]
+  OPAMP?_LPOTR:
+    TRIMLPOFFSETN:  [0, 31]
+    TRIMLPOFFSETP:  [0, 31]
+
+  OPAMP1_CSR:
+    OPA_RANGE:
+      LOW:          [0, "low range (VDDA < 2.4V"]
+      HIGH:         [1, "low range (VDDA >2.4V"]
+