rename CFGR to Config

stm32-rs · burrbull · May 25, 2025 · May 27, 2025 · May 29, 2025 · May 29, 2025
commit 63e7ae9c431e64d88cfaf9b195514d8321a3fd2f
diff --git a/examples/analog-stopwatch-with-spi-ssd1306.rs b/examples/analog-stopwatch-with-spi-ssd1306.rs
@@ -8,7 +8,7 @@
 #![no_main]
 
 use panic_semihosting as _;
-use stm32f4xx_hal::{self as hal, rcc::CFGR};
+use stm32f4xx_hal::{self as hal, rcc::Config};
 
 use crate::hal::{
     gpio::{Edge, Input, PA0},
@@ -223,7 +223,7 @@ fn main() -> ! {
 
 fn setup_clocks(rcc: pac::RCC) -> Rcc {
     rcc.freeze(
-        CFGR::hsi()
+        Config::hsi()
             .hclk(180.MHz())
             .sysclk(180.MHz())
             .pclk1(45.MHz())

diff --git a/examples/blinky-timer-irq.rs b/examples/blinky-timer-irq.rs
@@ -8,7 +8,7 @@
 
 use panic_halt as _;
 
-use stm32f4xx_hal::{self as hal, rcc::CFGR};
+use stm32f4xx_hal::{self as hal, rcc::Config};
 
 use crate::hal::{
     gpio::{self, Output, PushPull},
@@ -66,7 +66,7 @@ fn TIM2() {
 fn main() -> ! {
     let dp = Peripherals::take().unwrap();
 
-    let rcc = dp.RCC.freeze(CFGR::hsi().sysclk(16.MHz()).pclk1(8.MHz()));
+    let rcc = dp.RCC.freeze(Config::hsi().sysclk(16.MHz()).pclk1(8.MHz()));
 
     // Configure PA5 pin to blink LED
     let gpioa = dp.GPIOA.split();

diff --git a/examples/can-send.rs b/examples/can-send.rs
@@ -10,7 +10,7 @@ use bxcan::filter::Mask32;
 use bxcan::{Fifo, Frame, StandardId};
 use cortex_m_rt::entry;
 use nb::block;
-use stm32f4xx_hal::rcc::CFGR;
+use stm32f4xx_hal::rcc::Config;
 use stm32f4xx_hal::{pac, prelude::*};
 
 #[entry]
@@ -20,7 +20,7 @@ fn main() -> ! {
     // To meet CAN clock accuracy requirements an external crystal or ceramic
     // resonator must be used. The blue pill has a 8MHz external crystal.
     // Other boards might have a crystal with another frequency or none at all.
-    let _rcc = dp.RCC.freeze(CFGR::hse(8.MHz()));
+    let _rcc = dp.RCC.freeze(Config::hse(8.MHz()));
 
     let gpiob = dp.GPIOB.split();
     let mut can1 = {

diff --git a/examples/delay-syst-blinky.rs b/examples/delay-syst-blinky.rs
@@ -9,7 +9,7 @@
 use panic_halt as _; // panic handler
 
 use cortex_m_rt::entry;
-use stm32f4xx_hal::{self as hal, rcc::CFGR};
+use stm32f4xx_hal::{self as hal, rcc::Config};
 
 use crate::hal::{pac, prelude::*};
 
@@ -24,7 +24,7 @@ fn main() -> ! {
         let mut led = gpioa.pa5.into_push_pull_output();
 
         // Set up the system clock. We want to run at 48MHz for this one.
-        let rcc = dp.RCC.freeze(CFGR::hsi().sysclk(48.MHz()));
+        let rcc = dp.RCC.freeze(Config::hsi().sysclk(48.MHz()));
 
         // Create a delay abstraction based on SysTick
         let mut delay = cp.SYST.delay(&rcc.clocks);

diff --git a/examples/delay-timer-blinky.rs b/examples/delay-timer-blinky.rs
@@ -9,7 +9,7 @@
 use panic_halt as _; // panic handler
 
 use cortex_m_rt::entry;
-use stm32f4xx_hal::{self as hal, rcc::CFGR};
+use stm32f4xx_hal::{self as hal, rcc::Config};
 
 use crate::hal::{pac, prelude::*};
 
@@ -24,7 +24,7 @@ fn main() -> ! {
         let mut led = gpioc.pc13.into_push_pull_output();
 
         // Set up the system clock. We want to run at 48MHz for this one.
-        let rcc = dp.RCC.freeze(CFGR::hse(25.MHz()).sysclk(48.MHz()));
+        let rcc = dp.RCC.freeze(Config::hse(25.MHz()).sysclk(48.MHz()));
 
         // Create a delay abstraction based on general-pupose 32-bit timer TIM5
         let mut delay = dp.TIM5.delay_us(&rcc.clocks);

diff --git a/examples/display-touch.rs b/examples/display-touch.rs
@@ -22,7 +22,7 @@ use stm32f4xx_hal::{
     gpio::Speed,
     pac,
     prelude::*,
-    rcc::CFGR,
+    rcc::Config,
 };
 
 use embedded_graphics_07::{
@@ -53,7 +53,7 @@ fn main() -> ! {
     let p = pac::Peripherals::take().unwrap();
     let cp = cortex_m::Peripherals::take().unwrap();
 
-    let rcc = p.RCC.freeze(CFGR::hsi().sysclk(100.MHz()));
+    let rcc = p.RCC.freeze(Config::hsi().sysclk(100.MHz()));
     let mut delay = cp.SYST.delay(&rcc.clocks);
 
     let gpiob = p.GPIOB.split();

diff --git a/examples/dwt-blinky.rs b/examples/dwt-blinky.rs
@@ -11,7 +11,7 @@ use crate::hal::{
 };
 use cortex_m_rt::entry;
 use panic_halt as _;
-use stm32f4xx_hal::{self as hal, rcc::CFGR};
+use stm32f4xx_hal::{self as hal, rcc::Config};
 
 #[entry]
 fn main() -> ! {
@@ -25,7 +25,7 @@ fn main() -> ! {
         let mut led2 = gpiog.pg14.into_push_pull_output();
 
         // Set up the system clock. We want to run at 48MHz for this one.
-        let rcc = dp.RCC.freeze(CFGR::hsi().sysclk(48.MHz()));
+        let rcc = dp.RCC.freeze(Config::hsi().sysclk(48.MHz()));
 
         // Create a delay abstraction based on DWT cycle counter
         let dwt = cp.DWT.constrain(cp.DCB, &rcc.clocks);

diff --git a/examples/f413disco-lcd-ferris.rs b/examples/f413disco-lcd-ferris.rs
@@ -13,7 +13,7 @@
 use panic_halt as _;
 use rtt_target::{self, rtt_init_print, ChannelMode};
 
-use stm32f4xx_hal::{self as hal, rcc::CFGR};
+use stm32f4xx_hal::{self as hal, rcc::Config};
 
 use crate::hal::{
     fsmc_lcd::{DataPins16, FsmcLcd, LcdPins, Timing},
@@ -705,7 +705,7 @@ fn main() -> ! {
         let gpiog = p.GPIOG.split();
 
         // Configure and lock the clocks at maximum warp
-        let rcc = p.RCC.freeze(CFGR::hsi().sysclk(100.MHz()));
+        let rcc = p.RCC.freeze(Config::hsi().sysclk(100.MHz()));
 
         // Define the pins we need for our 16bit parallel bus
         use stm32f4xx_hal::gpio::alt::fsmc as alt;

diff --git a/examples/f469disco-lcd-test.rs b/examples/f469disco-lcd-test.rs
@@ -14,7 +14,7 @@ use cortex_m_rt::entry;
 use defmt_rtt as _;
 use panic_probe as _;
 
-use stm32f4xx_hal::{self as hal, rcc::CFGR};
+use stm32f4xx_hal::{self as hal, rcc::Config};
 
 use crate::hal::{
     dsi::{
@@ -55,7 +55,7 @@ fn main() -> ! {
     let hse_freq = 8.MHz();
     let rcc = dp
         .RCC
-        .freeze(CFGR::hse(hse_freq).pclk2(32.MHz()).sysclk(180.MHz()));
+        .freeze(Config::hse(hse_freq).pclk2(32.MHz()).sysclk(180.MHz()));
     let mut delay = cp.SYST.delay(&rcc.clocks);
 
     let gpioh = dp.GPIOH.split();

diff --git a/examples/fmc-sdram.rs b/examples/fmc-sdram.rs
@@ -7,7 +7,7 @@
 use panic_probe as _;
 
 use core::{mem, slice};
-use stm32f4xx_hal::{fmc::FmcExt, gpio::alt::fmc as alt, pac, prelude::*, rcc::CFGR};
+use stm32f4xx_hal::{fmc::FmcExt, gpio::alt::fmc as alt, pac, prelude::*, rcc::Config};
 
 use cortex_m::peripheral::Peripherals;
 
@@ -49,7 +49,7 @@ impl XorShift32 {
 #[entry]
 fn main() -> ! {
     if let (Some(p), Some(cp)) = (pac::Peripherals::take(), Peripherals::take()) {
-        let rcc = p.RCC.freeze(CFGR::hsi().sysclk(180.MHz()));
+        let rcc = p.RCC.freeze(Config::hsi().sysclk(180.MHz()));
 
         let mut delay = cp.SYST.delay(&rcc.clocks);
 

diff --git a/examples/i2s-audio-out.rs b/examples/i2s-audio-out.rs
@@ -56,7 +56,7 @@ use stm32f4xx_hal::i2s::I2s;
 use stm32f4xx_hal::nb::block;
 use stm32f4xx_hal::pac::Peripherals;
 use stm32f4xx_hal::prelude::*;
-use stm32f4xx_hal::rcc::CFGR;
+use stm32f4xx_hal::rcc::Config;
 
 const SAMPLE_RATE: u32 = 48_000;
 
@@ -97,9 +97,11 @@ fn main() -> ! {
 
     // The 61440 kHz frequency can be divided to get exactly 48 kHz sample rate even when
     // generating master clock
-    let rcc = dp
-        .RCC
-        .freeze(CFGR::hse(8u32.MHz()).sysclk(96.MHz()).i2s_clk(61440.kHz()));
+    let rcc = dp.RCC.freeze(
+        Config::hse(8u32.MHz())
+            .sysclk(96.MHz())
+            .i2s_clk(61440.kHz()),
+    );
 
     let i2s_pins = (gpioa.pa4, gpioc.pc10, NoPin::new(), gpioc.pc12);
     let i2s = I2s::new(dp.SPI3, i2s_pins, &rcc.clocks);

diff --git a/examples/ltdc-screen/main.rs b/examples/ltdc-screen/main.rs
@@ -17,7 +17,7 @@ use stm32f4xx_hal::{
     ltdc::{BluePins, GreenPins, Layer, LtdcPins, PixelFormat, RedPins},
     pac,
     prelude::*,
-    rcc::{Rcc, CFGR},
+    rcc::{Config, Rcc},
 };
 
 mod screen;
@@ -68,7 +68,7 @@ fn main() -> ! {
     // HSE osc out in High Z
     gpioh.ph1.into_floating_input();
     let _rcc_hal = rcc_hal.freeze(
-        CFGR::hse(25.MHz())
+        Config::hse(25.MHz())
             .bypass_hse_oscillator()
             .sysclk(216.MHz())
             .hclk(216.MHz()),

diff --git a/examples/pwm-dead-time.rs b/examples/pwm-dead-time.rs
@@ -7,15 +7,15 @@
 use panic_halt as _; // panic handler
 
 use cortex_m_rt::entry;
-use stm32f4xx_hal::{self as hal, rcc::CFGR};
+use stm32f4xx_hal::{self as hal, rcc::Config};
 
 use hal::{pac, prelude::*, timer::Polarity};
 
 #[entry]
 fn main() -> ! {
     if let Some(dp) = pac::Peripherals::take() {
         // Set up the system clock. We want to run at 84MHz for this one.
-        let rcc = dp.RCC.freeze(CFGR::hsi().sysclk(25.MHz()));
+        let rcc = dp.RCC.freeze(Config::hsi().sysclk(25.MHz()));
 
         let gpioa = dp.GPIOA.split();
 

diff --git a/examples/pwm-sinus.rs b/examples/pwm-sinus.rs
@@ -8,13 +8,13 @@ use panic_halt as _;
 use core::f32::consts::FRAC_PI_2;
 use cortex_m_rt::entry;
 use micromath::F32Ext;
-use stm32f4xx_hal::{pac, prelude::*, rcc::CFGR};
+use stm32f4xx_hal::{pac, prelude::*, rcc::Config};
 
 #[entry]
 fn main() -> ! {
     if let Some(dp) = pac::Peripherals::take() {
         // Set up the system clock.
-        let rcc = dp.RCC.freeze(CFGR::hse(25.MHz()));
+        let rcc = dp.RCC.freeze(Config::hse(25.MHz()));
 
         let gpioa = dp.GPIOA.split();
 

diff --git a/examples/rng-display.rs b/examples/rng-display.rs
@@ -15,7 +15,7 @@
 #![no_main]
 
 use stm32f4xx_hal as hal;
-use stm32f4xx_hal::rcc::CFGR;
+use stm32f4xx_hal::rcc::Config;
 
 #[cfg(not(debug_assertions))]
 use panic_halt as _;
@@ -59,7 +59,7 @@ fn main() -> ! {
         // here we pick a simple clock configuration that ensures the pll48clk,
         // from which RNG_CLK is derived, is about 48 MHz
         // discovery board has 8 MHz crystal for HSE
-        let rcc = dp.RCC.freeze(CFGR::hse(8.MHz()).sysclk(128.MHz()));
+        let rcc = dp.RCC.freeze(Config::hse(8.MHz()).sysclk(128.MHz()));
 
         let mut delay_source = cp.SYST.delay(&rcc.clocks);
 

diff --git a/examples/rtc_alarm.rs b/examples/rtc_alarm.rs
@@ -31,7 +31,7 @@ fn main() -> ! {
 
     let mut p = hal::pac::Peripherals::take().unwrap();
 
-    let rcc = p.RCC.constrain();
+    let _rcc = p.RCC.constrain();
     let mut rtc = Rtc::new(p.RTC, &mut p.PWR);
 
     let today = date!(2023 - 05 - 28);

diff --git a/examples/rtic-adc-dma.rs b/examples/rtic-adc-dma.rs
@@ -16,7 +16,7 @@ mod app {
         dma::{config::DmaConfig, PeripheralToMemory, Stream0, StreamsTuple, Transfer},
         pac::{self, ADC1, DMA2},
         prelude::*,
-        rcc::CFGR,
+        rcc::Config,
         signature::{VtempCal110, VtempCal30},
     };
 
@@ -43,7 +43,7 @@ mod app {
         let device: pac::Peripherals = cx.device;
 
         let _rcc = device.RCC.freeze(
-            CFGR::hse(25.MHz())
+            Config::hse(25.MHz())
                 .require_pll48clk()
                 .sysclk(MONO_HZ.Hz())
                 .hclk(MONO_HZ.Hz())

diff --git a/examples/rtic-button.rs b/examples/rtic-button.rs
@@ -10,7 +10,7 @@ mod app {
     use stm32f4xx_hal::{
         gpio::{gpioa::PA0, gpioc::PC13, Edge, Input, Output, PinState, Pull},
         prelude::*,
-        rcc::CFGR,
+        rcc::Config,
     };
     const SYSFREQ: u32 = 100_000_000;
     // Shared resources go here
@@ -32,7 +32,7 @@ mod app {
         let _rcc = ctx
             .device
             .RCC
-            .freeze(CFGR::hse(25.MHz()).sysclk(SYSFREQ.Hz()));
+            .freeze(Config::hse(25.MHz()).sysclk(SYSFREQ.Hz()));
         // gpio ports A and C
         let gpioa = ctx.device.GPIOA.split();
         let gpioc = ctx.device.GPIOC.split();

diff --git a/examples/rtic-dual-i2s-audio-in-out.rs b/examples/rtic-dual-i2s-audio-in-out.rs
@@ -102,7 +102,7 @@ mod app {
         RightLsb,
     }
 
-    use stm32f4xx_hal::rcc::CFGR;
+    use stm32f4xx_hal::rcc::Config;
     use FrameState::{LeftLsb, LeftMsb, RightLsb, RightMsb};
 
     impl Default for FrameState {
@@ -154,7 +154,7 @@ mod app {
         let gpiob = device.GPIOB.split();
         let gpioc = device.GPIOC.split();
         let rcc = device.RCC.freeze(
-            CFGR::hse(8u32.MHz())
+            Config::hse(8u32.MHz())
                 .sysclk(96.MHz())
                 .hclk(96.MHz())
                 .pclk1(50.MHz())

diff --git a/examples/rtic-i2s-audio-in-out.rs b/examples/rtic-i2s-audio-in-out.rs
@@ -103,7 +103,7 @@ mod app {
         RightLsb,
     }
 
-    use stm32f4xx_hal::rcc::CFGR;
+    use stm32f4xx_hal::rcc::Config;
     use FrameState::{LeftLsb, LeftMsb, RightLsb, RightMsb};
 
     impl Default for FrameState {
@@ -158,7 +158,7 @@ mod app {
         let gpiob = device.GPIOB.split();
         let gpioc = device.GPIOC.split();
         let rcc = device.RCC.freeze(
-            CFGR::hse(8u32.MHz())
+            Config::hse(8u32.MHz())
                 .sysclk(96.MHz())
                 .hclk(96.MHz())
                 .pclk1(50.MHz())

diff --git a/examples/rtic-spi-slave-dma.rs b/examples/rtic-spi-slave-dma.rs
@@ -21,7 +21,7 @@ mod app {
     use panic_semihosting as _;
     use systick_monotonic::*;
 
-    use stm32f4xx_hal::{self as hal, rcc::CFGR};
+    use stm32f4xx_hal::{self as hal, rcc::Config};
 
     const ARRAY_SIZE: usize = 3;
 
@@ -56,7 +56,7 @@ mod app {
 
         let _rcc = device_peripherals
             .RCC
-            .freeze(CFGR::hsi().sysclk(100.MHz()).pclk1(36.MHz()));
+            .freeze(Config::hsi().sysclk(100.MHz()).pclk1(36.MHz()));
 
         let mono = Systick::new(core.SYST, 100_000_000);
 

diff --git a/examples/rtic-tick.rs b/examples/rtic-tick.rs
@@ -11,7 +11,7 @@ mod app {
         gpio::{Output, PC13},
         pac,
         prelude::*,
-        rcc::CFGR,
+        rcc::Config,
         timer::MonoTimer64Us, // Extended 64-bit timer for 16/32-bit TIMs
     };
 
@@ -30,7 +30,7 @@ mod app {
 
     #[init]
     fn init(ctx: init::Context) -> (Shared, Local, init::Monotonics) {
-        let rcc = ctx.device.RCC.freeze(CFGR::DEFAULT.sysclk(48.MHz()));
+        let rcc = ctx.device.RCC.freeze(Config::DEFAULT.sysclk(48.MHz()));
 
         let gpioc = ctx.device.GPIOC.split();
         let led = gpioc.pc13.into_push_pull_output();