Content-Length: 252576 | pFad | http://github.com/stm32-rs/stm32f4xx-hal/pull/836.patch

thub.com From b80bc639f86b088ea75e75d1a4b933d3c284e625 Mon Sep 17 00:00:00 2001 From: Andrey Zgarbul Date: Sun, 25 May 2025 07:59:17 +0300 Subject: [PATCH 1/5] use &mut RCC --- CHANGELOG.md | 1 + src/adc.rs | 5 +- src/fmpi2c.rs | 4 +- src/rcc/f4/enable.rs | 19 ++-- src/rcc/f4/mod.rs | 232 +++------------------------------------ src/rcc/mod.rs | 193 ++++++++++++++++++++++++++++++++ src/rtc.rs | 22 ++-- src/serial/uart_impls.rs | 3 +- 8 files changed, 237 insertions(+), 242 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 19b4db71..833043c0 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -10,6 +10,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/). - Implement `embedded_hal::i2c::I2c` for `I2cMasterDma` [#838] - Back to `stm32f4` - Implement `Ptr`, `Sealed`, `Steal` for generic `Periph` [#834] + - Use `&mut RCC` for `PER::enable/reset` - Unmacro `Adc` [#832] - Use `write` instead of `modify` to clear flags [#829] - Bump `stm32f4-staging` to 0.18, update other dependencies [#831] diff --git a/src/adc.rs b/src/adc.rs index 25785fa9..94e72074 100644 --- a/src/adc.rs +++ b/src/adc.rs @@ -532,16 +532,15 @@ impl Adc { //Set the sample time for the channel let st = sample_time as u8; - let ch = channel as u8; match channel { 0..=9 => self .adc_reg .smpr2() - .modify(|_, w| unsafe { w.smp(ch).bits(st) }), + .modify(|_, w| unsafe { w.smp(channel).bits(st) }), 10..=18 => self .adc_reg .smpr1() - .modify(|_, w| unsafe { w.smp(ch - 10).bits(st) }), + .modify(|_, w| unsafe { w.smp(channel - 10).bits(st) }), _ => unimplemented!(), }; } diff --git a/src/fmpi2c.rs b/src/fmpi2c.rs index d455498c..f952a43f 100644 --- a/src/fmpi2c.rs +++ b/src/fmpi2c.rs @@ -198,7 +198,7 @@ fn calculate_timing( let mut presc: u8; // if ratio is > (scll+sclh)*presc. that frequancy is not possible to generate. so // minimum frequancy possible is generated - if product > 8192 as f32 { + if product > 8192_f32 { // TODO: should we panic or use minimum allowed frequancy scl_l = 0x7fu8; scl_h = 0x7fu8; @@ -214,7 +214,7 @@ fn calculate_timing( let deviation = product % tmp_presc as f32; if min_deviation > deviation { min_deviation = deviation; - presc = tmp_presc as u8; + presc = tmp_presc; } } // now that we have optimal prescalar value. optimal scl_l and scl_h diff --git a/src/rcc/f4/enable.rs b/src/rcc/f4/enable.rs index 433f3cc8..80251083 100644 --- a/src/rcc/f4/enable.rs +++ b/src/rcc/f4/enable.rs @@ -5,7 +5,7 @@ macro_rules! bus_enable { ($PER:ident => $bit:literal) => { impl Enable for crate::pac::$PER { #[inline(always)] - fn enable(rcc: &RccRB) { + fn enable(rcc: &mut RCC) { unsafe { bb::set(Self::Bus::enr(rcc), $bit); } @@ -13,14 +13,14 @@ macro_rules! bus_enable { cortex_m::asm::dsb(); } #[inline(always)] - fn disable(rcc: &RccRB) { + fn disable(rcc: &mut RCC) { unsafe { bb::clear(Self::Bus::enr(rcc), $bit); } } #[inline(always)] fn is_enabled() -> bool { - let rcc = pac::RCC::ptr(); + let rcc = RCC::ptr(); (Self::Bus::enr(unsafe { &*rcc }).read().bits() >> $bit) & 0x1 != 0 } } @@ -30,7 +30,7 @@ macro_rules! bus_lpenable { ($PER:ident => $bit:literal) => { impl LPEnable for crate::pac::$PER { #[inline(always)] - fn enable_in_low_power(rcc: &RccRB) { + fn enable_in_low_power(rcc: &mut RCC) { unsafe { bb::set(Self::Bus::lpenr(rcc), $bit); } @@ -38,14 +38,14 @@ macro_rules! bus_lpenable { cortex_m::asm::dsb(); } #[inline(always)] - fn disable_in_low_power(rcc: &RccRB) { + fn disable_in_low_power(rcc: &mut RCC) { unsafe { bb::clear(Self::Bus::lpenr(rcc), $bit); } } #[inline(always)] fn is_enabled_in_low_power() -> bool { - let rcc = pac::RCC::ptr(); + let rcc = RCC::ptr(); (Self::Bus::lpenr(unsafe { &*rcc }).read().bits() >> $bit) & 0x1 != 0 } } @@ -55,10 +55,11 @@ macro_rules! bus_reset { ($PER:ident => $bit:literal) => { impl Reset for crate::pac::$PER { #[inline(always)] - fn reset(rcc: &RccRB) { + fn reset(rcc: &mut RCC) { + let rstr = Self::Bus::rstr(rcc); unsafe { - bb::set(Self::Bus::rstr(rcc), $bit); - bb::clear(Self::Bus::rstr(rcc), $bit); + bb::set(rstr, $bit); + bb::clear(rstr, $bit); } } } diff --git a/src/rcc/f4/mod.rs b/src/rcc/f4/mod.rs index bde4bfb0..559d3fd7 100644 --- a/src/rcc/f4/mod.rs +++ b/src/rcc/f4/mod.rs @@ -1,7 +1,7 @@ use crate::pac::rcc::cfgr::{HPRE, SW}; -use crate::pac::{self, rcc, RCC}; +use crate::pac::RCC; -use super::{BusClock, BusTimerClock, RccBus}; +use super::*; use fugit::HertzU32 as Hertz; use fugit::RateExtU32; @@ -9,204 +9,11 @@ use fugit::RateExtU32; mod pll; mod enable; -use crate::pac::rcc::RegisterBlock as RccRB; - -//github.com/ Enable/disable peripheral -#[allow(clippy::missing_safety_doc)] -pub trait Enable: RccBus { - //github.com/ Enables peripheral - fn enable(rcc: &RccRB); - - //github.com/ Disables peripheral - fn disable(rcc: &RccRB); - - //github.com/ Check if peripheral enabled - fn is_enabled() -> bool; - - //github.com/ Check if peripheral disabled - #[inline] - fn is_disabled() -> bool { - !Self::is_enabled() - } - - //github.com/ # Safety - //github.com/ - //github.com/ Enables peripheral. Takes access to RCC internally - unsafe fn enable_unchecked() { - let rcc = &*pac::RCC::ptr(); - Self::enable(rcc); - } - - //github.com/ # Safety - //github.com/ - //github.com/ Disables peripheral. Takes access to RCC internally - unsafe fn disable_unchecked() { - let rcc = pac::RCC::ptr(); - Self::disable(&*rcc); - } -} - -//github.com/ Low power enable/disable peripheral -#[allow(clippy::missing_safety_doc)] -pub trait LPEnable: RccBus { - //github.com/ Enables peripheral in low power mode - fn enable_in_low_power(rcc: &RccRB); - - //github.com/ Disables peripheral in low power mode - fn disable_in_low_power(rcc: &RccRB); - - //github.com/ Check if peripheral enabled in low power mode - fn is_enabled_in_low_power() -> bool; - - //github.com/ Check if peripheral disabled in low power mode - #[inline] - fn is_disabled_in_low_power() -> bool { - !Self::is_enabled_in_low_power() - } - - //github.com/ # Safety - //github.com/ - //github.com/ Enables peripheral in low power mode. Takes access to RCC internally - unsafe fn enable_in_low_power_unchecked() { - let rcc = pac::RCC::ptr(); - Self::enable_in_low_power(&*rcc); - } - - //github.com/ # Safety - //github.com/ - //github.com/ Disables peripheral in low power mode. Takes access to RCC internally - unsafe fn disable_in_low_power_unchecked() { - let rcc = pac::RCC::ptr(); - Self::disable_in_low_power(&*rcc); - } -} - -//github.com/ Reset peripheral -#[allow(clippy::missing_safety_doc)] -pub trait Reset: RccBus { - //github.com/ Resets peripheral - fn reset(rcc: &RccRB); - - //github.com/ # Safety - //github.com/ - //github.com/ Resets peripheral. Takes access to RCC internally - unsafe fn reset_unchecked() { - let rcc = pac::RCC::ptr(); - Self::reset(&*rcc); - } -} - -//github.com/ Extension trait that constrains the `RCC` peripheral -pub trait RccExt { - //github.com/ Constrains the `RCC` peripheral so it plays nicely with the other abstractions - fn constrain(self) -> Rcc; -} - -macro_rules! bus_struct { - ($( $(#[$attr:meta])* $busX:ident => ($EN:ident, $en:ident, $LPEN:ident, $lpen:ident, $RST:ident, $rst:ident, $doc:literal),)+) => { - $( - $(#[$attr])* - #[doc = $doc] - #[non_exhaustive] - pub struct $busX; - - $(#[$attr])* - impl $busX { - pub(crate) fn enr(rcc: &RccRB) -> &rcc::$EN { - rcc.$en() - } - - pub(crate) fn lpenr(rcc: &RccRB) -> &rcc::$LPEN { - rcc.$lpen() - } - - pub(crate) fn rstr(rcc: &RccRB) -> &rcc::$RST { - rcc.$rst() - } - } - )+ - }; -} - -bus_struct! { - APB1 => (APB1ENR, apb1enr, APB1LPENR, apb1lpenr, APB1RSTR, apb1rstr, "Advanced Peripheral Bus 1 (APB1) registers"), - APB2 => (APB2ENR, apb2enr, APB2LPENR, apb2lpenr, APB2RSTR, apb2rstr, "Advanced Peripheral Bus 2 (APB2) registers"), - AHB1 => (AHB1ENR, ahb1enr, AHB1LPENR, ahb1lpenr, AHB1RSTR, ahb1rstr, "Advanced High-performance Bus 1 (AHB1) registers"), - #[cfg(not(feature = "gpio-f410"))] - AHB2 => (AHB2ENR, ahb2enr, AHB2LPENR, ahb2lpenr, AHB2RSTR, ahb2rstr, "Advanced High-performance Bus 2 (AHB2) registers"), - //#[cfg(any(feature = "fsmc", feature = "fmc"))] - //AHB3 => (AHB3ENR, ahb3enr, AHB3LPENR, ahb3lpenr, AHB3RSTR, ahb3rstr, "Advanced High-performance Bus 3 (AHB3) registers"), -} - -//github.com/ AMBA High-performance Bus 3 (AHB3) registers -#[cfg(any(feature = "fsmc", feature = "fmc"))] -#[non_exhaustive] -pub struct AHB3; - -#[cfg(any(feature = "fsmc", feature = "fmc"))] -impl AHB3 { - #[inline(always)] - fn enr(rcc: &RccRB) -> &rcc::AHB3ENR { - rcc.ahb3enr() - } - #[cfg(feature = "fmc")] - #[inline(always)] - fn lpenr(rcc: &RccRB) -> &rcc::AHB3LPENR { - rcc.ahb3lpenr() - } - #[inline(always)] - fn rstr(rcc: &RccRB) -> &rcc::AHB3RSTR { - rcc.ahb3rstr() - } -} - -impl BusClock for AHB1 { - fn clock(clocks: &Clocks) -> Hertz { - clocks.hclk - } -} - -#[cfg(not(feature = "gpio-f410"))] -impl BusClock for AHB2 { - fn clock(clocks: &Clocks) -> Hertz { - clocks.hclk - } -} - -#[cfg(any(feature = "fsmc", feature = "fmc"))] -impl BusClock for AHB3 { - fn clock(clocks: &Clocks) -> Hertz { - clocks.hclk - } -} - -impl BusClock for APB1 { - fn clock(clocks: &Clocks) -> Hertz { - clocks.pclk1 - } -} - -impl BusClock for APB2 { - fn clock(clocks: &Clocks) -> Hertz { - clocks.pclk2 - } -} - -impl BusTimerClock for APB1 { - fn timer_clock(clocks: &Clocks) -> Hertz { - clocks.timclk1 - } -} - -impl BusTimerClock for APB2 { - fn timer_clock(clocks: &Clocks) -> Hertz { - clocks.timclk2 - } -} impl RccExt for RCC { fn constrain(self) -> Rcc { Rcc { + rb: self, cfgr: CFGR { hse: None, hse_bypass: false, @@ -233,11 +40,6 @@ impl RccExt for RCC { } } -//github.com/ Constrained RCC peripheral -pub struct Rcc { - pub cfgr: CFGR, -} - //github.com/ Built-in high speed clock frequency pub const HSI: u32 = 16_000_000; // Hz @@ -917,31 +719,31 @@ impl RealSaiClocks { #[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Copy, Clone, PartialEq, Eq, Debug)] pub struct Clocks { - hclk: Hertz, - pclk1: Hertz, - pclk2: Hertz, - timclk1: Hertz, - timclk2: Hertz, - sysclk: Hertz, - pll48clk: Option, + pub(super) hclk: Hertz, + pub(super) pclk1: Hertz, + pub(super) pclk2: Hertz, + pub(super) timclk1: Hertz, + pub(super) timclk2: Hertz, + pub(super) sysclk: Hertz, + pub(super) pll48clk: Option, #[cfg(not(feature = "rcc_i2s_apb"))] - i2s_clk: Option, + pub(super) i2s_clk: Option, #[cfg(feature = "rcc_i2s_apb")] - i2s_apb1_clk: Option, + pub(super) i2s_apb1_clk: Option, #[cfg(feature = "rcc_i2s_apb")] - i2s_apb2_clk: Option, + pub(super) i2s_apb2_clk: Option, #[cfg(feature = "sai")] #[cfg(not(feature = "sai2"))] - saia_clk: Option, + pub(super) saia_clk: Option, #[cfg(feature = "sai")] #[cfg(not(feature = "sai2"))] - saib_clk: Option, + pub(super) saib_clk: Option, #[cfg(feature = "sai2")] - sai1_clk: Option, + pub(super) sai1_clk: Option, #[cfg(feature = "sai2")] - sai2_clk: Option, + pub(super) sai2_clk: Option, } impl Clocks { diff --git a/src/rcc/mod.rs b/src/rcc/mod.rs index f843f521..f99c9bbd 100644 --- a/src/rcc/mod.rs +++ b/src/rcc/mod.rs @@ -42,8 +42,36 @@ mod f4; pub use f4::*; +use crate::pac::rcc::{self, RegisterBlock as RccRB}; +use crate::pac::RCC; +use core::ops::{Deref, DerefMut}; use fugit::HertzU32 as Hertz; +//github.com/ Constrained RCC peripheral +pub struct Rcc { + pub cfgr: CFGR, + pub(crate) rb: RCC, +} + +impl Deref for Rcc { + type Target = RCC; + fn deref(&self) -> &Self::Target { + &self.rb + } +} + +impl DerefMut for Rcc { + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.rb + } +} + +//github.com/ Extension trait that constrains the `RCC` peripheral +pub trait RccExt { + //github.com/ Constrains the `RCC` peripheral so it plays nicely with the other abstractions + fn constrain(self) -> Rcc; +} + //github.com/ Bus associated to peripheral pub trait RccBus: crate::Sealed { //github.com/ Bus type; @@ -81,3 +109,168 @@ where T::Bus::timer_clock(clocks) } } + +//github.com/ Enable/disable peripheral +pub trait Enable: RccBus { + //github.com/ Enables peripheral + fn enable(rcc: &mut RCC); + + //github.com/ Disables peripheral + fn disable(rcc: &mut RCC); + + //github.com/ Check if peripheral enabled + fn is_enabled() -> bool; + + //github.com/ Check if peripheral disabled + #[inline] + fn is_disabled() -> bool { + !Self::is_enabled() + } + + //github.com/ # Safety + //github.com/ + //github.com/ Enables peripheral. Takes access to RCC internally + unsafe fn enable_unchecked() { + let mut rcc = RCC::steal(); + Self::enable(&mut rcc); + } + + //github.com/ # Safety + //github.com/ + //github.com/ Disables peripheral. Takes access to RCC internally + unsafe fn disable_unchecked() { + let mut rcc = RCC::steal(); + Self::disable(&mut rcc); + } +} + +//github.com/ Low power enable/disable peripheral +pub trait LPEnable: RccBus { + //github.com/ Enables peripheral in low power mode + fn enable_in_low_power(rcc: &mut RCC); + + //github.com/ Disables peripheral in low power mode + fn disable_in_low_power(rcc: &mut RCC); + + //github.com/ Check if peripheral enabled in low power mode + fn is_enabled_in_low_power() -> bool; + + //github.com/ Check if peripheral disabled in low power mode + #[inline] + fn is_disabled_in_low_power() -> bool { + !Self::is_enabled_in_low_power() + } + + //github.com/ # Safety + //github.com/ + //github.com/ Enables peripheral in low power mode. Takes access to RCC internally + unsafe fn enable_in_low_power_unchecked() { + let mut rcc = RCC::steal(); + Self::enable_in_low_power(&mut rcc); + } + + //github.com/ # Safety + //github.com/ + //github.com/ Disables peripheral in low power mode. Takes access to RCC internally + unsafe fn disable_in_low_power_unchecked() { + let mut rcc = RCC::steal(); + Self::disable_in_low_power(&mut rcc); + } +} + +//github.com/ Reset peripheral +pub trait Reset: RccBus { + //github.com/ Resets peripheral + fn reset(rcc: &mut RCC); + + //github.com/ # Safety + //github.com/ + //github.com/ Resets peripheral. Takes access to RCC internally + unsafe fn reset_unchecked() { + let mut rcc = RCC::steal(); + Self::reset(&mut rcc); + } +} + +macro_rules! bus_struct { + ($($busX:ident => ($EN:ident, $en:ident, $LPEN:ident, $lpen:ident, $RST:ident, $rst:ident, $doc:literal),)+) => { + $( + #[doc = $doc] + #[non_exhaustive] + pub struct $busX; + + impl $busX { + pub(crate) fn enr(rcc: &RccRB) -> &rcc::$EN { + rcc.$en() + } + + pub(crate) fn lpenr(rcc: &RccRB) -> &rcc::$LPEN { + rcc.$lpen() + } + + pub(crate) fn rstr(rcc: &RccRB) -> &rcc::$RST { + rcc.$rst() + } + } + )+ + }; +} +use bus_struct; + +bus_struct! { + APB1 => (APB1ENR, apb1enr, APB1LPENR, apb1lpenr, APB1RSTR, apb1rstr, "Advanced Peripheral Bus 1 (APB1) registers"), + APB2 => (APB2ENR, apb2enr, APB2LPENR, apb2lpenr, APB2RSTR, apb2rstr, "Advanced Peripheral Bus 2 (APB2) registers"), + AHB1 => (AHB1ENR, ahb1enr, AHB1LPENR, ahb1lpenr, AHB1RSTR, ahb1rstr, "Advanced High-performance Bus 1 (AHB1) registers"), +} +#[cfg(not(feature = "gpio-f410"))] +bus_struct! { + AHB2 => (AHB2ENR, ahb2enr, AHB2LPENR, ahb2lpenr, AHB2RSTR, ahb2rstr, "Advanced High-performance Bus 2 (AHB2) registers"), +} +#[cfg(any(feature = "fsmc", feature = "fmc"))] +bus_struct! { + AHB3 => (AHB3ENR, ahb3enr, AHB3LPENR, ahb3lpenr, AHB3RSTR, ahb3rstr, "Advanced High-performance Bus 3 (AHB3) registers"), +} + +impl BusClock for AHB1 { + fn clock(clocks: &Clocks) -> Hertz { + clocks.hclk + } +} + +#[cfg(not(feature = "gpio-f410"))] +impl BusClock for AHB2 { + fn clock(clocks: &Clocks) -> Hertz { + clocks.hclk + } +} + +#[cfg(any(feature = "fsmc", feature = "fmc"))] +impl BusClock for AHB3 { + fn clock(clocks: &Clocks) -> Hertz { + clocks.hclk + } +} + +impl BusClock for APB1 { + fn clock(clocks: &Clocks) -> Hertz { + clocks.pclk1 + } +} + +impl BusClock for APB2 { + fn clock(clocks: &Clocks) -> Hertz { + clocks.pclk2 + } +} + +impl BusTimerClock for APB1 { + fn timer_clock(clocks: &Clocks) -> Hertz { + clocks.timclk1 + } +} + +impl BusTimerClock for APB2 { + fn timer_clock(clocks: &Clocks) -> Hertz { + clocks.timclk2 + } +} diff --git a/src/rtc.rs b/src/rtc.rs index dadb822c..bd00d7f1 100644 --- a/src/rtc.rs +++ b/src/rtc.rs @@ -4,7 +4,7 @@ use crate::bb; use crate::pac::rtc::{dr, tr}; -use crate::pac::{self, rcc::RegisterBlock, PWR, RCC, RTC}; +use crate::pac::{self, PWR, RCC, RTC}; use crate::rcc::Enable; use core::fmt; use fugit::RateExtU32; @@ -152,14 +152,14 @@ impl Rtc { // Enable write protect unsafe { - let rcc = &(*RCC::ptr()); + let mut rcc = RCC::steal(); // As per the sample code, unlock comes first. (Enable PWR and DBP) - result.unlock(rcc, pwr); + result.unlock(&mut rcc, pwr); match result.clock_source { ClockSource::Lse(mode) => { // If necessary, enable the LSE. if rcc.bdcr().read().lserdy().bit_is_clear() { - result.enable_lse(rcc, mode); + result.enable_lse(&mut rcc, mode); } // Set clock source to LSE. rcc.bdcr().modify(|_, w| w.rtcsel().lse()); @@ -167,13 +167,13 @@ impl Rtc { ClockSource::Lsi => { // If necessary, enable the LSE. if rcc.csr().read().lsirdy().bit_is_clear() { - result.enable_lsi(rcc); + result.enable_lsi(&mut rcc); } // Set clock source to LSI. rcc.bdcr().modify(|_, w| w.rtcsel().lsi()); } } - result.enable(rcc); + result.enable(&mut rcc); } result.modify(true, |regs| { @@ -191,7 +191,7 @@ impl Rtc { //github.com/ Enable the low frequency external oscillator. This is the only mode currently //github.com/ supported, to avoid exposing the `CR` and `CRS` registers. - fn enable_lse(&mut self, rcc: &RegisterBlock, mode: LSEClockMode) { + fn enable_lse(&mut self, rcc: &mut RCC, mode: LSEClockMode) { unsafe { // Force a reset of the backup domain. self.backup_reset(rcc); @@ -221,7 +221,7 @@ impl Rtc { Self::with_config(regs, pwr, ClockSource::Lsi, prediv_s, prediv_a) } - fn enable_lsi(&mut self, rcc: &RegisterBlock) { + fn enable_lsi(&mut self, rcc: &mut RCC) { // Force a reset of the backup domain. self.backup_reset(rcc); // Enable the LSI. @@ -229,7 +229,7 @@ impl Rtc { while rcc.csr().read().lsirdy().is_not_ready() {} } - fn unlock(&mut self, rcc: &RegisterBlock, pwr: &mut PWR) { + fn unlock(&mut self, rcc: &mut RCC, pwr: &mut PWR) { // Enable the backup interface // Set APB1 - Bit 28 (PWREN) PWR::enable(rcc); @@ -238,7 +238,7 @@ impl Rtc { pwr.cr().modify(|_, w| w.dbp().set_bit()); } - fn backup_reset(&mut self, rcc: &RegisterBlock) { + fn backup_reset(&mut self, rcc: &mut RCC) { unsafe { // Set BDCR - Bit 16 (BDRST) bb::set(rcc.bdcr(), 16); @@ -247,7 +247,7 @@ impl Rtc { } } - fn enable(&mut self, rcc: &RegisterBlock) { + fn enable(&mut self, rcc: &mut RCC) { // Start the actual RTC. // Set BDCR - Bit 15 (RTCEN) unsafe { diff --git a/src/serial/uart_impls.rs b/src/serial/uart_impls.rs index 34109cf9..e1eb6963 100644 --- a/src/serial/uart_impls.rs +++ b/src/serial/uart_impls.rs @@ -126,8 +126,7 @@ pub trait RegisterBlockImpl: UartRB { } #[inline(always)] fn clear_flags(&self, flags: BitFlags) { - self.sr() - .write(|w| unsafe { w.bits(0xffff & !flags.bits()) }); + self.sr().write(|w| unsafe { w.bits(!flags.bits()) }); } fn clear_idle_interrupt(&self) { let _ = self.sr().read(); From 78df5461e09edbdb082f30488bedcbc067b69d17 Mon Sep 17 00:00:00 2001 From: Andrey Zgarbul Date: Tue, 27 May 2025 06:12:54 +0300 Subject: [PATCH 2/5] make CFGR copy --- src/rcc/f4/mod.rs | 1 + 1 file changed, 1 insertion(+) diff --git a/src/rcc/f4/mod.rs b/src/rcc/f4/mod.rs index 559d3fd7..78350f80 100644 --- a/src/rcc/f4/mod.rs +++ b/src/rcc/f4/mod.rs @@ -104,6 +104,7 @@ pub const PCLK2_MAX: u32 = SYSCLK_MAX / 2; //github.com/ Maximum APB1 peripheral clock frequency pub const PCLK1_MAX: u32 = PCLK2_MAX / 2; +#[derive(Clone, Copy, Debug)] pub struct CFGR { hse: Option, hse_bypass: bool, From 0bd0c7e0ad8333bcd1be2c40aa9d982ac3945a16 Mon Sep 17 00:00:00 2001 From: Andrey Zgarbul Date: Thu, 29 May 2025 06:47:45 +0300 Subject: [PATCH 3/5] Rcc inspired by g0/g4xx-hal --- examples/analog-stopwatch-with-spi-ssd1306.rs | 29 ++-- examples/blinky-timer-irq.rs | 7 +- examples/can-send.rs | 5 +- examples/delay-syst-blinky.rs | 7 +- examples/delay-timer-blinky.rs | 7 +- examples/display-touch.rs | 10 +- examples/dwt-blinky.rs | 7 +- examples/dynamic-gpio.rs | 6 +- examples/f413disco-lcd-ferris.rs | 7 +- examples/f469disco-lcd-test.rs | 17 +-- examples/fmc-sdram.rs | 11 +- examples/hd44780.rs | 3 +- examples/i2c_scanner.rs | 3 +- examples/i2s-audio-out.rs | 13 +- examples/ist7920-bidi-normal-spi.rs | 8 +- examples/ltdc-screen/main.rs | 15 +- examples/pwm-dead-time.rs | 7 +- examples/pwm-input.rs | 5 +- examples/pwm-sinus.rs | 9 +- examples/pwm.rs | 3 +- examples/qei.rs | 3 +- examples/rng-display.rs | 16 +- examples/rtc.rs | 4 +- examples/rtc_alarm.rs | 1 - examples/rtic-adc-dma.rs | 19 ++- examples/rtic-button.rs | 7 +- examples/rtic-dual-i2s-audio-in-out.rs | 21 ++- examples/rtic-i2s-audio-in-out.rs | 23 ++- examples/rtic-serial-dma-rx-idle.rs | 5 +- examples/rtic-spi-slave-dma.rs | 8 +- examples/rtic-tick.rs | 9 +- examples/rtic-usart-shell-ssd1306.rs | 16 +- examples/rtic-usart-shell.rs | 9 +- examples/rtic-usb-cdc-echo.rs | 17 +-- examples/rtic2-tick.rs | 9 +- examples/sai-duplex.rs | 21 +-- examples/sd.rs | 21 ++- examples/serial-9bit.rs | 10 +- examples/serial-dma.rs | 3 +- examples/serial.rs | 12 +- examples/spi-dma.rs | 3 +- examples/spi_slave.rs | 3 +- examples/ssd1306-image.rs | 8 +- examples/st7789-lcd.rs | 6 +- ...with-ssd1306-and-interrupts-and-dma-i2c.rs | 28 ++-- .../stopwatch-with-ssd1306-and-interrupts.rs | 28 ++-- examples/timer-periph.rs | 7 +- examples/timer-syst.rs | 7 +- examples/uart-dma.rs | 3 +- examples/usb-serial-irq.rs | 9 +- examples/usb-serial-poll.rs | 14 +- examples/ws2812-spi.rs | 9 +- src/rcc/f4/mod.rs | 140 ++++++++++++------ src/rcc/mod.rs | 19 ++- 54 files changed, 351 insertions(+), 346 deletions(-) diff --git a/examples/analog-stopwatch-with-spi-ssd1306.rs b/examples/analog-stopwatch-with-spi-ssd1306.rs index 8c09e2c8..5bbafbef 100644 --- a/examples/analog-stopwatch-with-spi-ssd1306.rs +++ b/examples/analog-stopwatch-with-spi-ssd1306.rs @@ -8,13 +8,13 @@ #![no_main] use panic_semihosting as _; -use stm32f4xx_hal as hal; +use stm32f4xx_hal::{self as hal, rcc::CFGR}; use crate::hal::{ gpio::{Edge, Input, PA0}, interrupt, pac, prelude::*, - rcc::{Clocks, Rcc}, + rcc::Rcc, spi::{Mode, Phase, Polarity, Spi}, timer::{CounterUs, Event, FTimer, Flag, Timer}, }; @@ -84,9 +84,7 @@ fn main() -> ! { let cp = cortex_m::peripheral::Peripherals::take().unwrap(); dp.RCC.apb2enr().write(|w| w.syscfgen().enabled()); - let rcc = dp.RCC.constrain(); - - let clocks = setup_clocks(rcc); + let rcc = setup_clocks(dp.RCC); let mut syscfg = dp.SYSCFG.constrain(); @@ -117,7 +115,7 @@ fn main() -> ! { phase: Phase::CaptureOnFirstTransition, }, 2000.kHz(), - &clocks, + &rcc.clocks, ); // Set up the LEDs. On the stm32f429i-disco they are connected to pin PG13 and PG14. @@ -127,7 +125,7 @@ fn main() -> ! { let dc = gpioe.pe3.into_push_pull_output(); let mut ss = gpioe.pe4.into_push_pull_output(); - let mut delay = Timer::syst(cp.SYST, &clocks).delay(); + let mut delay = Timer::syst(cp.SYST, &rcc.clocks).delay(); ss.set_high(); delay.delay_ms(100); @@ -142,7 +140,7 @@ fn main() -> ! { disp.flush().unwrap(); // Create a 1ms periodic interrupt from TIM2 - let mut timer = FTimer::new(dp.TIM2, &clocks).counter(); + let mut timer = FTimer::new(dp.TIM2, &rcc.clocks).counter(); timer.start(1.secs()).unwrap(); timer.listen(Event::Update); @@ -223,13 +221,14 @@ fn main() -> ! { } } -fn setup_clocks(rcc: Rcc) -> Clocks { - rcc.cfgr - .hclk(180.MHz()) - .sysclk(180.MHz()) - .pclk1(45.MHz()) - .pclk2(90.MHz()) - .freeze() +fn setup_clocks(rcc: pac::RCC) -> Rcc { + rcc.freeze( + CFGR::hsi() + .hclk(180.MHz()) + .sysclk(180.MHz()) + .pclk1(45.MHz()) + .pclk2(90.MHz()), + ) } #[interrupt] diff --git a/examples/blinky-timer-irq.rs b/examples/blinky-timer-irq.rs index dd4cc90f..89ba0b3e 100644 --- a/examples/blinky-timer-irq.rs +++ b/examples/blinky-timer-irq.rs @@ -8,7 +8,7 @@ use panic_halt as _; -use stm32f4xx_hal as hal; +use stm32f4xx_hal::{self as hal, rcc::CFGR}; use crate::hal::{ gpio::{self, Output, PushPull}, @@ -66,8 +66,7 @@ fn TIM2() { fn main() -> ! { let dp = Peripherals::take().unwrap(); - let rcc = dp.RCC.constrain(); - let clocks = rcc.cfgr.sysclk(16.MHz()).pclk1(8.MHz()).freeze(); + let rcc = dp.RCC.freeze(CFGR::hsi().sysclk(16.MHz()).pclk1(8.MHz())); // Configure PA5 pin to blink LED let gpioa = dp.GPIOA.split(); @@ -78,7 +77,7 @@ fn main() -> ! { cortex_m::interrupt::free(|cs| *G_LED.borrow(cs).borrow_mut() = Some(led)); // Set up a timer expiring after 1s - let mut timer = dp.TIM2.counter(&clocks); + let mut timer = dp.TIM2.counter(&rcc.clocks); timer.start(1.secs()).unwrap(); // Generate an interrupt when the timer expires diff --git a/examples/can-send.rs b/examples/can-send.rs index e91af23d..7c946219 100644 --- a/examples/can-send.rs +++ b/examples/can-send.rs @@ -10,18 +10,17 @@ use bxcan::filter::Mask32; use bxcan::{Fifo, Frame, StandardId}; use cortex_m_rt::entry; use nb::block; +use stm32f4xx_hal::rcc::CFGR; use stm32f4xx_hal::{pac, prelude::*}; #[entry] fn main() -> ! { let dp = pac::Peripherals::take().unwrap(); - let rcc = dp.RCC.constrain(); - // To meet CAN clock accuracy requirements an external crystal or ceramic // resonator must be used. The blue pill has a 8MHz external crystal. // Other boards might have a crystal with another frequency or none at all. - rcc.cfgr.use_hse(8.MHz()).freeze(); + let _rcc = dp.RCC.freeze(CFGR::hse(8.MHz())); let gpiob = dp.GPIOB.split(); let mut can1 = { diff --git a/examples/delay-syst-blinky.rs b/examples/delay-syst-blinky.rs index c3a05869..0c76d72e 100644 --- a/examples/delay-syst-blinky.rs +++ b/examples/delay-syst-blinky.rs @@ -9,7 +9,7 @@ use panic_halt as _; // panic handler use cortex_m_rt::entry; -use stm32f4xx_hal as hal; +use stm32f4xx_hal::{self as hal, rcc::CFGR}; use crate::hal::{pac, prelude::*}; @@ -24,11 +24,10 @@ fn main() -> ! { let mut led = gpioa.pa5.into_push_pull_output(); // Set up the system clock. We want to run at 48MHz for this one. - let rcc = dp.RCC.constrain(); - let clocks = rcc.cfgr.sysclk(48.MHz()).freeze(); + let rcc = dp.RCC.freeze(CFGR::hsi().sysclk(48.MHz())); // Create a delay abstraction based on SysTick - let mut delay = cp.SYST.delay(&clocks); + let mut delay = cp.SYST.delay(&rcc.clocks); loop { // On for 1s, off for 1s. diff --git a/examples/delay-timer-blinky.rs b/examples/delay-timer-blinky.rs index 6f0f73b8..3862aae6 100644 --- a/examples/delay-timer-blinky.rs +++ b/examples/delay-timer-blinky.rs @@ -9,7 +9,7 @@ use panic_halt as _; // panic handler use cortex_m_rt::entry; -use stm32f4xx_hal as hal; +use stm32f4xx_hal::{self as hal, rcc::CFGR}; use crate::hal::{pac, prelude::*}; @@ -24,11 +24,10 @@ fn main() -> ! { let mut led = gpioc.pc13.into_push_pull_output(); // Set up the system clock. We want to run at 48MHz for this one. - let rcc = dp.RCC.constrain(); - let clocks = rcc.cfgr.use_hse(25.MHz()).sysclk(48.MHz()).freeze(); + let rcc = dp.RCC.freeze(CFGR::hse(25.MHz()).sysclk(48.MHz())); // Create a delay abstraction based on general-pupose 32-bit timer TIM5 - let mut delay = dp.TIM5.delay_us(&clocks); + let mut delay = dp.TIM5.delay_us(&rcc.clocks); loop { // On for 1s, off for 3s. diff --git a/examples/display-touch.rs b/examples/display-touch.rs index 11857897..16752052 100644 --- a/examples/display-touch.rs +++ b/examples/display-touch.rs @@ -22,7 +22,7 @@ use stm32f4xx_hal::{ gpio::Speed, pac, prelude::*, - rcc::Rcc, + rcc::CFGR, }; use embedded_graphics_07::{ @@ -53,10 +53,8 @@ fn main() -> ! { let p = pac::Peripherals::take().unwrap(); let cp = cortex_m::Peripherals::take().unwrap(); - let rcc: Rcc = p.RCC.constrain(); - - let clocks = rcc.cfgr.sysclk(100.MHz()).freeze(); - let mut delay = cp.SYST.delay(&clocks); + let rcc = p.RCC.freeze(CFGR::hsi().sysclk(100.MHz())); + let mut delay = cp.SYST.delay(&rcc.clocks); let gpiob = p.GPIOB.split(); let gpioc = p.GPIOC.split(); @@ -148,7 +146,7 @@ fn main() -> ! { // STM32F412 uses I2c1 type for i2c bus. // The pins are mentioned in documentation -um2135-discovery-kit-with-stm32f412zg-mcu-stmicroelectronics #[cfg(feature = "stm32f412")] - let mut i2c = { I2c::new(p.I2C1, (gpiob.pb6, gpiob.pb7), 400.kHz(), &clocks) }; + let mut i2c = { I2c::new(p.I2C1, (gpiob.pb6, gpiob.pb7), 400.kHz(), &rcc.clocks) }; // STM32F413 uses FMPI2C1 type. // The pins are mentioned in documentation -um2135-discovery-kit-with-stm32f413zh-mcu-stmicroelectronics diff --git a/examples/dwt-blinky.rs b/examples/dwt-blinky.rs index fed1f18c..fa00b09f 100644 --- a/examples/dwt-blinky.rs +++ b/examples/dwt-blinky.rs @@ -11,7 +11,7 @@ use crate::hal::{ }; use cortex_m_rt::entry; use panic_halt as _; -use stm32f4xx_hal as hal; +use stm32f4xx_hal::{self as hal, rcc::CFGR}; #[entry] fn main() -> ! { @@ -25,11 +25,10 @@ fn main() -> ! { let mut led2 = gpiog.pg14.into_push_pull_output(); // Set up the system clock. We want to run at 48MHz for this one. - let rcc = dp.RCC.constrain(); - let clocks = rcc.cfgr.sysclk(48.MHz()).freeze(); + let rcc = dp.RCC.freeze(CFGR::hsi().sysclk(48.MHz())); // Create a delay abstraction based on DWT cycle counter - let dwt = cp.DWT.constrain(cp.DCB, &clocks); + let dwt = cp.DWT.constrain(cp.DCB, &rcc.clocks); let mut delay = dwt.delay(); // Create a stopwatch for maximum 9 laps diff --git a/examples/dynamic-gpio.rs b/examples/dynamic-gpio.rs index 96a4bdb3..ed42ebe1 100644 --- a/examples/dynamic-gpio.rs +++ b/examples/dynamic-gpio.rs @@ -18,18 +18,16 @@ fn main() -> ! { let dp = pac::Peripherals::take().unwrap(); // Take ownership over raw device and convert it into the corresponding HAL struct - let rcc = dp.RCC.constrain(); - // Freeze the configuration of all the clocks in the system and store the frozen frequencies in // `clocks` - let clocks = rcc.cfgr.freeze(); + let rcc = dp.RCC.constrain(); // Acquire the GPIOC peripheral let gpioc = dp.GPIOC.split(); let mut pin = gpioc.pc13.into_dynamic(); // Configure the syst timer to trigger an update every second - let mut timer = Timer::syst(cp.SYST, &clocks).counter_us(); + let mut timer = Timer::syst(cp.SYST, &rcc.clocks).counter_us(); timer.start(1.secs()).unwrap(); // Wait for the timer to trigger an update and change the state of the LED diff --git a/examples/f413disco-lcd-ferris.rs b/examples/f413disco-lcd-ferris.rs index ea4d3807..40a95368 100644 --- a/examples/f413disco-lcd-ferris.rs +++ b/examples/f413disco-lcd-ferris.rs @@ -13,7 +13,7 @@ use panic_halt as _; use rtt_target::{self, rtt_init_print, ChannelMode}; -use stm32f4xx_hal as hal; +use stm32f4xx_hal::{self as hal, rcc::CFGR}; use crate::hal::{ fsmc_lcd::{DataPins16, FsmcLcd, LcdPins, Timing}, @@ -705,8 +705,7 @@ fn main() -> ! { let gpiog = p.GPIOG.split(); // Configure and lock the clocks at maximum warp - let rcc = p.RCC.constrain(); - let clocks = rcc.cfgr.sysclk(100.MHz()).freeze(); + let rcc = p.RCC.freeze(CFGR::hsi().sysclk(100.MHz())); // Define the pins we need for our 16bit parallel bus use stm32f4xx_hal::gpio::alt::fsmc as alt; @@ -729,7 +728,7 @@ fn main() -> ! { let mut _te = gpiob.pb14.into_floating_input(); // Get delay provider - let mut delay = cp.SYST.delay(&clocks); + let mut delay = cp.SYST.delay(&rcc.clocks); // Set up timing let write_timing = Timing::default().data(3).address_setup(3).bus_turnaround(0); diff --git a/examples/f469disco-lcd-test.rs b/examples/f469disco-lcd-test.rs index 53f3d9f5..459a1d13 100644 --- a/examples/f469disco-lcd-test.rs +++ b/examples/f469disco-lcd-test.rs @@ -14,7 +14,7 @@ use cortex_m_rt::entry; use defmt_rtt as _; use panic_probe as _; -use stm32f4xx_hal as hal; +use stm32f4xx_hal::{self as hal, rcc::CFGR}; use crate::hal::{ dsi::{ @@ -52,16 +52,11 @@ fn main() -> ! { let dp = Peripherals::take().unwrap(); let cp = CorePeripherals::take().unwrap(); - let rcc = dp.RCC.constrain(); - let hse_freq = 8.MHz(); - let clocks = rcc - .cfgr - .use_hse(hse_freq) - .pclk2(32.MHz()) - .sysclk(180.MHz()) - .freeze(); - let mut delay = cp.SYST.delay(&clocks); + let rcc = dp + .RCC + .freeze(CFGR::hse(hse_freq).pclk2(32.MHz()).sysclk(180.MHz())); + let mut delay = cp.SYST.delay(&rcc.clocks); let gpioh = dp.GPIOH.split(); @@ -112,7 +107,7 @@ fn main() -> ! { DISPLAY_CONFIGURATION, dsi_config, dp.DSI, - &clocks, + &rcc.clocks, ) .unwrap(); diff --git a/examples/fmc-sdram.rs b/examples/fmc-sdram.rs index 58b9563e..922a50eb 100644 --- a/examples/fmc-sdram.rs +++ b/examples/fmc-sdram.rs @@ -7,7 +7,7 @@ use panic_probe as _; use core::{mem, slice}; -use stm32f4xx_hal::{fmc::FmcExt, gpio::alt::fmc as alt, pac, prelude::*}; +use stm32f4xx_hal::{fmc::FmcExt, gpio::alt::fmc as alt, pac, prelude::*, rcc::CFGR}; use cortex_m::peripheral::Peripherals; @@ -49,10 +49,9 @@ impl XorShift32 { #[entry] fn main() -> ! { if let (Some(p), Some(cp)) = (pac::Peripherals::take(), Peripherals::take()) { - let rcc = p.RCC.constrain(); + let rcc = p.RCC.freeze(CFGR::hsi().sysclk(180.MHz())); - let clocks = rcc.cfgr.sysclk(180.MHz()).freeze(); - let mut delay = cp.SYST.delay(&clocks); + let mut delay = cp.SYST.delay(&rcc.clocks); let gpioc = p.GPIOC.split(); let gpiod = p.GPIOD.split(); @@ -86,7 +85,9 @@ fn main() -> ! { rprintln!("Initializing SDRAM...\r"); - let mut sdram = p.FMC.sdram(pins, is42s32400f_6::Is42s32400f6 {}, &clocks); + let mut sdram = p + .FMC + .sdram(pins, is42s32400f_6::Is42s32400f6 {}, &rcc.clocks); let len_bytes = 16 * 1024 * 1024; let len_words = len_bytes / mem::size_of::(); let ram_ptr: *mut u32 = sdram.init(&mut delay); diff --git a/examples/hd44780.rs b/examples/hd44780.rs index 73c3ac2a..90005443 100644 --- a/examples/hd44780.rs +++ b/examples/hd44780.rs @@ -25,8 +25,7 @@ fn main() -> ! { let rcc = dp.RCC.constrain(); let gpiob = dp.GPIOB.split(); - let clocks = rcc.cfgr.freeze(); - let mut delay = dp.TIM1.delay_us(&clocks); + let mut delay = dp.TIM1.delay_us(&rcc.clocks); let rs = gpiob.pb7.into_push_pull_output(); let en = gpiob.pb8.into_push_pull_output(); diff --git a/examples/i2c_scanner.rs b/examples/i2c_scanner.rs index 7002796e..f423649c 100644 --- a/examples/i2c_scanner.rs +++ b/examples/i2c_scanner.rs @@ -20,7 +20,6 @@ fn main() -> ! { let dp = pac::Peripherals::take().unwrap(); let rcc = dp.RCC.constrain(); - let clocks = rcc.cfgr.freeze(); let gpiob = dp.GPIOB.split(); @@ -31,7 +30,7 @@ fn main() -> ! { dp.I2C1, (scl, sda), hal::i2c::Mode::standard(100.kHz()), - &clocks, + &rcc.clocks, ); rprintln!("Start i2c scanning..."); diff --git a/examples/i2s-audio-out.rs b/examples/i2s-audio-out.rs index 5eada776..9f80ec69 100644 --- a/examples/i2s-audio-out.rs +++ b/examples/i2s-audio-out.rs @@ -55,6 +55,7 @@ use stm32f4xx_hal::i2s::I2s; use stm32f4xx_hal::nb::block; use stm32f4xx_hal::pac::{Peripherals, SPI3}; use stm32f4xx_hal::prelude::*; +use stm32f4xx_hal::rcc::CFGR; const SAMPLE_RATE: u32 = 48_000; @@ -93,18 +94,14 @@ fn main() -> ! { let gpioa = dp.GPIOA.split(); let gpioc = dp.GPIOC.split(); - let rcc = dp.RCC.constrain(); // The 61440 kHz frequency can be divided to get exactly 48 kHz sample rate even when // generating master clock - let clocks = rcc - .cfgr - .use_hse(8u32.MHz()) - .sysclk(96.MHz()) - .i2s_clk(61440.kHz()) - .freeze(); + let rcc = dp + .RCC + .freeze(CFGR::hse(8u32.MHz()).sysclk(96.MHz()).i2s_clk(61440.kHz())); let i2s_pins = (gpioa.pa4, gpioc.pc10, SPI3::NoMck, gpioc.pc12); - let i2s = I2s::new(dp.SPI3, i2s_pins, &clocks); + let i2s = I2s::new(dp.SPI3, i2s_pins, &rcc.clocks); let i2s_config = I2sTransferConfig::new_master() .transmit() .standard(Philips) diff --git a/examples/ist7920-bidi-normal-spi.rs b/examples/ist7920-bidi-normal-spi.rs index b0fb740b..4bb902e4 100644 --- a/examples/ist7920-bidi-normal-spi.rs +++ b/examples/ist7920-bidi-normal-spi.rs @@ -23,8 +23,6 @@ fn main() -> ! { let gpiob = dp.GPIOB.split(); let rcc = dp.RCC.constrain(); - let clocks = rcc.cfgr.freeze(); - let mut led = gpioa.pa5.into_push_pull_output(); led.set_low(); @@ -35,7 +33,7 @@ fn main() -> ! { let mut res = gpiob.pb10.into_push_pull_output(); let cs = gpiob.pb13.into_push_pull_output(); - let mut delay = Timer::syst(cp.SYST, &clocks).delay(); + let mut delay = Timer::syst(cp.SYST, &rcc.clocks).delay(); let mode = Mode { polarity: Polarity::IdleLow, @@ -43,11 +41,11 @@ fn main() -> ! { }; // Change spi transfer mode to Bidi for more efficient operations. - // let spi = Spi::new(dp.SPI1, (sck, miso, mosi), mode, 8.MHz(), &clocks).to_bidi_transfer_mode(); + // let spi = Spi::new(dp.SPI1, (Some(sck), Some(miso), Some(mosi)), mode, 8.MHz(), &rcc.clocks).to_bidi_transfer_mode(); // or let spi = dp .SPI1 - .spi_bidi((Some(sck), Some(mosi)), mode, 8.MHz(), &clocks); + .spi_bidi((Some(sck), Some(mosi)), mode, 8.MHz(), &rcc.clocks); let iface = SPIInterface::new(spi, dc, cs); diff --git a/examples/ltdc-screen/main.rs b/examples/ltdc-screen/main.rs index 660dc08d..f417adc9 100644 --- a/examples/ltdc-screen/main.rs +++ b/examples/ltdc-screen/main.rs @@ -17,7 +17,7 @@ use stm32f4xx_hal::{ ltdc::{BluePins, GreenPins, Layer, LtdcPins, PixelFormat, RedPins}, pac, prelude::*, - rcc::Rcc, + rcc::{Rcc, CFGR}, }; mod screen; @@ -67,13 +67,12 @@ fn main() -> ! { // HSE osc out in High Z gpioh.ph1.into_floating_input(); - let _clocks = rcc_hal - .cfgr - .use_hse(25.MHz()) - .bypass_hse_oscillator() - .sysclk(216.MHz()) - .hclk(216.MHz()) - .freeze(); + let _rcc_hal = rcc_hal.freeze( + CFGR::hse(25.MHz()) + .bypass_hse_oscillator() + .sysclk(216.MHz()) + .hclk(216.MHz()), + ); // LCD enable: set it low first to avoid LCD bleed while setting up timings let mut disp_on = gpioi.pi12.into_push_pull_output(); diff --git a/examples/pwm-dead-time.rs b/examples/pwm-dead-time.rs index 071481ef..df7aa07c 100644 --- a/examples/pwm-dead-time.rs +++ b/examples/pwm-dead-time.rs @@ -7,7 +7,7 @@ use panic_halt as _; // panic handler use cortex_m_rt::entry; -use stm32f4xx_hal as hal; +use stm32f4xx_hal::{self as hal, rcc::CFGR}; use hal::{pac, prelude::*, timer::Polarity}; @@ -15,12 +15,11 @@ use hal::{pac, prelude::*, timer::Polarity}; fn main() -> ! { if let Some(dp) = pac::Peripherals::take() { // Set up the system clock. We want to run at 84MHz for this one. - let rcc = dp.RCC.constrain(); - let clocks = rcc.cfgr.sysclk(25.MHz()).freeze(); + let rcc = dp.RCC.freeze(CFGR::hsi().sysclk(25.MHz())); let gpioa = dp.GPIOA.split(); - let (mut pwm_mngr, (pwm_c1, ..)) = dp.TIM1.pwm_hz(20.kHz(), &clocks); + let (mut pwm_mngr, (pwm_c1, ..)) = dp.TIM1.pwm_hz(20.kHz(), &rcc.clocks); let mut pwm_c1 = pwm_c1.with(gpioa.pa8).with_complementary(gpioa.pa7); diff --git a/examples/pwm-input.rs b/examples/pwm-input.rs index e2189eac..e56a717b 100644 --- a/examples/pwm-input.rs +++ b/examples/pwm-input.rs @@ -13,13 +13,12 @@ fn main() -> ! { if let Some(dp) = pac::Peripherals::take() { // Set up the system clock. let rcc = dp.RCC.constrain(); - let clocks = rcc.cfgr.freeze(); let gpioa = dp.GPIOA.split(); let gpioc = dp.GPIOC.split(); // configure tim1 as a PWM output of known frequency. - let (_, (ch1, ch2, ..)) = Timer::new(dp.TIM1, &clocks).pwm_hz(501.Hz()); + let (_, (ch1, ch2, ..)) = Timer::new(dp.TIM1, &rcc.clocks).pwm_hz(501.Hz()); let mut ch1 = ch1.with(gpioa.pa8); let mut _ch2 = ch2.with(gpioa.pa9); let max_duty = ch1.get_max_duty(); @@ -30,7 +29,7 @@ fn main() -> ! { let pwm_reader_ch1 = gpioc.pc6; // configure tim8 as a PWM input, using the best-guess frequency of the input signal. - let monitor = Timer::new(dp.TIM8, &clocks).pwm_input(500.Hz(), pwm_reader_ch1); + let monitor = Timer::new(dp.TIM8, &rcc.clocks).pwm_input(500.Hz(), pwm_reader_ch1); // NOTE: this value may only be accurately observed at the CC2 interrupt. let _duty = monitor.get_duty_cycle(); diff --git a/examples/pwm-sinus.rs b/examples/pwm-sinus.rs index 3121d365..49e2fe4c 100644 --- a/examples/pwm-sinus.rs +++ b/examples/pwm-sinus.rs @@ -8,22 +8,21 @@ use panic_halt as _; use core::f32::consts::FRAC_PI_2; use cortex_m_rt::entry; use micromath::F32Ext; -use stm32f4xx_hal::{pac, prelude::*}; +use stm32f4xx_hal::{pac, prelude::*, rcc::CFGR}; #[entry] fn main() -> ! { if let Some(dp) = pac::Peripherals::take() { // Set up the system clock. - let rcc = dp.RCC.constrain(); - let clocks = rcc.cfgr.use_hse(25.MHz()).freeze(); + let rcc = dp.RCC.freeze(CFGR::hse(25.MHz())); let gpioa = dp.GPIOA.split(); - let (_, (pwm_c1, pwm_c2, ..)) = dp.TIM1.pwm_us(100.micros(), &clocks); + let (_, (pwm_c1, pwm_c2, ..)) = dp.TIM1.pwm_us(100.micros(), &rcc.clocks); let mut pwm_c1 = pwm_c1.with(gpioa.pa8); let mut pwm_c2 = pwm_c2.with(gpioa.pa9); - let mut counter = dp.TIM2.counter_us(&clocks); + let mut counter = dp.TIM2.counter_us(&rcc.clocks); let max_duty = pwm_c1.get_max_duty(); const N: usize = 50; diff --git a/examples/pwm.rs b/examples/pwm.rs index 76e17f17..39cc47c5 100644 --- a/examples/pwm.rs +++ b/examples/pwm.rs @@ -13,11 +13,10 @@ fn main() -> ! { if let Some(dp) = pac::Peripherals::take() { // Set up the system clock. let rcc = dp.RCC.constrain(); - let clocks = rcc.cfgr.freeze(); let gpioa = dp.GPIOA.split(); - let (_, (ch1, ch2, ..)) = dp.TIM1.pwm_us(100.micros(), &clocks); + let (_, (ch1, ch2, ..)) = dp.TIM1.pwm_us(100.micros(), &rcc.clocks); let mut ch1 = ch1.with(gpioa.pa8); let mut _ch2 = ch2.with(gpioa.pa9); diff --git a/examples/qei.rs b/examples/qei.rs index e3b25ce6..205ee177 100644 --- a/examples/qei.rs +++ b/examples/qei.rs @@ -28,10 +28,9 @@ fn main() -> ! { // Set up the system clock. let rcc = dp.RCC.constrain(); - let clocks = rcc.cfgr.freeze(); // Create a delay abstraction based on SysTick. - let mut delay = cp.SYST.delay(&clocks); + let mut delay = cp.SYST.delay(&rcc.clocks); let gpioa = dp.GPIOA.split(); diff --git a/examples/rng-display.rs b/examples/rng-display.rs index 943ddf57..6aae31bf 100644 --- a/examples/rng-display.rs +++ b/examples/rng-display.rs @@ -15,6 +15,7 @@ #![no_main] use stm32f4xx_hal as hal; +use stm32f4xx_hal::rcc::CFGR; #[cfg(not(debug_assertions))] use panic_halt as _; @@ -53,19 +54,14 @@ fn main() -> ! { cortex_m::peripheral::Peripherals::take(), ) { // Set up the system clock. - let rcc = dp.RCC.constrain(); - // Clock configuration is critical for RNG to work properly; otherwise // RNG_SR CECS bit will constantly report an error (if RNG_CLK < HCLK/16) // here we pick a simple clock configuration that ensures the pll48clk, // from which RNG_CLK is derived, is about 48 MHz - let clocks = rcc - .cfgr - .use_hse(8.MHz()) //discovery board has 8 MHz crystal for HSE - .sysclk(128.MHz()) - .freeze(); + // discovery board has 8 MHz crystal for HSE + let rcc = dp.RCC.freeze(CFGR::hse(8.MHz()).sysclk(128.MHz())); - let mut delay_source = cp.SYST.delay(&clocks); + let mut delay_source = cp.SYST.delay(&rcc.clocks); // Set up I2C1: SCL is PB8 and SDA is PB9; they are set to Alternate Function 4 // as per the STM32F407 datasheet. Pin assignment as per the @@ -73,7 +69,7 @@ fn main() -> ! { let gpiob = dp.GPIOB.split(); let scl = gpiob.pb8; let sda = gpiob.pb9; - let i2c = I2c::new(dp.I2C1, (scl, sda), 400.kHz(), &clocks); + let i2c = I2c::new(dp.I2C1, (scl, sda), 400.kHz(), &rcc.clocks); // Set up the display let interface = I2CDisplayInterface::new(i2c); @@ -83,7 +79,7 @@ fn main() -> ! { // enable the RNG peripheral and its clock // this will panic if the clock configuration is unsuitable - let mut rand_source = dp.RNG.constrain(&clocks); + let mut rand_source = dp.RNG.constrain(&rcc.clocks); let mut format_buf = String::<20>::new(); loop { //display clear diff --git a/examples/rtc.rs b/examples/rtc.rs index 0b07c4ce..71489d1a 100644 --- a/examples/rtc.rs +++ b/examples/rtc.rs @@ -21,10 +21,8 @@ fn main() -> ! { let mut p = pac::Peripherals::take().unwrap(); let rcc = p.RCC.constrain(); - let clocks = rcc.cfgr.freeze(); - let mut rtc = Rtc::new(p.RTC, &mut p.PWR); - let mut delay = p.TIM5.delay_us(&clocks); + let mut delay = p.TIM5.delay_us(&rcc.clocks); rtc.set_datetime(&PrimitiveDateTime::new( date!(2022 - 02 - 07), diff --git a/examples/rtc_alarm.rs b/examples/rtc_alarm.rs index c7dd4410..4248c404 100644 --- a/examples/rtc_alarm.rs +++ b/examples/rtc_alarm.rs @@ -32,7 +32,6 @@ fn main() -> ! { let mut p = hal::pac::Peripherals::take().unwrap(); let rcc = p.RCC.constrain(); - let _clocks = rcc.cfgr.freeze(); let mut rtc = Rtc::new(p.RTC, &mut p.PWR); let today = date!(2023 - 05 - 28); diff --git a/examples/rtic-adc-dma.rs b/examples/rtic-adc-dma.rs index d1e6f847..06f8ab2a 100644 --- a/examples/rtic-adc-dma.rs +++ b/examples/rtic-adc-dma.rs @@ -16,6 +16,7 @@ mod app { dma::{config::DmaConfig, PeripheralToMemory, Stream0, StreamsTuple, Transfer}, pac::{self, ADC1, DMA2}, prelude::*, + rcc::CFGR, signature::{VtempCal110, VtempCal30}, }; @@ -41,16 +42,14 @@ mod app { fn init(cx: init::Context) -> (Shared, Local, init::Monotonics) { let device: pac::Peripherals = cx.device; - let rcc = device.RCC.constrain(); - let _clocks = rcc - .cfgr - .use_hse(25.MHz()) - .require_pll48clk() - .sysclk(MONO_HZ.Hz()) - .hclk(MONO_HZ.Hz()) - .pclk1(42.MHz()) - .pclk2(84.MHz()) - .freeze(); + let _rcc = device.RCC.freeze( + CFGR::hse(25.MHz()) + .require_pll48clk() + .sysclk(MONO_HZ.Hz()) + .hclk(MONO_HZ.Hz()) + .pclk1(42.MHz()) + .pclk2(84.MHz()), + ); let mut dcb = cx.core.DCB; let dwt = cx.core.DWT; diff --git a/examples/rtic-button.rs b/examples/rtic-button.rs index eab3e89e..0bc668c7 100644 --- a/examples/rtic-button.rs +++ b/examples/rtic-button.rs @@ -10,6 +10,7 @@ mod app { use stm32f4xx_hal::{ gpio::{gpioa::PA0, gpioc::PC13, Edge, Input, Output, PinState, Pull}, prelude::*, + rcc::CFGR, }; const SYSFREQ: u32 = 100_000_000; // Shared resources go here @@ -28,8 +29,10 @@ mod app { // syscfg let mut syscfg = ctx.device.SYSCFG.constrain(); // clocks - let rcc = ctx.device.RCC.constrain(); - let _clocks = rcc.cfgr.sysclk(SYSFREQ.Hz()).use_hse(25.MHz()).freeze(); + let _rcc = ctx + .device + .RCC + .freeze(CFGR::hse(25.MHz()).sysclk(SYSFREQ.Hz())); // gpio ports A and C let gpioa = ctx.device.GPIOA.split(); let gpioc = ctx.device.GPIOC.split(); diff --git a/examples/rtic-dual-i2s-audio-in-out.rs b/examples/rtic-dual-i2s-audio-in-out.rs index de101d69..4dad3ac0 100644 --- a/examples/rtic-dual-i2s-audio-in-out.rs +++ b/examples/rtic-dual-i2s-audio-in-out.rs @@ -102,6 +102,7 @@ mod app { RightLsb, } + use stm32f4xx_hal::rcc::CFGR; use FrameState::{LeftLsb, LeftMsb, RightLsb, RightMsb}; impl Default for FrameState { @@ -152,16 +153,14 @@ mod app { let mut exti = device.EXTI; let gpiob = device.GPIOB.split(); let gpioc = device.GPIOC.split(); - let rcc = device.RCC.constrain(); - let clocks = rcc - .cfgr - .use_hse(8u32.MHz()) - .sysclk(96.MHz()) - .hclk(96.MHz()) - .pclk1(50.MHz()) - .pclk2(100.MHz()) - .i2s_clk(61440.kHz()) - .freeze(); + let rcc = device.RCC.freeze( + CFGR::hse(8u32.MHz()) + .sysclk(96.MHz()) + .hclk(96.MHz()) + .pclk1(50.MHz()) + .pclk2(100.MHz()) + .i2s_clk(61440.kHz()), + ); // I2S pins: (WS, CK, MCLK, SD) for I2S2 let i2s2_pins = ( @@ -171,7 +170,7 @@ mod app { gpiob.pb15, //SD gpiob.pb14, //ExtSD ); - let i2s2 = DualI2s::new(device.SPI2, device.I2S2EXT, i2s2_pins, &clocks); + let i2s2 = DualI2s::new(device.SPI2, device.I2S2EXT, i2s2_pins, &rcc.clocks); let i2s2_config = DualI2sDriverConfig::new_master() .direction(Receive, Transmit) .standard(Philips) diff --git a/examples/rtic-i2s-audio-in-out.rs b/examples/rtic-i2s-audio-in-out.rs index fd855aa6..648abd09 100644 --- a/examples/rtic-i2s-audio-in-out.rs +++ b/examples/rtic-i2s-audio-in-out.rs @@ -86,6 +86,7 @@ mod app { use hal::pac::Interrupt; use hal::pac::{EXTI, SPI2, SPI3}; use hal::prelude::*; + use hal::rcc::CFGR; use heapless::spsc::*; @@ -156,16 +157,14 @@ mod app { let gpioa = device.GPIOA.split(); let gpiob = device.GPIOB.split(); let gpioc = device.GPIOC.split(); - let rcc = device.RCC.constrain(); - let clocks = rcc - .cfgr - .use_hse(8u32.MHz()) - .sysclk(96.MHz()) - .hclk(96.MHz()) - .pclk1(50.MHz()) - .pclk2(100.MHz()) - .i2s_clk(61440.kHz()) - .freeze(); + let rcc = device.RCC.freeze( + CFGR::hse(8u32.MHz()) + .sysclk(96.MHz()) + .hclk(96.MHz()) + .pclk1(50.MHz()) + .pclk2(100.MHz()) + .i2s_clk(61440.kHz()), + ); // I2S pins: (WS, CK, MCLK, SD) for I2S2 let i2s2_pins = ( @@ -174,7 +173,7 @@ mod app { Some(gpioc.pc6), //MCK gpiob.pb15, //SD ); - let i2s2 = I2s::new(device.SPI2, i2s2_pins, &clocks); + let i2s2 = I2s::new(device.SPI2, i2s2_pins, &rcc.clocks); let i2s2_config = I2sDriverConfig::new_master() .receive() .standard(Philips) @@ -188,7 +187,7 @@ mod app { // I2S3 pins: (WS, CK, NoMck, SD) for I2S3 let i2s3_pins = (gpioa.pa4, gpioc.pc10, SPI3::NoMck, gpioc.pc12); - let i2s3 = I2s::new(device.SPI3, i2s3_pins, &clocks); + let i2s3 = I2s::new(device.SPI3, i2s3_pins, &rcc.clocks); let i2s3_config = i2s2_config.to_slave().transmit(); let mut i2s3_driver = I2sDriver::new(i2s3, i2s3_config); i2s3_driver.set_tx_interrupt(true); diff --git a/examples/rtic-serial-dma-rx-idle.rs b/examples/rtic-serial-dma-rx-idle.rs index ae51236e..04fd8fc2 100644 --- a/examples/rtic-serial-dma-rx-idle.rs +++ b/examples/rtic-serial-dma-rx-idle.rs @@ -57,9 +57,8 @@ mod app { let dp: hal::pac::Peripherals = cx.device; let rcc = dp.RCC.constrain(); - let clocks = rcc.cfgr.freeze(); - let mono = Systick::new(core.SYST, clocks.sysclk().to_Hz()); + let mono = Systick::new(core.SYST, rcc.clocks.sysclk().to_Hz()); let gpioa = dp.GPIOA.split(); @@ -72,7 +71,7 @@ mod app { serial::Config::default() .baudrate(9600.bps()) .dma(serial::config::DmaConfig::Rx), - &clocks, + &rcc.clocks, ) .unwrap(); diff --git a/examples/rtic-spi-slave-dma.rs b/examples/rtic-spi-slave-dma.rs index 914cc6c6..3c5d0c1a 100644 --- a/examples/rtic-spi-slave-dma.rs +++ b/examples/rtic-spi-slave-dma.rs @@ -21,7 +21,7 @@ mod app { use panic_semihosting as _; use systick_monotonic::*; - use stm32f4xx_hal as hal; + use stm32f4xx_hal::{self as hal, rcc::CFGR}; const ARRAY_SIZE: usize = 3; @@ -54,9 +54,9 @@ mod app { let device_peripherals: hal::pac::Peripherals = cx.device; - let rcc = device_peripherals.RCC; - let rcc = rcc.constrain(); - let _clocks = rcc.cfgr.sysclk(100.MHz()).pclk1(36.MHz()).freeze(); + let _rcc = device_peripherals + .RCC + .freeze(CFGR::hsi().sysclk(100.MHz()).pclk1(36.MHz())); let mono = Systick::new(core.SYST, 100_000_000); diff --git a/examples/rtic-tick.rs b/examples/rtic-tick.rs index b29ab427..bcc0ca99 100644 --- a/examples/rtic-tick.rs +++ b/examples/rtic-tick.rs @@ -11,7 +11,7 @@ mod app { gpio::{Output, PC13}, pac, prelude::*, - //timer::MonoTimerUs, // Easy monotonic timer for 32-bit TIMs only + rcc::CFGR, timer::MonoTimer64Us, // Extended 64-bit timer for 16/32-bit TIMs }; @@ -30,15 +30,14 @@ mod app { #[init] fn init(ctx: init::Context) -> (Shared, Local, init::Monotonics) { - let rcc = ctx.device.RCC.constrain(); - let clocks = rcc.cfgr.sysclk(48.MHz()).freeze(); + let rcc = ctx.device.RCC.freeze(CFGR::DEFAULT.sysclk(48.MHz())); let gpioc = ctx.device.GPIOC.split(); let led = gpioc.pc13.into_push_pull_output(); defmt::info!("Start"); - //let mono = ctx.device.TIM2.monotonic_us(&clocks); - let mono = ctx.device.TIM3.monotonic64_us(&clocks); + //let mono = ctx.device.TIM2.monotonic_us(&rcc.clocks); + let mono = ctx.device.TIM3.monotonic64_us(&rcc.clocks); tick::spawn().ok(); (Shared {}, Local { led }, init::Monotonics(mono)) } diff --git a/examples/rtic-usart-shell-ssd1306.rs b/examples/rtic-usart-shell-ssd1306.rs index 3c5d5c96..90b3392c 100644 --- a/examples/rtic-usart-shell-ssd1306.rs +++ b/examples/rtic-usart-shell-ssd1306.rs @@ -23,9 +23,9 @@ mod usart_shell { use stm32f4xx_hal::{ gpio::{gpioa::PA0, gpioc::PC13, Edge, Input, Output, PushPull}, i2c::I2c, - pac::I2C1, - pac::USART1, + pac::{I2C1, USART1}, prelude::*, + rcc::CFGR, serial::{self, config::Config, Serial}, timer::Event, }; @@ -81,8 +81,10 @@ mod usart_shell { // syscfg let mut syscfg = ctx.device.SYSCFG.constrain(); // clocks - let rcc = ctx.device.RCC.constrain(); - let clocks = rcc.cfgr.sysclk(SYSFREQ.Hz()).use_hse(25.MHz()).freeze(); + let rcc = ctx + .device + .RCC + .freeze(CFGR::hse(25.MHz()).sysclk(SYSFREQ.Hz())); // monotonic timer let mono = DwtSystick::new(&mut ctx.core.DCB, ctx.core.DWT, ctx.core.SYST, SYSFREQ); // gpio ports A and C @@ -99,14 +101,14 @@ mod usart_shell { // i2c let scl = gpiob.pb8; let sda = gpiob.pb9; - let i2c = I2c::new(ctx.device.I2C1, (scl, sda), 400.kHz(), &clocks); + let i2c = I2c::new(ctx.device.I2C1, (scl, sda), 400.kHz(), &rcc.clocks); // serial let pins = (gpioa.pa9, gpioa.pa10); let mut serial = Serial::new( ctx.device.USART1, pins, Config::default().baudrate(115_200.bps()).wordlength_8(), - &clocks, + &rcc.clocks, ) .unwrap() .with_u8_data(); @@ -121,7 +123,7 @@ mod usart_shell { .into_buffered_graphics_mode(); ldisp.init().unwrap(); - let mut timer = ctx.device.TIM2.counter_hz(&clocks); + let mut timer = ctx.device.TIM2.counter_hz(&rcc.clocks); //let mut timer = FTimer::new(ctx.device.TIM1, &clocks).counter_hz(); timer.start(FPS.Hz()).unwrap(); timer.listen(Event::Update); diff --git a/examples/rtic-usart-shell.rs b/examples/rtic-usart-shell.rs index f5c3b21e..e9482e02 100644 --- a/examples/rtic-usart-shell.rs +++ b/examples/rtic-usart-shell.rs @@ -13,6 +13,7 @@ mod usart_shell { gpio::{gpioa::PA0, gpioc::PC13, Edge, Input, Output, PushPull}, pac::USART1, prelude::*, + rcc::CFGR, serial::{self, config::Config, Serial}, }; @@ -52,8 +53,10 @@ mod usart_shell { // syscfg let mut syscfg = ctx.device.SYSCFG.constrain(); // clocks - let rcc = ctx.device.RCC.constrain(); - let clocks = rcc.cfgr.sysclk(SYSFREQ.Hz()).use_hse(25.MHz()).freeze(); + let rcc = ctx + .device + .RCC + .freeze(CFGR::hse(25.MHz()).sysclk(SYSFREQ.Hz())); // monotonic timer let mono = DwtSystick::new(&mut ctx.core.DCB, ctx.core.DWT, ctx.core.SYST, SYSFREQ); // gpio ports A and C @@ -72,7 +75,7 @@ mod usart_shell { ctx.device.USART1, pins, Config::default().baudrate(115_200.bps()).wordlength_8(), - &clocks, + &rcc.clocks, ) .unwrap() .with_u8_data(); diff --git a/examples/rtic-usb-cdc-echo.rs b/examples/rtic-usb-cdc-echo.rs index 2f114680..e6fcd540 100644 --- a/examples/rtic-usb-cdc-echo.rs +++ b/examples/rtic-usb-cdc-echo.rs @@ -10,6 +10,7 @@ mod app { otg_fs::{UsbBus, UsbBusType, USB}, pac, prelude::*, + rcc::CFGR, timer::MonoTimerUs, }; @@ -37,22 +38,16 @@ mod app { let dp = ctx.device; - let rcc = dp.RCC.constrain(); // Setup system clocks - let hse = 25.MHz(); - let sysclk = 84.MHz(); - let clocks = rcc - .cfgr - .use_hse(hse) - .sysclk(sysclk) - .require_pll48clk() - .freeze(); + let rcc = dp + .RCC + .freeze(CFGR::hse(25.MHz()).sysclk(84.MHz()).require_pll48clk()); let gpioa = dp.GPIOA.split(); let gpioc = dp.GPIOC.split(); let led = gpioc.pc13.into_push_pull_output(); - let mono = dp.TIM2.monotonic_us(&clocks); + let mono = dp.TIM2.monotonic_us(&rcc.clocks); tick::spawn().ok(); // *** Begin USB setup *** @@ -62,7 +57,7 @@ mod app { usb_pwrclk: dp.OTG_FS_PWRCLK, pin_dm: gpioa.pa11.into(), pin_dp: gpioa.pa12.into(), - hclk: clocks.hclk(), + hclk: rcc.clocks.hclk(), }; unsafe { USB_BUS.replace(UsbBus::new(usb, &mut EP_MEMORY)); diff --git a/examples/rtic2-tick.rs b/examples/rtic2-tick.rs index f7b9b5ba..73f41d49 100644 --- a/examples/rtic2-tick.rs +++ b/examples/rtic2-tick.rs @@ -26,6 +26,8 @@ use rtic::app; #[app(device = pac, dispatchers = [USART1], peripherals = true)] mod app { + use stm32f4xx_hal::rcc::CFGR; + use super::*; #[shared] @@ -38,11 +40,12 @@ mod app { #[init] fn init(mut ctx: init::Context) -> (Shared, Local) { - let rcc = ctx.device.RCC.constrain(); - let clocks = rcc.cfgr.sysclk(48.MHz()).freeze(); + let rcc = ctx.device.RCC.freeze(CFGR::hsi().sysclk(48.MHz())); // Create TIM3 monotonic and initialize timer queue - ctx.device.TIM3.monotonic_us(&mut ctx.core.NVIC, &clocks); + ctx.device + .TIM3 + .monotonic_us(&mut ctx.core.NVIC, &rcc.clocks); // Uncomment if use SysTick as monotonic timer //Mono::start(ctx.core.SYST, 48_000_000); diff --git a/examples/sai-duplex.rs b/examples/sai-duplex.rs index 5f237e0b..52b55f8e 100644 --- a/examples/sai-duplex.rs +++ b/examples/sai-duplex.rs @@ -5,7 +5,7 @@ use panic_halt as _; -use stm32f4xx_hal as hal; +use stm32f4xx_hal::{self as hal, rcc::CFGR}; use crate::hal::{ pac, @@ -22,16 +22,12 @@ fn main() -> ! { // I2S-encoded audio. // Initialize clocks. - let rcc = p.RCC.constrain(); - let clocks = rcc - .cfgr - .use_hse(8.MHz()) - .saia_clk(172.MHz()) - .saib_clk(172.MHz()) - .freeze(); + let rcc = p + .RCC + .freeze(CFGR::hse(8.MHz()).saia_clk(172.MHz()).saib_clk(172.MHz())); // Test that the SAI clock is suitable for 48000KHz audio. - assert!(clocks.saia_clk() == Some(172.MHz())); - assert!(clocks.saib_clk() == Some(172.MHz())); + assert!(rcc.clocks.saia_clk() == Some(172.MHz())); + assert!(rcc.clocks.saib_clk() == Some(172.MHz())); let gpioe = p.GPIOE.split(); // SAIB is made synchronous to A. @@ -46,7 +42,7 @@ fn main() -> ! { (Some(gpioe.pe2), gpioe.pe4, gpioe.pe5, gpioe.pe6), protocol, 48.kHz(), - &clocks, + &rcc.clocks, ); let rx = saib.slave_rx(gpioe.pe3, protocol); @@ -61,8 +57,7 @@ fn main() -> ! { // The following code configures the A sub-block of SAI as a master transmitter for PCM-encoded audio. // Initialize clocks. - let rcc = p.RCC.constrain(); - let clocks = rcc.cfgr.use_hse(8.MHz()).saia_clk(172.MHz()).freeze(); + let rcc = p.RCC.freeze(CFGR::hse(8.MHz()).saia_clk(172.MHz())); // Test that the SAI clock is suitable for 48000KHz audio. assert!(clocks.saia_clk() == Some(172.MHz())); diff --git a/examples/sd.rs b/examples/sd.rs index 5312c83b..5e785082 100644 --- a/examples/sd.rs +++ b/examples/sd.rs @@ -8,6 +8,7 @@ use panic_semihosting as _; use stm32f4xx_hal::{ pac, prelude::*, + rcc::CFGR, sdio::{ClockFreq, SdCard, Sdio}, }; @@ -16,20 +17,18 @@ fn main() -> ! { let device = pac::Peripherals::take().unwrap(); let core = cortex_m::Peripherals::take().unwrap(); - let rcc = device.RCC.constrain(); - let clocks = rcc - .cfgr - .use_hse(12.MHz()) - .require_pll48clk() - .sysclk(168.MHz()) - .hclk(168.MHz()) - .pclk1(42.MHz()) - .pclk2(84.MHz()) - .freeze(); + let rcc = device.RCC.freeze( + CFGR::hse(12.MHz()) + .require_pll48clk() + .sysclk(168.MHz()) + .hclk(168.MHz()) + .pclk1(42.MHz()) + .pclk2(84.MHz()), + ); assert!(clocks.is_pll48clk_valid()); - let mut delay = core.SYST.delay(&clocks); + let mut delay = core.SYST.delay(&rcc.clocks); let gpioc = device.GPIOC.split(); let gpiod = device.GPIOD.split(); diff --git a/examples/serial-9bit.rs b/examples/serial-9bit.rs index 9e6721a3..d4bc43ba 100644 --- a/examples/serial-9bit.rs +++ b/examples/serial-9bit.rs @@ -32,7 +32,7 @@ use panic_halt as _; use cortex_m_rt::entry; -use stm32f4xx_hal as hal; +use stm32f4xx_hal::{self as hal, rcc::CFGR}; use crate::hal::{block, pac, prelude::*, serial::config::Config}; @@ -51,11 +51,9 @@ fn main() -> ! { let mut led_bit7 = gpiod.pd14.into_push_pull_output(); let mut led_bit8 = gpiod.pd15.into_push_pull_output(); - let rcc = dp.RCC.constrain(); + let rcc = dp.RCC.freeze(CFGR::hse(8.MHz())); - let clocks = rcc.cfgr.use_hse(8.MHz()).freeze(); - - let mut delay = cp.SYST.delay(&clocks); + let mut delay = cp.SYST.delay(&rcc.clocks); // define RX/TX pins let tx_pin = gpioa.pa2; @@ -67,7 +65,7 @@ fn main() -> ! { .serial( (tx_pin, rx_pin), Config::default().baudrate(9600.bps()).wordlength_9(), - &clocks, + &rcc.clocks, ) .unwrap() // Make this Serial object use u16s instead of u8s diff --git a/examples/serial-dma.rs b/examples/serial-dma.rs index 711402da..364f7141 100644 --- a/examples/serial-dma.rs +++ b/examples/serial-dma.rs @@ -42,7 +42,6 @@ fn main() -> ! { if let Some(dp) = pac::Peripherals::take() { // Set up the system clock. let rcc = dp.RCC.constrain(); - let clocks = rcc.cfgr.freeze(); // Enable DMA1. let dma1 = StreamsTuple::new(dp.DMA1); @@ -61,7 +60,7 @@ fn main() -> ! { .parity_none() .stopbits(StopBits::STOP1) .dma(serial::config::DmaConfig::TxRx), - &clocks, + &rcc.clocks, ) .unwrap(); diff --git a/examples/serial.rs b/examples/serial.rs index 39021a72..86847934 100644 --- a/examples/serial.rs +++ b/examples/serial.rs @@ -4,7 +4,7 @@ use panic_halt as _; use cortex_m_rt::entry; -use stm32f4xx_hal as hal; +use stm32f4xx_hal::{self as hal, rcc::CFGR}; use crate::hal::{pac, prelude::*}; @@ -16,19 +16,17 @@ fn main() -> ! { let gpioa = dp.GPIOA.split(); - let rcc = dp.RCC.constrain(); + let rcc = dp.RCC.freeze(CFGR::hse(25.MHz())); - let clocks = rcc.cfgr.use_hse(25.MHz()).freeze(); - - let mut delay = dp.TIM1.delay_ms(&clocks); + let mut delay = dp.TIM1.delay_ms(&rcc.clocks); // define RX/TX pins let tx_pin = gpioa.pa9; // configure serial - // let mut tx = Serial::tx(dp.USART1, tx_pin, 9600.bps(), &clocks).unwrap(); + // let mut tx = Serial::tx(dp.USART1, tx_pin, 9600.bps(), &rcc.clocks).unwrap(); // or - let mut tx = dp.USART1.tx(tx_pin, 9600.bps(), &clocks).unwrap(); + let mut tx = dp.USART1.tx(tx_pin, 9600.bps(), &rcc.clocks).unwrap(); let mut value: u8 = 0; diff --git a/examples/spi-dma.rs b/examples/spi-dma.rs index 0371a4ce..84ce7876 100644 --- a/examples/spi-dma.rs +++ b/examples/spi-dma.rs @@ -30,7 +30,6 @@ fn main() -> ! { if let Some(dp) = pac::Peripherals::take() { // Set up the system clock. let rcc = dp.RCC.constrain(); - let clocks = rcc.cfgr.freeze(); let steams = StreamsTuple::new(dp.DMA1); let stream = steams.4; @@ -56,7 +55,7 @@ fn main() -> ! { (Some(pb13), SPI2::NoMiso, Some(pb15)), mode, 3.MHz(), - &clocks, + &rcc.clocks, ); let buffer = cortex_m::singleton!(: [u8; ARRAY_SIZE] = [1; ARRAY_SIZE]).unwrap(); diff --git a/examples/spi_slave.rs b/examples/spi_slave.rs index 7b7c9996..0efb4b34 100644 --- a/examples/spi_slave.rs +++ b/examples/spi_slave.rs @@ -19,8 +19,7 @@ pub const MODE: Mode = Mode { fn main() -> ! { let p = pac::Peripherals::take().unwrap(); - let rcc = p.RCC.constrain(); - let _clocks = rcc.cfgr.freeze(); + let _rcc = p.RCC.constrain(); let gpioa = p.GPIOA.split(); diff --git a/examples/ssd1306-image.rs b/examples/ssd1306-image.rs index 930e30ce..a47c6ef7 100644 --- a/examples/ssd1306-image.rs +++ b/examples/ssd1306-image.rs @@ -15,6 +15,7 @@ use panic_semihosting as _; use stm32f4xx_hal as hal; +use stm32f4xx_hal::rcc::CFGR; use cortex_m_rt::ExceptionFrame; use cortex_m_rt::{entry, exception}; @@ -30,17 +31,16 @@ fn main() -> ! { cortex_m::peripheral::Peripherals::take(), ) { // Set up the system clock. We want to run at 48MHz for this one. - let rcc = dp.RCC.constrain(); - let clocks = rcc.cfgr.sysclk(48.MHz()).freeze(); + let rcc = dp.RCC.freeze(CFGR::hsi().sysclk(48.MHz())); // Set up I2C - SCL is PB8 and SDA is PB9; they are set to Alternate Function 4 // as per the STM32F446xC/E datasheet page 60. Pin assignment as per the Nucleo-F446 board. let gpiob = dp.GPIOB.split(); let scl = gpiob.pb8.internal_pull_up(true); let sda = gpiob.pb9.internal_pull_up(true); - // let i2c = I2c::new(dp.I2C1, (scl, sda), 400.kHz(), &clocks); + // let i2c = I2c::new(dp.I2C1, (scl, sda), 400.kHz(), &rcc.clocks); // or - let i2c = dp.I2C1.i2c((scl, sda), 400.kHz(), &clocks); + let i2c = dp.I2C1.i2c((scl, sda), 400.kHz(), &rcc.clocks); // There's a button on PC13. On the Nucleo board, it's pulled up by a 4.7kOhm resistor // and therefore is active LOW. There's even a 100nF capacitor for debouncing - nice for us diff --git a/examples/st7789-lcd.rs b/examples/st7789-lcd.rs index 964c5bb2..ef218d9e 100644 --- a/examples/st7789-lcd.rs +++ b/examples/st7789-lcd.rs @@ -33,17 +33,17 @@ use st7789::ST7789; use stm32f4xx_hal::fsmc_lcd::{DataPins16, FsmcLcd, LcdPins, Timing}; use stm32f4xx_hal::pac::{CorePeripherals, Peripherals}; use stm32f4xx_hal::prelude::*; +use stm32f4xx_hal::rcc::CFGR; #[entry] fn main() -> ! { let cp = CorePeripherals::take().unwrap(); let dp = Peripherals::take().unwrap(); - let rcc = dp.RCC.constrain(); // Make HCLK faster to allow updating the display more quickly - let clocks = rcc.cfgr.hclk(100.MHz()).freeze(); + let rcc = dp.RCC.freeze(CFGR::hsi().hclk(100.MHz())); - let mut delay = cp.SYST.delay(&clocks); + let mut delay = cp.SYST.delay(&rcc.clocks); let gpiod = dp.GPIOD.split(); let gpioe = dp.GPIOE.split(); diff --git a/examples/stopwatch-with-ssd1306-and-interrupts-and-dma-i2c.rs b/examples/stopwatch-with-ssd1306-and-interrupts-and-dma-i2c.rs index 0cd79283..18cd531f 100644 --- a/examples/stopwatch-with-ssd1306-and-interrupts-and-dma-i2c.rs +++ b/examples/stopwatch-with-ssd1306-and-interrupts-and-dma-i2c.rs @@ -19,7 +19,7 @@ #![no_main] use panic_semihosting as _; // logs messages to the host stderr; requires a debugger -use stm32f4xx_hal as hal; +use stm32f4xx_hal::{self as hal, rcc::CFGR}; use crate::hal::{ dma::{Stream1, StreamsTuple}, @@ -29,7 +29,7 @@ use crate::hal::{ interrupt, pac, pac::{DMA1, I2C1}, prelude::*, - rcc::{Clocks, Rcc}, + rcc::Rcc, timer::{CounterUs, Event, Flag, Timer}, }; use core::cell::{Cell, RefCell}; @@ -160,10 +160,9 @@ impl WriteOnlyDataCommand for DMAI2cInterface { #[entry] fn main() -> ! { if let (Some(mut dp), Some(cp)) = (pac::Peripherals::take(), cortex_m::Peripherals::take()) { - let rcc = dp.RCC.constrain(); - let clocks = setup_clocks(rcc); + let rcc = setup_clocks(dp.RCC); let gpiob = dp.GPIOB.split(); - let i2c = I2c::new(dp.I2C1, (gpiob.pb8, gpiob.pb9), 400.kHz(), &clocks); + let i2c = I2c::new(dp.I2C1, (gpiob.pb8, gpiob.pb9), 400.kHz(), &rcc.clocks); // Then convert it to DMA let streams = StreamsTuple::new(dp.DMA1); @@ -199,7 +198,7 @@ fn main() -> ! { disp.flush().unwrap(); // Create a 1ms periodic interrupt from TIM2 - let mut timer = dp.TIM2.counter(&clocks); + let mut timer = dp.TIM2.counter(&rcc.clocks); timer.start(1.secs()).unwrap(); timer.listen(Event::Update); @@ -218,7 +217,7 @@ fn main() -> ! { pac::NVIC::unmask(btn_int_num); }; - let mut delay = Timer::syst(cp.SYST, &clocks).delay(); + let mut delay = Timer::syst(cp.SYST, &rcc.clocks).delay(); loop { let elapsed = free(|cs| ELAPSED_MS.borrow(cs).get()); @@ -320,13 +319,14 @@ fn I2C1_ER() { }); } -fn setup_clocks(rcc: Rcc) -> Clocks { - rcc.cfgr - .hclk(48.MHz()) - .sysclk(48.MHz()) - .pclk1(24.MHz()) - .pclk2(24.MHz()) - .freeze() +fn setup_clocks(rcc: pac::RCC) -> Rcc { + rcc.freeze( + CFGR::hsi() + .hclk(48.MHz()) + .sysclk(48.MHz()) + .pclk1(24.MHz()) + .pclk2(24.MHz()), + ) } fn stopwatch_start(cs: &CriticalSection) { diff --git a/examples/stopwatch-with-ssd1306-and-interrupts.rs b/examples/stopwatch-with-ssd1306-and-interrupts.rs index 0777959c..b80690e5 100644 --- a/examples/stopwatch-with-ssd1306-and-interrupts.rs +++ b/examples/stopwatch-with-ssd1306-and-interrupts.rs @@ -19,14 +19,14 @@ #![no_main] use panic_semihosting as _; // logs messages to the host stderr; requires a debugger -use stm32f4xx_hal as hal; +use stm32f4xx_hal::{self as hal, rcc::CFGR}; use crate::hal::{ gpio::{Edge, Input, PC13}, i2c::I2c, interrupt, pac, prelude::*, - rcc::{Clocks, Rcc}, + rcc::Rcc, timer::{CounterUs, Event, Flag, Timer}, }; use core::cell::{Cell, RefCell}; @@ -62,10 +62,9 @@ enum StopwatchState { #[entry] fn main() -> ! { if let (Some(mut dp), Some(cp)) = (pac::Peripherals::take(), cortex_m::Peripherals::take()) { - let rcc = dp.RCC.constrain(); - let clocks = setup_clocks(rcc); + let rcc = setup_clocks(dp.RCC); let gpiob = dp.GPIOB.split(); - let i2c = I2c::new(dp.I2C1, (gpiob.pb8, gpiob.pb9), 400.kHz(), &clocks); + let i2c = I2c::new(dp.I2C1, (gpiob.pb8, gpiob.pb9), 400.kHz(), &rcc.clocks); let mut syscfg = dp.SYSCFG.constrain(); @@ -83,7 +82,7 @@ fn main() -> ! { disp.flush().unwrap(); // Create a 1ms periodic interrupt from TIM2 - let mut timer = dp.TIM2.counter(&clocks); + let mut timer = dp.TIM2.counter(&rcc.clocks); timer.start(1.secs()).unwrap(); timer.listen(Event::Update); @@ -101,7 +100,7 @@ fn main() -> ! { pac::NVIC::unmask(btn_int_num); }; - let mut delay = Timer::syst(cp.SYST, &clocks).delay(); + let mut delay = Timer::syst(cp.SYST, &rcc.clocks).delay(); loop { let elapsed = free(|cs| ELAPSED_MS.borrow(cs).get()); @@ -184,13 +183,14 @@ fn EXTI15_10() { }); } -fn setup_clocks(rcc: Rcc) -> Clocks { - rcc.cfgr - .hclk(48.MHz()) - .sysclk(48.MHz()) - .pclk1(24.MHz()) - .pclk2(24.MHz()) - .freeze() +fn setup_clocks(rcc: pac::RCC) -> Rcc { + rcc.freeze( + CFGR::hsi() + .hclk(48.MHz()) + .sysclk(48.MHz()) + .pclk1(24.MHz()) + .pclk2(24.MHz()), + ) } fn stopwatch_start(cs: &CriticalSection) { diff --git a/examples/timer-periph.rs b/examples/timer-periph.rs index 4ec7c0e4..68174f95 100644 --- a/examples/timer-periph.rs +++ b/examples/timer-periph.rs @@ -16,18 +16,17 @@ use cortex_m_rt::entry; use cortex_m_semihosting::hprintln; use hal::timer::Error; -use stm32f4xx_hal as hal; +use stm32f4xx_hal::{self as hal, rcc::CFGR}; use crate::hal::{pac, prelude::*}; #[entry] fn main() -> ! { let dp = pac::Peripherals::take().unwrap(); - let rcc = dp.RCC.constrain(); - let clocks = rcc.cfgr.sysclk(24.MHz()).freeze(); + let rcc = dp.RCC.freeze(CFGR::hsi().sysclk(24.MHz())); // Create a timer based on SysTick - let mut timer = dp.TIM1.counter_ms(&clocks); + let mut timer = dp.TIM1.counter_ms(&rcc.clocks); timer.start(1.secs()).unwrap(); hprintln!("hello!"); diff --git a/examples/timer-syst.rs b/examples/timer-syst.rs index 4eb007fe..fc0645a5 100644 --- a/examples/timer-syst.rs +++ b/examples/timer-syst.rs @@ -16,7 +16,7 @@ use cortex_m_rt::entry; use cortex_m_semihosting::hprintln; use hal::timer::Error; -use stm32f4xx_hal as hal; +use stm32f4xx_hal::{self as hal, rcc::CFGR}; use crate::hal::{pac, prelude::*}; @@ -24,11 +24,10 @@ use crate::hal::{pac, prelude::*}; fn main() -> ! { let dp = pac::Peripherals::take().unwrap(); let cp = cortex_m::peripheral::Peripherals::take().unwrap(); - let rcc = dp.RCC.constrain(); - let clocks = rcc.cfgr.sysclk(24.MHz()).freeze(); + let rcc = dp.RCC.freeze(CFGR::hsi().sysclk(24.MHz())); // Create a timer based on SysTick - let mut timer = cp.SYST.counter_us(&clocks); + let mut timer = cp.SYST.counter_us(&rcc.clocks); timer.start(42.millis()).unwrap(); hprintln!("hello!"); diff --git a/examples/uart-dma.rs b/examples/uart-dma.rs index 24c0ed4a..547bdd43 100644 --- a/examples/uart-dma.rs +++ b/examples/uart-dma.rs @@ -128,7 +128,6 @@ fn main() -> ! { if let Some(dp) = pac::Peripherals::take() { // Set up the system clock. let rcc = dp.RCC.constrain(); - let clocks = rcc.cfgr.freeze(); let dma1 = StreamsTuple::new(dp.DMA1); @@ -145,7 +144,7 @@ fn main() -> ! { .parity_none() .stopbits(StopBits::STOP1) .dma(serial::config::DmaConfig::Rx), - &clocks, + &rcc.clocks, ) .unwrap(); diff --git a/examples/usb-serial-irq.rs b/examples/usb-serial-irq.rs index e648f315..3e601b7d 100644 --- a/examples/usb-serial-irq.rs +++ b/examples/usb-serial-irq.rs @@ -4,6 +4,7 @@ #![no_main] use panic_halt as _; +use stm32f4xx_hal::rcc::CFGR; use core::cell::RefCell; use cortex_m::interrupt::Mutex; @@ -30,16 +31,16 @@ fn main() -> ! { let dp = pac::Peripherals::take().unwrap(); - let rcc = dp.RCC.constrain(); - - let clocks = rcc.cfgr.sysclk((168).MHz()).pclk1((8).MHz()).freeze(); + let rcc = dp + .RCC + .freeze(CFGR::hsi().sysclk((168).MHz()).pclk1((8).MHz())); let gpioa = dp.GPIOA.split(); let usb = USB::new( (dp.OTG_FS_GLOBAL, dp.OTG_FS_DEVICE, dp.OTG_FS_PWRCLK), (gpioa.pa11, gpioa.pa12), - &clocks, + &rcc.clocks, ); *USB_BUS = Some(stm32f4xx_hal::otg_fs::UsbBusType::new(usb, EP_MEMORY)); diff --git a/examples/usb-serial-poll.rs b/examples/usb-serial-poll.rs index acce819c..6b9af65b 100644 --- a/examples/usb-serial-poll.rs +++ b/examples/usb-serial-poll.rs @@ -7,6 +7,7 @@ use panic_halt as _; use cortex_m_rt::entry; use stm32f4xx_hal::otg_fs::{UsbBus, USB}; +use stm32f4xx_hal::rcc::CFGR; use stm32f4xx_hal::{pac, prelude::*}; use usb_device::prelude::*; @@ -16,21 +17,16 @@ static mut EP_MEMORY: [u32; 1024] = [0; 1024]; fn main() -> ! { let dp = pac::Peripherals::take().unwrap(); - let rcc = dp.RCC.constrain(); - - let clocks = rcc - .cfgr - .use_hse(25.MHz()) - .sysclk(48.MHz()) - .require_pll48clk() - .freeze(); + let rcc = dp + .RCC + .freeze(CFGR::hse(25.MHz()).sysclk(48.MHz()).require_pll48clk()); let gpioa = dp.GPIOA.split(); let usb = USB::new( (dp.OTG_FS_GLOBAL, dp.OTG_FS_DEVICE, dp.OTG_FS_PWRCLK), (gpioa.pa11, gpioa.pa12), - &clocks, + &rcc.clocks, ); let usb_bus = UsbBus::new(usb, unsafe { &mut EP_MEMORY }); diff --git a/examples/ws2812-spi.rs b/examples/ws2812-spi.rs index 5a5f0213..30028262 100644 --- a/examples/ws2812-spi.rs +++ b/examples/ws2812-spi.rs @@ -3,7 +3,7 @@ #![no_std] use panic_halt as _; -use stm32f4xx_hal as hal; +use stm32f4xx_hal::{self as hal, rcc::CFGR}; use cortex_m_rt::entry; use hal::{ @@ -18,17 +18,16 @@ fn main() -> ! { let dp = pac::Peripherals::take().expect("cannot take peripherals"); // Configure APB bus clock to 48 MHz, cause ws2812b requires 3 Mbps SPI - let rcc = dp.RCC.constrain(); - let clocks = rcc.cfgr.use_hse(25.MHz()).sysclk(48.MHz()).freeze(); + let rcc = dp.RCC.freeze(CFGR::hse(25.MHz()).sysclk(48.MHz())); - let mut delay = dp.TIM1.delay_us(&clocks); + let mut delay = dp.TIM1.delay_us(&rcc.clocks); let gpioa = dp.GPIOA.split(); let spi = dp.SPI1.spi( (Some(gpioa.pa5), SPI1::NoMiso, Some(gpioa.pa7)), ws2812::MODE, 3000.kHz(), - &clocks, + &rcc.clocks, ); const NUM_LEDS: usize = 20; diff --git a/src/rcc/f4/mod.rs b/src/rcc/f4/mod.rs index 78350f80..99c474c9 100644 --- a/src/rcc/f4/mod.rs +++ b/src/rcc/f4/mod.rs @@ -10,36 +10,6 @@ mod pll; mod enable; -impl RccExt for RCC { - fn constrain(self) -> Rcc { - Rcc { - rb: self, - cfgr: CFGR { - hse: None, - hse_bypass: false, - hclk: None, - pclk1: None, - pclk2: None, - sysclk: None, - pll48clk: false, - i2s_ckin: None, - - #[cfg(not(feature = "rcc_i2s_apb"))] - i2s_clk: None, - #[cfg(feature = "rcc_i2s_apb")] - i2s_apb1_clk: None, - #[cfg(feature = "rcc_i2s_apb")] - i2s_apb2_clk: None, - - #[cfg(feature = "sai")] - sai1_clk: None, - #[cfg(feature = "sai")] - sai2_clk: None, - }, - } - } -} - //github.com/ Built-in high speed clock frequency pub const HSI: u32 = 16_000_000; // Hz @@ -129,7 +99,45 @@ pub struct CFGR { sai2_clk: Option, } +impl Default for CFGR { + fn default() -> Self { + Self::DEFAULT + } +} + impl CFGR { + pub const DEFAULT: Self = Self { + hse: None, + hse_bypass: false, + hclk: None, + pclk1: None, + pclk2: None, + sysclk: None, + pll48clk: false, + + i2s_ckin: None, + + #[cfg(not(feature = "rcc_i2s_apb"))] + i2s_clk: None, + #[cfg(feature = "rcc_i2s_apb")] + i2s_apb1_clk: None, + #[cfg(feature = "rcc_i2s_apb")] + i2s_apb2_clk: None, + + #[cfg(feature = "sai")] + sai1_clk: None, + #[cfg(feature = "sai")] + sai2_clk: None, + }; + + pub fn hsi() -> Self { + Self::DEFAULT + } + + pub fn hse(freq: Hertz) -> Self { + Self::DEFAULT.use_hse(freq) + } + //github.com/ Uses HSE (external oscillator) instead of HSI (internal RC oscillator) as the clock source. //github.com/ Will result in a hang if an external oscillator is not connected or it fails to start. pub fn use_hse(mut self, freq: Hertz) -> Self { @@ -302,7 +310,7 @@ impl CFGR { } } -impl CFGR { +impl Rcc { fn flash_setup(sysclk: u32) { use crate::pac::FLASH; @@ -333,10 +341,9 @@ impl CFGR { } } - //github.com/ Initialises the hardware according to CFGR state returning a Clocks instance. - //github.com/ Panics if overclocking is attempted. - pub fn freeze(self) -> Clocks { - self.freeze_internal(false) + //github.com/ Apply clock configuration + pub fn freeze(self, rcc_cfg: CFGR) -> Self { + self.freeze_internal(rcc_cfg, false) } //github.com/ Initialises the hardware according to CFGR state returning a Clocks instance. @@ -346,18 +353,18 @@ impl CFGR { //github.com/ //github.com/ This method does not check if the clocks are bigger or smaller than the officially //github.com/ recommended. - pub unsafe fn freeze_unchecked(self) -> Clocks { - self.freeze_internal(true) + pub unsafe fn freeze_unchecked(self, rcc_cfg: CFGR) -> Self { + self.freeze_internal(rcc_cfg, true) } - fn freeze_internal(self, unchecked: bool) -> Clocks { + fn freeze_internal(self, rcc_cfg: CFGR, unchecked: bool) -> Self { let rcc = unsafe { &*RCC::ptr() }; - let pllsrcclk = self.hse.unwrap_or(HSI); - let sysclk = self.sysclk.unwrap_or(pllsrcclk); + let pllsrcclk = rcc_cfg.hse.unwrap_or(HSI); + let sysclk = rcc_cfg.sysclk.unwrap_or(pllsrcclk); let sysclk_on_pll = sysclk != pllsrcclk; - let plls = pll::PllSetup::from_cfgr(&self, pllsrcclk, sysclk_on_pll.then_some(sysclk)); + let plls = pll::PllSetup::from_cfgr(&rcc_cfg, pllsrcclk, sysclk_on_pll.then_some(sysclk)); let sysclk = if sysclk_on_pll { plls.pllsysclk.unwrap() } else { @@ -366,7 +373,7 @@ impl CFGR { assert!(unchecked || !sysclk_on_pll || (SYSCLK_MIN..=SYSCLK_MAX).contains(&sysclk)); - let hclk = self.hclk.unwrap_or(sysclk); + let hclk = rcc_cfg.hclk.unwrap_or(sysclk); let (hpre_bits, hpre_div) = match (sysclk + hclk - 1) / hclk { 0 => unreachable!(), 1 => (HPRE::Div1, 1), @@ -383,7 +390,7 @@ impl CFGR { // Calculate real AHB clock let hclk = sysclk / hpre_div; - let pclk1 = self + let pclk1 = rcc_cfg .pclk1 .unwrap_or_else(|| crate::min_u32(PCLK1_MAX, hclk)); let (ppre1_bits, ppre1) = match (hclk + pclk1 - 1) / pclk1 { @@ -400,7 +407,7 @@ impl CFGR { assert!(unchecked || pclk1 <= PCLK1_MAX); - let pclk2 = self + let pclk2 = rcc_cfg .pclk2 .unwrap_or_else(|| crate::min_u32(PCLK2_MAX, hclk)); let (ppre2_bits, ppre2) = match (hclk + pclk2 - 1) / pclk2 { @@ -419,10 +426,10 @@ impl CFGR { Self::flash_setup(sysclk); - if self.hse.is_some() { + if rcc_cfg.hse.is_some() { // enable HSE and wait for it to be ready rcc.cr().modify(|_, w| { - if self.hse_bypass { + if rcc_cfg.hse_bypass { w.hsebyp().bypassed(); } w.hseon().set_bit() @@ -493,7 +500,7 @@ impl CFGR { rcc.cfgr().modify(|_, w| { w.sw().variant(if sysclk_on_pll { SW::Pll - } else if self.hse.is_some() { + } else if rcc_cfg.hse.is_some() { SW::Hse } else { SW::Hsi @@ -534,11 +541,14 @@ impl CFGR { sai2_clk: plls.sai.sai2_clk.map(Hertz::from_raw), }; - if self.pll48clk { + if rcc_cfg.pll48clk { assert!(clocks.is_pll48clk_valid()); } - clocks + Self { + rb: self.rb, + clocks, + } } } @@ -747,6 +757,38 @@ pub struct Clocks { pub(super) sai2_clk: Option, } +impl Default for Clocks { + fn default() -> Clocks { + let freq = HSI.Hz(); + Clocks { + hclk: freq, + pclk1: freq, + pclk2: freq, + timclk1: freq, + timclk2: freq, + sysclk: freq, + pll48clk: None, + #[cfg(not(feature = "rcc_i2s_apb"))] + i2s_clk: None, + #[cfg(feature = "rcc_i2s_apb")] + i2s_apb1_clk: None, + #[cfg(feature = "rcc_i2s_apb")] + i2s_apb2_clk: None, + + #[cfg(feature = "sai")] + #[cfg(not(feature = "sai2"))] + saia_clk: None, + #[cfg(feature = "sai")] + #[cfg(not(feature = "sai2"))] + saib_clk: None, + #[cfg(feature = "sai2")] + sai1_clk: None, + #[cfg(feature = "sai2")] + sai2_clk: None, + } + } +} + impl Clocks { //github.com/ Returns the frequency of the AHB1 pub fn hclk(&self) -> Hertz { diff --git a/src/rcc/mod.rs b/src/rcc/mod.rs index f99c9bbd..df95ee34 100644 --- a/src/rcc/mod.rs +++ b/src/rcc/mod.rs @@ -49,7 +49,7 @@ use fugit::HertzU32 as Hertz; //github.com/ Constrained RCC peripheral pub struct Rcc { - pub cfgr: CFGR, + pub clocks: Clocks, pub(crate) rb: RCC, } @@ -70,6 +70,22 @@ impl DerefMut for Rcc { pub trait RccExt { //github.com/ Constrains the `RCC` peripheral so it plays nicely with the other abstractions fn constrain(self) -> Rcc; + + //github.com/ Constrains the `RCC` peripheral and apply clock configuration + fn freeze(self, rcc_cfg: CFGR) -> Rcc; +} + +impl RccExt for RCC { + fn constrain(self) -> Rcc { + Rcc { + rb: self, + clocks: Clocks::default(), + } + } + + fn freeze(self, rcc_cfg: CFGR) -> Rcc { + self.constrain().freeze(rcc_cfg) + } } //github.com/ Bus associated to peripheral @@ -204,6 +220,7 @@ macro_rules! bus_struct { rcc.$en() } + #[allow(unused)] pub(crate) fn lpenr(rcc: &RccRB) -> &rcc::$LPEN { rcc.$lpen() } From 0ba01f4fb3f19b0eea40d8ea2403e2e9d4e41609 Mon Sep 17 00:00:00 2001 From: Andrey Zgarbul Date: Thu, 29 May 2025 07:13:41 +0300 Subject: [PATCH 4/5] rename CFGR to Config --- examples/analog-stopwatch-with-spi-ssd1306.rs | 4 +-- examples/blinky-timer-irq.rs | 4 +-- examples/can-send.rs | 4 +-- examples/delay-syst-blinky.rs | 4 +-- examples/delay-timer-blinky.rs | 4 +-- examples/display-touch.rs | 4 +-- examples/dwt-blinky.rs | 4 +-- examples/f413disco-lcd-ferris.rs | 4 +-- examples/f469disco-lcd-test.rs | 4 +-- examples/fmc-sdram.rs | 4 +-- examples/i2s-audio-out.rs | 10 ++++--- examples/ltdc-screen/main.rs | 4 +-- examples/pwm-dead-time.rs | 4 +-- examples/pwm-sinus.rs | 4 +-- examples/rng-display.rs | 4 +-- examples/rtc_alarm.rs | 2 +- examples/rtic-adc-dma.rs | 4 +-- examples/rtic-button.rs | 4 +-- examples/rtic-dual-i2s-audio-in-out.rs | 4 +-- examples/rtic-i2s-audio-in-out.rs | 4 +-- examples/rtic-spi-slave-dma.rs | 4 +-- examples/rtic-tick.rs | 4 +-- examples/rtic-usart-shell-ssd1306.rs | 4 +-- examples/rtic-usart-shell.rs | 4 +-- examples/rtic-usb-cdc-echo.rs | 4 +-- examples/rtic2-tick.rs | 4 +-- examples/sai-duplex.rs | 6 ++--- examples/sd.rs | 4 +-- examples/serial-9bit.rs | 4 +-- examples/serial.rs | 4 +-- examples/ssd1306-image.rs | 4 +-- examples/st7789-lcd.rs | 4 +-- ...with-ssd1306-and-interrupts-and-dma-i2c.rs | 4 +-- .../stopwatch-with-ssd1306-and-interrupts.rs | 4 +-- examples/timer-periph.rs | 4 +-- examples/timer-syst.rs | 4 +-- examples/usb-serial-irq.rs | 4 +-- examples/usb-serial-poll.rs | 4 +-- examples/ws2812-spi.rs | 4 +-- src/rcc/f4/mod.rs | 26 +++++++++---------- src/rcc/f4/pll.rs | 8 +++--- src/rcc/mod.rs | 4 +-- src/rng.rs | 2 +- 43 files changed, 102 insertions(+), 100 deletions(-) diff --git a/examples/analog-stopwatch-with-spi-ssd1306.rs b/examples/analog-stopwatch-with-spi-ssd1306.rs index 5bbafbef..8077d759 100644 --- a/examples/analog-stopwatch-with-spi-ssd1306.rs +++ b/examples/analog-stopwatch-with-spi-ssd1306.rs @@ -8,7 +8,7 @@ #![no_main] use panic_semihosting as _; -use stm32f4xx_hal::{self as hal, rcc::CFGR}; +use stm32f4xx_hal::{self as hal, rcc::Config}; use crate::hal::{ gpio::{Edge, Input, PA0}, @@ -223,7 +223,7 @@ fn main() -> ! { fn setup_clocks(rcc: pac::RCC) -> Rcc { rcc.freeze( - CFGR::hsi() + Config::hsi() .hclk(180.MHz()) .sysclk(180.MHz()) .pclk1(45.MHz()) diff --git a/examples/blinky-timer-irq.rs b/examples/blinky-timer-irq.rs index 89ba0b3e..de5d0fa4 100644 --- a/examples/blinky-timer-irq.rs +++ b/examples/blinky-timer-irq.rs @@ -8,7 +8,7 @@ use panic_halt as _; -use stm32f4xx_hal::{self as hal, rcc::CFGR}; +use stm32f4xx_hal::{self as hal, rcc::Config}; use crate::hal::{ gpio::{self, Output, PushPull}, @@ -66,7 +66,7 @@ fn TIM2() { fn main() -> ! { let dp = Peripherals::take().unwrap(); - let rcc = dp.RCC.freeze(CFGR::hsi().sysclk(16.MHz()).pclk1(8.MHz())); + let rcc = dp.RCC.freeze(Config::hsi().sysclk(16.MHz()).pclk1(8.MHz())); // Configure PA5 pin to blink LED let gpioa = dp.GPIOA.split(); diff --git a/examples/can-send.rs b/examples/can-send.rs index 7c946219..3476af1c 100644 --- a/examples/can-send.rs +++ b/examples/can-send.rs @@ -10,7 +10,7 @@ use bxcan::filter::Mask32; use bxcan::{Fifo, Frame, StandardId}; use cortex_m_rt::entry; use nb::block; -use stm32f4xx_hal::rcc::CFGR; +use stm32f4xx_hal::rcc::Config; use stm32f4xx_hal::{pac, prelude::*}; #[entry] @@ -20,7 +20,7 @@ fn main() -> ! { // To meet CAN clock accuracy requirements an external crystal or ceramic // resonator must be used. The blue pill has a 8MHz external crystal. // Other boards might have a crystal with another frequency or none at all. - let _rcc = dp.RCC.freeze(CFGR::hse(8.MHz())); + let _rcc = dp.RCC.freeze(Config::hse(8.MHz())); let gpiob = dp.GPIOB.split(); let mut can1 = { diff --git a/examples/delay-syst-blinky.rs b/examples/delay-syst-blinky.rs index 0c76d72e..98642cb4 100644 --- a/examples/delay-syst-blinky.rs +++ b/examples/delay-syst-blinky.rs @@ -9,7 +9,7 @@ use panic_halt as _; // panic handler use cortex_m_rt::entry; -use stm32f4xx_hal::{self as hal, rcc::CFGR}; +use stm32f4xx_hal::{self as hal, rcc::Config}; use crate::hal::{pac, prelude::*}; @@ -24,7 +24,7 @@ fn main() -> ! { let mut led = gpioa.pa5.into_push_pull_output(); // Set up the system clock. We want to run at 48MHz for this one. - let rcc = dp.RCC.freeze(CFGR::hsi().sysclk(48.MHz())); + let rcc = dp.RCC.freeze(Config::hsi().sysclk(48.MHz())); // Create a delay abstraction based on SysTick let mut delay = cp.SYST.delay(&rcc.clocks); diff --git a/examples/delay-timer-blinky.rs b/examples/delay-timer-blinky.rs index 3862aae6..8f2553ec 100644 --- a/examples/delay-timer-blinky.rs +++ b/examples/delay-timer-blinky.rs @@ -9,7 +9,7 @@ use panic_halt as _; // panic handler use cortex_m_rt::entry; -use stm32f4xx_hal::{self as hal, rcc::CFGR}; +use stm32f4xx_hal::{self as hal, rcc::Config}; use crate::hal::{pac, prelude::*}; @@ -24,7 +24,7 @@ fn main() -> ! { let mut led = gpioc.pc13.into_push_pull_output(); // Set up the system clock. We want to run at 48MHz for this one. - let rcc = dp.RCC.freeze(CFGR::hse(25.MHz()).sysclk(48.MHz())); + let rcc = dp.RCC.freeze(Config::hse(25.MHz()).sysclk(48.MHz())); // Create a delay abstraction based on general-pupose 32-bit timer TIM5 let mut delay = dp.TIM5.delay_us(&rcc.clocks); diff --git a/examples/display-touch.rs b/examples/display-touch.rs index 16752052..1fbc79fc 100644 --- a/examples/display-touch.rs +++ b/examples/display-touch.rs @@ -22,7 +22,7 @@ use stm32f4xx_hal::{ gpio::Speed, pac, prelude::*, - rcc::CFGR, + rcc::Config, }; use embedded_graphics_07::{ @@ -53,7 +53,7 @@ fn main() -> ! { let p = pac::Peripherals::take().unwrap(); let cp = cortex_m::Peripherals::take().unwrap(); - let rcc = p.RCC.freeze(CFGR::hsi().sysclk(100.MHz())); + let rcc = p.RCC.freeze(Config::hsi().sysclk(100.MHz())); let mut delay = cp.SYST.delay(&rcc.clocks); let gpiob = p.GPIOB.split(); diff --git a/examples/dwt-blinky.rs b/examples/dwt-blinky.rs index fa00b09f..05c3fbec 100644 --- a/examples/dwt-blinky.rs +++ b/examples/dwt-blinky.rs @@ -11,7 +11,7 @@ use crate::hal::{ }; use cortex_m_rt::entry; use panic_halt as _; -use stm32f4xx_hal::{self as hal, rcc::CFGR}; +use stm32f4xx_hal::{self as hal, rcc::Config}; #[entry] fn main() -> ! { @@ -25,7 +25,7 @@ fn main() -> ! { let mut led2 = gpiog.pg14.into_push_pull_output(); // Set up the system clock. We want to run at 48MHz for this one. - let rcc = dp.RCC.freeze(CFGR::hsi().sysclk(48.MHz())); + let rcc = dp.RCC.freeze(Config::hsi().sysclk(48.MHz())); // Create a delay abstraction based on DWT cycle counter let dwt = cp.DWT.constrain(cp.DCB, &rcc.clocks); diff --git a/examples/f413disco-lcd-ferris.rs b/examples/f413disco-lcd-ferris.rs index 40a95368..05054ed8 100644 --- a/examples/f413disco-lcd-ferris.rs +++ b/examples/f413disco-lcd-ferris.rs @@ -13,7 +13,7 @@ use panic_halt as _; use rtt_target::{self, rtt_init_print, ChannelMode}; -use stm32f4xx_hal::{self as hal, rcc::CFGR}; +use stm32f4xx_hal::{self as hal, rcc::Config}; use crate::hal::{ fsmc_lcd::{DataPins16, FsmcLcd, LcdPins, Timing}, @@ -705,7 +705,7 @@ fn main() -> ! { let gpiog = p.GPIOG.split(); // Configure and lock the clocks at maximum warp - let rcc = p.RCC.freeze(CFGR::hsi().sysclk(100.MHz())); + let rcc = p.RCC.freeze(Config::hsi().sysclk(100.MHz())); // Define the pins we need for our 16bit parallel bus use stm32f4xx_hal::gpio::alt::fsmc as alt; diff --git a/examples/f469disco-lcd-test.rs b/examples/f469disco-lcd-test.rs index 459a1d13..1dcf36b0 100644 --- a/examples/f469disco-lcd-test.rs +++ b/examples/f469disco-lcd-test.rs @@ -14,7 +14,7 @@ use cortex_m_rt::entry; use defmt_rtt as _; use panic_probe as _; -use stm32f4xx_hal::{self as hal, rcc::CFGR}; +use stm32f4xx_hal::{self as hal, rcc::Config}; use crate::hal::{ dsi::{ @@ -55,7 +55,7 @@ fn main() -> ! { let hse_freq = 8.MHz(); let rcc = dp .RCC - .freeze(CFGR::hse(hse_freq).pclk2(32.MHz()).sysclk(180.MHz())); + .freeze(Config::hse(hse_freq).pclk2(32.MHz()).sysclk(180.MHz())); let mut delay = cp.SYST.delay(&rcc.clocks); let gpioh = dp.GPIOH.split(); diff --git a/examples/fmc-sdram.rs b/examples/fmc-sdram.rs index 922a50eb..0c0f71dd 100644 --- a/examples/fmc-sdram.rs +++ b/examples/fmc-sdram.rs @@ -7,7 +7,7 @@ use panic_probe as _; use core::{mem, slice}; -use stm32f4xx_hal::{fmc::FmcExt, gpio::alt::fmc as alt, pac, prelude::*, rcc::CFGR}; +use stm32f4xx_hal::{fmc::FmcExt, gpio::alt::fmc as alt, pac, prelude::*, rcc::Config}; use cortex_m::peripheral::Peripherals; @@ -49,7 +49,7 @@ impl XorShift32 { #[entry] fn main() -> ! { if let (Some(p), Some(cp)) = (pac::Peripherals::take(), Peripherals::take()) { - let rcc = p.RCC.freeze(CFGR::hsi().sysclk(180.MHz())); + let rcc = p.RCC.freeze(Config::hsi().sysclk(180.MHz())); let mut delay = cp.SYST.delay(&rcc.clocks); diff --git a/examples/i2s-audio-out.rs b/examples/i2s-audio-out.rs index 9f80ec69..fadf8215 100644 --- a/examples/i2s-audio-out.rs +++ b/examples/i2s-audio-out.rs @@ -55,7 +55,7 @@ use stm32f4xx_hal::i2s::I2s; use stm32f4xx_hal::nb::block; use stm32f4xx_hal::pac::{Peripherals, SPI3}; use stm32f4xx_hal::prelude::*; -use stm32f4xx_hal::rcc::CFGR; +use stm32f4xx_hal::rcc::Config; const SAMPLE_RATE: u32 = 48_000; @@ -96,9 +96,11 @@ fn main() -> ! { // The 61440 kHz frequency can be divided to get exactly 48 kHz sample rate even when // generating master clock - let rcc = dp - .RCC - .freeze(CFGR::hse(8u32.MHz()).sysclk(96.MHz()).i2s_clk(61440.kHz())); + let rcc = dp.RCC.freeze( + Config::hse(8u32.MHz()) + .sysclk(96.MHz()) + .i2s_clk(61440.kHz()), + ); let i2s_pins = (gpioa.pa4, gpioc.pc10, SPI3::NoMck, gpioc.pc12); let i2s = I2s::new(dp.SPI3, i2s_pins, &rcc.clocks); diff --git a/examples/ltdc-screen/main.rs b/examples/ltdc-screen/main.rs index f417adc9..d33b8126 100644 --- a/examples/ltdc-screen/main.rs +++ b/examples/ltdc-screen/main.rs @@ -17,7 +17,7 @@ use stm32f4xx_hal::{ ltdc::{BluePins, GreenPins, Layer, LtdcPins, PixelFormat, RedPins}, pac, prelude::*, - rcc::{Rcc, CFGR}, + rcc::{Config, Rcc}, }; mod screen; @@ -68,7 +68,7 @@ fn main() -> ! { // HSE osc out in High Z gpioh.ph1.into_floating_input(); let _rcc_hal = rcc_hal.freeze( - CFGR::hse(25.MHz()) + Config::hse(25.MHz()) .bypass_hse_oscillator() .sysclk(216.MHz()) .hclk(216.MHz()), diff --git a/examples/pwm-dead-time.rs b/examples/pwm-dead-time.rs index df7aa07c..f72ca0c2 100644 --- a/examples/pwm-dead-time.rs +++ b/examples/pwm-dead-time.rs @@ -7,7 +7,7 @@ use panic_halt as _; // panic handler use cortex_m_rt::entry; -use stm32f4xx_hal::{self as hal, rcc::CFGR}; +use stm32f4xx_hal::{self as hal, rcc::Config}; use hal::{pac, prelude::*, timer::Polarity}; @@ -15,7 +15,7 @@ use hal::{pac, prelude::*, timer::Polarity}; fn main() -> ! { if let Some(dp) = pac::Peripherals::take() { // Set up the system clock. We want to run at 84MHz for this one. - let rcc = dp.RCC.freeze(CFGR::hsi().sysclk(25.MHz())); + let rcc = dp.RCC.freeze(Config::hsi().sysclk(25.MHz())); let gpioa = dp.GPIOA.split(); diff --git a/examples/pwm-sinus.rs b/examples/pwm-sinus.rs index 49e2fe4c..7fce8650 100644 --- a/examples/pwm-sinus.rs +++ b/examples/pwm-sinus.rs @@ -8,13 +8,13 @@ use panic_halt as _; use core::f32::consts::FRAC_PI_2; use cortex_m_rt::entry; use micromath::F32Ext; -use stm32f4xx_hal::{pac, prelude::*, rcc::CFGR}; +use stm32f4xx_hal::{pac, prelude::*, rcc::Config}; #[entry] fn main() -> ! { if let Some(dp) = pac::Peripherals::take() { // Set up the system clock. - let rcc = dp.RCC.freeze(CFGR::hse(25.MHz())); + let rcc = dp.RCC.freeze(Config::hse(25.MHz())); let gpioa = dp.GPIOA.split(); diff --git a/examples/rng-display.rs b/examples/rng-display.rs index 6aae31bf..24b5105f 100644 --- a/examples/rng-display.rs +++ b/examples/rng-display.rs @@ -15,7 +15,7 @@ #![no_main] use stm32f4xx_hal as hal; -use stm32f4xx_hal::rcc::CFGR; +use stm32f4xx_hal::rcc::Config; #[cfg(not(debug_assertions))] use panic_halt as _; @@ -59,7 +59,7 @@ fn main() -> ! { // here we pick a simple clock configuration that ensures the pll48clk, // from which RNG_CLK is derived, is about 48 MHz // discovery board has 8 MHz crystal for HSE - let rcc = dp.RCC.freeze(CFGR::hse(8.MHz()).sysclk(128.MHz())); + let rcc = dp.RCC.freeze(Config::hse(8.MHz()).sysclk(128.MHz())); let mut delay_source = cp.SYST.delay(&rcc.clocks); diff --git a/examples/rtc_alarm.rs b/examples/rtc_alarm.rs index 4248c404..7fb7d0ea 100644 --- a/examples/rtc_alarm.rs +++ b/examples/rtc_alarm.rs @@ -31,7 +31,7 @@ fn main() -> ! { let mut p = hal::pac::Peripherals::take().unwrap(); - let rcc = p.RCC.constrain(); + let _rcc = p.RCC.constrain(); let mut rtc = Rtc::new(p.RTC, &mut p.PWR); let today = date!(2023 - 05 - 28); diff --git a/examples/rtic-adc-dma.rs b/examples/rtic-adc-dma.rs index 06f8ab2a..a22e8617 100644 --- a/examples/rtic-adc-dma.rs +++ b/examples/rtic-adc-dma.rs @@ -16,7 +16,7 @@ mod app { dma::{config::DmaConfig, PeripheralToMemory, Stream0, StreamsTuple, Transfer}, pac::{self, ADC1, DMA2}, prelude::*, - rcc::CFGR, + rcc::Config, signature::{VtempCal110, VtempCal30}, }; @@ -43,7 +43,7 @@ mod app { let device: pac::Peripherals = cx.device; let _rcc = device.RCC.freeze( - CFGR::hse(25.MHz()) + Config::hse(25.MHz()) .require_pll48clk() .sysclk(MONO_HZ.Hz()) .hclk(MONO_HZ.Hz()) diff --git a/examples/rtic-button.rs b/examples/rtic-button.rs index 0bc668c7..05c2519f 100644 --- a/examples/rtic-button.rs +++ b/examples/rtic-button.rs @@ -10,7 +10,7 @@ mod app { use stm32f4xx_hal::{ gpio::{gpioa::PA0, gpioc::PC13, Edge, Input, Output, PinState, Pull}, prelude::*, - rcc::CFGR, + rcc::Config, }; const SYSFREQ: u32 = 100_000_000; // Shared resources go here @@ -32,7 +32,7 @@ mod app { let _rcc = ctx .device .RCC - .freeze(CFGR::hse(25.MHz()).sysclk(SYSFREQ.Hz())); + .freeze(Config::hse(25.MHz()).sysclk(SYSFREQ.Hz())); // gpio ports A and C let gpioa = ctx.device.GPIOA.split(); let gpioc = ctx.device.GPIOC.split(); diff --git a/examples/rtic-dual-i2s-audio-in-out.rs b/examples/rtic-dual-i2s-audio-in-out.rs index 4dad3ac0..5c778d9f 100644 --- a/examples/rtic-dual-i2s-audio-in-out.rs +++ b/examples/rtic-dual-i2s-audio-in-out.rs @@ -102,7 +102,7 @@ mod app { RightLsb, } - use stm32f4xx_hal::rcc::CFGR; + use stm32f4xx_hal::rcc::Config; use FrameState::{LeftLsb, LeftMsb, RightLsb, RightMsb}; impl Default for FrameState { @@ -154,7 +154,7 @@ mod app { let gpiob = device.GPIOB.split(); let gpioc = device.GPIOC.split(); let rcc = device.RCC.freeze( - CFGR::hse(8u32.MHz()) + Config::hse(8u32.MHz()) .sysclk(96.MHz()) .hclk(96.MHz()) .pclk1(50.MHz()) diff --git a/examples/rtic-i2s-audio-in-out.rs b/examples/rtic-i2s-audio-in-out.rs index 648abd09..7d5327de 100644 --- a/examples/rtic-i2s-audio-in-out.rs +++ b/examples/rtic-i2s-audio-in-out.rs @@ -86,7 +86,7 @@ mod app { use hal::pac::Interrupt; use hal::pac::{EXTI, SPI2, SPI3}; use hal::prelude::*; - use hal::rcc::CFGR; + use hal::rcc::Config; use heapless::spsc::*; @@ -158,7 +158,7 @@ mod app { let gpiob = device.GPIOB.split(); let gpioc = device.GPIOC.split(); let rcc = device.RCC.freeze( - CFGR::hse(8u32.MHz()) + Config::hse(8u32.MHz()) .sysclk(96.MHz()) .hclk(96.MHz()) .pclk1(50.MHz()) diff --git a/examples/rtic-spi-slave-dma.rs b/examples/rtic-spi-slave-dma.rs index 3c5d0c1a..fdac75ec 100644 --- a/examples/rtic-spi-slave-dma.rs +++ b/examples/rtic-spi-slave-dma.rs @@ -21,7 +21,7 @@ mod app { use panic_semihosting as _; use systick_monotonic::*; - use stm32f4xx_hal::{self as hal, rcc::CFGR}; + use stm32f4xx_hal::{self as hal, rcc::Config}; const ARRAY_SIZE: usize = 3; @@ -56,7 +56,7 @@ mod app { let _rcc = device_peripherals .RCC - .freeze(CFGR::hsi().sysclk(100.MHz()).pclk1(36.MHz())); + .freeze(Config::hsi().sysclk(100.MHz()).pclk1(36.MHz())); let mono = Systick::new(core.SYST, 100_000_000); diff --git a/examples/rtic-tick.rs b/examples/rtic-tick.rs index bcc0ca99..08934adf 100644 --- a/examples/rtic-tick.rs +++ b/examples/rtic-tick.rs @@ -11,7 +11,7 @@ mod app { gpio::{Output, PC13}, pac, prelude::*, - rcc::CFGR, + rcc::Config, timer::MonoTimer64Us, // Extended 64-bit timer for 16/32-bit TIMs }; @@ -30,7 +30,7 @@ mod app { #[init] fn init(ctx: init::Context) -> (Shared, Local, init::Monotonics) { - let rcc = ctx.device.RCC.freeze(CFGR::DEFAULT.sysclk(48.MHz())); + let rcc = ctx.device.RCC.freeze(Config::DEFAULT.sysclk(48.MHz())); let gpioc = ctx.device.GPIOC.split(); let led = gpioc.pc13.into_push_pull_output(); diff --git a/examples/rtic-usart-shell-ssd1306.rs b/examples/rtic-usart-shell-ssd1306.rs index 90b3392c..64c161a8 100644 --- a/examples/rtic-usart-shell-ssd1306.rs +++ b/examples/rtic-usart-shell-ssd1306.rs @@ -25,7 +25,7 @@ mod usart_shell { i2c::I2c, pac::{I2C1, USART1}, prelude::*, - rcc::CFGR, + rcc, serial::{self, config::Config, Serial}, timer::Event, }; @@ -84,7 +84,7 @@ mod usart_shell { let rcc = ctx .device .RCC - .freeze(CFGR::hse(25.MHz()).sysclk(SYSFREQ.Hz())); + .freeze(rcc::Config::hse(25.MHz()).sysclk(SYSFREQ.Hz())); // monotonic timer let mono = DwtSystick::new(&mut ctx.core.DCB, ctx.core.DWT, ctx.core.SYST, SYSFREQ); // gpio ports A and C diff --git a/examples/rtic-usart-shell.rs b/examples/rtic-usart-shell.rs index e9482e02..410d8e64 100644 --- a/examples/rtic-usart-shell.rs +++ b/examples/rtic-usart-shell.rs @@ -13,7 +13,7 @@ mod usart_shell { gpio::{gpioa::PA0, gpioc::PC13, Edge, Input, Output, PushPull}, pac::USART1, prelude::*, - rcc::CFGR, + rcc, serial::{self, config::Config, Serial}, }; @@ -56,7 +56,7 @@ mod usart_shell { let rcc = ctx .device .RCC - .freeze(CFGR::hse(25.MHz()).sysclk(SYSFREQ.Hz())); + .freeze(rcc::Config::hse(25.MHz()).sysclk(SYSFREQ.Hz())); // monotonic timer let mono = DwtSystick::new(&mut ctx.core.DCB, ctx.core.DWT, ctx.core.SYST, SYSFREQ); // gpio ports A and C diff --git a/examples/rtic-usb-cdc-echo.rs b/examples/rtic-usb-cdc-echo.rs index e6fcd540..ce6b5919 100644 --- a/examples/rtic-usb-cdc-echo.rs +++ b/examples/rtic-usb-cdc-echo.rs @@ -10,7 +10,7 @@ mod app { otg_fs::{UsbBus, UsbBusType, USB}, pac, prelude::*, - rcc::CFGR, + rcc::Config, timer::MonoTimerUs, }; @@ -41,7 +41,7 @@ mod app { // Setup system clocks let rcc = dp .RCC - .freeze(CFGR::hse(25.MHz()).sysclk(84.MHz()).require_pll48clk()); + .freeze(Config::hse(25.MHz()).sysclk(84.MHz()).require_pll48clk()); let gpioa = dp.GPIOA.split(); let gpioc = dp.GPIOC.split(); diff --git a/examples/rtic2-tick.rs b/examples/rtic2-tick.rs index 73f41d49..8569c3f9 100644 --- a/examples/rtic2-tick.rs +++ b/examples/rtic2-tick.rs @@ -26,7 +26,7 @@ use rtic::app; #[app(device = pac, dispatchers = [USART1], peripherals = true)] mod app { - use stm32f4xx_hal::rcc::CFGR; + use stm32f4xx_hal::rcc::Config; use super::*; @@ -40,7 +40,7 @@ mod app { #[init] fn init(mut ctx: init::Context) -> (Shared, Local) { - let rcc = ctx.device.RCC.freeze(CFGR::hsi().sysclk(48.MHz())); + let rcc = ctx.device.RCC.freeze(Config::hsi().sysclk(48.MHz())); // Create TIM3 monotonic and initialize timer queue ctx.device diff --git a/examples/sai-duplex.rs b/examples/sai-duplex.rs index 52b55f8e..a5614f69 100644 --- a/examples/sai-duplex.rs +++ b/examples/sai-duplex.rs @@ -5,7 +5,7 @@ use panic_halt as _; -use stm32f4xx_hal::{self as hal, rcc::CFGR}; +use stm32f4xx_hal::{self as hal, rcc::Config}; use crate::hal::{ pac, @@ -24,7 +24,7 @@ fn main() -> ! { // Initialize clocks. let rcc = p .RCC - .freeze(CFGR::hse(8.MHz()).saia_clk(172.MHz()).saib_clk(172.MHz())); + .freeze(Config::hse(8.MHz()).saia_clk(172.MHz()).saib_clk(172.MHz())); // Test that the SAI clock is suitable for 48000KHz audio. assert!(rcc.clocks.saia_clk() == Some(172.MHz())); assert!(rcc.clocks.saib_clk() == Some(172.MHz())); @@ -57,7 +57,7 @@ fn main() -> ! { // The following code configures the A sub-block of SAI as a master transmitter for PCM-encoded audio. // Initialize clocks. - let rcc = p.RCC.freeze(CFGR::hse(8.MHz()).saia_clk(172.MHz())); + let rcc = p.RCC.freeze(Config::hse(8.MHz()).saia_clk(172.MHz())); // Test that the SAI clock is suitable for 48000KHz audio. assert!(clocks.saia_clk() == Some(172.MHz())); diff --git a/examples/sd.rs b/examples/sd.rs index 5e785082..54fc539f 100644 --- a/examples/sd.rs +++ b/examples/sd.rs @@ -8,7 +8,7 @@ use panic_semihosting as _; use stm32f4xx_hal::{ pac, prelude::*, - rcc::CFGR, + rcc::Config, sdio::{ClockFreq, SdCard, Sdio}, }; @@ -18,7 +18,7 @@ fn main() -> ! { let core = cortex_m::Peripherals::take().unwrap(); let rcc = device.RCC.freeze( - CFGR::hse(12.MHz()) + Config::hse(12.MHz()) .require_pll48clk() .sysclk(168.MHz()) .hclk(168.MHz()) diff --git a/examples/serial-9bit.rs b/examples/serial-9bit.rs index d4bc43ba..4473a910 100644 --- a/examples/serial-9bit.rs +++ b/examples/serial-9bit.rs @@ -32,7 +32,7 @@ use panic_halt as _; use cortex_m_rt::entry; -use stm32f4xx_hal::{self as hal, rcc::CFGR}; +use stm32f4xx_hal::{self as hal, rcc}; use crate::hal::{block, pac, prelude::*, serial::config::Config}; @@ -51,7 +51,7 @@ fn main() -> ! { let mut led_bit7 = gpiod.pd14.into_push_pull_output(); let mut led_bit8 = gpiod.pd15.into_push_pull_output(); - let rcc = dp.RCC.freeze(CFGR::hse(8.MHz())); + let rcc = dp.RCC.freeze(rcc::Config::hse(8.MHz())); let mut delay = cp.SYST.delay(&rcc.clocks); diff --git a/examples/serial.rs b/examples/serial.rs index 86847934..af7bfa03 100644 --- a/examples/serial.rs +++ b/examples/serial.rs @@ -4,7 +4,7 @@ use panic_halt as _; use cortex_m_rt::entry; -use stm32f4xx_hal::{self as hal, rcc::CFGR}; +use stm32f4xx_hal::{self as hal, rcc::Config}; use crate::hal::{pac, prelude::*}; @@ -16,7 +16,7 @@ fn main() -> ! { let gpioa = dp.GPIOA.split(); - let rcc = dp.RCC.freeze(CFGR::hse(25.MHz())); + let rcc = dp.RCC.freeze(Config::hse(25.MHz())); let mut delay = dp.TIM1.delay_ms(&rcc.clocks); diff --git a/examples/ssd1306-image.rs b/examples/ssd1306-image.rs index a47c6ef7..22c9c048 100644 --- a/examples/ssd1306-image.rs +++ b/examples/ssd1306-image.rs @@ -15,7 +15,7 @@ use panic_semihosting as _; use stm32f4xx_hal as hal; -use stm32f4xx_hal::rcc::CFGR; +use stm32f4xx_hal::rcc::Config; use cortex_m_rt::ExceptionFrame; use cortex_m_rt::{entry, exception}; @@ -31,7 +31,7 @@ fn main() -> ! { cortex_m::peripheral::Peripherals::take(), ) { // Set up the system clock. We want to run at 48MHz for this one. - let rcc = dp.RCC.freeze(CFGR::hsi().sysclk(48.MHz())); + let rcc = dp.RCC.freeze(Config::hsi().sysclk(48.MHz())); // Set up I2C - SCL is PB8 and SDA is PB9; they are set to Alternate Function 4 // as per the STM32F446xC/E datasheet page 60. Pin assignment as per the Nucleo-F446 board. diff --git a/examples/st7789-lcd.rs b/examples/st7789-lcd.rs index ef218d9e..c02387d7 100644 --- a/examples/st7789-lcd.rs +++ b/examples/st7789-lcd.rs @@ -33,7 +33,7 @@ use st7789::ST7789; use stm32f4xx_hal::fsmc_lcd::{DataPins16, FsmcLcd, LcdPins, Timing}; use stm32f4xx_hal::pac::{CorePeripherals, Peripherals}; use stm32f4xx_hal::prelude::*; -use stm32f4xx_hal::rcc::CFGR; +use stm32f4xx_hal::rcc::Config; #[entry] fn main() -> ! { @@ -41,7 +41,7 @@ fn main() -> ! { let dp = Peripherals::take().unwrap(); // Make HCLK faster to allow updating the display more quickly - let rcc = dp.RCC.freeze(CFGR::hsi().hclk(100.MHz())); + let rcc = dp.RCC.freeze(Config::hsi().hclk(100.MHz())); let mut delay = cp.SYST.delay(&rcc.clocks); diff --git a/examples/stopwatch-with-ssd1306-and-interrupts-and-dma-i2c.rs b/examples/stopwatch-with-ssd1306-and-interrupts-and-dma-i2c.rs index 18cd531f..1a0d3409 100644 --- a/examples/stopwatch-with-ssd1306-and-interrupts-and-dma-i2c.rs +++ b/examples/stopwatch-with-ssd1306-and-interrupts-and-dma-i2c.rs @@ -19,7 +19,7 @@ #![no_main] use panic_semihosting as _; // logs messages to the host stderr; requires a debugger -use stm32f4xx_hal::{self as hal, rcc::CFGR}; +use stm32f4xx_hal::{self as hal, rcc::Config}; use crate::hal::{ dma::{Stream1, StreamsTuple}, @@ -321,7 +321,7 @@ fn I2C1_ER() { fn setup_clocks(rcc: pac::RCC) -> Rcc { rcc.freeze( - CFGR::hsi() + Config::hsi() .hclk(48.MHz()) .sysclk(48.MHz()) .pclk1(24.MHz()) diff --git a/examples/stopwatch-with-ssd1306-and-interrupts.rs b/examples/stopwatch-with-ssd1306-and-interrupts.rs index b80690e5..6e8ee9e8 100644 --- a/examples/stopwatch-with-ssd1306-and-interrupts.rs +++ b/examples/stopwatch-with-ssd1306-and-interrupts.rs @@ -19,7 +19,7 @@ #![no_main] use panic_semihosting as _; // logs messages to the host stderr; requires a debugger -use stm32f4xx_hal::{self as hal, rcc::CFGR}; +use stm32f4xx_hal::{self as hal, rcc::Config}; use crate::hal::{ gpio::{Edge, Input, PC13}, @@ -185,7 +185,7 @@ fn EXTI15_10() { fn setup_clocks(rcc: pac::RCC) -> Rcc { rcc.freeze( - CFGR::hsi() + Config::hsi() .hclk(48.MHz()) .sysclk(48.MHz()) .pclk1(24.MHz()) diff --git a/examples/timer-periph.rs b/examples/timer-periph.rs index 68174f95..6334c981 100644 --- a/examples/timer-periph.rs +++ b/examples/timer-periph.rs @@ -16,14 +16,14 @@ use cortex_m_rt::entry; use cortex_m_semihosting::hprintln; use hal::timer::Error; -use stm32f4xx_hal::{self as hal, rcc::CFGR}; +use stm32f4xx_hal::{self as hal, rcc::Config}; use crate::hal::{pac, prelude::*}; #[entry] fn main() -> ! { let dp = pac::Peripherals::take().unwrap(); - let rcc = dp.RCC.freeze(CFGR::hsi().sysclk(24.MHz())); + let rcc = dp.RCC.freeze(Config::hsi().sysclk(24.MHz())); // Create a timer based on SysTick let mut timer = dp.TIM1.counter_ms(&rcc.clocks); diff --git a/examples/timer-syst.rs b/examples/timer-syst.rs index fc0645a5..62abd5de 100644 --- a/examples/timer-syst.rs +++ b/examples/timer-syst.rs @@ -16,7 +16,7 @@ use cortex_m_rt::entry; use cortex_m_semihosting::hprintln; use hal::timer::Error; -use stm32f4xx_hal::{self as hal, rcc::CFGR}; +use stm32f4xx_hal::{self as hal, rcc::Config}; use crate::hal::{pac, prelude::*}; @@ -24,7 +24,7 @@ use crate::hal::{pac, prelude::*}; fn main() -> ! { let dp = pac::Peripherals::take().unwrap(); let cp = cortex_m::peripheral::Peripherals::take().unwrap(); - let rcc = dp.RCC.freeze(CFGR::hsi().sysclk(24.MHz())); + let rcc = dp.RCC.freeze(Config::hsi().sysclk(24.MHz())); // Create a timer based on SysTick let mut timer = cp.SYST.counter_us(&rcc.clocks); diff --git a/examples/usb-serial-irq.rs b/examples/usb-serial-irq.rs index 3e601b7d..ca5c981a 100644 --- a/examples/usb-serial-irq.rs +++ b/examples/usb-serial-irq.rs @@ -4,7 +4,7 @@ #![no_main] use panic_halt as _; -use stm32f4xx_hal::rcc::CFGR; +use stm32f4xx_hal::rcc::Config; use core::cell::RefCell; use cortex_m::interrupt::Mutex; @@ -33,7 +33,7 @@ fn main() -> ! { let rcc = dp .RCC - .freeze(CFGR::hsi().sysclk((168).MHz()).pclk1((8).MHz())); + .freeze(Config::hsi().sysclk((168).MHz()).pclk1((8).MHz())); let gpioa = dp.GPIOA.split(); diff --git a/examples/usb-serial-poll.rs b/examples/usb-serial-poll.rs index 6b9af65b..994cd56c 100644 --- a/examples/usb-serial-poll.rs +++ b/examples/usb-serial-poll.rs @@ -7,7 +7,7 @@ use panic_halt as _; use cortex_m_rt::entry; use stm32f4xx_hal::otg_fs::{UsbBus, USB}; -use stm32f4xx_hal::rcc::CFGR; +use stm32f4xx_hal::rcc::Config; use stm32f4xx_hal::{pac, prelude::*}; use usb_device::prelude::*; @@ -19,7 +19,7 @@ fn main() -> ! { let rcc = dp .RCC - .freeze(CFGR::hse(25.MHz()).sysclk(48.MHz()).require_pll48clk()); + .freeze(Config::hse(25.MHz()).sysclk(48.MHz()).require_pll48clk()); let gpioa = dp.GPIOA.split(); diff --git a/examples/ws2812-spi.rs b/examples/ws2812-spi.rs index 30028262..7786b211 100644 --- a/examples/ws2812-spi.rs +++ b/examples/ws2812-spi.rs @@ -3,7 +3,7 @@ #![no_std] use panic_halt as _; -use stm32f4xx_hal::{self as hal, rcc::CFGR}; +use stm32f4xx_hal::{self as hal, rcc::Config}; use cortex_m_rt::entry; use hal::{ @@ -18,7 +18,7 @@ fn main() -> ! { let dp = pac::Peripherals::take().expect("cannot take peripherals"); // Configure APB bus clock to 48 MHz, cause ws2812b requires 3 Mbps SPI - let rcc = dp.RCC.freeze(CFGR::hse(25.MHz()).sysclk(48.MHz())); + let rcc = dp.RCC.freeze(Config::hse(25.MHz()).sysclk(48.MHz())); let mut delay = dp.TIM1.delay_us(&rcc.clocks); let gpioa = dp.GPIOA.split(); diff --git a/src/rcc/f4/mod.rs b/src/rcc/f4/mod.rs index 99c474c9..daa78e13 100644 --- a/src/rcc/f4/mod.rs +++ b/src/rcc/f4/mod.rs @@ -75,7 +75,7 @@ pub const PCLK2_MAX: u32 = SYSCLK_MAX / 2; pub const PCLK1_MAX: u32 = PCLK2_MAX / 2; #[derive(Clone, Copy, Debug)] -pub struct CFGR { +pub struct Config { hse: Option, hse_bypass: bool, hclk: Option, @@ -99,13 +99,13 @@ pub struct CFGR { sai2_clk: Option, } -impl Default for CFGR { +impl Default for Config { fn default() -> Self { Self::DEFAULT } } -impl CFGR { +impl Config { pub const DEFAULT: Self = Self { hse: None, hse_bypass: false, @@ -195,7 +195,7 @@ impl CFGR { } #[cfg(not(feature = "rcc_i2s_apb"))] -impl CFGR { +impl Config { //github.com/ Selects an I2S clock frequency and enables the I2S clock. pub fn i2s_clk(mut self, freq: Hertz) -> Self { self.i2s_clk = Some(freq.raw()); @@ -204,7 +204,7 @@ impl CFGR { } #[cfg(feature = "rcc_i2s_apb")] -impl CFGR { +impl Config { //github.com/ Selects an I2S clock frequency for the first set of I2S instancesand enables the I2S clock. pub fn i2s_apb1_clk(mut self, freq: Hertz) -> Self { self.i2s_apb1_clk = Some(freq.raw()); @@ -220,7 +220,7 @@ impl CFGR { #[cfg(feature = "sai")] #[cfg(not(feature = "sai2"))] -impl CFGR { +impl Config { //github.com/ Selects a SAIA clock frequency and enables the SAIA clock. pub fn saia_clk(mut self, freq: Hertz) -> Self { self.sai1_clk = Some(freq.raw()); @@ -235,7 +235,7 @@ impl CFGR { } #[cfg(feature = "sai2")] -impl CFGR { +impl Config { //github.com/ Selects a SAI1 clock frequency and enables the SAI1 clock. pub fn sai1_clk(mut self, freq: Hertz) -> Self { self.sai1_clk = Some(freq.raw()); @@ -250,7 +250,7 @@ impl CFGR { } #[cfg(feature = "sai")] -impl CFGR { +impl Config { fn sai_clocks(&self) -> SaiClocks { let sai1_ext = self.sai1_clk.is_some() && self.sai1_clk == self.i2s_ckin; #[cfg(not(feature = "sai2"))] @@ -274,7 +274,7 @@ impl CFGR { } } -impl CFGR { +impl Config { #[cfg(feature = "rcc_i2s_apb")] fn i2s_clocks(&self) -> I2sClocks { let i2s_apb1_ext = self.i2s_apb1_clk.is_some() && self.i2s_apb1_clk == self.i2s_ckin; @@ -342,22 +342,22 @@ impl Rcc { } //github.com/ Apply clock configuration - pub fn freeze(self, rcc_cfg: CFGR) -> Self { + pub fn freeze(self, rcc_cfg: Config) -> Self { self.freeze_internal(rcc_cfg, false) } - //github.com/ Initialises the hardware according to CFGR state returning a Clocks instance. + //github.com/ Initialises the hardware according to Config state returning a Clocks instance. //github.com/ Allows overclocking. //github.com/ //github.com/ # Safety //github.com/ //github.com/ This method does not check if the clocks are bigger or smaller than the officially //github.com/ recommended. - pub unsafe fn freeze_unchecked(self, rcc_cfg: CFGR) -> Self { + pub unsafe fn freeze_unchecked(self, rcc_cfg: Config) -> Self { self.freeze_internal(rcc_cfg, true) } - fn freeze_internal(self, rcc_cfg: CFGR, unchecked: bool) -> Self { + fn freeze_internal(self, rcc_cfg: Config, unchecked: bool) -> Self { let rcc = unsafe { &*RCC::ptr() }; let pllsrcclk = rcc_cfg.hse.unwrap_or(HSI); diff --git a/src/rcc/f4/pll.rs b/src/rcc/f4/pll.rs index f4e7b532..e78b5cbc 100644 --- a/src/rcc/f4/pll.rs +++ b/src/rcc/f4/pll.rs @@ -1,4 +1,4 @@ -use super::CFGR; +use super::Config; use crate::pac::RCC; #[cfg_attr(feature = "defmt", derive(defmt::Format))] @@ -22,7 +22,7 @@ pub struct PllSetup { impl PllSetup { #[cfg(feature = "gpio-f410")] #[inline(always)] - pub fn from_cfgr(cfgr: &CFGR, pllsrcclk: u32, pllsysclk: Option) -> Self { + pub fn from_cfgr(cfgr: &Config, pllsrcclk: u32, pllsysclk: Option) -> Self { let i2s_clocks = cfgr.i2s_clocks(); let (main_pll, plli2sclk) = if let Some(i2s_clk) = i2s_clocks.pll_i2s_clk { @@ -53,7 +53,7 @@ impl PllSetup { #[cfg(feature = "gpio-f413")] #[inline(always)] - pub fn from_cfgr(cfgr: &CFGR, pllsrcclk: u32, pllsysclk: Option) -> Self { + pub fn from_cfgr(cfgr: &Config, pllsrcclk: u32, pllsysclk: Option) -> Self { let rcc = unsafe { &*RCC::ptr() }; let i2s_clocks = cfgr.i2s_clocks(); @@ -118,7 +118,7 @@ impl PllSetup { #[cfg(not(any(feature = "gpio-f410", feature = "gpio-f413")))] #[inline(always)] - pub fn from_cfgr(cfgr: &CFGR, pllsrcclk: u32, pllsysclk: Option) -> Self { + pub fn from_cfgr(cfgr: &Config, pllsrcclk: u32, pllsysclk: Option) -> Self { let i2s_clocks = cfgr.i2s_clocks(); #[cfg(feature = "sai")] let sai_clocks = cfgr.sai_clocks(); diff --git a/src/rcc/mod.rs b/src/rcc/mod.rs index df95ee34..8a5690eb 100644 --- a/src/rcc/mod.rs +++ b/src/rcc/mod.rs @@ -72,7 +72,7 @@ pub trait RccExt { fn constrain(self) -> Rcc; //github.com/ Constrains the `RCC` peripheral and apply clock configuration - fn freeze(self, rcc_cfg: CFGR) -> Rcc; + fn freeze(self, rcc_cfg: Config) -> Rcc; } impl RccExt for RCC { @@ -83,7 +83,7 @@ impl RccExt for RCC { } } - fn freeze(self, rcc_cfg: CFGR) -> Rcc { + fn freeze(self, rcc_cfg: Config) -> Rcc { self.constrain().freeze(rcc_cfg) } } diff --git a/src/rng.rs b/src/rng.rs index 3d5645f8..4c1a2afb 100644 --- a/src/rng.rs +++ b/src/rng.rs @@ -69,7 +69,7 @@ pub trait RngExt { //github.com/ ClockError (CECS error). //github.com/ As the `RNG_CLK` always seems to be connected to the `PLL48_CLK` and the //github.com/ maximum value of `HCLK` is 168MHz, this is always true as long as the `PLL48_CLK` is enabled. - //github.com/ This can be done with the [require_pll48clk](crate::rcc::CFGR::require_pll48clk) function. + //github.com/ This can be done with the [require_pll48clk](crate::rcc::Config::require_pll48clk) function. //github.com/ //github.com/ See reference manual section 24.4.2 for more details //github.com/ From f2d333a5f31c45c2619d9bab0140b8651fdaa5a8 Mon Sep 17 00:00:00 2001 From: Andrey Zgarbul Date: Thu, 29 May 2025 08:30:49 +0300 Subject: [PATCH 5/5] gpio rcc --- examples/analog-stopwatch-with-spi-ssd1306.rs | 14 ++-- examples/blinky-timer-irq.rs | 6 +- examples/blinky.rs | 4 +- examples/can-send.rs | 8 +-- examples/delay-syst-blinky.rs | 8 +-- examples/delay-timer-blinky.rs | 10 +-- examples/display-touch.rs | 18 ++--- examples/dwt-blinky.rs | 8 +-- examples/dynamic-gpio.rs | 4 +- examples/f413disco-lcd-ferris.rs | 19 +++--- examples/f469disco-lcd-test.rs | 6 +- examples/fmc-sdram.rs | 16 ++--- examples/hd44780.rs | 6 +- examples/i2c_scanner.rs | 6 +- examples/i2s-audio-out.rs | 10 +-- examples/ist7920-bidi-normal-spi.rs | 11 ++-- examples/ltdc-screen/main.rs | 18 ++--- examples/pwm-dead-time.rs | 6 +- examples/pwm-input.rs | 10 +-- examples/pwm-sinus.rs | 8 +-- examples/pwm.rs | 6 +- examples/qei.rs | 12 ++-- examples/qspi-w25q.rs | 14 ++-- examples/rng-display.rs | 8 +-- examples/rtc.rs | 6 +- examples/rtc_alarm.rs | 4 +- examples/rtic-adc-dma.rs | 8 +-- examples/rtic-button.rs | 10 +-- examples/rtic-dual-i2s-audio-in-out.rs | 10 +-- examples/rtic-i2s-audio-in-out.rs | 14 ++-- examples/rtic-serial-dma-rx-idle.rs | 8 +-- examples/rtic-spi-slave-dma.rs | 15 +++-- examples/rtic-tick.rs | 8 +-- examples/rtic-usart-shell-ssd1306.rs | 20 +++--- examples/rtic-usart-shell.rs | 12 ++-- examples/rtic-usb-cdc-echo.rs | 8 +-- examples/rtic2-tick.rs | 8 +-- examples/sai-duplex.rs | 6 +- examples/sd.rs | 10 +-- examples/serial-9bit.rs | 10 +-- examples/serial-dma.rs | 8 +-- examples/serial.rs | 10 +-- examples/spi-dma.rs | 8 +-- examples/spi_slave.rs | 14 ++-- examples/ssd1306-image.rs | 10 +-- examples/st7789-lcd.rs | 10 +-- ...with-ssd1306-and-interrupts-and-dma-i2c.rs | 16 ++--- .../stopwatch-with-ssd1306-and-interrupts.rs | 12 ++-- examples/timer-periph.rs | 4 +- examples/uart-dma.rs | 8 +-- examples/usb-serial-irq.rs | 4 +- examples/usb-serial-poll.rs | 4 +- examples/ws2812-spi.rs | 8 +-- src/adc.rs | 18 +++-- src/can.rs | 40 ++++++------ src/crc32.rs | 12 ++-- src/dac.rs | 20 +++--- src/dma/mod.rs | 9 ++- src/dsi.rs | 10 ++- src/fmpi2c.rs | 59 +++++++---------- src/fsmc_lcd/mod.rs | 24 ++++--- src/gpio.rs | 16 ++--- src/i2c.rs | 20 +++--- src/i2s.rs | 40 +++++------- src/qei.rs | 13 ++-- src/qspi.rs | 18 ++--- src/rng.rs | 16 ++--- src/rtc.rs | 56 ++++++++-------- src/sai.rs | 25 +++---- src/sdio.rs | 14 ++-- src/serial.rs | 44 ++++++------- src/spi.rs | 65 ++++++++++--------- src/syscfg.rs | 10 ++- src/timer.rs | 59 ++++++++--------- src/timer/monotonic.rs | 32 ++++----- src/timer/monotonics.rs | 12 ++-- src/timer/pwm.rs | 18 ++--- tools/check.py | 2 +- 78 files changed, 569 insertions(+), 592 deletions(-) diff --git a/examples/analog-stopwatch-with-spi-ssd1306.rs b/examples/analog-stopwatch-with-spi-ssd1306.rs index 8077d759..ff78a3b2 100644 --- a/examples/analog-stopwatch-with-spi-ssd1306.rs +++ b/examples/analog-stopwatch-with-spi-ssd1306.rs @@ -84,12 +84,12 @@ fn main() -> ! { let cp = cortex_m::peripheral::Peripherals::take().unwrap(); dp.RCC.apb2enr().write(|w| w.syscfgen().enabled()); - let rcc = setup_clocks(dp.RCC); + let mut rcc = setup_clocks(dp.RCC); - let mut syscfg = dp.SYSCFG.constrain(); + let mut syscfg = dp.SYSCFG.constrain(&mut rcc); - let gpioa = dp.GPIOA.split(); - let gpioe = dp.GPIOE.split(); + let gpioa = dp.GPIOA.split(&mut rcc); + let gpioe = dp.GPIOE.split(&mut rcc); let mut board_btn = gpioa.pa0.into_pull_down_input(); board_btn.make_interrupt_source(&mut syscfg); @@ -115,11 +115,11 @@ fn main() -> ! { phase: Phase::CaptureOnFirstTransition, }, 2000.kHz(), - &rcc.clocks, + &mut rcc, ); // Set up the LEDs. On the stm32f429i-disco they are connected to pin PG13 and PG14. - let gpiog = dp.GPIOG.split(); + let gpiog = dp.GPIOG.split(&mut rcc); let mut led3 = gpiog.pg13.into_push_pull_output(); let mut led4 = gpiog.pg14.into_push_pull_output(); @@ -140,7 +140,7 @@ fn main() -> ! { disp.flush().unwrap(); // Create a 1ms periodic interrupt from TIM2 - let mut timer = FTimer::new(dp.TIM2, &rcc.clocks).counter(); + let mut timer = FTimer::new(dp.TIM2, &mut rcc).counter(); timer.start(1.secs()).unwrap(); timer.listen(Event::Update); diff --git a/examples/blinky-timer-irq.rs b/examples/blinky-timer-irq.rs index de5d0fa4..2110e80e 100644 --- a/examples/blinky-timer-irq.rs +++ b/examples/blinky-timer-irq.rs @@ -66,10 +66,10 @@ fn TIM2() { fn main() -> ! { let dp = Peripherals::take().unwrap(); - let rcc = dp.RCC.freeze(Config::hsi().sysclk(16.MHz()).pclk1(8.MHz())); + let mut rcc = dp.RCC.freeze(Config::hsi().sysclk(16.MHz()).pclk1(8.MHz())); // Configure PA5 pin to blink LED - let gpioa = dp.GPIOA.split(); + let gpioa = dp.GPIOA.split(&mut rcc); let mut led = gpioa.pa5.into_push_pull_output(); led.set_high(); // Turn off @@ -77,7 +77,7 @@ fn main() -> ! { cortex_m::interrupt::free(|cs| *G_LED.borrow(cs).borrow_mut() = Some(led)); // Set up a timer expiring after 1s - let mut timer = dp.TIM2.counter(&rcc.clocks); + let mut timer = dp.TIM2.counter(&mut rcc); timer.start(1.secs()).unwrap(); // Generate an interrupt when the timer expires diff --git a/examples/blinky.rs b/examples/blinky.rs index efddc884..a76c3451 100644 --- a/examples/blinky.rs +++ b/examples/blinky.rs @@ -16,7 +16,9 @@ use cortex_m_rt::entry; fn main() -> ! { let p = pac::Peripherals::take().unwrap(); - let gpioc = p.GPIOC.split(); + let mut rcc = p.RCC.constrain(); + + let gpioc = p.GPIOC.split(&mut rcc); let mut led = gpioc.pc13.into_push_pull_output(); loop { diff --git a/examples/can-send.rs b/examples/can-send.rs index 3476af1c..acca08e1 100644 --- a/examples/can-send.rs +++ b/examples/can-send.rs @@ -20,16 +20,16 @@ fn main() -> ! { // To meet CAN clock accuracy requirements an external crystal or ceramic // resonator must be used. The blue pill has a 8MHz external crystal. // Other boards might have a crystal with another frequency or none at all. - let _rcc = dp.RCC.freeze(Config::hse(8.MHz())); + let mut rcc = dp.RCC.freeze(Config::hse(8.MHz())); - let gpiob = dp.GPIOB.split(); + let gpiob = dp.GPIOB.split(&mut rcc); let mut can1 = { let rx = gpiob.pb8; let tx = gpiob.pb9; // let can = Can::new(dp.CAN1, (tx, rx)); // or - let can = dp.CAN1.can((tx, rx)); + let can = dp.CAN1.can((tx, rx), &mut rcc); bxcan::Can::builder(can) // APB1 (PCLK1): 8MHz, Bit rate: 500kBit/s, Sample Point 87.5% @@ -46,7 +46,7 @@ fn main() -> ! { let tx = gpiob.pb13; let rx = gpiob.pb12; - let can = dp.CAN2.can((tx, rx)); + let can = dp.CAN2.can((tx, rx), &mut rcc); let can2 = bxcan::Can::builder(can) // APB1 (PCLK1): 8MHz, Bit rate: 500kBit/s, Sample Point 87.5% diff --git a/examples/delay-syst-blinky.rs b/examples/delay-syst-blinky.rs index 98642cb4..bf12724d 100644 --- a/examples/delay-syst-blinky.rs +++ b/examples/delay-syst-blinky.rs @@ -19,13 +19,13 @@ fn main() -> ! { pac::Peripherals::take(), cortex_m::peripheral::Peripherals::take(), ) { + // Set up the system clock. We want to run at 48MHz for this one. + let mut rcc = dp.RCC.freeze(Config::hsi().sysclk(48.MHz())); + // Set up the LED. On the Nucleo-446RE it's connected to pin PA5. - let gpioa = dp.GPIOA.split(); + let gpioa = dp.GPIOA.split(&mut rcc); let mut led = gpioa.pa5.into_push_pull_output(); - // Set up the system clock. We want to run at 48MHz for this one. - let rcc = dp.RCC.freeze(Config::hsi().sysclk(48.MHz())); - // Create a delay abstraction based on SysTick let mut delay = cp.SYST.delay(&rcc.clocks); diff --git a/examples/delay-timer-blinky.rs b/examples/delay-timer-blinky.rs index 8f2553ec..1aedbe32 100644 --- a/examples/delay-timer-blinky.rs +++ b/examples/delay-timer-blinky.rs @@ -19,15 +19,15 @@ fn main() -> ! { pac::Peripherals::take(), cortex_m::peripheral::Peripherals::take(), ) { + // Set up the system clock. We want to run at 48MHz for this one. + let mut rcc = dp.RCC.freeze(Config::hse(25.MHz()).sysclk(48.MHz())); + // Set up the LED. On the Mini-F4 it's connected to pin PC13. - let gpioc = dp.GPIOC.split(); + let gpioc = dp.GPIOC.split(&mut rcc); let mut led = gpioc.pc13.into_push_pull_output(); - // Set up the system clock. We want to run at 48MHz for this one. - let rcc = dp.RCC.freeze(Config::hse(25.MHz()).sysclk(48.MHz())); - // Create a delay abstraction based on general-pupose 32-bit timer TIM5 - let mut delay = dp.TIM5.delay_us(&rcc.clocks); + let mut delay = dp.TIM5.delay_us(&mut rcc); loop { // On for 1s, off for 3s. diff --git a/examples/display-touch.rs b/examples/display-touch.rs index 1fbc79fc..85c47231 100644 --- a/examples/display-touch.rs +++ b/examples/display-touch.rs @@ -53,15 +53,15 @@ fn main() -> ! { let p = pac::Peripherals::take().unwrap(); let cp = cortex_m::Peripherals::take().unwrap(); - let rcc = p.RCC.freeze(Config::hsi().sysclk(100.MHz())); + let mut rcc = p.RCC.freeze(Config::hsi().sysclk(100.MHz())); let mut delay = cp.SYST.delay(&rcc.clocks); - let gpiob = p.GPIOB.split(); - let gpioc = p.GPIOC.split(); - let gpiod = p.GPIOD.split(); - let gpioe = p.GPIOE.split(); - let gpiof = p.GPIOF.split(); - let gpiog = p.GPIOG.split(); + let gpiob = p.GPIOB.split(&mut rcc); + let gpioc = p.GPIOC.split(&mut rcc); + let gpiod = p.GPIOD.split(&mut rcc); + let gpioe = p.GPIOE.split(&mut rcc); + let gpiof = p.GPIOF.split(&mut rcc); + let gpiog = p.GPIOG.split(&mut rcc); // Pins connected to the LCD on the board use stm32f4xx_hal::gpio::alt::fsmc as alt; @@ -120,7 +120,7 @@ fn main() -> ! { let read_timing = Timing::default().data(8).address_setup(8).bus_turnaround(0); // Initialise FSMC memory provider - let (_fsmc, interface) = FsmcLcd::new(p.FSMC, lcd_pins, &read_timing, &write_timing); + let (_fsmc, interface) = FsmcLcd::new(p.FSMC, lcd_pins, &read_timing, &write_timing, &mut rcc); // Pass display-interface instance ST7789 driver to setup a new display let mut disp = ST7789::new( @@ -146,7 +146,7 @@ fn main() -> ! { // STM32F412 uses I2c1 type for i2c bus. // The pins are mentioned in documentation -um2135-discovery-kit-with-stm32f412zg-mcu-stmicroelectronics #[cfg(feature = "stm32f412")] - let mut i2c = { I2c::new(p.I2C1, (gpiob.pb6, gpiob.pb7), 400.kHz(), &rcc.clocks) }; + let mut i2c = { I2c::new(p.I2C1, (gpiob.pb6, gpiob.pb7), 400.kHz(), &mut rcc) }; // STM32F413 uses FMPI2C1 type. // The pins are mentioned in documentation -um2135-discovery-kit-with-stm32f413zh-mcu-stmicroelectronics diff --git a/examples/dwt-blinky.rs b/examples/dwt-blinky.rs index 05c3fbec..c538239d 100644 --- a/examples/dwt-blinky.rs +++ b/examples/dwt-blinky.rs @@ -19,14 +19,14 @@ fn main() -> ! { pac::Peripherals::take(), cortex_m::peripheral::Peripherals::take(), ) { + // Set up the system clock. We want to run at 48MHz for this one. + let mut rcc = dp.RCC.freeze(Config::hsi().sysclk(48.MHz())); + // Set up the LEDs. On the STM32F429I-DISC[O1] they are connected to pin PG13/14. - let gpiog = dp.GPIOG.split(); + let gpiog = dp.GPIOG.split(&mut rcc); let mut led1 = gpiog.pg13.into_push_pull_output(); let mut led2 = gpiog.pg14.into_push_pull_output(); - // Set up the system clock. We want to run at 48MHz for this one. - let rcc = dp.RCC.freeze(Config::hsi().sysclk(48.MHz())); - // Create a delay abstraction based on DWT cycle counter let dwt = cp.DWT.constrain(cp.DCB, &rcc.clocks); let mut delay = dwt.delay(); diff --git a/examples/dynamic-gpio.rs b/examples/dynamic-gpio.rs index ed42ebe1..d7b79345 100644 --- a/examples/dynamic-gpio.rs +++ b/examples/dynamic-gpio.rs @@ -20,10 +20,10 @@ fn main() -> ! { // Take ownership over raw device and convert it into the corresponding HAL struct // Freeze the configuration of all the clocks in the system and store the frozen frequencies in // `clocks` - let rcc = dp.RCC.constrain(); + let mut rcc = dp.RCC.constrain(); // Acquire the GPIOC peripheral - let gpioc = dp.GPIOC.split(); + let gpioc = dp.GPIOC.split(&mut rcc); let mut pin = gpioc.pc13.into_dynamic(); // Configure the syst timer to trigger an update every second diff --git a/examples/f413disco-lcd-ferris.rs b/examples/f413disco-lcd-ferris.rs index 05054ed8..71ae8308 100644 --- a/examples/f413disco-lcd-ferris.rs +++ b/examples/f413disco-lcd-ferris.rs @@ -697,15 +697,15 @@ fn main() -> ! { rtt_init_print!(ChannelMode::NoBlockTrim); if let (Some(p), Some(cp)) = (Peripherals::take(), CorePeripherals::take()) { - // Split all the GPIO blocks we need - let gpiob = p.GPIOB.split(); - let gpiod = p.GPIOD.split(); - let gpioe = p.GPIOE.split(); - let gpiof = p.GPIOF.split(); - let gpiog = p.GPIOG.split(); - // Configure and lock the clocks at maximum warp - let rcc = p.RCC.freeze(Config::hsi().sysclk(100.MHz())); + let mut rcc = p.RCC.freeze(Config::hsi().sysclk(100.MHz())); + + // Split all the GPIO blocks we need + let gpiob = p.GPIOB.split(&mut rcc); + let gpiod = p.GPIOD.split(&mut rcc); + let gpioe = p.GPIOE.split(&mut rcc); + let gpiof = p.GPIOF.split(&mut rcc); + let gpiog = p.GPIOG.split(&mut rcc); // Define the pins we need for our 16bit parallel bus use stm32f4xx_hal::gpio::alt::fsmc as alt; @@ -735,7 +735,8 @@ fn main() -> ! { let read_timing = Timing::default().data(8).address_setup(8).bus_turnaround(0); // Initialise FSMC memory provider - let (_fsmc, interface) = FsmcLcd::new(p.FSMC, lcd_pins, &read_timing, &write_timing); + let (_fsmc, interface) = + FsmcLcd::new(p.FSMC, lcd_pins, &read_timing, &write_timing, &mut rcc); // Pass display-interface instance ST7789 driver to setup a new display let mut disp = ST7789::new( diff --git a/examples/f469disco-lcd-test.rs b/examples/f469disco-lcd-test.rs index 1dcf36b0..5c9e89cd 100644 --- a/examples/f469disco-lcd-test.rs +++ b/examples/f469disco-lcd-test.rs @@ -53,12 +53,12 @@ fn main() -> ! { let cp = CorePeripherals::take().unwrap(); let hse_freq = 8.MHz(); - let rcc = dp + let mut rcc = dp .RCC .freeze(Config::hse(hse_freq).pclk2(32.MHz()).sysclk(180.MHz())); let mut delay = cp.SYST.delay(&rcc.clocks); - let gpioh = dp.GPIOH.split(); + let gpioh = dp.GPIOH.split(&mut rcc); // Reset display let mut lcd_reset = gpioh.ph7.into_push_pull_output(); @@ -107,7 +107,7 @@ fn main() -> ! { DISPLAY_CONFIGURATION, dsi_config, dp.DSI, - &rcc.clocks, + &mut rcc, ) .unwrap(); diff --git a/examples/fmc-sdram.rs b/examples/fmc-sdram.rs index 0c0f71dd..d98da423 100644 --- a/examples/fmc-sdram.rs +++ b/examples/fmc-sdram.rs @@ -49,17 +49,17 @@ impl XorShift32 { #[entry] fn main() -> ! { if let (Some(p), Some(cp)) = (pac::Peripherals::take(), Peripherals::take()) { - let rcc = p.RCC.freeze(Config::hsi().sysclk(180.MHz())); + let mut rcc = p.RCC.freeze(Config::hsi().sysclk(180.MHz())); let mut delay = cp.SYST.delay(&rcc.clocks); - let gpioc = p.GPIOC.split(); - let gpiod = p.GPIOD.split(); - let gpioe = p.GPIOE.split(); - let gpiof = p.GPIOF.split(); - let gpiog = p.GPIOG.split(); - let gpioh = p.GPIOH.split(); - let gpioi = p.GPIOI.split(); + let gpioc = p.GPIOC.split(&mut rcc); + let gpiod = p.GPIOD.split(&mut rcc); + let gpioe = p.GPIOE.split(&mut rcc); + let gpiof = p.GPIOF.split(&mut rcc); + let gpiog = p.GPIOG.split(&mut rcc); + let gpioh = p.GPIOH.split(&mut rcc); + let gpioi = p.GPIOI.split(&mut rcc); #[rustfmt::skip] let pins = fmc_pins! { diff --git a/examples/hd44780.rs b/examples/hd44780.rs index 90005443..6471efb5 100644 --- a/examples/hd44780.rs +++ b/examples/hd44780.rs @@ -22,10 +22,10 @@ use stm32f4xx_hal::{pac, prelude::*}; fn main() -> ! { let dp = pac::Peripherals::take().unwrap(); - let rcc = dp.RCC.constrain(); - let gpiob = dp.GPIOB.split(); + let mut rcc = dp.RCC.constrain(); + let gpiob = dp.GPIOB.split(&mut rcc); - let mut delay = dp.TIM1.delay_us(&rcc.clocks); + let mut delay = dp.TIM1.delay_us(&mut rcc); let rs = gpiob.pb7.into_push_pull_output(); let en = gpiob.pb8.into_push_pull_output(); diff --git a/examples/i2c_scanner.rs b/examples/i2c_scanner.rs index f423649c..080cb645 100644 --- a/examples/i2c_scanner.rs +++ b/examples/i2c_scanner.rs @@ -19,9 +19,9 @@ fn main() -> ! { rtt_init_print!(); let dp = pac::Peripherals::take().unwrap(); - let rcc = dp.RCC.constrain(); + let mut rcc = dp.RCC.constrain(); - let gpiob = dp.GPIOB.split(); + let gpiob = dp.GPIOB.split(&mut rcc); // Configure I2C1 let scl = gpiob.pb8; @@ -30,7 +30,7 @@ fn main() -> ! { dp.I2C1, (scl, sda), hal::i2c::Mode::standard(100.kHz()), - &rcc.clocks, + &mut rcc, ); rprintln!("Start i2c scanning..."); diff --git a/examples/i2s-audio-out.rs b/examples/i2s-audio-out.rs index fadf8215..0e994085 100644 --- a/examples/i2s-audio-out.rs +++ b/examples/i2s-audio-out.rs @@ -91,19 +91,19 @@ fn main() -> ! { rtt_init_print!(); let dp = Peripherals::take().unwrap(); - let gpioa = dp.GPIOA.split(); - let gpioc = dp.GPIOC.split(); - // The 61440 kHz frequency can be divided to get exactly 48 kHz sample rate even when // generating master clock - let rcc = dp.RCC.freeze( + let mut rcc = dp.RCC.freeze( Config::hse(8u32.MHz()) .sysclk(96.MHz()) .i2s_clk(61440.kHz()), ); + let gpioa = dp.GPIOA.split(&mut rcc); + let gpioc = dp.GPIOC.split(&mut rcc); + let i2s_pins = (gpioa.pa4, gpioc.pc10, SPI3::NoMck, gpioc.pc12); - let i2s = I2s::new(dp.SPI3, i2s_pins, &rcc.clocks); + let i2s = I2s::new(dp.SPI3, i2s_pins, &mut rcc); let i2s_config = I2sTransferConfig::new_master() .transmit() .standard(Philips) diff --git a/examples/ist7920-bidi-normal-spi.rs b/examples/ist7920-bidi-normal-spi.rs index 4bb902e4..7a3dd358 100644 --- a/examples/ist7920-bidi-normal-spi.rs +++ b/examples/ist7920-bidi-normal-spi.rs @@ -19,9 +19,10 @@ fn main() -> ! { let dp = pac::Peripherals::take().unwrap(); let cp = cortex_m::peripheral::Peripherals::take().unwrap(); - let gpioa = dp.GPIOA.split(); - let gpiob = dp.GPIOB.split(); - let rcc = dp.RCC.constrain(); + let mut rcc = dp.RCC.constrain(); + + let gpioa = dp.GPIOA.split(&mut rcc); + let gpiob = dp.GPIOB.split(&mut rcc); let mut led = gpioa.pa5.into_push_pull_output(); led.set_low(); @@ -41,11 +42,11 @@ fn main() -> ! { }; // Change spi transfer mode to Bidi for more efficient operations. - // let spi = Spi::new(dp.SPI1, (Some(sck), Some(miso), Some(mosi)), mode, 8.MHz(), &rcc.clocks).to_bidi_transfer_mode(); + // let spi = Spi::new(dp.SPI1, (Some(sck), Some(miso), Some(mosi)), mode, 8.MHz(), &mut rcc).to_bidi_transfer_mode(); // or let spi = dp .SPI1 - .spi_bidi((Some(sck), Some(mosi)), mode, 8.MHz(), &rcc.clocks); + .spi_bidi((Some(sck), Some(mosi)), mode, 8.MHz(), &mut rcc); let iface = SPIInterface::new(spi, dc, cs); diff --git a/examples/ltdc-screen/main.rs b/examples/ltdc-screen/main.rs index d33b8126..0c573707 100644 --- a/examples/ltdc-screen/main.rs +++ b/examples/ltdc-screen/main.rs @@ -35,17 +35,17 @@ fn main() -> ! { let perif = pac::Peripherals::take().unwrap(); let _cp = cortex_m::Peripherals::take().unwrap(); - let rcc_hal: Rcc = perif.RCC.constrain(); + let mut rcc_hal: Rcc = perif.RCC.constrain(); // Set up pins - let _gpioa = perif.GPIOA.split(); - let _gpiob = perif.GPIOB.split(); - let gpioe = perif.GPIOE.split(); - let gpiog = perif.GPIOG.split(); - let gpioh = perif.GPIOH.split(); - let gpioi = perif.GPIOI.split(); - let gpioj = perif.GPIOJ.split(); - let gpiok = perif.GPIOK.split(); + let _gpioa = perif.GPIOA.split(&mut rcc_hal); + let _gpiob = perif.GPIOB.split(&mut rcc_hal); + let gpioe = perif.GPIOE.split(&mut rcc_hal); + let gpiog = perif.GPIOG.split(&mut rcc_hal); + let gpioh = perif.GPIOH.split(&mut rcc_hal); + let gpioi = perif.GPIOI.split(&mut rcc_hal); + let gpioj = perif.GPIOJ.split(&mut rcc_hal); + let gpiok = perif.GPIOK.split(&mut rcc_hal); let pins = LtdcPins::new( RedPins::new( diff --git a/examples/pwm-dead-time.rs b/examples/pwm-dead-time.rs index f72ca0c2..f12dd7bb 100644 --- a/examples/pwm-dead-time.rs +++ b/examples/pwm-dead-time.rs @@ -15,11 +15,11 @@ use hal::{pac, prelude::*, timer::Polarity}; fn main() -> ! { if let Some(dp) = pac::Peripherals::take() { // Set up the system clock. We want to run at 84MHz for this one. - let rcc = dp.RCC.freeze(Config::hsi().sysclk(25.MHz())); + let mut rcc = dp.RCC.freeze(Config::hsi().sysclk(25.MHz())); - let gpioa = dp.GPIOA.split(); + let gpioa = dp.GPIOA.split(&mut rcc); - let (mut pwm_mngr, (pwm_c1, ..)) = dp.TIM1.pwm_hz(20.kHz(), &rcc.clocks); + let (mut pwm_mngr, (pwm_c1, ..)) = dp.TIM1.pwm_hz(20.kHz(), &mut rcc); let mut pwm_c1 = pwm_c1.with(gpioa.pa8).with_complementary(gpioa.pa7); diff --git a/examples/pwm-input.rs b/examples/pwm-input.rs index e56a717b..0605d6d6 100644 --- a/examples/pwm-input.rs +++ b/examples/pwm-input.rs @@ -12,13 +12,13 @@ use stm32f4xx_hal::{pac, prelude::*, timer::Timer}; fn main() -> ! { if let Some(dp) = pac::Peripherals::take() { // Set up the system clock. - let rcc = dp.RCC.constrain(); + let mut rcc = dp.RCC.constrain(); - let gpioa = dp.GPIOA.split(); - let gpioc = dp.GPIOC.split(); + let gpioa = dp.GPIOA.split(&mut rcc); + let gpioc = dp.GPIOC.split(&mut rcc); // configure tim1 as a PWM output of known frequency. - let (_, (ch1, ch2, ..)) = Timer::new(dp.TIM1, &rcc.clocks).pwm_hz(501.Hz()); + let (_, (ch1, ch2, ..)) = Timer::new(dp.TIM1, &mut rcc).pwm_hz(501.Hz()); let mut ch1 = ch1.with(gpioa.pa8); let mut _ch2 = ch2.with(gpioa.pa9); let max_duty = ch1.get_max_duty(); @@ -29,7 +29,7 @@ fn main() -> ! { let pwm_reader_ch1 = gpioc.pc6; // configure tim8 as a PWM input, using the best-guess frequency of the input signal. - let monitor = Timer::new(dp.TIM8, &rcc.clocks).pwm_input(500.Hz(), pwm_reader_ch1); + let monitor = Timer::new(dp.TIM8, &mut rcc).pwm_input(500.Hz(), pwm_reader_ch1); // NOTE: this value may only be accurately observed at the CC2 interrupt. let _duty = monitor.get_duty_cycle(); diff --git a/examples/pwm-sinus.rs b/examples/pwm-sinus.rs index 7fce8650..ef9b2976 100644 --- a/examples/pwm-sinus.rs +++ b/examples/pwm-sinus.rs @@ -14,15 +14,15 @@ use stm32f4xx_hal::{pac, prelude::*, rcc::Config}; fn main() -> ! { if let Some(dp) = pac::Peripherals::take() { // Set up the system clock. - let rcc = dp.RCC.freeze(Config::hse(25.MHz())); + let mut rcc = dp.RCC.freeze(Config::hse(25.MHz())); - let gpioa = dp.GPIOA.split(); + let gpioa = dp.GPIOA.split(&mut rcc); - let (_, (pwm_c1, pwm_c2, ..)) = dp.TIM1.pwm_us(100.micros(), &rcc.clocks); + let (_, (pwm_c1, pwm_c2, ..)) = dp.TIM1.pwm_us(100.micros(), &mut rcc); let mut pwm_c1 = pwm_c1.with(gpioa.pa8); let mut pwm_c2 = pwm_c2.with(gpioa.pa9); - let mut counter = dp.TIM2.counter_us(&rcc.clocks); + let mut counter = dp.TIM2.counter_us(&mut rcc); let max_duty = pwm_c1.get_max_duty(); const N: usize = 50; diff --git a/examples/pwm.rs b/examples/pwm.rs index 39cc47c5..11ab6351 100644 --- a/examples/pwm.rs +++ b/examples/pwm.rs @@ -12,11 +12,11 @@ use stm32f4xx_hal::{pac, prelude::*}; fn main() -> ! { if let Some(dp) = pac::Peripherals::take() { // Set up the system clock. - let rcc = dp.RCC.constrain(); + let mut rcc = dp.RCC.constrain(); - let gpioa = dp.GPIOA.split(); + let gpioa = dp.GPIOA.split(&mut rcc); - let (_, (ch1, ch2, ..)) = dp.TIM1.pwm_us(100.micros(), &rcc.clocks); + let (_, (ch1, ch2, ..)) = dp.TIM1.pwm_us(100.micros(), &mut rcc); let mut ch1 = ch1.with(gpioa.pa8); let mut _ch2 = ch2.with(gpioa.pa9); diff --git a/examples/qei.rs b/examples/qei.rs index 205ee177..4a019664 100644 --- a/examples/qei.rs +++ b/examples/qei.rs @@ -21,23 +21,23 @@ fn main() -> ! { let dp = pac::Peripherals::take().expect("Failed to get stm32 peripherals"); let cp = cortex_m::peripheral::Peripherals::take().expect("Failed to get cortex_m peripherals"); + // Set up the system clock. + let mut rcc = dp.RCC.constrain(); + // Set up the LED. This is pin C13 on the "black pill" USB C board here: // https://stm32-base.org/boards/STM32F411CEU6-WeAct-Black-Pill-V2.0 - let gpioc = dp.GPIOC.split(); + let gpioc = dp.GPIOC.split(&mut rcc); let mut led = gpioc.pc13.into_push_pull_output(); - // Set up the system clock. - let rcc = dp.RCC.constrain(); - // Create a delay abstraction based on SysTick. let mut delay = cp.SYST.delay(&rcc.clocks); - let gpioa = dp.GPIOA.split(); + let gpioa = dp.GPIOA.split(&mut rcc); // Connect a rotary encoder to pins A0 and A1. let rotary_encoder_pins = (gpioa.pa0, gpioa.pa1); let rotary_encoder_timer = dp.TIM2; - let rotary_encoder = Qei::new(rotary_encoder_timer, rotary_encoder_pins); + let rotary_encoder = Qei::new(rotary_encoder_timer, rotary_encoder_pins, &mut rcc); let mut current_count = rotary_encoder.count(); diff --git a/examples/qspi-w25q.rs b/examples/qspi-w25q.rs index 019cf1ed..e1a95122 100644 --- a/examples/qspi-w25q.rs +++ b/examples/qspi-w25q.rs @@ -8,11 +8,11 @@ use cortex_m_rt::entry; use cortex_m_semihosting::hprintln; use panic_semihosting as _; use stm32f4xx_hal as hal; -use stm32f4xx_hal::gpio::GpioExt; use stm32f4xx_hal::qspi::{ FlashSize, MemoryMapped, Qspi, QspiConfig, QspiError, QspiMemoryMappedConfig, QspiMode, QspiPins, QspiReadCommand, QspiWriteCommand, }; +use stm32f4xx_hal::{gpio::GpioExt, rcc::RccExt}; pub struct W25Q { qspi: Qspi, @@ -147,10 +147,13 @@ where #[entry] fn main() -> ! { if let Some(dp) = stm32f4xx_hal::pac::Peripherals::take() { - let gpioa = dp.GPIOA.split(); - let gpiob = dp.GPIOB.split(); - let gpiod = dp.GPIOD.split(); - let gpioe = dp.GPIOE.split(); + // Set up the system clock. + let mut rcc = dp.RCC.constrain(); + + let gpioa = dp.GPIOA.split(&mut rcc); + let gpiob = dp.GPIOB.split(&mut rcc); + let gpiod = dp.GPIOD.split(&mut rcc); + let gpioe = dp.GPIOE.split(&mut rcc); let qspi = Qspi::bank1( dp.QUADSPI, @@ -162,6 +165,7 @@ fn main() -> ! { .flash_size(FlashSize::from_megabytes(16)) .clock_prescaler(0) .sample_shift(hal::qspi::SampleShift::HalfACycle), + &mut rcc, ); let mut flash = W25Q::new(qspi).unwrap(); diff --git a/examples/rng-display.rs b/examples/rng-display.rs index 24b5105f..078939da 100644 --- a/examples/rng-display.rs +++ b/examples/rng-display.rs @@ -59,17 +59,17 @@ fn main() -> ! { // here we pick a simple clock configuration that ensures the pll48clk, // from which RNG_CLK is derived, is about 48 MHz // discovery board has 8 MHz crystal for HSE - let rcc = dp.RCC.freeze(Config::hse(8.MHz()).sysclk(128.MHz())); + let mut rcc = dp.RCC.freeze(Config::hse(8.MHz()).sysclk(128.MHz())); let mut delay_source = cp.SYST.delay(&rcc.clocks); // Set up I2C1: SCL is PB8 and SDA is PB9; they are set to Alternate Function 4 // as per the STM32F407 datasheet. Pin assignment as per the // stm32f4-discovery (ST32F407G-DISC1) board. - let gpiob = dp.GPIOB.split(); + let gpiob = dp.GPIOB.split(&mut rcc); let scl = gpiob.pb8; let sda = gpiob.pb9; - let i2c = I2c::new(dp.I2C1, (scl, sda), 400.kHz(), &rcc.clocks); + let i2c = I2c::new(dp.I2C1, (scl, sda), 400.kHz(), &mut rcc); // Set up the display let interface = I2CDisplayInterface::new(i2c); @@ -79,7 +79,7 @@ fn main() -> ! { // enable the RNG peripheral and its clock // this will panic if the clock configuration is unsuitable - let mut rand_source = dp.RNG.constrain(&rcc.clocks); + let mut rand_source = dp.RNG.constrain(&mut rcc); let mut format_buf = String::<20>::new(); loop { //display clear diff --git a/examples/rtc.rs b/examples/rtc.rs index 71489d1a..8d0cf18b 100644 --- a/examples/rtc.rs +++ b/examples/rtc.rs @@ -19,10 +19,10 @@ use time::{ fn main() -> ! { rtt_init_print!(); let mut p = pac::Peripherals::take().unwrap(); - let rcc = p.RCC.constrain(); + let mut rcc = p.RCC.constrain(); - let mut rtc = Rtc::new(p.RTC, &mut p.PWR); - let mut delay = p.TIM5.delay_us(&rcc.clocks); + let mut rtc = Rtc::new(p.RTC, &mut rcc, &mut p.PWR); + let mut delay = p.TIM5.delay_us(&mut rcc); rtc.set_datetime(&PrimitiveDateTime::new( date!(2022 - 02 - 07), diff --git a/examples/rtc_alarm.rs b/examples/rtc_alarm.rs index 7fb7d0ea..6f023215 100644 --- a/examples/rtc_alarm.rs +++ b/examples/rtc_alarm.rs @@ -31,8 +31,8 @@ fn main() -> ! { let mut p = hal::pac::Peripherals::take().unwrap(); - let _rcc = p.RCC.constrain(); - let mut rtc = Rtc::new(p.RTC, &mut p.PWR); + let mut rcc = p.RCC.constrain(); + let mut rtc = Rtc::new(p.RTC, &mut rcc, &mut p.PWR); let today = date!(2023 - 05 - 28); rtc.set_datetime(&PrimitiveDateTime::new(today, time!(21:57:32))) diff --git a/examples/rtic-adc-dma.rs b/examples/rtic-adc-dma.rs index a22e8617..cd9ca35e 100644 --- a/examples/rtic-adc-dma.rs +++ b/examples/rtic-adc-dma.rs @@ -42,7 +42,7 @@ mod app { fn init(cx: init::Context) -> (Shared, Local, init::Monotonics) { let device: pac::Peripherals = cx.device; - let _rcc = device.RCC.freeze( + let mut rcc = device.RCC.freeze( Config::hse(25.MHz()) .require_pll48clk() .sysclk(MONO_HZ.Hz()) @@ -57,10 +57,10 @@ mod app { let mono = DwtSystick::new(&mut dcb, dwt, systick, MONO_HZ); - let gpiob = device.GPIOB.split(); + let gpiob = device.GPIOB.split(&mut rcc); let voltage = gpiob.pb1.into_analog(); - let dma = StreamsTuple::new(device.DMA2); + let dma = StreamsTuple::new(device.DMA2, &mut rcc); let config = DmaConfig::default() .transfer_complete_interrupt(true) @@ -71,7 +71,7 @@ mod app { .dma(Dma::Continuous) .scan(Scan::Enabled); - let mut adc = Adc::new(device.ADC1, true, adc_config); + let mut adc = Adc::new(device.ADC1, true, adc_config, &mut rcc); adc.configure_channel(&Temperature, Sequence::One, SampleTime::Cycles_480); adc.configure_channel(&voltage, Sequence::Two, SampleTime::Cycles_480); adc.enable_temperature_and_vref(); diff --git a/examples/rtic-button.rs b/examples/rtic-button.rs index 05c2519f..0dc6e7a2 100644 --- a/examples/rtic-button.rs +++ b/examples/rtic-button.rs @@ -26,16 +26,16 @@ mod app { #[init] fn init(mut ctx: init::Context) -> (Shared, Local, init::Monotonics) { - // syscfg - let mut syscfg = ctx.device.SYSCFG.constrain(); // clocks - let _rcc = ctx + let mut rcc = ctx .device .RCC .freeze(Config::hse(25.MHz()).sysclk(SYSFREQ.Hz())); + // syscfg + let mut syscfg = ctx.device.SYSCFG.constrain(&mut rcc); // gpio ports A and C - let gpioa = ctx.device.GPIOA.split(); - let gpioc = ctx.device.GPIOC.split(); + let gpioa = ctx.device.GPIOA.split(&mut rcc); + let gpioc = ctx.device.GPIOC.split(&mut rcc); // button let mut button = Input::new(gpioa.pa0, Pull::Up); // or diff --git a/examples/rtic-dual-i2s-audio-in-out.rs b/examples/rtic-dual-i2s-audio-in-out.rs index 5c778d9f..49b1ff89 100644 --- a/examples/rtic-dual-i2s-audio-in-out.rs +++ b/examples/rtic-dual-i2s-audio-in-out.rs @@ -149,11 +149,8 @@ mod app { let (adc_p, process_c) = queue_1.split(); let (process_p, dac_c) = queue_2.split(); let device = cx.device; - let mut syscfg = device.SYSCFG.constrain(); let mut exti = device.EXTI; - let gpiob = device.GPIOB.split(); - let gpioc = device.GPIOC.split(); - let rcc = device.RCC.freeze( + let mut rcc = device.RCC.freeze( Config::hse(8u32.MHz()) .sysclk(96.MHz()) .hclk(96.MHz()) @@ -161,6 +158,9 @@ mod app { .pclk2(100.MHz()) .i2s_clk(61440.kHz()), ); + let mut syscfg = device.SYSCFG.constrain(&mut rcc); + let gpiob = device.GPIOB.split(&mut rcc); + let gpioc = device.GPIOC.split(&mut rcc); // I2S pins: (WS, CK, MCLK, SD) for I2S2 let i2s2_pins = ( @@ -170,7 +170,7 @@ mod app { gpiob.pb15, //SD gpiob.pb14, //ExtSD ); - let i2s2 = DualI2s::new(device.SPI2, device.I2S2EXT, i2s2_pins, &rcc.clocks); + let i2s2 = DualI2s::new(device.SPI2, device.I2S2EXT, i2s2_pins, &mut rcc); let i2s2_config = DualI2sDriverConfig::new_master() .direction(Receive, Transmit) .standard(Philips) diff --git a/examples/rtic-i2s-audio-in-out.rs b/examples/rtic-i2s-audio-in-out.rs index 7d5327de..2eb23ab4 100644 --- a/examples/rtic-i2s-audio-in-out.rs +++ b/examples/rtic-i2s-audio-in-out.rs @@ -152,12 +152,8 @@ mod app { let (adc_p, process_c) = queue_1.split(); let (process_p, dac_c) = queue_2.split(); let device = cx.device; - let mut syscfg = device.SYSCFG.constrain(); let mut exti = device.EXTI; - let gpioa = device.GPIOA.split(); - let gpiob = device.GPIOB.split(); - let gpioc = device.GPIOC.split(); - let rcc = device.RCC.freeze( + let mut rcc = device.RCC.freeze( Config::hse(8u32.MHz()) .sysclk(96.MHz()) .hclk(96.MHz()) @@ -165,6 +161,10 @@ mod app { .pclk2(100.MHz()) .i2s_clk(61440.kHz()), ); + let mut syscfg = device.SYSCFG.constrain(&mut rcc); + let gpioa = device.GPIOA.split(&mut rcc); + let gpiob = device.GPIOB.split(&mut rcc); + let gpioc = device.GPIOC.split(&mut rcc); // I2S pins: (WS, CK, MCLK, SD) for I2S2 let i2s2_pins = ( @@ -173,7 +173,7 @@ mod app { Some(gpioc.pc6), //MCK gpiob.pb15, //SD ); - let i2s2 = I2s::new(device.SPI2, i2s2_pins, &rcc.clocks); + let i2s2 = I2s::new(device.SPI2, i2s2_pins, &mut rcc); let i2s2_config = I2sDriverConfig::new_master() .receive() .standard(Philips) @@ -187,7 +187,7 @@ mod app { // I2S3 pins: (WS, CK, NoMck, SD) for I2S3 let i2s3_pins = (gpioa.pa4, gpioc.pc10, SPI3::NoMck, gpioc.pc12); - let i2s3 = I2s::new(device.SPI3, i2s3_pins, &rcc.clocks); + let i2s3 = I2s::new(device.SPI3, i2s3_pins, &mut rcc); let i2s3_config = i2s2_config.to_slave().transmit(); let mut i2s3_driver = I2sDriver::new(i2s3, i2s3_config); i2s3_driver.set_tx_interrupt(true); diff --git a/examples/rtic-serial-dma-rx-idle.rs b/examples/rtic-serial-dma-rx-idle.rs index 04fd8fc2..2d13b412 100644 --- a/examples/rtic-serial-dma-rx-idle.rs +++ b/examples/rtic-serial-dma-rx-idle.rs @@ -56,11 +56,11 @@ mod app { let core = cx.core; let dp: hal::pac::Peripherals = cx.device; - let rcc = dp.RCC.constrain(); + let mut rcc = dp.RCC.constrain(); let mono = Systick::new(core.SYST, rcc.clocks.sysclk().to_Hz()); - let gpioa = dp.GPIOA.split(); + let gpioa = dp.GPIOA.split(&mut rcc); // Initialize UART with DMA events let rx_pin = gpioa.pa10; @@ -71,14 +71,14 @@ mod app { serial::Config::default() .baudrate(9600.bps()) .dma(serial::config::DmaConfig::Rx), - &rcc.clocks, + &mut rcc, ) .unwrap(); // Listen UART IDLE event, which will be call USART1 interrupt rx.listen_idle(); - let dma2 = StreamsTuple::new(dp.DMA2); + let dma2 = StreamsTuple::new(dp.DMA2, &mut rcc); // Note! It is better to use memory pools, such as heapless::pool::Pool. But it not work with embedded_dma yet. // See CHANGELOG of unreleased main branch and issue https://github.com/japaric/heapless/pull/362 for details. diff --git a/examples/rtic-spi-slave-dma.rs b/examples/rtic-spi-slave-dma.rs index fdac75ec..38dcc3b4 100644 --- a/examples/rtic-spi-slave-dma.rs +++ b/examples/rtic-spi-slave-dma.rs @@ -54,19 +54,19 @@ mod app { let device_peripherals: hal::pac::Peripherals = cx.device; - let _rcc = device_peripherals + let mut rcc = device_peripherals .RCC .freeze(Config::hsi().sysclk(100.MHz()).pclk1(36.MHz())); let mono = Systick::new(core.SYST, 100_000_000); - let gpioc = device_peripherals.GPIOC.split(); + let gpioc = device_peripherals.GPIOC.split(&mut rcc); let mut led = gpioc.pc13.into_push_pull_output(); let gpiob = device_peripherals.GPIOB; let spi = device_peripherals.SPI3; - let gpiob = gpiob.split(); + let gpiob = gpiob.split(&mut rcc); let sck = gpiob.pb3.into_alternate(); let miso = gpiob.pb4.into_alternate(); @@ -77,12 +77,17 @@ mod app { phase: Phase::CaptureOnFirstTransition, }; - let mut spi3 = SpiSlave::new(spi, (Some(sck), Some(miso), Some(mosi), SPI3::NoNss), mode); + let mut spi3 = SpiSlave::new( + spi, + (Some(sck), Some(miso), Some(mosi), SPI3::NoNss), + mode, + &mut rcc, + ); spi3.set_internal_nss(false); let (tx, rx) = spi3.use_dma().txrx(); - let streams = StreamsTuple::new(device_peripherals.DMA1); + let streams = StreamsTuple::new(device_peripherals.DMA1, &mut rcc); let tx_stream = streams.5; let rx_stream = streams.0; diff --git a/examples/rtic-tick.rs b/examples/rtic-tick.rs index 08934adf..73f4aa81 100644 --- a/examples/rtic-tick.rs +++ b/examples/rtic-tick.rs @@ -30,14 +30,14 @@ mod app { #[init] fn init(ctx: init::Context) -> (Shared, Local, init::Monotonics) { - let rcc = ctx.device.RCC.freeze(Config::DEFAULT.sysclk(48.MHz())); + let mut rcc = ctx.device.RCC.freeze(Config::DEFAULT.sysclk(48.MHz())); - let gpioc = ctx.device.GPIOC.split(); + let gpioc = ctx.device.GPIOC.split(&mut rcc); let led = gpioc.pc13.into_push_pull_output(); defmt::info!("Start"); - //let mono = ctx.device.TIM2.monotonic_us(&rcc.clocks); - let mono = ctx.device.TIM3.monotonic64_us(&rcc.clocks); + //let mono = ctx.device.TIM2.monotonic_us(&mut rcc); + let mono = ctx.device.TIM3.monotonic64_us(&mut rcc); tick::spawn().ok(); (Shared {}, Local { led }, init::Monotonics(mono)) } diff --git a/examples/rtic-usart-shell-ssd1306.rs b/examples/rtic-usart-shell-ssd1306.rs index 64c161a8..018a0a0a 100644 --- a/examples/rtic-usart-shell-ssd1306.rs +++ b/examples/rtic-usart-shell-ssd1306.rs @@ -78,19 +78,19 @@ mod usart_shell { #[init] fn init(mut ctx: init::Context) -> (Shared, Local, init::Monotonics) { - // syscfg - let mut syscfg = ctx.device.SYSCFG.constrain(); // clocks - let rcc = ctx + let mut rcc = ctx .device .RCC .freeze(rcc::Config::hse(25.MHz()).sysclk(SYSFREQ.Hz())); + // syscfg + let mut syscfg = ctx.device.SYSCFG.constrain(&mut rcc); // monotonic timer let mono = DwtSystick::new(&mut ctx.core.DCB, ctx.core.DWT, ctx.core.SYST, SYSFREQ); // gpio ports A and C - let gpioa = ctx.device.GPIOA.split(); - let gpiob = ctx.device.GPIOB.split(); - let gpioc = ctx.device.GPIOC.split(); + let gpioa = ctx.device.GPIOA.split(&mut rcc); + let gpiob = ctx.device.GPIOB.split(&mut rcc); + let gpioc = ctx.device.GPIOC.split(&mut rcc); // button let mut button = gpioa.pa0.into_pull_up_input(); button.make_interrupt_source(&mut syscfg); @@ -101,14 +101,14 @@ mod usart_shell { // i2c let scl = gpiob.pb8; let sda = gpiob.pb9; - let i2c = I2c::new(ctx.device.I2C1, (scl, sda), 400.kHz(), &rcc.clocks); + let i2c = I2c::new(ctx.device.I2C1, (scl, sda), 400.kHz(), &mut rcc); // serial let pins = (gpioa.pa9, gpioa.pa10); let mut serial = Serial::new( ctx.device.USART1, pins, Config::default().baudrate(115_200.bps()).wordlength_8(), - &rcc.clocks, + &mut rcc, ) .unwrap() .with_u8_data(); @@ -123,8 +123,8 @@ mod usart_shell { .into_buffered_graphics_mode(); ldisp.init().unwrap(); - let mut timer = ctx.device.TIM2.counter_hz(&rcc.clocks); - //let mut timer = FTimer::new(ctx.device.TIM1, &clocks).counter_hz(); + let mut timer = ctx.device.TIM2.counter_hz(&mut rcc); + //let mut timer = FTimer::new(ctx.device.TIM1, &mut rcc).counter_hz(); timer.start(FPS.Hz()).unwrap(); timer.listen(Event::Update); diff --git a/examples/rtic-usart-shell.rs b/examples/rtic-usart-shell.rs index 410d8e64..59ffe59d 100644 --- a/examples/rtic-usart-shell.rs +++ b/examples/rtic-usart-shell.rs @@ -50,18 +50,18 @@ mod usart_shell { #[init] fn init(mut ctx: init::Context) -> (Shared, Local, init::Monotonics) { - // syscfg - let mut syscfg = ctx.device.SYSCFG.constrain(); // clocks - let rcc = ctx + let mut rcc = ctx .device .RCC .freeze(rcc::Config::hse(25.MHz()).sysclk(SYSFREQ.Hz())); + // syscfg + let mut syscfg = ctx.device.SYSCFG.constrain(&mut rcc); // monotonic timer let mono = DwtSystick::new(&mut ctx.core.DCB, ctx.core.DWT, ctx.core.SYST, SYSFREQ); // gpio ports A and C - let gpioa = ctx.device.GPIOA.split(); - let gpioc = ctx.device.GPIOC.split(); + let gpioa = ctx.device.GPIOA.split(&mut rcc); + let gpioc = ctx.device.GPIOC.split(&mut rcc); // button let mut button = gpioa.pa0.into_pull_up_input(); button.make_interrupt_source(&mut syscfg); @@ -75,7 +75,7 @@ mod usart_shell { ctx.device.USART1, pins, Config::default().baudrate(115_200.bps()).wordlength_8(), - &rcc.clocks, + &mut rcc, ) .unwrap() .with_u8_data(); diff --git a/examples/rtic-usb-cdc-echo.rs b/examples/rtic-usb-cdc-echo.rs index ce6b5919..aa824696 100644 --- a/examples/rtic-usb-cdc-echo.rs +++ b/examples/rtic-usb-cdc-echo.rs @@ -39,15 +39,15 @@ mod app { let dp = ctx.device; // Setup system clocks - let rcc = dp + let mut rcc = dp .RCC .freeze(Config::hse(25.MHz()).sysclk(84.MHz()).require_pll48clk()); - let gpioa = dp.GPIOA.split(); - let gpioc = dp.GPIOC.split(); + let gpioa = dp.GPIOA.split(&mut rcc); + let gpioc = dp.GPIOC.split(&mut rcc); let led = gpioc.pc13.into_push_pull_output(); - let mono = dp.TIM2.monotonic_us(&rcc.clocks); + let mono = dp.TIM2.monotonic_us(&mut rcc); tick::spawn().ok(); // *** Begin USB setup *** diff --git a/examples/rtic2-tick.rs b/examples/rtic2-tick.rs index 8569c3f9..f5586baa 100644 --- a/examples/rtic2-tick.rs +++ b/examples/rtic2-tick.rs @@ -40,17 +40,15 @@ mod app { #[init] fn init(mut ctx: init::Context) -> (Shared, Local) { - let rcc = ctx.device.RCC.freeze(Config::hsi().sysclk(48.MHz())); + let mut rcc = ctx.device.RCC.freeze(Config::hsi().sysclk(48.MHz())); // Create TIM3 monotonic and initialize timer queue - ctx.device - .TIM3 - .monotonic_us(&mut ctx.core.NVIC, &rcc.clocks); + ctx.device.TIM3.monotonic_us(&mut ctx.core.NVIC, &mut rcc); // Uncomment if use SysTick as monotonic timer //Mono::start(ctx.core.SYST, 48_000_000); - let gpioc = ctx.device.GPIOC.split(); + let gpioc = ctx.device.GPIOC.split(&mut rcc); let led = gpioc.pc13.into_push_pull_output(); defmt::info!("Start"); diff --git a/examples/sai-duplex.rs b/examples/sai-duplex.rs index a5614f69..2b1dd474 100644 --- a/examples/sai-duplex.rs +++ b/examples/sai-duplex.rs @@ -22,16 +22,16 @@ fn main() -> ! { // I2S-encoded audio. // Initialize clocks. - let rcc = p + let mut rcc = p .RCC .freeze(Config::hse(8.MHz()).saia_clk(172.MHz()).saib_clk(172.MHz())); // Test that the SAI clock is suitable for 48000KHz audio. assert!(rcc.clocks.saia_clk() == Some(172.MHz())); assert!(rcc.clocks.saib_clk() == Some(172.MHz())); - let gpioe = p.GPIOE.split(); + let gpioe = p.GPIOE.split(&mut rcc); // SAIB is made synchronous to A. - let (saia, saib) = p.SAI.split_sync_b(); + let (saia, saib) = p.SAI.split_sync_b(&mut rcc); let protocol = Protocol { sync: Synchronization::I2S, word_size: WordSize::Bit16, diff --git a/examples/sd.rs b/examples/sd.rs index 54fc539f..f5b84f85 100644 --- a/examples/sd.rs +++ b/examples/sd.rs @@ -17,7 +17,7 @@ fn main() -> ! { let device = pac::Peripherals::take().unwrap(); let core = cortex_m::Peripherals::take().unwrap(); - let rcc = device.RCC.freeze( + let mut rcc = device.RCC.freeze( Config::hse(12.MHz()) .require_pll48clk() .sysclk(168.MHz()) @@ -26,12 +26,12 @@ fn main() -> ! { .pclk2(84.MHz()), ); - assert!(clocks.is_pll48clk_valid()); + assert!(rcc.clocks.is_pll48clk_valid()); let mut delay = core.SYST.delay(&rcc.clocks); - let gpioc = device.GPIOC.split(); - let gpiod = device.GPIOD.split(); + let gpioc = device.GPIOC.split(&mut rcc); + let gpiod = device.GPIOD.split(&mut rcc); let d0 = gpioc.pc8.internal_pull_up(true); let d1 = gpioc.pc9.internal_pull_up(true); @@ -39,7 +39,7 @@ fn main() -> ! { let d3 = gpioc.pc11.internal_pull_up(true); let clk = gpioc.pc12; let cmd = gpiod.pd2.internal_pull_up(true); - let mut sdio: Sdio = Sdio::new(device.SDIO, (clk, cmd, d0, d1, d2, d3), &clocks); + let mut sdio: Sdio = Sdio::new(device.SDIO, (clk, cmd, d0, d1, d2, d3), &mut rcc); hprintln!("Waiting for card..."); diff --git a/examples/serial-9bit.rs b/examples/serial-9bit.rs index 4473a910..0612395f 100644 --- a/examples/serial-9bit.rs +++ b/examples/serial-9bit.rs @@ -43,16 +43,16 @@ fn main() -> ! { let dp = pac::Peripherals::take().unwrap(); let cp = cortex_m::peripheral::Peripherals::take().unwrap(); - let gpioa = dp.GPIOA.split(); - let gpiod = dp.GPIOD.split(); + let mut rcc = dp.RCC.freeze(rcc::Config::hse(8.MHz())); + + let gpioa = dp.GPIOA.split(&mut rcc); + let gpiod = dp.GPIOD.split(&mut rcc); let mut led_bit5 = gpiod.pd12.into_push_pull_output(); let mut led_bit6 = gpiod.pd13.into_push_pull_output(); let mut led_bit7 = gpiod.pd14.into_push_pull_output(); let mut led_bit8 = gpiod.pd15.into_push_pull_output(); - let rcc = dp.RCC.freeze(rcc::Config::hse(8.MHz())); - let mut delay = cp.SYST.delay(&rcc.clocks); // define RX/TX pins @@ -65,7 +65,7 @@ fn main() -> ! { .serial( (tx_pin, rx_pin), Config::default().baudrate(9600.bps()).wordlength_9(), - &rcc.clocks, + &mut rcc, ) .unwrap() // Make this Serial object use u16s instead of u8s diff --git a/examples/serial-dma.rs b/examples/serial-dma.rs index 364f7141..9ad38a63 100644 --- a/examples/serial-dma.rs +++ b/examples/serial-dma.rs @@ -41,13 +41,13 @@ static DONE: AtomicBool = AtomicBool::new(false); fn main() -> ! { if let Some(dp) = pac::Peripherals::take() { // Set up the system clock. - let rcc = dp.RCC.constrain(); + let mut rcc = dp.RCC.constrain(); // Enable DMA1. - let dma1 = StreamsTuple::new(dp.DMA1); + let dma1 = StreamsTuple::new(dp.DMA1, &mut rcc); // Enable GPIOA. - let gpioa = dp.GPIOA.split(); + let gpioa = dp.GPIOA.split(&mut rcc); // Configure USART2. let rx_2 = gpioa.pa3.into_alternate(); @@ -60,7 +60,7 @@ fn main() -> ! { .parity_none() .stopbits(StopBits::STOP1) .dma(serial::config::DmaConfig::TxRx), - &rcc.clocks, + &mut rcc, ) .unwrap(); diff --git a/examples/serial.rs b/examples/serial.rs index af7bfa03..2fdaf3a0 100644 --- a/examples/serial.rs +++ b/examples/serial.rs @@ -14,19 +14,19 @@ use core::fmt::Write; // for pretty formatting of the serial output fn main() -> ! { let dp = pac::Peripherals::take().unwrap(); - let gpioa = dp.GPIOA.split(); + let mut rcc = dp.RCC.freeze(Config::hse(25.MHz())); - let rcc = dp.RCC.freeze(Config::hse(25.MHz())); + let gpioa = dp.GPIOA.split(&mut rcc); - let mut delay = dp.TIM1.delay_ms(&rcc.clocks); + let mut delay = dp.TIM1.delay_ms(&mut rcc); // define RX/TX pins let tx_pin = gpioa.pa9; // configure serial - // let mut tx = Serial::tx(dp.USART1, tx_pin, 9600.bps(), &rcc.clocks).unwrap(); + // let mut tx = Serial::tx(dp.USART1, tx_pin, 9600.bps(), &mut rcc).unwrap(); // or - let mut tx = dp.USART1.tx(tx_pin, 9600.bps(), &rcc.clocks).unwrap(); + let mut tx = dp.USART1.tx(tx_pin, 9600.bps(), &mut rcc).unwrap(); let mut value: u8 = 0; diff --git a/examples/spi-dma.rs b/examples/spi-dma.rs index 84ce7876..038cf6f4 100644 --- a/examples/spi-dma.rs +++ b/examples/spi-dma.rs @@ -29,12 +29,12 @@ static G_TRANSFER: Mutex>> = Mutex::new(RefCell::new(None fn main() -> ! { if let Some(dp) = pac::Peripherals::take() { // Set up the system clock. - let rcc = dp.RCC.constrain(); + let mut rcc = dp.RCC.constrain(); - let steams = StreamsTuple::new(dp.DMA1); + let steams = StreamsTuple::new(dp.DMA1, &mut rcc); let stream = steams.4; - let gpiob = dp.GPIOB.split(); + let gpiob = dp.GPIOB.split(&mut rcc); // Note. We set GPIO speed as VeryHigh to it corresponds to SPI frequency 3MHz. // Otherwise it may lead to the 'wrong last bit in every received byte' problem. @@ -55,7 +55,7 @@ fn main() -> ! { (Some(pb13), SPI2::NoMiso, Some(pb15)), mode, 3.MHz(), - &rcc.clocks, + &mut rcc, ); let buffer = cortex_m::singleton!(: [u8; ARRAY_SIZE] = [1; ARRAY_SIZE]).unwrap(); diff --git a/examples/spi_slave.rs b/examples/spi_slave.rs index 0efb4b34..3eb8d938 100644 --- a/examples/spi_slave.rs +++ b/examples/spi_slave.rs @@ -19,9 +19,9 @@ pub const MODE: Mode = Mode { fn main() -> ! { let p = pac::Peripherals::take().unwrap(); - let _rcc = p.RCC.constrain(); + let mut rcc = p.RCC.constrain(); - let gpioa = p.GPIOA.split(); + let gpioa = p.GPIOA.split(&mut rcc); let sck = gpioa.pa5.internal_resistor(Pull::Up); let miso = gpioa.pa6.internal_resistor(Pull::Down); @@ -29,11 +29,13 @@ fn main() -> ! { // clock speed is determined by the master let nss = gpioa.pa4.internal_resistor(Pull::Up); - let mut spi = p - .SPI1 - .spi_slave((Some(sck), Some(miso), Some(mosi), Some(nss)), MODE); + let mut spi = p.SPI1.spi_slave( + (Some(sck), Some(miso), Some(mosi), Some(nss)), + MODE, + &mut rcc, + ); // alternativelly you could use software `chip select` - // let mut spi = SpiSlave::new(p.SPI1, (sck, miso, mosi, None), MODE); + // let mut spi = SpiSlave::new(p.SPI1, (sck, miso, mosi, None), MODE, &mut rcc); // spi.set_internal_nss(false); let mut data = [0x1]; diff --git a/examples/ssd1306-image.rs b/examples/ssd1306-image.rs index 22c9c048..cbfd88c8 100644 --- a/examples/ssd1306-image.rs +++ b/examples/ssd1306-image.rs @@ -31,21 +31,21 @@ fn main() -> ! { cortex_m::peripheral::Peripherals::take(), ) { // Set up the system clock. We want to run at 48MHz for this one. - let rcc = dp.RCC.freeze(Config::hsi().sysclk(48.MHz())); + let mut rcc = dp.RCC.freeze(Config::hsi().sysclk(48.MHz())); // Set up I2C - SCL is PB8 and SDA is PB9; they are set to Alternate Function 4 // as per the STM32F446xC/E datasheet page 60. Pin assignment as per the Nucleo-F446 board. - let gpiob = dp.GPIOB.split(); + let gpiob = dp.GPIOB.split(&mut rcc); let scl = gpiob.pb8.internal_pull_up(true); let sda = gpiob.pb9.internal_pull_up(true); - // let i2c = I2c::new(dp.I2C1, (scl, sda), 400.kHz(), &rcc.clocks); + // let i2c = I2c::new(dp.I2C1, (scl, sda), 400.kHz(), &mut rcc); // or - let i2c = dp.I2C1.i2c((scl, sda), 400.kHz(), &rcc.clocks); + let i2c = dp.I2C1.i2c((scl, sda), 400.kHz(), &mut rcc); // There's a button on PC13. On the Nucleo board, it's pulled up by a 4.7kOhm resistor // and therefore is active LOW. There's even a 100nF capacitor for debouncing - nice for us // since otherwise we'd have to debounce in software. - let gpioc = dp.GPIOC.split(); + let gpioc = dp.GPIOC.split(&mut rcc); let btn = gpioc.pc13.into_pull_down_input(); // Set up the display diff --git a/examples/st7789-lcd.rs b/examples/st7789-lcd.rs index c02387d7..8a82bee2 100644 --- a/examples/st7789-lcd.rs +++ b/examples/st7789-lcd.rs @@ -41,13 +41,13 @@ fn main() -> ! { let dp = Peripherals::take().unwrap(); // Make HCLK faster to allow updating the display more quickly - let rcc = dp.RCC.freeze(Config::hsi().hclk(100.MHz())); + let mut rcc = dp.RCC.freeze(Config::hsi().hclk(100.MHz())); let mut delay = cp.SYST.delay(&rcc.clocks); - let gpiod = dp.GPIOD.split(); - let gpioe = dp.GPIOE.split(); - let gpiof = dp.GPIOF.split(); + let gpiod = dp.GPIOD.split(&mut rcc); + let gpioe = dp.GPIOE.split(&mut rcc); + let gpiof = dp.GPIOF.split(&mut rcc); // Pins connected to the LCD on the 32F412GDISCOVERY board use stm32f4xx_hal::gpio::alt::fsmc as alt; @@ -83,7 +83,7 @@ fn main() -> ! { // Bus turnaround time is zero, because no particular interval is required between transactions. let write_timing = Timing::default().data(3).address_setup(3).bus_turnaround(0); - let (_fsmc, interface) = FsmcLcd::new(dp.FSMC, lcd_pins, &read_timing, &write_timing); + let (_fsmc, interface) = FsmcLcd::new(dp.FSMC, lcd_pins, &read_timing, &write_timing, &mut rcc); // The 32F412GDISCOVERY board has an FRD154BP2902-CTP LCD. There is no easily available // datasheet, so the behavior of this code is based on the working demonstration C code: diff --git a/examples/stopwatch-with-ssd1306-and-interrupts-and-dma-i2c.rs b/examples/stopwatch-with-ssd1306-and-interrupts-and-dma-i2c.rs index 1a0d3409..ea8ccf0d 100644 --- a/examples/stopwatch-with-ssd1306-and-interrupts-and-dma-i2c.rs +++ b/examples/stopwatch-with-ssd1306-and-interrupts-and-dma-i2c.rs @@ -160,12 +160,12 @@ impl WriteOnlyDataCommand for DMAI2cInterface { #[entry] fn main() -> ! { if let (Some(mut dp), Some(cp)) = (pac::Peripherals::take(), cortex_m::Peripherals::take()) { - let rcc = setup_clocks(dp.RCC); - let gpiob = dp.GPIOB.split(); - let i2c = I2c::new(dp.I2C1, (gpiob.pb8, gpiob.pb9), 400.kHz(), &rcc.clocks); + let mut rcc = setup_clocks(dp.RCC); + let gpiob = dp.GPIOB.split(&mut rcc); + let i2c = I2c::new(dp.I2C1, (gpiob.pb8, gpiob.pb9), 400.kHz(), &mut rcc); // Then convert it to DMA - let streams = StreamsTuple::new(dp.DMA1); + let streams = StreamsTuple::new(dp.DMA1, &mut rcc); let i2c_dma: I2c1Handle = i2c.use_dma_tx(streams.1); free(|cs| { I2C1.borrow(cs).replace(Some(i2c_dma)); @@ -178,13 +178,13 @@ fn main() -> ! { }; // On my board it is required to manually toggle Reset Pin of display - let gpioa = dp.GPIOA.split(); + let gpioa = dp.GPIOA.split(&mut rcc); gpioa.pa8.into_push_pull_output().set_high(); - let mut syscfg = dp.SYSCFG.constrain(); + let mut syscfg = dp.SYSCFG.constrain(&mut rcc); // Create a button input with an interrupt - let gpioc = dp.GPIOC.split(); + let gpioc = dp.GPIOC.split(&mut rcc); let mut board_btn = gpioc.pc13.into_pull_up_input(); board_btn.make_interrupt_source(&mut syscfg); board_btn.enable_interrupt(&mut dp.EXTI); @@ -198,7 +198,7 @@ fn main() -> ! { disp.flush().unwrap(); // Create a 1ms periodic interrupt from TIM2 - let mut timer = dp.TIM2.counter(&rcc.clocks); + let mut timer = dp.TIM2.counter(&mut rcc); timer.start(1.secs()).unwrap(); timer.listen(Event::Update); diff --git a/examples/stopwatch-with-ssd1306-and-interrupts.rs b/examples/stopwatch-with-ssd1306-and-interrupts.rs index 6e8ee9e8..9899071a 100644 --- a/examples/stopwatch-with-ssd1306-and-interrupts.rs +++ b/examples/stopwatch-with-ssd1306-and-interrupts.rs @@ -62,14 +62,14 @@ enum StopwatchState { #[entry] fn main() -> ! { if let (Some(mut dp), Some(cp)) = (pac::Peripherals::take(), cortex_m::Peripherals::take()) { - let rcc = setup_clocks(dp.RCC); - let gpiob = dp.GPIOB.split(); - let i2c = I2c::new(dp.I2C1, (gpiob.pb8, gpiob.pb9), 400.kHz(), &rcc.clocks); + let mut rcc = setup_clocks(dp.RCC); + let gpiob = dp.GPIOB.split(&mut rcc); + let i2c = I2c::new(dp.I2C1, (gpiob.pb8, gpiob.pb9), 400.kHz(), &mut rcc); - let mut syscfg = dp.SYSCFG.constrain(); + let mut syscfg = dp.SYSCFG.constrain(&mut rcc); // Create a button input with an interrupt - let gpioc = dp.GPIOC.split(); + let gpioc = dp.GPIOC.split(&mut rcc); let mut board_btn = gpioc.pc13.into_pull_up_input(); board_btn.make_interrupt_source(&mut syscfg); board_btn.enable_interrupt(&mut dp.EXTI); @@ -82,7 +82,7 @@ fn main() -> ! { disp.flush().unwrap(); // Create a 1ms periodic interrupt from TIM2 - let mut timer = dp.TIM2.counter(&rcc.clocks); + let mut timer = dp.TIM2.counter(&mut rcc); timer.start(1.secs()).unwrap(); timer.listen(Event::Update); diff --git a/examples/timer-periph.rs b/examples/timer-periph.rs index 6334c981..5a37c873 100644 --- a/examples/timer-periph.rs +++ b/examples/timer-periph.rs @@ -23,10 +23,10 @@ use crate::hal::{pac, prelude::*}; #[entry] fn main() -> ! { let dp = pac::Peripherals::take().unwrap(); - let rcc = dp.RCC.freeze(Config::hsi().sysclk(24.MHz())); + let mut rcc = dp.RCC.freeze(Config::hsi().sysclk(24.MHz())); // Create a timer based on SysTick - let mut timer = dp.TIM1.counter_ms(&rcc.clocks); + let mut timer = dp.TIM1.counter_ms(&mut rcc); timer.start(1.secs()).unwrap(); hprintln!("hello!"); diff --git a/examples/uart-dma.rs b/examples/uart-dma.rs index 547bdd43..15cb0142 100644 --- a/examples/uart-dma.rs +++ b/examples/uart-dma.rs @@ -127,11 +127,11 @@ pub fn uart3_write(data: &[u8]) -> Result<(), serial::Error> { fn main() -> ! { if let Some(dp) = pac::Peripherals::take() { // Set up the system clock. - let rcc = dp.RCC.constrain(); + let mut rcc = dp.RCC.constrain(); - let dma1 = StreamsTuple::new(dp.DMA1); + let dma1 = StreamsTuple::new(dp.DMA1, &mut rcc); - let gpiod = dp.GPIOD.split(); + let gpiod = dp.GPIOD.split(&mut rcc); // configure UART, it is important to configure this to use DMA let rx_3 = gpiod.pd9.into_alternate(); @@ -144,7 +144,7 @@ fn main() -> ! { .parity_none() .stopbits(StopBits::STOP1) .dma(serial::config::DmaConfig::Rx), - &rcc.clocks, + &mut rcc, ) .unwrap(); diff --git a/examples/usb-serial-irq.rs b/examples/usb-serial-irq.rs index ca5c981a..4b193fb0 100644 --- a/examples/usb-serial-irq.rs +++ b/examples/usb-serial-irq.rs @@ -31,11 +31,11 @@ fn main() -> ! { let dp = pac::Peripherals::take().unwrap(); - let rcc = dp + let mut rcc = dp .RCC .freeze(Config::hsi().sysclk((168).MHz()).pclk1((8).MHz())); - let gpioa = dp.GPIOA.split(); + let gpioa = dp.GPIOA.split(&mut rcc); let usb = USB::new( (dp.OTG_FS_GLOBAL, dp.OTG_FS_DEVICE, dp.OTG_FS_PWRCLK), diff --git a/examples/usb-serial-poll.rs b/examples/usb-serial-poll.rs index 994cd56c..9c0e2f6c 100644 --- a/examples/usb-serial-poll.rs +++ b/examples/usb-serial-poll.rs @@ -17,11 +17,11 @@ static mut EP_MEMORY: [u32; 1024] = [0; 1024]; fn main() -> ! { let dp = pac::Peripherals::take().unwrap(); - let rcc = dp + let mut rcc = dp .RCC .freeze(Config::hse(25.MHz()).sysclk(48.MHz()).require_pll48clk()); - let gpioa = dp.GPIOA.split(); + let gpioa = dp.GPIOA.split(&mut rcc); let usb = USB::new( (dp.OTG_FS_GLOBAL, dp.OTG_FS_DEVICE, dp.OTG_FS_PWRCLK), diff --git a/examples/ws2812-spi.rs b/examples/ws2812-spi.rs index 7786b211..8005aaa0 100644 --- a/examples/ws2812-spi.rs +++ b/examples/ws2812-spi.rs @@ -18,16 +18,16 @@ fn main() -> ! { let dp = pac::Peripherals::take().expect("cannot take peripherals"); // Configure APB bus clock to 48 MHz, cause ws2812b requires 3 Mbps SPI - let rcc = dp.RCC.freeze(Config::hse(25.MHz()).sysclk(48.MHz())); + let mut rcc = dp.RCC.freeze(Config::hse(25.MHz()).sysclk(48.MHz())); - let mut delay = dp.TIM1.delay_us(&rcc.clocks); - let gpioa = dp.GPIOA.split(); + let mut delay = dp.TIM1.delay_us(&mut rcc); + let gpioa = dp.GPIOA.split(&mut rcc); let spi = dp.SPI1.spi( (Some(gpioa.pa5), SPI1::NoMiso, Some(gpioa.pa7)), ws2812::MODE, 3000.kHz(), - &rcc.clocks, + &mut rcc, ); const NUM_LEDS: usize = 20; diff --git a/src/adc.rs b/src/adc.rs index 94e72074..b8eef7df 100644 --- a/src/adc.rs +++ b/src/adc.rs @@ -133,7 +133,7 @@ use crate::dma::PeripheralToMemory; use crate::rcc; use crate::{ gpio::{self, Analog}, - pac, + pac::{self, RCC}, signature::VrefCal, signature::VDDA_CALIB, }; @@ -273,17 +273,15 @@ where //github.com/ Enables the ADC clock, resets the peripheral (optionally), runs calibration and applies the supplied config //github.com/ # Arguments //github.com/ * `reset` - should a reset be performed. This is provided because on some devices multiple ADCs share the same common reset - pub fn new(adc: ADC, reset: bool, config: config::AdcConfig) -> Adc { - unsafe { - // All ADCs share the same reset interface. + pub fn new(adc: ADC, reset: bool, config: config::AdcConfig, rcc: &mut RCC) -> Adc { + // All ADCs share the same reset interface. - //Enable the clock - ADC::enable_unchecked(); + //Enable the clock + ADC::enable(rcc); - if reset { - //Reset the peripheral(s) - ADC::reset_unchecked(); - } + if reset { + //Reset the peripheral(s) + ADC::reset(rcc); } let mut s = Self { diff --git a/src/can.rs b/src/can.rs index 5decaf90..7d099d22 100644 --- a/src/can.rs +++ b/src/can.rs @@ -2,7 +2,7 @@ //! use crate::gpio; -use crate::pac; +use crate::pac::{self, RCC}; use crate::rcc; pub trait Instance: crate::Sealed + rcc::Enable + rcc::Reset + gpio::alt::CanCommon {} @@ -37,24 +37,24 @@ mod can3 { } pub trait CanExt: Sized + Instance { - fn can(self, pins: (impl Into, impl Into)) -> Can; + fn can(self, pins: (impl Into, impl Into), rcc: &mut RCC) -> Can; - fn tx(self, tx_pin: impl Into) -> Can; + fn tx(self, tx_pin: impl Into, rcc: &mut RCC) -> Can; - fn rx(self, rx_pin: impl Into) -> Can; + fn rx(self, rx_pin: impl Into, rcc: &mut RCC) -> Can; } impl CanExt for CAN { - fn can(self, pins: (impl Into, impl Into)) -> Can { - Can::new(self, pins) + fn can(self, pins: (impl Into, impl Into), rcc: &mut RCC) -> Can { + Can::new(self, pins, rcc) } - fn tx(self, tx_pin: impl Into) -> Can { - Can::tx(self, tx_pin) + fn tx(self, tx_pin: impl Into, rcc: &mut RCC) -> Can { + Can::tx(self, tx_pin, rcc) } - fn rx(self, rx_pin: impl Into) -> Can { - Can::rx(self, rx_pin) + fn rx(self, rx_pin: impl Into, rcc: &mut RCC) -> Can { + Can::rx(self, rx_pin, rcc) } } @@ -66,14 +66,12 @@ pub struct Can { impl Can { //github.com/ Creates a CAN interface. - pub fn new(can: CAN, pins: (impl Into, impl Into)) -> Self { - Self::_new(can, (Some(pins.0.into()), Some(pins.1.into()))) + pub fn new(can: CAN, pins: (impl Into, impl Into), rcc: &mut RCC) -> Self { + Self::_new(can, (Some(pins.0.into()), Some(pins.1.into())), rcc) } - fn _new(can: CAN, pins: (Option, Option)) -> Self { - unsafe { - CAN::enable_unchecked(); - CAN::reset_unchecked(); - } + fn _new(can: CAN, pins: (Option, Option), rcc: &mut RCC) -> Self { + CAN::enable(rcc); + CAN::reset(rcc); Can { can, pins } } @@ -84,12 +82,12 @@ impl Can { } impl Can { - pub fn tx(usart: CAN, tx_pin: impl Into) -> Self { - Self::_new(usart, (Some(tx_pin.into()), None)) + pub fn tx(usart: CAN, tx_pin: impl Into, rcc: &mut RCC) -> Self { + Self::_new(usart, (Some(tx_pin.into()), None), rcc) } - pub fn rx(usart: CAN, rx_pin: impl Into) -> Self { - Self::_new(usart, (None, Some(rx_pin.into()))) + pub fn rx(usart: CAN, rx_pin: impl Into, rcc: &mut RCC) -> Self { + Self::_new(usart, (None, Some(rx_pin.into())), rcc) } } diff --git a/src/crc32.rs b/src/crc32.rs index a1f75ee4..21367678 100644 --- a/src/crc32.rs +++ b/src/crc32.rs @@ -7,7 +7,7 @@ //! It operates word-at-a-time, and takes 4 AHB/HCLK cycles per word //! to calculate. This operation stalls the AHB bus for that time. -use crate::pac::CRC; +use crate::pac::{CRC, RCC}; use crate::rcc::{Enable, Reset}; use core::mem::MaybeUninit; use core::ptr::copy_nonoverlapping; @@ -19,12 +19,10 @@ pub struct Crc32 { impl Crc32 { //github.com/ Create a new Crc32 HAL peripheral - pub fn new(crc: CRC) -> Self { - unsafe { - // enable CRC clock. - CRC::enable_unchecked(); - CRC::reset_unchecked(); - } + pub fn new(crc: CRC, rcc: &mut RCC) -> Self { + // enable CRC clock. + CRC::enable(rcc); + CRC::reset(rcc); let mut new = Self { periph: crc }; new.init(); diff --git a/src/dac.rs b/src/dac.rs index 0b0777b1..8a93b163 100644 --- a/src/dac.rs +++ b/src/dac.rs @@ -6,7 +6,7 @@ use crate::{ gpio::{Analog, PA4, PA5}, - pac::DAC, + pac::{DAC, RCC}, rcc::{Enable, Reset}, }; @@ -49,17 +49,15 @@ impl Pins for (PA4, PA5) { } } -pub fn dac(_dac: DAC, _pins: PINS) -> PINS::Output +pub fn dac(_dac: DAC, _pins: PINS, rcc: &mut RCC) -> PINS::Output where PINS: Pins, { - unsafe { - // Enable and reset clock. - DAC::enable_unchecked(); - DAC::reset_unchecked(); + // Enable and reset clock. + DAC::enable(rcc); + DAC::reset(rcc); - PINS::init() - } + PINS::init() } macro_rules! dac { @@ -86,17 +84,17 @@ macro_rules! dac { } pub trait DacExt { - fn constrain(self, pins: PINS) -> PINS::Output + fn constrain(self, pins: PINS, rcc: &mut RCC) -> PINS::Output where PINS: Pins; } impl DacExt for DAC { - fn constrain(self, pins: PINS) -> PINS::Output + fn constrain(self, pins: PINS, rcc: &mut RCC) -> PINS::Output where PINS: Pins, { - dac(self, pins) + dac(self, pins, rcc) } } diff --git a/src/dma/mod.rs b/src/dma/mod.rs index 6f673a96..e5bee19f 100644 --- a/src/dma/mod.rs +++ b/src/dma/mod.rs @@ -18,6 +18,7 @@ use core::{ use embedded_dma::{ReadBuffer, WriteBuffer}; use enumflags2::BitFlags; +use crate::pac::RCC; use crate::{pac, rcc}; pub mod traits; @@ -432,11 +433,9 @@ pub struct StreamsTuple( impl StreamsTuple { //github.com/ Splits the DMA peripheral into streams. - pub fn new(_regs: DMA) -> Self { - unsafe { - DMA::enable_unchecked(); - DMA::reset_unchecked(); - } + pub fn new(_regs: DMA, rcc: &mut RCC) -> Self { + DMA::enable(rcc); + DMA::reset(rcc); Self( StreamX::new(), StreamX::new(), diff --git a/src/dsi.rs b/src/dsi.rs index 0ad6b43c..0b10667a 100644 --- a/src/dsi.rs +++ b/src/dsi.rs @@ -3,7 +3,7 @@ //! Interface with MIPI D-PHY use crate::ltdc::DisplayConfig; -use crate::rcc::{Clocks, Enable}; +use crate::rcc::{Enable, Rcc}; use crate::{pac::DSI, time::Hertz}; use core::cmp::{max, min}; use embedded_display_controller::dsi::{DsiHostCtrlIo, DsiReadCommand, DsiWriteCommand}; @@ -159,17 +159,15 @@ impl DsiHost { display_config: DisplayConfig, dsi_config: DsiConfig, dsi: DSI, - clocks: &Clocks, + rcc: &mut Rcc, ) -> Result { - unsafe { - DSI::enable_unchecked(); - } + DSI::enable(rcc); // Bring DSI peripheral out of reset dsi.cr().modify(|_, w| w.en().set_bit()); //RCC_D1CCIPR: DSI clock from PHY is selected as DSI byte lane clock (default after reset) - let cycles_1ms = clocks.sysclk().raw() / 1_000; + let cycles_1ms = rcc.clocks.sysclk().raw() / 1_000; // Enable regulator dsi.wrpcr().modify(|_, w| w.regen().set_bit()); diff --git a/src/fmpi2c.rs b/src/fmpi2c.rs index f952a43f..2fa9f65b 100644 --- a/src/fmpi2c.rs +++ b/src/fmpi2c.rs @@ -3,8 +3,8 @@ use core::ops::Deref; use crate::gpio; use crate::pac::fmpi2c1 as i2c1; -use crate::pac::{self, rcc, RCC}; -use crate::rcc::{BusClock, Clocks, Enable, Reset}; +use crate::pac::{self, rcc}; +use crate::rcc::{BusClock, Enable, Rcc, Reset}; use fugit::{HertzU32 as Hertz, RateExtU32}; use micromath::F32Ext; @@ -102,17 +102,11 @@ impl From for Mode { } #[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum ClockSource<'a> { - Apb(&'a Clocks), +pub enum ClockSource { + Apb, Hsi, } -impl<'a> From<&'a Clocks> for ClockSource<'a> { - fn from(value: &'a Clocks) -> Self { - Self::Apb(value) - } -} - // hddat and vddat are removed because SDADEL is always going to be 0 in this implementation so // condition is always met struct I2cSpec { @@ -238,42 +232,43 @@ fn calculate_timing( } pub trait I2cExt: Sized + Instance { - fn i2c<'a>( + fn i2c( self, pins: (impl Into, impl Into), mode: impl Into, - clocks: impl Into>, + rcc: &mut Rcc, + clocks: ClockSource, ) -> I2c; } impl I2cExt for I2C { - fn i2c<'a>( + fn i2c( self, pins: (impl Into, impl Into), mode: impl Into, - clocks: impl Into>, + rcc: &mut Rcc, + clocks: ClockSource, ) -> I2c { - I2c::new(self, pins, mode, clocks) + I2c::new(self, pins, mode, rcc, clocks) } } impl I2c { - pub fn new<'a>( + pub fn new( i2c: I2C, pins: (impl Into, impl Into), mode: impl Into, - clocks: impl Into>, + rcc: &mut Rcc, + clocks: ClockSource, ) -> Self { - unsafe { - // Enable and reset clock. - I2C::enable_unchecked(); - I2C::reset_unchecked(); - } + // Enable and reset clock. + I2C::enable(rcc); + I2C::reset(rcc); let pins = (pins.0.into(), pins.1.into()); let i2c = I2c { i2c, pins }; - i2c.i2c_init(mode, clocks.into()); + i2c.i2c_init(mode, rcc, clocks); i2c } @@ -283,7 +278,7 @@ impl I2c { } impl I2c { - fn i2c_init(&self, mode: impl Into, clocks: ClockSource<'_>) { + fn i2c_init(&self, mode: impl Into, rcc: &mut Rcc, clocks: ClockSource) { let mode = mode.into(); // Make sure the I2C unit is disabled so we can configure it @@ -294,13 +289,9 @@ impl I2c { let dnf = cr1.dnf().bits(); let i2c_timingr = match clocks { - ClockSource::Apb(clocks) => { - // NOTE(unsafe) this reference will only be used for atomic writes with no side effects. - unsafe { - let rcc = &(*RCC::ptr()); - I2C::set_clock_source(rcc, I2cSel::Apb); - } - let pclk = I2C::clock(clocks); + ClockSource::Apb => { + I2C::set_clock_source(rcc, I2cSel::Apb); + let pclk = I2C::clock(&rcc.clocks); match mode { Mode::Standard { frequency } => { calculate_timing(I2C_STANDARD_MODE_SPEC, pclk, frequency, an_filter, dnf) @@ -315,11 +306,7 @@ impl I2c { } } ClockSource::Hsi => { - // NOTE(unsafe) this reference will only be used for atomic writes with no side effects. - unsafe { - let rcc = &(*RCC::ptr()); - I2C::set_clock_source(rcc, I2cSel::Hsi); - } + I2C::set_clock_source(rcc, I2cSel::Hsi); // We're using the HSI clock to keep things simple so this is going to be always 16 MHz const FREQ: u32 = 16_000_000; diff --git a/src/fsmc_lcd/mod.rs b/src/fsmc_lcd/mod.rs index 7cac9641..722c8193 100644 --- a/src/fsmc_lcd/mod.rs +++ b/src/fsmc_lcd/mod.rs @@ -49,7 +49,7 @@ //! 1. Create an `LcdPins` object containing the pins used to communicate with the LCD //! //! 2. Create default `Timing` objects for the write and read timing -//! +//! //! a. (Optional) Adjust the timing to make read and write operations faster, within the limits //! of the wiring and LCD controller //! @@ -68,6 +68,7 @@ use core::marker::PhantomData; pub use self::pins::{AddressPins, ChipSelectPins, DataPins, DataPins16, DataPins8, LcdPins, Pins}; pub use self::timing::{AccessMode, Timing}; +use crate::pac::RCC; use crate::rcc::{Enable, Reset}; // Use the FMC or FSMC, whichever is available, and treat it like an FSMC @@ -216,13 +217,12 @@ where pins: PINS, read_timing: &Timing, write_timing: &Timing, + rcc: &mut RCC, ) -> (Self, PINS::Lcds) { use self::sealed::Conjure; - unsafe { - // Enable the FSMC/FMC peripheral - FSMC::enable_unchecked(); - FSMC::reset_unchecked(); - } + // Enable the FSMC/FMC peripheral + FSMC::enable(rcc); + FSMC::reset(rcc); // Configure memory type and basic interface settings // The reference manuals are sometimes unclear on the distinction between banks @@ -256,13 +256,11 @@ where //github.com/ uses //github.com/ //github.com/ This function also resets and disables the FSMC. - pub fn release(self, _lcds: PINS::Lcds) -> (FSMC, PINS) { - unsafe { - // Reset FSMC/FMC - FSMC::reset_unchecked(); - // Disable the FSMC/FMC peripheral - FSMC::disable_unchecked(); - } + pub fn release(self, _lcds: PINS::Lcds, rcc: &mut RCC) -> (FSMC, PINS) { + // Reset FSMC/FMC + FSMC::reset(rcc); + // Disable the FSMC/FMC peripheral + FSMC::disable(rcc); (self.fsmc, self.pins) } diff --git a/src/gpio.rs b/src/gpio.rs index 2b3b7c22..83d58124 100644 --- a/src/gpio.rs +++ b/src/gpio.rs @@ -56,7 +56,7 @@ use core::marker::PhantomData; -use crate::pac; +use crate::pac::{self, RCC}; pub mod alt; mod convert; pub use convert::PinMode; @@ -82,7 +82,7 @@ pub trait GpioExt { type Parts; //github.com/ Splits the GPIO block into independent pins and registers - fn split(self) -> Self::Parts; + fn split(self, rcc: &mut RCC) -> Self::Parts; } //github.com/ Id, port and mode for any pin @@ -558,7 +558,7 @@ macro_rules! gpio { ]) => { //github.com/ GPIO pub mod $gpiox { - use crate::pac::$GPIOX; + use crate::pac::{$GPIOX, RCC}; use crate::rcc::{Enable, Reset}; //github.com/ GPIO parts @@ -572,12 +572,10 @@ macro_rules! gpio { impl super::GpioExt for $GPIOX { type Parts = Parts; - fn split(self) -> Parts { - unsafe { - // Enable clock. - $GPIOX::enable_unchecked(); - $GPIOX::reset_unchecked(); - } + fn split(self, rcc: &mut RCC) -> Parts { + // Enable clock. + $GPIOX::enable(rcc); + $GPIOX::reset(rcc); Parts { $( $pxi: $PXi::new(), diff --git a/src/i2c.rs b/src/i2c.rs index 73d47b3f..16bee1d6 100644 --- a/src/i2c.rs +++ b/src/i2c.rs @@ -5,7 +5,7 @@ use crate::rcc::{Enable, Reset}; use crate::gpio; -use crate::rcc::Clocks; +use crate::rcc::Rcc; use fugit::{HertzU32 as Hertz, RateExtU32}; mod common; @@ -104,7 +104,7 @@ pub trait I2cExt: Sized + Instance { self, pins: (impl Into, impl Into), mode: impl Into, - clocks: &Clocks, + rcc: &mut Rcc, ) -> I2c; } @@ -113,9 +113,9 @@ impl I2cExt for I2C { self, pins: (impl Into, impl Into), mode: impl Into, - clocks: &Clocks, + rcc: &mut Rcc, ) -> I2c { - I2c::new(self, pins, mode, clocks) + I2c::new(self, pins, mode, rcc) } } @@ -124,18 +124,16 @@ impl I2c { i2c: I2C, pins: (impl Into, impl Into), mode: impl Into, - clocks: &Clocks, + rcc: &mut Rcc, ) -> Self { - unsafe { - // Enable and reset clock. - I2C::enable_unchecked(); - I2C::reset_unchecked(); - } + // Enable and reset clock. + I2C::enable(rcc); + I2C::reset(rcc); let pins = (pins.0.into(), pins.1.into()); let i2c = I2c { i2c, pins }; - i2c.i2c_init(mode, clocks.pclk1()); + i2c.i2c_init(mode, rcc.clocks.pclk1()); i2c } diff --git a/src/i2s.rs b/src/i2s.rs index 083ab346..1a92a3c0 100644 --- a/src/i2s.rs +++ b/src/i2s.rs @@ -9,7 +9,7 @@ use crate::gpio::{self, PinSpeed, Speed}; use crate::pac; #[allow(unused)] -use crate::rcc::{self, Clocks, Reset}; +use crate::rcc::{self, Clocks, Rcc, Reset}; use fugit::HertzU32 as Hertz; #[cfg(feature = "i2s")] @@ -89,7 +89,7 @@ pub trait I2sExt: Sized + Instance { Option>, impl Into, ), - clocks: &Clocks, + rcc: &mut Rcc, ) -> I2s; } @@ -102,9 +102,9 @@ impl I2sExt for SPI { Option>, impl Into, ), - clocks: &Clocks, + rcc: &mut Rcc, ) -> I2s { - I2s::new(self, pins, clocks) + I2s::new(self, pins, rcc) } } @@ -120,7 +120,7 @@ pub trait DualI2sExt: Sized + DualInstance { impl Into, impl Into, ), - clocks: &Clocks, + rcc: &mut Rcc, ) -> DualI2s; } @@ -135,9 +135,9 @@ impl DualI2sExt for SPI { impl Into, impl Into, ), - clocks: &Clocks, + rcc: &mut Rcc, ) -> DualI2s { - DualI2s::new(self, i2s_ext, pins, clocks) + DualI2s::new(self, i2s_ext, pins, rcc) } } @@ -171,14 +171,12 @@ impl I2s { Option>, impl Into, ), - clocks: &Clocks, + rcc: &mut Rcc, ) -> Self { - let input_clock = SPI::i2s_freq(clocks); - unsafe { - // Enable clock, enable reset, clear, reset - SPI::enable_unchecked(); - SPI::reset_unchecked(); - } + let input_clock = SPI::i2s_freq(&rcc.clocks); + // Enable clock, enable reset, clear, reset + SPI::enable(rcc); + SPI::reset(rcc); let pins = ( pins.0.into(), @@ -319,15 +317,13 @@ impl DualI2s { impl Into, impl Into, ), - clocks: &Clocks, + rcc: &mut Rcc, ) -> Self { - let input_clock = SPI::i2s_freq(clocks); - unsafe { - // Enable clock, enable reset, clear, reset - // Note: this also affect the I2SEXT peripheral - SPI::enable_unchecked(); - SPI::reset_unchecked(); - } + let input_clock = SPI::i2s_freq(&rcc.clocks); + // Enable clock, enable reset, clear, reset + // Note: this also affect the I2SEXT peripheral + SPI::enable(rcc); + SPI::reset(rcc); let pins = ( pins.0.into(), diff --git a/src/qei.rs b/src/qei.rs index 5a9c2e36..bee63deb 100644 --- a/src/qei.rs +++ b/src/qei.rs @@ -1,4 +1,6 @@ //! # Quadrature Encoder Interface +use crate::pac::RCC; + use crate::{ gpio::PushPull, pac, rcc, @@ -12,6 +14,7 @@ pub trait QeiExt: Sized + Instance { impl Into<>::Ch>, impl Into<>::Ch>, ), + rcc: &mut RCC, ) -> Qei; } @@ -22,8 +25,9 @@ impl QeiExt for TIM { impl Into<>::Ch>, impl Into<>::Ch>, ), + rcc: &mut RCC, ) -> Qei { - Qei::new(self, pins) + Qei::new(self, pins, rcc) } } @@ -44,12 +48,11 @@ impl Qei { impl Into<>::Ch>, impl Into<>::Ch>, ), + rcc: &mut RCC, ) -> Self { // Enable and reset clock. - unsafe { - TIM::enable_unchecked(); - TIM::reset_unchecked(); - } + TIM::enable(rcc); + TIM::reset(rcc); let pins = (pins.0.into(), pins.1.into()); tim.setup_qei(); diff --git a/src/qspi.rs b/src/qspi.rs index 1f0332cd..479219c1 100644 --- a/src/qspi.rs +++ b/src/qspi.rs @@ -12,7 +12,7 @@ pub use crate::gpio::alt::QuadSpiBank; use crate::{ gpio::{alt::quadspi as alt, PinSpeed, Speed}, - pac::QUADSPI, + pac::{QUADSPI, RCC}, rcc::Enable, }; pub use alt::{Bank1, Bank2}; @@ -221,8 +221,9 @@ impl Qspi { impl Into, ), config: QspiConfig, + rcc: &mut RCC, ) -> Self { - Self::new(qspi, pins, config) + Self::new(qspi, pins, config, rcc) } } @@ -239,8 +240,9 @@ impl Qspi { impl Into, ), config: QspiConfig, + rcc: &mut RCC, ) -> Self { - Self::new(qspi, pins, config) + Self::new(qspi, pins, config, rcc) } } @@ -270,11 +272,10 @@ where impl Into, ), config: QspiConfig, + rcc: &mut RCC, ) -> Self { // Enable quad SPI in the clocks. - unsafe { - QUADSPI::enable_unchecked(); - } + QUADSPI::enable(rcc); let pins = ( pins.0.into().speed(Speed::VeryHigh), @@ -320,11 +321,10 @@ impl Qspi { impl Into, ), config: QspiConfig, + rcc: &mut RCC, ) -> Self { // Enable quad SPI in the clocks. - unsafe { - QUADSPI::enable_unchecked(); - } + QUADSPI::enable(rcc); let pins = ( pins.0.into().speed(Speed::VeryHigh), diff --git a/src/rng.rs b/src/rng.rs index 4c1a2afb..60818cca 100644 --- a/src/rng.rs +++ b/src/rng.rs @@ -24,7 +24,7 @@ use core::cmp; use core::mem; use crate::pac::RNG; -use crate::rcc::{Clocks, Enable, Reset}; +use crate::rcc::{Enable, Rcc, Reset}; use core::num::NonZeroU32; use core::ops::Shl; use embedded_hal_02::blocking::rng; @@ -76,21 +76,19 @@ pub trait RngExt { //github.com/ # Panics //github.com/ //github.com/ This function will panic if `PLL48_CLK < 1/16 HCLK`. - fn constrain(self, clocks: &Clocks) -> Rng; + fn constrain(self, rcc: &mut Rcc) -> Rng; } impl RngExt for RNG { - fn constrain(self, clocks: &Clocks) -> Rng { + fn constrain(self, rcc: &mut Rcc) -> Rng { cortex_m::interrupt::free(|_| { // enable RNG_CLK (peripheral clock) - unsafe { - RNG::enable_unchecked(); - RNG::reset_unchecked(); - } + RNG::enable(rcc); + RNG::reset(rcc); // verify the clock configuration is valid - let hclk = clocks.hclk(); - let rng_clk = clocks.pll48clk().unwrap_or_else(|| 0.Hz()); + let hclk = rcc.clocks.hclk(); + let rng_clk = rcc.clocks.pll48clk().unwrap_or_else(|| 0.Hz()); assert!(rng_clk >= (hclk / 16)); // enable the RNG peripheral diff --git a/src/rtc.rs b/src/rtc.rs index bd00d7f1..e61caa49 100644 --- a/src/rtc.rs +++ b/src/rtc.rs @@ -121,8 +121,8 @@ pub enum LSEClockMode { impl Rtc { //github.com/ Create and enable a new RTC with external crystal or ceramic resonator and default prescalers. - pub fn new(regs: RTC, pwr: &mut PWR) -> Self { - Self::with_config(regs, pwr, LSEClockMode::Oscillator, 255, 127) + pub fn new(regs: RTC, rcc: &mut RCC, pwr: &mut PWR) -> Self { + Self::with_config(regs, rcc, pwr, LSEClockMode::Oscillator, 255, 127) } //github.com/ Create and enable a new RTC, and configure its clock source and prescalers. //github.com/ @@ -130,6 +130,7 @@ impl Rtc { //github.com/ set `prediv_s` to 255 (249 for LSI), and `prediv_a` to 127 to get a calendar clock of 1Hz. pub fn with_config( regs: RTC, + rcc: &mut RCC, pwr: &mut PWR, clock_source: impl Into, prediv_s: u16, @@ -151,30 +152,27 @@ impl Rtc { // Exit Init // Enable write protect - unsafe { - let mut rcc = RCC::steal(); - // As per the sample code, unlock comes first. (Enable PWR and DBP) - result.unlock(&mut rcc, pwr); - match result.clock_source { - ClockSource::Lse(mode) => { - // If necessary, enable the LSE. - if rcc.bdcr().read().lserdy().bit_is_clear() { - result.enable_lse(&mut rcc, mode); - } - // Set clock source to LSE. - rcc.bdcr().modify(|_, w| w.rtcsel().lse()); + // As per the sample code, unlock comes first. (Enable PWR and DBP) + result.unlock(rcc, pwr); + match result.clock_source { + ClockSource::Lse(mode) => { + // If necessary, enable the LSE. + if rcc.bdcr().read().lserdy().bit_is_clear() { + result.enable_lse(rcc, mode); } - ClockSource::Lsi => { - // If necessary, enable the LSE. - if rcc.csr().read().lsirdy().bit_is_clear() { - result.enable_lsi(&mut rcc); - } - // Set clock source to LSI. - rcc.bdcr().modify(|_, w| w.rtcsel().lsi()); + // Set clock source to LSE. + rcc.bdcr().modify(|_, w| w.rtcsel().lse()); + } + ClockSource::Lsi => { + // If necessary, enable the LSE. + if rcc.csr().read().lsirdy().bit_is_clear() { + result.enable_lsi(rcc); } + // Set clock source to LSI. + rcc.bdcr().modify(|_, w| w.rtcsel().lsi()); } - result.enable(&mut rcc); } + result.enable(rcc); result.modify(true, |regs| { // Set 24 Hour @@ -209,16 +207,22 @@ impl Rtc { } //github.com/ Create and enable a new RTC with internal crystal and default prescalers. - pub fn new_lsi(regs: RTC, pwr: &mut PWR) -> Self { - Self::with_config(regs, pwr, ClockSource::Lsi, 249, 127) + pub fn new_lsi(regs: RTC, rcc: &mut RCC, pwr: &mut PWR) -> Self { + Self::with_config(regs, rcc, pwr, ClockSource::Lsi, 249, 127) } //github.com/ Create and enable a new RTC, and configure its clock source and prescalers. //github.com/ //github.com/ From AN3371, Table 3, when using the LSI, //github.com/ set `prediv_s` to 249, and `prediv_a` to 127 to get a calendar clock of 1Hz. - pub fn lsi_with_config(regs: RTC, pwr: &mut PWR, prediv_s: u16, prediv_a: u8) -> Self { - Self::with_config(regs, pwr, ClockSource::Lsi, prediv_s, prediv_a) + pub fn lsi_with_config( + regs: RTC, + rcc: &mut RCC, + pwr: &mut PWR, + prediv_s: u16, + prediv_a: u8, + ) -> Self { + Self::with_config(regs, rcc, pwr, ClockSource::Lsi, prediv_s, prediv_a) } fn enable_lsi(&mut self, rcc: &mut RCC) { diff --git a/src/sai.rs b/src/sai.rs index c3ea0be8..9b8f9066 100644 --- a/src/sai.rs +++ b/src/sai.rs @@ -22,6 +22,7 @@ use core::ops::Deref; use crate::gpio::alt::SaiChannel; +use crate::pac::RCC; #[cfg(feature = "sai2")] use crate::pac::SAI2; #[cfg(any( @@ -486,6 +487,7 @@ where //github.com/ Splits the SAI instance into two asynchronous sub-blocks. fn split( self, + rcc: &mut RCC, ) -> ( SubBlock, Asynchronous>, SubBlock, Asynchronous>, @@ -497,6 +499,7 @@ where //github.com/ block. fn split_sync_a( self, + rcc: &mut RCC, ) -> ( SubBlock, Synchronous>, SubBlock, Asynchronous>, @@ -508,6 +511,7 @@ where //github.com/ block. fn split_sync_b( self, + rcc: &mut RCC, ) -> ( SubBlock, Asynchronous>, SubBlock, Synchronous>, @@ -527,6 +531,7 @@ where { fn split( self, + rcc: &mut RCC, ) -> ( SubBlock, Asynchronous>, SubBlock, Asynchronous>, @@ -534,10 +539,8 @@ where where Self: Sized, { - unsafe { - SAI::enable_unchecked(); - SAI::reset_unchecked(); - } + SAI::enable(rcc); + SAI::reset(rcc); ( SubBlock { channel: SAIA::new(self), @@ -554,6 +557,7 @@ where fn split_sync_a( self, + rcc: &mut RCC, ) -> ( SubBlock, Synchronous>, SubBlock, Asynchronous>, @@ -561,10 +565,8 @@ where where Self: Sized, { - unsafe { - SAI::enable_unchecked(); - SAI::reset_unchecked(); - } + SAI::enable(rcc); + SAI::reset(rcc); ( SubBlock { channel: SAIA::new(self), @@ -581,6 +583,7 @@ where fn split_sync_b( self, + rcc: &mut RCC, ) -> ( SubBlock, Asynchronous>, SubBlock, Synchronous>, @@ -588,10 +591,8 @@ where where Self: Sized, { - unsafe { - SAI::enable_unchecked(); - SAI::reset_unchecked(); - } + SAI::enable(rcc); + SAI::reset(rcc); ( SubBlock { channel: SAIA::new(self), diff --git a/src/sdio.rs b/src/sdio.rs index 31a70762..9a8a44db 100644 --- a/src/sdio.rs +++ b/src/sdio.rs @@ -2,7 +2,7 @@ use crate::gpio::alt::sdio as alt; use crate::pac::{self, SDIO}; -use crate::rcc::{Clocks, Enable, Reset}; +use crate::rcc::{Enable, Rcc, Reset}; #[allow(unused_imports)] use fugit::HertzU32 as Hertz; pub use sdio_host::{ @@ -167,12 +167,10 @@ pub struct Emmc { impl Sdio

{ //github.com/ Create and enable the Sdio device - pub fn new(sdio: SDIO, pins: PINS, clocks: &Clocks) -> Self { - unsafe { - // Enable and reset the sdio peripheral, it's the same bit position for both registers - SDIO::enable_unchecked(); - SDIO::reset_unchecked(); - } + pub fn new(sdio: SDIO, pins: PINS, rcc: &mut Rcc) -> Self { + // Enable and reset the sdio peripheral, it's the same bit position for both registers + SDIO::enable(rcc); + SDIO::reset(rcc); // Configure clock sdio.clkcr().write(|w| { @@ -196,7 +194,7 @@ impl Sdio

{ sdio, bw: PINS::BUSWIDTH, card: None, - clock: clocks.sysclk(), + clock: rcc.clocks.sysclk(), }; // Make sure card is powered off diff --git a/src/serial.rs b/src/serial.rs index 4ddc53ea..fe5e6c35 100644 --- a/src/serial.rs +++ b/src/serial.rs @@ -29,7 +29,7 @@ use crate::gpio::{self, PushPull}; use crate::pac; -use crate::rcc::{self, Clocks}; +use crate::rcc::{self, Rcc}; pub mod dma; use crate::dma::{ @@ -218,21 +218,21 @@ pub trait SerialExt: Sized + Instance { self, pins: (impl Into>, impl Into>), config: impl Into, - clocks: &Clocks, + rcc: &mut Rcc, ) -> Result, config::InvalidConfig>; fn tx( self, tx_pin: impl Into>, config: impl Into, - clocks: &Clocks, + rcc: &mut Rcc, ) -> Result, config::InvalidConfig>; fn rx( self, rx_pin: impl Into>, config: impl Into, - clocks: &Clocks, + rcc: &mut Rcc, ) -> Result, config::InvalidConfig>; } @@ -244,9 +244,9 @@ impl Serial { impl Into>, ), config: impl Into, - clocks: &Clocks, + rcc: &mut Rcc, ) -> Result { - Self::_new(uart, (Some(pins.0), Some(pins.1)), config, clocks) + Self::_new(uart, (Some(pins.0), Some(pins.1)), config, rcc) } fn _new( uart: USART, @@ -255,18 +255,16 @@ impl Serial { Option>>, ), config: impl Into, - clocks: &Clocks, + rcc: &mut Rcc, ) -> Result { use self::config::*; let config = config.into(); - unsafe { - // Enable clock. - USART::enable_unchecked(); - USART::reset_unchecked(); - } + // Enable clock. + USART::enable(rcc); + USART::reset(rcc); - let pclk_freq = USART::clock(clocks).raw(); + let pclk_freq = USART::clock(&rcc.clocks).raw(); let baud = config.baudrate.0; if !USART::RB::IRDA && config.irda != IrdaMode::None { @@ -668,25 +666,25 @@ impl SerialExt for UART { self, pins: (impl Into>, impl Into>), config: impl Into, - clocks: &Clocks, + rcc: &mut Rcc, ) -> Result, config::InvalidConfig> { - Serial::new(self, pins, config, clocks) + Serial::new(self, pins, config, rcc) } fn tx( self, tx_pin: impl Into>, config: impl Into, - clocks: &Clocks, + rcc: &mut Rcc, ) -> Result, config::InvalidConfig> { - Serial::tx(self, tx_pin, config, clocks) + Serial::tx(self, tx_pin, config, rcc) } fn rx( self, rx_pin: impl Into>, config: impl Into, - clocks: &Clocks, + rcc: &mut Rcc, ) -> Result, config::InvalidConfig> { - Serial::rx(self, rx_pin, config, clocks) + Serial::rx(self, rx_pin, config, rcc) } } @@ -695,13 +693,13 @@ impl Serial { usart: UART, tx_pin: impl Into>, config: impl Into, - clocks: &Clocks, + rcc: &mut Rcc, ) -> Result, config::InvalidConfig> { Self::_new( usart, (Some(tx_pin), None::>), config, - clocks, + rcc, ) .map(|s| s.split().0) } @@ -712,13 +710,13 @@ impl Serial { usart: UART, rx_pin: impl Into>, config: impl Into, - clocks: &Clocks, + rcc: &mut Rcc, ) -> Result, config::InvalidConfig> { Self::_new( usart, (None::>, Some(rx_pin)), config, - clocks, + rcc, ) .map(|s| s.split().1) } diff --git a/src/spi.rs b/src/spi.rs index 662648dc..2a187137 100644 --- a/src/spi.rs +++ b/src/spi.rs @@ -36,10 +36,9 @@ pub struct Mode { mod hal_02; mod hal_1; -use crate::pac::spi1; -use crate::rcc; +use crate::pac::{spi1, RCC}; +use crate::rcc::{self, Rcc}; -use crate::rcc::Clocks; use enumflags2::BitFlags; use fugit::HertzU32 as Hertz; @@ -259,7 +258,7 @@ pub trait SpiExt: Sized + Instance { ), mode: impl Into, freq: Hertz, - clocks: &Clocks, + rcc: &mut Rcc, ) -> Spi; fn spi_bidi( @@ -267,7 +266,7 @@ pub trait SpiExt: Sized + Instance { pins: (Option>, Option>), mode: impl Into, freq: Hertz, - clocks: &Clocks, + rcc: &mut Rcc, ) -> Spi; fn spi_slave( @@ -279,6 +278,7 @@ pub trait SpiExt: Sized + Instance { Option>, ), mode: impl Into, + rcc: &mut RCC, ) -> SpiSlave; fn spi_bidi_slave( @@ -289,6 +289,7 @@ pub trait SpiExt: Sized + Instance { Option>, ), mode: impl Into, + rcc: &mut RCC, ) -> SpiSlave; } @@ -307,9 +308,9 @@ impl SpiExt for SPI { ), mode: impl Into, freq: Hertz, - clocks: &Clocks, + rcc: &mut Rcc, ) -> Spi { - Spi::new(self, pins, mode, freq, clocks) + Spi::new(self, pins, mode, freq, rcc) } //github.com/ Enables the SPI clock, resets the peripheral, sets `Alternate` mode for `pins` and initialize the peripheral as SPI Master BIDI mode. //github.com/ @@ -321,9 +322,9 @@ impl SpiExt for SPI { pins: (Option>, Option>), mode: impl Into, freq: Hertz, - clocks: &Clocks, + rcc: &mut Rcc, ) -> Spi { - Spi::new_bidi(self, pins, mode, freq, clocks) + Spi::new_bidi(self, pins, mode, freq, rcc) } //github.com/ Enables the SPI clock, resets the peripheral, sets `Alternate` mode for `pins` and initialize the peripheral as SPI Slave Normal mode. //github.com/ @@ -339,8 +340,9 @@ impl SpiExt for SPI { Option>, ), mode: impl Into, + rcc: &mut RCC, ) -> SpiSlave { - SpiSlave::new(self, pins, mode) + SpiSlave::new(self, pins, mode, rcc) } //github.com/ Enables the SPI clock, resets the peripheral, sets `Alternate` mode for `pins` and initialize the peripheral as SPI Slave BIDI mode. //github.com/ @@ -355,8 +357,9 @@ impl SpiExt for SPI { Option>, ), mode: impl Into, + rcc: &mut RCC, ) -> SpiSlave { - SpiSlave::new_bidi(self, pins, mode) + SpiSlave::new_bidi(self, pins, mode, rcc) } } @@ -471,17 +474,19 @@ impl Spi { ), mode: impl Into, freq: Hertz, - clocks: &Clocks, + rcc: &mut Rcc, ) -> Self { - unsafe { - SPI::enable_unchecked(); - SPI::reset_unchecked(); - } + SPI::enable(rcc); + SPI::reset(rcc); - let pins = (pins.0, pins.1, pins.2); + let pins = ( + pins.0.map(Into::into), + pins.1.map(Into::into), + pins.2.map(Into::into), + ); Self::_new(spi, pins) - .pre_init(mode.into(), freq, SPI::clock(clocks)) + .pre_init(mode.into(), freq, SPI::clock(&rcc.clocks)) .init() } } @@ -497,17 +502,15 @@ impl Spi { pins: (Option>, Option>), mode: impl Into, freq: Hertz, - clocks: &Clocks, + rcc: &mut Rcc, ) -> Self { - unsafe { - SPI::enable_unchecked(); - SPI::reset_unchecked(); - } + SPI::enable(rcc); + SPI::reset(rcc); let pins = (pins.0, SPI::NoMiso, pins.1); Self::_new(spi, pins) - .pre_init(mode.into(), freq, SPI::clock(clocks)) + .pre_init(mode.into(), freq, SPI::clock(&rcc.clocks)) .init() } } @@ -527,11 +530,10 @@ impl SpiSlave { Option>, ), mode: impl Into, + rcc: &mut RCC, ) -> Self { - unsafe { - SPI::enable_unchecked(); - SPI::reset_unchecked(); - } + SPI::enable(rcc); + SPI::reset(rcc); let pins = (pins.0, pins.1, pins.2, pins.3); @@ -553,11 +555,10 @@ impl SpiSlave { Option>, ), mode: impl Into, + rcc: &mut RCC, ) -> Self { - unsafe { - SPI::enable_unchecked(); - SPI::reset_unchecked(); - } + SPI::enable(rcc); + SPI::reset(rcc); let pins = (pins.0, pins.1, SPI::NoMosi, pins.2); diff --git a/src/syscfg.rs b/src/syscfg.rs index 6221cd84..7805b91e 100644 --- a/src/syscfg.rs +++ b/src/syscfg.rs @@ -1,4 +1,4 @@ -use crate::pac::SYSCFG; +use crate::pac::{RCC, SYSCFG}; use crate::rcc::Enable; use core::fmt; use core::ops::Deref; @@ -6,15 +6,13 @@ use core::ops::Deref; //github.com/ Extension trait that constrains the `SYSCFG` peripheral pub trait SysCfgExt { //github.com/ Constrains the `SYSCFG` peripheral so it plays nicely with the other abstractions - fn constrain(self) -> SysCfg; + fn constrain(self, rcc: &mut RCC) -> SysCfg; } impl SysCfgExt for SYSCFG { - fn constrain(self) -> SysCfg { + fn constrain(self, rcc: &mut RCC) -> SysCfg { // Enable clock. - unsafe { - SYSCFG::enable_unchecked(); - } + SYSCFG::enable(rcc); SysCfg(self) } diff --git a/src/timer.rs b/src/timer.rs index 89c425dc..88cd7d8b 100644 --- a/src/timer.rs +++ b/src/timer.rs @@ -13,6 +13,7 @@ use crate::bb; use crate::pac; use crate::dma::traits::PeriAddress; +use crate::rcc::Rcc; use crate::rcc::{self, Clocks}; use fugit::HertzU32 as Hertz; @@ -170,51 +171,51 @@ pub enum Error { pub trait TimerExt: Sized { //github.com/ Non-blocking [Counter] with custom fixed precision - fn counter(self, clocks: &Clocks) -> Counter; + fn counter(self, rcc: &mut Rcc) -> Counter; //github.com/ Non-blocking [Counter] with fixed precision of 1 ms (1 kHz sampling) //github.com/ //github.com/ Can wait from 2 ms to 65 sec for 16-bit timer and from 2 ms to 49 days for 32-bit timer. //github.com/ //github.com/ NOTE: don't use this if your system frequency more than 65 MHz - fn counter_ms(self, clocks: &Clocks) -> CounterMs { - self.counter::<1_000>(clocks) + fn counter_ms(self, rcc: &mut Rcc) -> CounterMs { + self.counter::<1_000>(rcc) } //github.com/ Non-blocking [Counter] with fixed precision of 1 μs (1 MHz sampling) //github.com/ //github.com/ Can wait from 2 μs to 65 ms for 16-bit timer and from 2 μs to 71 min for 32-bit timer. - fn counter_us(self, clocks: &Clocks) -> CounterUs { - self.counter::<1_000_000>(clocks) + fn counter_us(self, rcc: &mut Rcc) -> CounterUs { + self.counter::<1_000_000>(rcc) } //github.com/ Non-blocking [Counter] with dynamic precision which uses `Hertz` as Duration units - fn counter_hz(self, clocks: &Clocks) -> CounterHz; + fn counter_hz(self, rcc: &mut Rcc) -> CounterHz; //github.com/ Blocking [Delay] with custom fixed precision - fn delay(self, clocks: &Clocks) -> Delay; + fn delay(self, rcc: &mut Rcc) -> Delay; //github.com/ Blocking [Delay] with fixed precision of 1 ms (1 kHz sampling) //github.com/ //github.com/ Can wait from 2 ms to 49 days. //github.com/ //github.com/ NOTE: don't use this if your system frequency more than 65 MHz - fn delay_ms(self, clocks: &Clocks) -> DelayMs { - self.delay::<1_000>(clocks) + fn delay_ms(self, rcc: &mut Rcc) -> DelayMs { + self.delay::<1_000>(rcc) } //github.com/ Blocking [Delay] with fixed precision of 1 μs (1 MHz sampling) //github.com/ //github.com/ Can wait from 2 μs to 71 min. - fn delay_us(self, clocks: &Clocks) -> DelayUs { - self.delay::<1_000_000>(clocks) + fn delay_us(self, rcc: &mut Rcc) -> DelayUs { + self.delay::<1_000_000>(rcc) } } impl TimerExt for TIM { - fn counter(self, clocks: &Clocks) -> Counter { - FTimer::new(self, clocks).counter() + fn counter(self, rcc: &mut Rcc) -> Counter { + FTimer::new(self, rcc).counter() } - fn counter_hz(self, clocks: &Clocks) -> CounterHz { - Timer::new(self, clocks).counter_hz() + fn counter_hz(self, rcc: &mut Rcc) -> CounterHz { + Timer::new(self, rcc).counter_hz() } - fn delay(self, clocks: &Clocks) -> Delay { - FTimer::new(self, clocks).delay() + fn delay(self, rcc: &mut Rcc) -> Delay { + FTimer::new(self, rcc).delay() } } @@ -706,15 +707,13 @@ macro_rules! with_pwm { impl Timer { //github.com/ Initialize timer - pub fn new(tim: TIM, clocks: &Clocks) -> Self { - unsafe { - // Enable and reset the timer peripheral - TIM::enable_unchecked(); - TIM::reset_unchecked(); - } + pub fn new(tim: TIM, rcc: &mut Rcc) -> Self { + // Enable and reset the timer peripheral + TIM::enable(rcc); + TIM::reset(rcc); Self { - clk: TIM::timer_clock(clocks), + clk: TIM::timer_clock(&rcc.clocks), tim, } } @@ -755,15 +754,13 @@ pub type FTimerMs = FTimer; impl FTimer { //github.com/ Initialize timer - pub fn new(tim: TIM, clocks: &Clocks) -> Self { - unsafe { - // Enable and reset the timer peripheral - TIM::enable_unchecked(); - TIM::reset_unchecked(); - } + pub fn new(tim: TIM, rcc: &mut Rcc) -> Self { + // Enable and reset the timer peripheral + TIM::enable(rcc); + TIM::reset(rcc); let mut t = Self { tim }; - t.configure(clocks); + t.configure(&rcc.clocks); t } diff --git a/src/timer/monotonic.rs b/src/timer/monotonic.rs index e3f2af2a..820d74bc 100644 --- a/src/timer/monotonic.rs +++ b/src/timer/monotonic.rs @@ -1,6 +1,6 @@ // RTICv1 Monotonic impl for the 32-bit timers use super::{Channel, Event, FTimer, Flag, General, Instance, WithPwm}; -use crate::rcc::Clocks; +use crate::rcc::Rcc; use crate::ReadFlags; use core::ops::{Deref, DerefMut}; pub use fugit::{self, ExtU32}; @@ -35,9 +35,9 @@ impl MonoTimer { } pub trait MonoTimerExt: Sized { - fn monotonic(self, clocks: &Clocks) -> MonoTimer; - fn monotonic_us(self, clocks: &Clocks) -> MonoTimer { - self.monotonic::<1_000_000>(clocks) + fn monotonic(self, rcc: &mut Rcc) -> MonoTimer; + fn monotonic_us(self, rcc: &mut Rcc) -> MonoTimer { + self.monotonic::<1_000_000>(rcc) } } @@ -45,15 +45,15 @@ impl MonoTimerExt for TIM where Self: Instance + General + WithPwm, { - fn monotonic(self, clocks: &Clocks) -> MonoTimer { - FTimer::new(self, clocks).monotonic() + fn monotonic(self, rcc: &mut Rcc) -> MonoTimer { + FTimer::new(self, rcc).monotonic() } } pub trait MonoTimer64Ext: Sized { - fn monotonic64(self, clocks: &Clocks) -> MonoTimer64; - fn monotonic64_us(self, clocks: &Clocks) -> MonoTimer64 { - self.monotonic64::<1_000_000>(clocks) + fn monotonic64(self, rcc: &mut Rcc) -> MonoTimer64; + fn monotonic64_us(self, rcc: &mut Rcc) -> MonoTimer64 { + self.monotonic64::<1_000_000>(rcc) } } @@ -61,21 +61,21 @@ impl MonoTimer64Ext for TIM where Self: Instance + General + WithPwm, { - fn monotonic64(self, clocks: &Clocks) -> MonoTimer64 { - FTimer::new(self, clocks).monotonic64() + fn monotonic64(self, rcc: &mut Rcc) -> MonoTimer64 { + FTimer::new(self, rcc).monotonic64() } } pub trait SysMonoTimerExt: Sized { - fn monotonic(self, clocks: &Clocks) -> Systick; - fn monotonic_us(self, clocks: &Clocks) -> Systick<1_000_000> { - self.monotonic::<1_000_000>(clocks) + fn monotonic(self, rcc: &mut Rcc) -> Systick; + fn monotonic_us(self, rcc: &mut Rcc) -> Systick<1_000_000> { + self.monotonic::<1_000_000>(rcc) } } impl SysMonoTimerExt for cortex_m::peripheral::SYST { - fn monotonic(self, clocks: &Clocks) -> Systick { - Systick::new(self, clocks.hclk().raw()) + fn monotonic(self, rcc: &mut Rcc) -> Systick { + Systick::new(self, rcc.clocks.hclk().raw()) } } diff --git a/src/timer/monotonics.rs b/src/timer/monotonics.rs index 2ed6466f..4854e703 100644 --- a/src/timer/monotonics.rs +++ b/src/timer/monotonics.rs @@ -1,6 +1,6 @@ // RTICv2 Monotonic impl use super::{FTimer, General}; -use crate::{pac, rcc::Clocks}; +use crate::{pac, rcc::Rcc}; use atomic_polyfill::{AtomicU64, Ordering}; use core::marker::PhantomData; use rtic_time::timer_queue::TimerQueueBackend; @@ -32,14 +32,14 @@ pub trait MonoTimerExt: Sized { fn monotonic( self, nvic: &mut cortex_m::peripheral::NVIC, - clocks: &Clocks, + rcc: &mut Rcc, ) -> MonoTimer; fn monotonic_us( self, nvic: &mut cortex_m::peripheral::NVIC, - clocks: &Clocks, + rcc: &mut Rcc, ) -> MonoTimer { - self.monotonic::<1_000_000>(nvic, clocks) + self.monotonic::<1_000_000>(nvic, rcc) } } @@ -147,9 +147,9 @@ macro_rules! make_timer { fn monotonic( self, nvic: &mut cortex_m::peripheral::NVIC, - clocks: &Clocks, + rcc: &mut Rcc, ) -> MonoTimer { - FTimer::new(self, clocks).monotonic(nvic) + FTimer::new(self, rcc).monotonic(nvic) } } diff --git a/src/timer/pwm.rs b/src/timer/pwm.rs index 0943d15a..cfd5a217 100644 --- a/src/timer/pwm.rs +++ b/src/timer/pwm.rs @@ -42,7 +42,7 @@ use super::{ }; pub use super::{Ch, C1, C2, C3, C4}; use crate::gpio::{OpenDrain, PushPull}; -use crate::rcc::Clocks; +use crate::rcc::Rcc; use core::ops::{Deref, DerefMut}; use fugit::{HertzU32 as Hertz, TimerDurationU32}; @@ -53,17 +53,17 @@ where fn pwm( self, time: TimerDurationU32, - clocks: &Clocks, + rcc: &mut Rcc, ) -> (PwmManager, Self::Channels); - fn pwm_hz(self, freq: Hertz, clocks: &Clocks) -> (PwmHzManager, Self::Channels); + fn pwm_hz(self, freq: Hertz, rcc: &mut Rcc) -> (PwmHzManager, Self::Channels); fn pwm_us( self, time: TimerDurationU32<1_000_000>, - clocks: &Clocks, + rcc: &mut Rcc, ) -> (PwmManager, Self::Channels) { - self.pwm::<1_000_000>(time, clocks) + self.pwm::<1_000_000>(time, rcc) } } @@ -74,13 +74,13 @@ where fn pwm( self, time: TimerDurationU32, - clocks: &Clocks, + rcc: &mut Rcc, ) -> (PwmManager, Self::Channels) { - FTimer::::new(self, clocks).pwm(time) + FTimer::::new(self, rcc).pwm(time) } - fn pwm_hz(self, time: Hertz, clocks: &Clocks) -> (PwmHzManager, Self::Channels) { - Timer::new(self, clocks).pwm_hz(time) + fn pwm_hz(self, time: Hertz, rcc: &mut Rcc) -> (PwmHzManager, Self::Channels) { + Timer::new(self, rcc).pwm_hz(time) } } diff --git a/tools/check.py b/tools/check.py index ff9b338d..d4c29044 100755 --- a/tools/check.py +++ b/tools/check.py @@ -28,7 +28,7 @@ def main(): crate_info = cargo_meta["packages"][0] - features = ["{},usb_fs,can,i2s,fsmc_lcd,rtic1,defmt,stm32-fmc".format(x) + features = ["{},usb_fs,can,i2s,fsmc_lcd,rtic1,defmt,stm32-fmc,sdio-host".format(x) for x in crate_info["features"].keys() if x.startswith("stm32f4")]









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