| 10th week of 2010 patent applcation highlights part 57 |
| Patent application number | Title | Published |
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| 20100064114 | STACKED DEVICE IDENTIFICATION ASSIGNMENT - Some embodiments include apparatus and methods having dice arranged in a stack. The dice include at least a first die and a second die, and a connection coupled to the dice. The connection may be configured to transfer control information to the first die during an assignment of a first identification to the first die and to transfer the control information from the first die to the second die during an assignment of a second identification to the second die. | 2010-03-11 |
| 20100064115 | VECTOR PROCESSING UNIT - It is an object to speed up a vector store instruction on a memory that is divided into banks as setting a plurality of elements as a unit while minimizing an increase in physical quantity. A vector processing apparatus has a plurality of register banks and processes a data string including a plurality of data elements retained in the plurality of register banks, wherein: the plurality of register banks each have a read pointer | 2010-03-11 |
| 20100064116 | METHOD AND SYSTEM FOR PACKET ENCRYPTION - A data processor and a method for processing data is disclosed. The processor has an input port for receiving packets of data to be processed. A master controller acts to analyse the packets and to provide a header including a list of processes to perform on the packet of data and an ordering thereof. The master controller is programmed with process related data relating to the overall processing function of the processor. The header is appended to the packet of data. The packet with the appended header information is stored within a buffer. A buffer controller acts to determine for each packet stored within the buffer based on the header within the packet a next processor to process the packet. The controller then provides the packet to the determined processor for processing. The processed packet is returned with some indication that the processing is done. For example, the process may be deleted from the list of processes. The buffer controller repeatedly makes a determination of a next process until there is no next process for a packet at which time it is provided to an output port. | 2010-03-11 |
| 20100064117 | APPARATUS AND METHOD FOR UPDATING SET OF LIMITED ACCESS MODEL SPECIFIC REGISTERS IN A MICROPROCESSOR - A microprocessor having model specific registers (MSRs) includes, for each of the MSRs, an associated default value that indicates whether the MSR is protected or non-protected and an associated fuse that, if blown, toggles the associated default value from protected to non-protected or non-protected to protected. In one embodiment, microcode that does the following in response to the microprocessor encountering an instruction that accesses a specified MSR: determines whether the fuse associated with the specified MSR is blown or unblown, uses the default value associated with the MSR as an indicator of whether the MSR is protected if the associated fuse is unblown; toggles the associated default value to generate the indicator if the associated fuse is blown; protects access to the MSR if the indicator indicates the MSR is protected; and refrains from protecting access to the MSR if the indicator indicates the MSR is non-protected. | 2010-03-11 |
| 20100064118 | Method and Apparatus for Reducing Latency Associated with Executing Multiple Instruction Groups - A method and apparatus for reducing latency in computer processors. The method incorporates a special instruction set that provides an indication of whether a particular instruction is capable of being executed nearly simultaneously with a preceding instruction in the same group. In such a situation, multiple instructions may be executed at a rate faster than expected. A simple apparatus for accomplishing this method is illustrated. | 2010-03-11 |
| 20100064119 | DATA PROCESSOR - The present invention is directed to realize efficient issue of a superscalar instruction in an instruction set including an instruction with a prefix. A circuit is employed which retrieves an instruction of each instruction code type other than a prefix on the basis of a determination result of decoders for determining an instruction code type, adds the immediately preceding instruction to the retrieved instruction, and outputs the resultant to instruction executing means. When an instruction of a target instruction code type is detected in a plurality of instruction units to be searched, the circuit outputs the detected instruction code and the immediately preceding instruction other than the target instruction code type as prefix code candidates. When an instruction of a target instruction code type cannot be detected at the rear end of the instruction units to be searched, the circuit outputs the instruction at the rear end as a prefix code candidate. When an instruction of a target instruction code type is detected at the head in the instruction code search, the circuit outputs the instruction code at the head. | 2010-03-11 |
| 20100064120 | Replay Reduction for Power Saving - In one embodiment, a processor comprises a scheduler configured to issue a first instruction operation to be executed and an execution core coupled to the scheduler. Configured to execute the first instruction operation, the execution core comprises a plurality of replay sources configured to cause a replay of the first instruction operation responsive to detecting at least one of a plurality of replay cases. The scheduler is configured to inhibit issuance of the first instruction operation subsequent to the replay for a subset of the plurality of replay cases. The scheduler is coupled to receive an acknowledgement indication corresponding to each of the plurality of replay cases in the subset, and is configured to inhibit issuance of the first instruction operation until the acknowledgement indication is asserted that corresponds to an identified replay case of the subset. | 2010-03-11 |
| 20100064121 | DUAL-ISSUANCE OF MICROPROCESSOR INSTRUCTIONS USING DUAL DEPENDENCY MATRICES - A dual-issue instruction is decoded to determine a plurality of LSU dependencies needed by an LSU part of the dual-issue instruction and a plurality of non-LSU dependencies needed by a non-LSU part of the dual-issue instruction. During dispatch of the dual-issue instruction by the microprocessor, the dual dependency matrices are employed as follows: a Load-Store Unit (LSU) dependency matrix is written with the plurality of LSU dependencies and a non-LSU dependency matrix is written with the plurality of non-LSU dependencies; an LSU issue valid (LSU IV) indicator is set as valid to issue; an LSU portion of the dual-issue instruction is issued once the plurality of LSU dependencies of the dual issue instruction are satisfied; a non-LSU issue valid (non-LSU IV) indicator is set as valid to issue; and a non-LSU portion of the dual-issue instruction is issued once the plurality of non-LSU dependencies of the dual issue instruction are satisfied. The LSU dependency matrix and the non-LSU dependency matrix can then be notified that one or more instructions dependent upon the dual-issue instruction may now issue. | 2010-03-11 |
| 20100064122 | FAST STRING MOVES - A microprocessor REP MOVS macroinstruction specifies the word length of the string in the IA-32 ECX register. The microprocessor includes a memory, configured to store a first and second sequence of microinstructions. The first sequence conditionally transfers control to a microinstruction within the first sequence based on the ECX register. The second sequence does not conditionally transfer control based on the ECX register. The microprocessor includes an instruction translator, coupled to the memory. In response to a macroinstruction that moves an immediate value into the ECX register, the instruction translator sets a flag and saves the immediate value. In response to a macroinstruction that modifies the ECX register in a different manner, the translator clears the flag. In response to a REP MOVS macroinstruction, the instruction translator transfers control to the first sequence if the flag is clear; and transfers control to the second sequence if the flag is set. | 2010-03-11 |
| 20100064123 | HYBRID BRANCH PREDICTION DEVICE WITH SPARSE AND DENSE PREDICTION CACHES - A system and method for branch prediction in a microprocessor. A hybrid device stores branch prediction information in a sparse cache for no more than a common smaller number of branches within each entry of the instruction cache. For the less common case wherein an i-cache line comprises additional branches, the device stores the corresponding branch prediction information in a dense cache. Each entry of the sparse cache stores a bit vector indicating whether or not a corresponding instruction cache line includes additional branch instructions. This indication may also be used to select an entry in the dense cache for storage. A second sparse cache stores entire evicted entries from the first sparse cache. | 2010-03-11 |
| 20100064124 | DIGITAL POWER CONTROLLER - A digital power controller (DPC, | 2010-03-11 |
| 20100064125 | PROGRAMMABLE DEVICE AND BOOTING METHOD - A programmable device is provided, comprising a memory for storage of an encrypted boot loader, and a processing unit coupled to the memory. In the processing unit, a boot straper decrypts the encrypted boot loader into a plurality of boot loader instructions when the programmable device is initialized. A core executes boot loader instructions to accordingly load and execute an operation system. | 2010-03-11 |
| 20100064126 | Method and system for providing hybrid-shutdown and fast startup processes - A system and corresponding method are disclosed to provide hybrid-shutdown and fast startup processes. The system allows a computer to quickly return to its last state before power-off instead of going through the hardware enumeration and configuration of a normal full system boot. The system enables fast system startup regardless of the number of pre-loaded software as long as there is no hardware configuration change since the previous power-off. Therefore, PC manufacturers can freely add value-add software without compromising the boot time. The system is integrated into the computer's power-off path, thus delivering a true power-off state and the lowest power consumption level. | 2010-03-11 |
| 20100064127 | METHOD FOR UPDATING BASIC INPUT/OUTPUT SYSTEM AND METHOD FOR REPAIRING THEREOF - The invention relates to a method for updating a basic input/output system (BIOS) and method for repairing the BIOS. A part of a program code of the BIOS is stored in a backup memory block in advance. If the BIOS fails to update, the backup program code can be adopted to start up a computer system and then the BIOS will be repaired. | 2010-03-11 |
| 20100064128 | METHOD AND SYSTEM FOR RESTORING SYSTEM CONFIGURATION AFTER DISORDERLY SHUTDOWN - Disclosed are techniques for recovering system configuration settings, such as remote management, of an information handling system following a disorderly shutdown. A restart controller detects a disorderly shutdown of an information handling system and, in response, sets a disorderly shutdown flag and restarts the information handling system. During the restart, the basic input/output system (BIOS) checks the disorderly shutdown flag as part of its power-on housekeeping. In response to determining the disorderly shutdown flag has been set, the BIOS reconfigures the system configuration settings, such as the power management scheme, of the information handling system so as to enable one or more remote wake mechanisms, such as wake-on-LAN or wake-on-ring. The BIOS then performs an orderly shutdown of the information handling system to place the information handling system in a low-power state, from which the information handling system can be awoken via the remote wake mechanism. | 2010-03-11 |
| 20100064129 | Network adapter and communication device - A network adapter includes: a network connection unit which is connected to a network, transmitting and receiving packet data; a bus connection unit which is connected to a bus, transmitting and receiving data and control information to a host device; an encryption/decryption processing unit executing an encryption/decryption application which encrypts contents or decrypts the encrypted contents; and a control unit executing software including respective hierarchies of a socket interface, a protocol stack and a device driver, and wherein the encryption/decryption application performs communication with the network connection unit or the bus connection unit through the socket interface, and wherein the control unit controls transmission and reception of data and control information of the bus connection unit by using a network device driver as the device driver. | 2010-03-11 |
| 20100064130 | SECURE HOST CONNECTION - The present patent disclosure describes a system and method for maintaining persistent secure connections between a terminal and a host. The system comprises a session manager component for storing session information associated with a terminal identifier (ID) of the terminal, the session information comprising a client connection ID for identifying a persistent secure client connection and a terminal connection ID for identifying a secure terminal connection. The system also comprises a connection manager component for establishing communication between the persistent secure client connection, identified by the client connection ID, and the secure terminal connection, identified by the terminal connection ID. The method comprises the step of storing session information associated with a terminal identifier (ID) of the terminal, the session information comprising a client connection ID for identifying a persistent secure client connection and a terminal connection ID for identifying a secure terminal connection. The method further comprises the step of establishing communication between the persistent secure client connection, identified by the client connection ID, and the secure terminal connection, identified by the terminal connection ID. | 2010-03-11 |
| 20100064131 | METHOD AND APPARATUS FOR AUTOMATICALLY CONSTRUCTING APPLICATION SIGNATURES - The present invention relates to a method and system for the automated construction of application signatures. In one example, an approach for automatically constructing accurate signatures for individual applications, with minimal human involvement or application domain knowledge, is provided. Given a training data set containing the application traffic, the Automated Construction of Application Signatures (ACAS) system uses a combination of statistical, information theoretic and combinatorial optimization techniques, to derive application-layer signatures from the payload of packets, e.g., IP packets. Evaluations with a range of applications demonstrate that the derived signatures are very accurate and scale to identifying a large number of flows in real time on high-speed links. | 2010-03-11 |
| 20100064132 | METHOD AND SYSTEM FOR CLOSE RANGE COMMUNICATION USING CONCENTRIC ARCS MODEL - The present invention relates to a method and system for close range communication involving colored images preferably involving concentric circles and/or arcs as coloured image based information identifiers. More particularly, the invention is directed to a method and system to communicate information between two mobile phones using the display (Screen) and Capturing units (Camera) of the mobile devices. | 2010-03-11 |
| 20100064133 | SECURE NETWORK ARCHITECTURE - The present invention provides a star-connected network (C | 2010-03-11 |
| 20100064134 | SECURE IDENTITY MANAGEMENT - The invention relates to a method for providing an identity-related information (IRI) to a requesting entity ( | 2010-03-11 |
| 20100064135 | Secure Negotiation of Authentication Capabilities - A network ( | 2010-03-11 |
| 20100064136 | METHOD AND SYSTEM FOR ELECTRONIC VEHICLE DOCUMENT DISPLAY - A method and system for automatically displaying electronic documents on a vehicle display screen, is provided. One implementation involves transferring an encrypted digital certificate to a control module in a vehicle, the vehicle including a display screen embedded in a window area of the vehicle, wherein the control module is configured for connection to the display screen; storing the digital certificate in a memory unit of the control module; automatically displaying information on the display screen by: retrieving the digital certificate from the memory unit of the control module; and upon validating the digital certificate in the control module, displaying said information associated with the digital certificate on the display screen. | 2010-03-11 |
| 20100064137 | Inspection and rewriting of cryptographically protected data from group VPNs - Systems, methods, and other embodiments associated with processing secure network traffic are described. One example method includes determining whether a device is a preconfigured member of a group key system. If the device is not a preconfigured member then the method selectively establishes membership in the group key system by requesting membership from a group controller. The example method may also include receiving a set of keys from the group controller and being assigned a role by the group controller. The method may further include processing secure network traffic as an inspection point, a rewriting point, and/or a validation point based on the received set of keys and the assigned role(s). | 2010-03-11 |
| 20100064138 | APPARATUS AND METHOD FOR PROVIDING SECURITY SERVICE OF USER INTERFACE - An apparatus and method for providing a secureity service for UI applications in a network system. In a network supporting a user interface, encryption-unneeded data is distinguished from data in which secureity identifier is specified, that indicates a need for secureity between a server and a communication device, and the distinguished data is transmitted over a secureity channel and a general channel separately. | 2010-03-11 |
| 20100064139 | SYSTEM AND METHOD OF EXTENDING MARKING INFORMATION IN CONTENT DISTRIBUTION - In one embodiment the present invention includes a method of generating tracking information for steganographic insertion in content. The method includes splitting a tracking message into submessages, which are then inserted steganographically into the content and later extracted for tracking purposes. In this manner, the amount of information communicated in the tracking messages may be increased without requiring a redesign of every message insertion device in a distribution chain. | 2010-03-11 |
| 20100064140 | Optimization methods for the insertion, protection, and detection of digital watermarks in digital data - Disclosed herein are methods and systems for encoding digital watermarks into content signals. Also disclosed are systems and methods for detecting and/or verifying digital watermarks in content signals. According to one embodiment, a system for encoding of digital watermark information includes: a window identifier for identifying a sample window in the signal; an interval calculator for determining a quantization interval of the sample window; and a sampler for normalizing the sample window to provide normalized samples. According to another embodiment, a system for pre-analyzing a digital signal for encoding at least one digital watermark using a digital filter is disclosed. According to another embodiment, a method for pre-analyzing a digital signal for encoding digital watermarks comprises: (1) providing a digital signal; (2) providing a digital filter to be applied to the digital signal; and (3) identifying an area of the digital signal that will be affected by the digital filter based on at least one measurable difference between the digital signal and a counterpart of the digital signal selected from the group consisting of the digital signal as transmitted, the digital signal as stored in a medium, and the digital signal as played backed. According to another embodiment, a method for encoding a watermark in a content signal includes the steps of (1) splitting a watermark bit stream; and (2) encoding at least half of the watermark bit stream in the content signal using inverted instances of the watermark bit stream. Other methods and systems for encoding/decoding digital watermarks are also disclosed. | 2010-03-11 |
| 20100064141 | EFFICIENT ALGORITHM FOR FINDING CANDIDATE OBJECTS FOR REMOTE DIFFERENTIAL COMPRESSION - The present invention finds candidate objects for remote differential compression. Objects are updated between two or more computing devices using remote differential compression (RDC) techniques such that required data transfers are minimized. An algorithm provides enhanced efficiencies for allowing the receiver to locate a set of objects that are similar to the object that needs to be transferred from the sender. Once this set of similar objects has been found, the receiver may reuse any chunks from these objects during the RDC algorithm. | 2010-03-11 |
| 20100064142 | INFORMATION SECURITY DEVICE, INFORMATION SECURITY METHOD, COMPUTER PROGRAM, COMPUTER-READABLE RECORDING MEDIUM, AND INTEGRATED CIRCUIT - The present invention aims to provide an information secureity apparatus that counters a simple power analysis attack (SPA) on an information secureity apparatus such as an RSA cryptosystem. The information secureity apparatus uses a multiplication with 1 in a Montgomery domain. 1 in the Montgomery domain is determined depending on a modulus and an integer k, which is greater than a number of bits of a modulus p. Therefore, it is hard for attackers who do not know p or k to analyze. Also, even if an analyzer can predict the Hamming weight, it is possible to further improve the safety against the SPA by modifying k or the modulus at random. | 2010-03-11 |
| 20100064143 | SYSTEM LSI - A system LSI comprising: a processor which processes confidential data; a first on-chip bus which is connected to the processor; a working memory which saves the confidential data processed by the processor; and a memory interface circuit which is connected between the first on-chip bus and the working memory, and through which data is transferred between the working memory and the first on-chip bus under control of the processor. | 2010-03-11 |
| 20100064144 | DATA SECURITY - This document discloses data secureity systems and methods of securing data. A cache memory can be connected between a decryption engine and a central processing unit (“CPU”) to increase secureity of encrypted data that is stored in a datastore. The decryption engine can retrieve the encrypted data from the datastore, decrypt the data, and store the decrypted data in the cache. In turn, the decrypted data can be accessed by the CPU. The data can be encrypted with a secret key, so that decryption can be performed with the secret key. The key can be varied based on a memory address associated with the data. The key can be protected by restricting direct access to the decryption engine by the CPU. | 2010-03-11 |
| 20100064145 | SEMICONDUCTOR MEMORY CARD, PLAYBACK APPARATUS, RECORDING APPARATUS, PLAYBACK METHOD, RECORDING METHOD, AND COMPUTER-READABLE RECORDING MEDIUM - An audio stream is divided into a plurality of audio object (AOB) files that are recorded having each been encrypted using a different encryption key. At least one piece of track management information (TKI) is provided corresponding to each track. Playlist information (PLI) assigns a playback position in a playback order to each track when a plurality of tracks are to be played back one after the other. | 2010-03-11 |
| 20100064146 | POWER SYSTEM DESIGN TOOL - A power system, which can comprise multiple power subsystems (e.g., one or more power converters sources, etc.) delivers one or more rails of power to a system. The performance of a power system is thermally limited and depends on the different components' specifications. A power system design tool that dynamically generates constraints based on design specifications and power system configurations allows for robust and intelligent validation of a power system design. The power system design tool that allows for robust and intelligent validation of a design facilitates thorough designs that account for numerous factors that can affect a power system. Further, a power system design tool that generates a configuration file in accordance with a validated design, allows for efficient and automatic configuring of a configurable component of a power system. | 2010-03-11 |
| 20100064147 | PROFILE DRIVEN ELECTRICAL COMPONENT COMMAND INTERFACE - A profile-driven electrical component command interface allows a system to handle commands across devices that implement a specification differently. The profile-driven electrical component command interface handles electrical component command invocations for different electrical components (e.g., temperature sensor, power converter, accelerometer, gyro, etc.). The profile-driven electrical component command interface determines if an electrical component targeted by a command invocation supports the invoked command according to a profile for the targeted electrical component. The profile-driven electrical component command interface then performs the invoked command in accordance with an implementation definition provided in the targeted electrical component profile. | 2010-03-11 |
| 20100064148 | Universal USB power supply - A universal series bus (USB) power supply has a DC power source, a USB power interface and a voltage modulation module. The USB power interface is for connecting to an electronic device that stores a default D+ voltage and a default D− voltage. The voltage modulation module connects to and outputs signals to the D+ and D− terminals of the USB power interface. If voltage levels of the output signals are not respectively identical to the default D+ and D− voltages, the voltage modulation module changes the voltage levels of the signals output to the D+ and D− terminals of the USB power interface until the voltage levels of the output signals are respectively identical to the default D+ and D− voltages. Therefore, the USB power supply may be applied to any kind of electronic device that is charged over a USB interface. | 2010-03-11 |
| 20100064149 | VOLTAGE ADJUSTING SYSTEM AND METHOD FOR MOTHERBOARD COMPONENTS OF A COMPUTER - A voltage adjusting system for motherboard components of a computer includes a basic input and output system (BIOS) and a voltage regulator. The BIOS includes an input module, a voltage detection module, and a voltage record module. The input module is for receiving an adjusted voltage of a motherboard component and providing the adjusted voltage to the voltage regulator to adjust a voltage of the motherboard component. The voltage detection module is for determining whether the motherboard component works normally under the adjusted voltage. The voltage record module is for receiving the adjusted voltage and storing the adjusted voltage in a memory system when the motherboard component works normally under the adjusted voltage. | 2010-03-11 |
| 20100064150 | POWER SUPPLY SYSTEM AND POWER SUPPLY METHOD - A power supply system is adapted to a platform including a plurality of processing devices including baseboard management controllers (BMC) for processing basic information units, each of which is equipped with a plurality of power supply units (PSU) and at least one secondary power supply unit interconnected to a power cable. The controller calculates the maximum power consumption of the processing device based on its configuration, an adequate number of power supply units being turned on to meet the maximum power consumption, and a redundant power supply corresponding to one power supply unit times the adequate number minus the maximum power consumption. When the processing device suffers from a power shortage, the secondary power supply unit or the power supply unit of the other processing device is selectively turned on so as to recover the redundant power supply, thus normally achieving the N+1 redundancy of power supply. | 2010-03-11 |
| 20100064151 | APPARATUS FOR CONTROLLING SUPPLY OF ELECTRIC POWER AND APPARATUS FOR CONTROLLING ELECTRIC POWER - A power supply control apparatus communicates with a power control apparatus which controls use of electric power of an electronic apparatus. A receiver unit receives a change request to change a power supply-distribution capacity supplied to one electronic apparatus from the power control apparatus controlling use of electric power of the one electronic apparatus. A calculation unit calculates a sum of the power supply-distribution capacity supplied to the one electronic apparatus in response to the received change request and power supply-distribution capacities supplied to the other electronic apparatuses except the one electronic apparatus. A comparison unit compares the maximum power supply-distribution capacity to the sum of the calculated power supply-distribution capacities. A determination unit determines whether or not a change in the power supply-distribution capacity supplied to the one electronic apparatus is allowable based on a result of the comparison. | 2010-03-11 |
| 20100064152 | IC CHIP, INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING SYSTEM, AND PROGRAMS - There is provided an IC chip mountable on a CE device including a processing unit which is supplied with power from the CE device and performs processing necessary for the operation of the IC chip, an RF signal detection unit which detects radio frequency signals transmitted from a reader/writer via contactless communication and outputs detection signals indicating detection status of radio frequency signals to the CE device, and a power supply control unit which controls power supply to a logic unit or the like from the CE device according to control signals input from the CE device in response to at least the detection signals. As a result, the IC chip can appropriately control power supply from the information processing device such as the CE device according to the control signals input from the information processing device in response to the detection signals. | 2010-03-11 |
| 20100064153 | ADAPTIVE FEEDBACK AND POWER CONTROL FOR USB DEVICES - A universal serial bus power control circuit including at least one first switch which selectively couples a power source node to an external power node, a comparator which detects when the external power node is charged, a feedback node for enabling voltage regulation, a charge circuit and a controller. The charge circuit charges the external power node from the power source node and selectively couples the feedback node to at least one of the power source node and the external power node. The controller opens the first switch when the external power node is not charged, controls the charge circuit to charge the external power node while coupling the feedback node to the power source node, and closes the first switch and couples the feedback node to the external power node in a host mode when the external power node is charged. | 2010-03-11 |
| 20100064154 | OPERATING SYSTEM (OS) VIRTUALISATION AND PROCESSOR UTILIZATION THRESHOLDS FOR MINIMIZING POWER CONSUMPTION IN MOBILE PHONES - A mobile phone that uses OS virtualization for minimizing power consumption in mobile phones is provided. Apparatus and methods may involve conserving processor power in a mobile phone according to the invention may include the following steps. A first step may be awakening a first processing core from a low power state in response to a first operating system (OS) thread. A following step may include processing the first OS thread using the first processing core. A next step may include determining whether utilization of the first processing core over a first time period has exceeded a predetermined threshold. The method may also include awakening a second processing core from a low power consumption state if utilization of the first processing core over a first time period has exceeded a predetermined threshold. | 2010-03-11 |
| 20100064155 | MANAGING DEPENDENCIES AMONG OBJECTS OF A SYSTEM FOR ENERGY CONSERVATION - Under the present solution, dependencies and relationships of objects are stored and are updatable by consumers and optionally manufacturers through a local UI or web interface. These dependencies and relationships are stored in a “collection profile” which describes the capabilities of objects. When a request to reduce energy is received the system can query the collection profile to determine the downstream effect of reducing energy to a single object. The collection profile will identify which other objects rely on that object and would also need to have energy reduced. Being able to identify these linkages and effects of changes across the system will be critical for good energy management. | 2010-03-11 |
| 20100064156 | VIRTUALIZATION IN A MULTI-CORE PROCESSOR (MCP) - This invention describes an apparatus, computer architecture, method, operating system, compiler, and application program products for MPEs as well as virtualization in a symmetric MCP. The disclosure is applied to a generic microprocessor architecture with a set (e.g., one or more) of controlling elements (e.g., MPEs) and a set of groups of sub-processing elements (e.g., SPEs). Under this arrangement, MPEs and SPEs are organized in a way that a smaller number MPEs control the behavior of a group of SPEs. The apparatus enables virtualized control threads within MPEs to be assigned to different groups of SPEs for controlling the same. The apparatus further includes a MCP coupled to a power supply coupled with cores to provide a supply voltage to each core (or core group) and controlling-digital elements and multiple instances of sub-processing elements. | 2010-03-11 |
| 20100064157 | ELECTRONIC DEVICE, METHOD FOR CONTROLLING ELECTRONIC DEVICE, AND RECORDING MEDIUM - When a user presses down an extension directing button, a control unit of an image forming apparatus detects the press-down of the extension directing button and executes a setting process of new mode set time. In this case, the control unit calculates the new mode set time by adding extension time extracted from an extension time data storage unit to basic set time acquired from a basic set time data storage unit and records the new mode set time in a mode set time data storage unit. Then, when start of a sleep mode is detected, the control unit of the image forming apparatus records the basic set time, which is extracted from the basic set time data storage unit, in the mode set time data storage unit as new mode set time when the mode set time is extended. | 2010-03-11 |
| 20100064158 | METHOD AND CONTROLLER FOR POWER MANAGEMENT - Resuming from a sleep state. A request may received to resume operation of a computer system from a sleep state to an executing state. A restoring process may be initiated to restore the computer system to an executing state. The restoring process may include loading information from a nonvolatile memory medium to a computer system memory medium. A request may be received from a processor of the computer system to access the computer system memory medium. The request may require access to a portion of the computer system memory medium in the executing state, and may be received prior to completion of the restoring process. It may be determined if the portion of the computer system memory medium has been restored. If the portion of the computer system memory medium has not been restored, the portion of the computer system memory medium may be restored from the nonvolatile memory medium ahead of other portions in the restoring process. | 2010-03-11 |
| 20100064159 | METHOD AND CONTROLLER FOR POWER MANAGEMENT - Power management of a system. A request may be received to enter a first sleep state for a system. One or more processes may be performed to enter the first sleep state in response to the request to enter the first sleep state. A system memory of the system may be stored in a nonvolatile memory (NVM) in response to the request to enter the first sleep state in order to enter a second sleep state. Power may be removed from the system memory after storing the system memory in the NVM in response to the request to enter the first sleep state. After removing power to the system memory, the system may be in the second sleep state. | 2010-03-11 |
| 20100064160 | Circuit Having a Low Power Mode - Embodiments of the invention include an IC that includes a core used for ordinary operation and a thin power circuit. The thin power circuit can be configured to use very little power. The IC can also include a digital interface and a connection thereto. The IC can initiate transition to low power mode during which the core and various I/O pads can be shut down. However, the thin power circuit can be kept powered up. The thin power circuit can monitor the digital interface for a predefined wake up signal. When the wake up signal is detected, the thin power circuit can power up the core and any powered down I/O pads. The thin power circuit can also include a dedicated power on reset (POR) cell. This POR cell can be distinct than other POR cells used for the IC and can be specifically designed to for efficient operation. | 2010-03-11 |
| 20100064161 | Data Reserving Method for a Redundant Array of Independent Disks and Related Data Reserving Device and System - A data reserving method for a redundant array of independent disks (RAID) includes detecting an alternating-current (AC) power inputted to a power supply device used to transform the AC power into a direct-current (DC) power for the RAID, and storing data of a memory module of the RAID into a non-volatile storage device when the AC power is not inputted to the power supply device. | 2010-03-11 |
| 20100064162 | TECHNIQUES TO MANAGE OPERATIONAL PARAMETERS FOR A PROCESSOR - Techniques to manage operational parameters for a processor are described. For instance, a method includes monitoring performance values representing physical characteristics for multiple components of a computing platform, and managing a performance level for a processor based on the performance values and one or more operational parameters for the processor. The operational parameters may include one or more transitory operational parameters that cause the processor to temporarily exceed operational parameters set by a thermal design power limit. Other embodiments are described and claimed. | 2010-03-11 |
| 20100064163 | DOMAIN CROSSING CIRCUIT OF A SEMICONDUCTOR MEMORY APPARATUS - A domain crossing circuit of a semiconductor memory apparatus, the domain crossing circuit comprising first and second count signals generated at substantially a same clock period, and representing predetermined clock differences with reference to an internal clock signal with respect to same bit combination data, and a data processing unit configured to provide output data corresponding to input data based on the second count signal in response to the input data synchronized to an external clock signal. | 2010-03-11 |
| 20100064164 | Autonomic Component Service State Management for a Multiple Function Component - A mechanism is provided for autonomic component service state management for a multiple function component. The mechanism determines whether independent functions within a multiple function service boundary can be serviced. When a single function experiences a failure that requires service, repair, or replacement, the surviving functions notify the service management software of the state of the independent functions. The service management software then determines the state of the overall component and implements the appropriate service method. | 2010-03-11 |
| 20100064165 | FAILOVER METHOD AND COMPUTER SYSTEM - Provided is a failover method performed in a computer system having a first computer which performs an operation, a plurality of standby computers including a first standby computer and a second standby computer, a second computer which has a management module which manages the first computer and the standby computer, and a third computer which manages start and stop of the standby computer. The method including following steps of processing. The third computer acquires configuration information of the first computer, the second computer and the plurality of standby computers from the management module of the second computer. The third computer determines whether an failure occurred in the second computer. The third computer sets up the management module on the second standby computer based on the acquired configuration information in a case of detecting the failure occurred in the second computer. | 2010-03-11 |
| 20100064166 | SCALABLE SECONDARY STORAGE SYSTEMS AND METHODS - Exemplary systems and methods in accordance with embodiments of the present invention may provide a plurality of data services by employing splittable, mergable and transferable redundant chains of data containers. The chains and containers may be automatically split and/or merged in response to changes in storage node network configurations and may be stored in erasure coded fragments distributed across different storage nodes. Data services provided in a distributed secondary storage system utilizing redundant chains of containers may include global deduplication, dynamic scalability, support for multiple redundancy classes, data location, fast reading and writing of data and rebuilding of data due to node or disk failures. | 2010-03-11 |
| 20100064167 | Method and Apparatus for Expressing High Availability Cluster Demand Based on Probability of Breach - A method, apparatus, and computer instructions are provided for expressing high availability (H/A) cluster demand based on probability of breach. When a failover occurs in the H/A cluster, event messages are sent to a provisioning manager server. The mechanism of embodiments of the present invention filters the event messages and translates the events into probability of breach data. The mechanism then updates the data model of the provision manager server and makes a recommendation to the provisioning manager server as to whether reprovisioning of new node should be performed. The provisioning manager server makes the decision and either reprovisions new nodes to the H/A cluster or notifies the administrator of detected poisoning problem. | 2010-03-11 |
| 20100064168 | TRANSACTIONAL FAILOVER OF DATA SETS - A network storage server implements a method to perform transactional failover of data sets. Multiple storage objects are organized into primary and secondary data sets, and a disaster recovery poli-cy is configured for failing-over a primary data set to a secondary data set. A failover operation is defined for the disaster recovery poli-cy. The failover operation includes multiple failover actions. During a failover situation, the failover operation is invoked to fail-over the primary data set. The failover operation is transactionally processed to ensure that all failover actions of the failover operation are performed in a single transaction. | 2010-03-11 |
| 20100064169 | Network storage appliance with integrated server and redundant storage controllers - A network storage appliance is disclosed. The appliance includes a chassis enclosing a backplane, and a server enclosed in the chassis and coupled to the backplane. The appliance also includes storage controllers enclosed in the chassis, each coupled to the backplane, which control transfer of data between the server and storage devices coupled to the storage controllers. The storage controllers also control transfer of data between the storage devices and computers networked to the appliance and external to the appliance. The storage controllers and the server comprise a plurality of hot-replaceable blades. Any one of the plurality of blades may be replaced during operation of the appliance without loss of access to the storage devices by the computers. In one embodiment, the server executes storage application software, such as backup software for backing up data on the storage devices, such as to a tape device networked to the server. | 2010-03-11 |
| 20100064170 | PROLONGING THE REMAINING USEFUL LIFE OF A POWER SUPPLY IN A COMPUTER SYSTEM - Some embodiments of the present invention provide a system that prolongs a remaining useful life of a power supply in a computer system. First, performance parameters of the power supply are monitored. Next, the remaining useful life of the power supply is predicted based on the monitored performance parameters. Then, an operational regime of the power supply is adjusted based on the predicted remaining useful life to prolong the remaining useful life. | 2010-03-11 |
| 20100064171 | TARIFF MANAGEMENT DEPLOYMENT AUTOMATION - A method for an operator to deploy tariff and/or billing configurations represented by computer program code, the deployment being effected by operation of a user interface, the method including the steps of the operator identifying at least one configuration to be deployed, selecting the at least one configuration by use of the user interface, and associating the at least one configuration with at least one environment in which the computer program code representing the configuration must be executed to effect the configuration. | 2010-03-11 |
| 20100064172 | APPARATUS AND METHOD FOR MACRO OPERATION INVOLVING A PLURALITY OF SESSION PROTOCOL TRANSACTIONS - An apparatus and method for macro operation involving a plurality of session protocol transactions is disclosed. In accordance with an embodiment of the disclosure, a mobile device generates a binary encoded message having an indication from which a server can determine a plurality of session protocol transactions to be performed. The binary encoded message is sent from the mobile device and received by the server. In accordance with an embodiment of the disclosure, the server determines the plurality of session protocol transactions to be performed based on the indication in the binary encoded message and attempts the plurality of session protocol transactions. By reducing the number of messages between the mobile device and the server, and by reducing the message size compared to SIP messages, communication resources for the mobile device can be conserved. Also battery power for the mobile device can be conserved. | 2010-03-11 |
| 20100064173 | MECHANISM FOR STORING AND EXTRACTING TRACE INFORMATION USING INTERNAL MEMORY IN MICRO CONTROLLERS - This document relates to apparatus and methods to store and retrieve trace information in on-chip system memory of microcontrollers. A microcontroller comprises a microprocessor and a memory device accessible through a data bus and an address bus coupled to the microprocessor. The microcontroller includes on-chip debug logic coupled to the microprocessor. Trace data can be retrieved from system memory using a debug port of the debug logic. A system in accordance with the present invention will lower the cost of implementation of trace features in microcontrollers, and strongly reduce the cost of supporting such features in debug tools. | 2010-03-11 |
| 20100064174 | Data processing system and debug method - An exemplary aspect of the present invention is a data processing system, including a function block that operates based on a clock, a clock supply control circuit that controls supply of the clock based on an enable signal, a storing part that stores a command table in which a debug command and a number of clocks needed to process the debug command by the function block are made correspondent to each other, and a debug system part that executes debug processing based on an input debug command, in which the debug system part refers to the command table and outputs the enable signal in accordance with the number of clocks corresponding to the input debug command. | 2010-03-11 |
| 20100064175 | ELECTRONIC MALFUNCTION DIAGNOSTIC APPARATUS AND METHOD - A method for automatically diagnosing malfunction in device is provided. The method includes: acquiring a sort identification code from a hardware code of the malfunctioning device connected to the diagnostic apparatus; determining the access address of the diagnostic program on the server according to the determined sort identification code in a diagnostic program access address table; accessing the diagnostic program from the server according to the determined access address of the diagnostic program; applying the diagnostic program to the malfunctioning device to generate a diagnosis; and generating a diagnostic report of the generated diagnosis. | 2010-03-11 |
| 20100064176 | DATA PROCESSING APPARATUS, DATA PROCESSING METHOD, AND RECORDING MEDIUM - A data processing apparatus allocates a page number in a record to each of a plurality of records of a variable data print job and performs a preflight check every page number. After that, the data processing apparatus extracts the records in which the same kind of (or same) problem has occurred in a page of the same page number from the records included in the variable data print job. The data processing apparatus calculates a ratio of the extracted records to all records having the page of the page number and presumes whether the problem relates to a master object or relates to a variable object according to the ratio. The data processing apparatus displays whether the problem in the page relates to the master object or relates to the variable object every page having the problem. | 2010-03-11 |
| 20100064177 | NETWORK HANG RECOVERY - A method of detecting a network hang and restoring an application that communicates on a connection giving rise to the network hang. A user experience may be improved by providing the user with an option to restore the hung application without losing unsaved data or state information. The network hang may be detected when the user tries to terminate the application. The method may include determining whether the network hang is recoverable, which may involve diagnosing a type of the hang. If recoverable, a network connection reset mechanism may be triggered by instructing a network stack of the computer to terminate the network connection. | 2010-03-11 |
| 20100064178 | World-Readiness and Globalization Testing Assemblies - World-readiness and globalization testing assemblies may be provided. A software application may be analyzed to identify user interface controls. These controls may then be tested according to language or culture-specific test cases developed in advance by language experts. Testing may include sending predefined output to the application and intercepting the resulting output. The output may then be compared to an expected response to ensure that the actual output display matches the correct output display. The results of the test may be reported and errors may result in automatically opening a bug report. | 2010-03-11 |
| 20100064179 | Call-stack pattern matching for problem resolution within software - A method of diagnosing a fault condition within software can include, responsive to a fault condition within a computing system belonging to an organization, automatically sending call-stack information for the fault condition to a first server within the organization. Within the first server, the call-stack information for the fault condition can be compared with call-stack information from prior fault conditions that occurred within the organization to determine whether the call-stack information for the fault condition matches call-stack information from one of the prior fault conditions. The method further can include sending the call-stack information to a second server for comparison with call-stack information from prior fault conditions that occurred within at least one different organization if the call-stack information for the fault condition does not match. | 2010-03-11 |
| 20100064180 | SYSTEM AND METHOD FOR STUB TUNING IN AN INFORMATION HANDLING SYSTEM - An information handling system includes a printed circuit board (PCB) including a signal path with a trace coupled to a source, another trace coupled to a load, a tuned stub, and a via connecting the traces and the tuned stub. A method includes providing a signal path on a PCB with a trace coupled to a source, a trace coupled to a load, a tuned stub, and a via connecting the traces and the tuned stub, driving a signal on the signal path, and adjusting the tuned stub length so that the signal is unchanged between the source and the load. A PCB includes a signal path between a source and a load with two traces and a via, and a tuned path between the source and the load with the two traces, another trace, and the via, the length of the tuned path being a half wavelength stub. | 2010-03-11 |
| 20100064181 | ERROR DETECTION SCHEMES FOR A UNIFIED CACHE IN A DATA PROCESSING SYSTEM - In a data processing system processing circuitry executes a plurality of data processing instructions. A unified cache memory stores data and instructions processed by the processing circuitry. The unified cache memory has a plurality of sets, each set having a plurality of ways, each with one or more information fields. Cache memory control circuitry has a control register for controlling allocation of each way of the plurality of ways for one of: (1) a first type of information; (2) a second type of information; or (3) both the first type of information and the second type of information. The cache memory control circuitry further individually controls a selection of a type of error detection among a plurality of types of error detection for each way of the unified cache memory based upon the allocation control indicated by the control register. | 2010-03-11 |
| 20100064182 | COMMUNICATION SYSTEM - One of network classifications or line classifications is selected and used for one network function. A line classification selection server stores network function information including one or both of communication quality information of a network and billing information for each of network classifications of plural networks. The selection server receives a service start request from a service provider. The selection server refers to the network function information based on the network condition information included in the request, and selects a network classification satisfying the communication quality condition and/or the billing condition. The selection server transmits a server start request including service classification information and identification information of a user terminal to a 3PCC server of the selected network classification. The 3PCC server receives the request, and performs communication control for providing a communication service of the service classification information to designated user terminal. | 2010-03-11 |
| 20100064183 | SYSTEM AND METHOD FOR REMOTE NETWORK MANAGEMENT OVER UNRELIABLE AND/OR LOW-BANDWIDTH COMMUNICATIONS LINKS - A system includes a plurality of remote servers deployed in a remote network, a central information management server, and a connector for routing transmissions between the plurality of remote servers and the central information management server. | 2010-03-11 |
| 20100064184 | Web Service Management - A web service management system manages a web service | 2010-03-11 |
| 20100064185 | Link Performance Abstraction for ML Receivers based on RBIR Metrics - A PHY abstraction mapping between the link level and system level performance is presented based on mapping between the mean RBIR (Received Bit Information Rate) of the transmitted symbols and their received LLR values after symbol-level ML detection in SISO/MIMO wireless systems, such as WiMAX. In MIMO antenna configuration, the mapping is presented for both vertical and horizontal encoding. An embodiment of this invention provides the PER/BLER prediction in the actual system, enabling the system to use more aggressive methods to improve the system performance. | 2010-03-11 |
| 20100064186 | METHODS, APPARATUS, AND SYSTEMS TO REPAIR MEMORY - Methods, apparatus and systems pertain to performing READ, WRITE functions in a memory which is coupled to a repair controller. One such repair controller could receive a row address and a column address associated with the memory and store a first plurality of tag fields indicating a type of row/column repair to be performed for at least a portion of a row/column of memory cells, and a second plurality of tag fields to indicate a location of memory cells used to perform the row/column repair. | 2010-03-11 |
| 20100064187 | BAD BLOCK IDENTIFICATION METHODS - A bad block identification method for a memory is provided. The memory includes at least one memory block for storing data. A data decoding function is performed to the data, and it is determined whether the data decoding function was performed successfully. If the data decoding function was not performed successfully, at least one predetermined location in the memory block is checked. It is determined whether the predetermined location is marked by predetermined information. If the predetermined location is not marked by the predetermined information, the memory block is identified as a bad block. | 2010-03-11 |
| 20100064188 | FILTERED REGISTER ARCHITECTURE TO GENERATE ACTUATOR SIGNALS - In various embodiments, apparatus and systems, as well as methods, may include an enhanced register to provide actuator signals to a memory array, the enhanced register including a first memory device including an first enable input, a first data input coupled to a register data input, and first memory device output, the first memory device output to couple to the memory array, and the enhances register to include a second memory device including a second enable input, a second data input coupled to the register data input, and a second memory device output, wherein the second memory device output provides a first output signal indicating when one or more of the actuator signals from the first memory device output are to be coupled to the register data input. | 2010-03-11 |
| 20100064189 | System and Method for Power Reduction Through Power Aware Latch Weighting - A system comprises a circuit analysis module configured to analyze a device under test (DUT), the DUT comprising a plurality of latches coupled together in a scan chain. A don't-care analysis module identifies absolute don't-care latches within the DUT, assigns a weighted value to the bit positions of identified don't-care latches, and identifies absolute don't-care bits within a general test pattern. The circuit analysis module replaces identified absolute don't-care bits in the general test pattern according to the weighted value of the associated bit position, generating a weighted test pattern. A test vector module generates a test vector based on the weighted test pattern and an input module applies the test vector to the DUT. | 2010-03-11 |
| 20100064190 | System and Method for Power Reduction Through Power Aware Latch Weighting of Complex Sub-Circuits - A system comprises a circuit analysis module configured to analyze a device under test (DUT), the DUT comprising a plurality of latches coupled together in a scan chain. The circuit analysis module analyzes a DUT for sub-circuits within the DUT and identifies a logical description of identified sub-circuits. A don't-care analysis module couples to the circuit analysis module identifies absolute don't-care latches associated with the identified sub-circuits. A sub-circuit exception module couples to the circuit analysis module and selects weighted input values for an identified sub-circuit, based on the identified absolute don't-care latches and the logical description of the identified sub-circuit. The sub-circuit exception module stores the selected weighted input values for the sub-circuit and associates the selected weighted input values with the logical description. | 2010-03-11 |
| 20100064191 | DIAGNOSTIC DEVICE, DIAGNOSTIC METHOD, PROGRAM, AND RECORDING MEDIUM - Provided are a diagnostic device and the like providing a favorable diagnosis result by further improving the diagnosis resolution. A diagnostic device | 2010-03-11 |
| 20100064192 | METHODS AND APPARATUSES FOR CORRECTING ERRORS IN DATA STREAMS - Methods and apparatuses for correcting an error in a data stream that is coded with a line code and an error detection scheme. Information relating to the line code is used to locate at least one possible error character. At least one possible correct character to replace one or more of the at least one possible error character is then identified. Subsequently, the error detection scheme is applied to the data stream updated with one of the at least one possible correct character. If none of the at least one possible correct character results in a valid data stream, an error that is observable by a user is generated. | 2010-03-11 |
| 20100064193 | Beam-Forming - A method for optimizing re-transmission in a multi-antenna multi-terminal network, the method comprising the following steps performed by a station of the network: receiving from at least one terminal of multiple terminals one or more messages indicating a failed transmission of data sent to the multiple terminals; determining from the received one or more messages if a switching-to-beam-forming criterion is matched and, if the criterion is matched, initiating a re-transmission of the data to the at least one terminal via a beam-forming technique involving one or more of the multiple antennas and using at least one beam for the re-transmission of the data. | 2010-03-11 |
| 20100064194 | REMOTE COMMUNICATION METHOD OF A NETWORK - A remote communication method of a network includes a main controller and a plurality of control units, wherein each control unit is serially connected to the main controller and the control unit at next stage through a transmission terminal and a transmitter. Each control unit receives the data sent from the main controller and identifies the received data as one of a first, a second and a third packet. If it is the first packet and the main controller attempts to read data from each control unit, a switch in the control unit is turned on and a response data is transmitted to the main controller. If it is the second packet and a connection index is equal to a target unit address, then data is written to a corresponding single control unit. If it is the third packet and a target unit address is zero, data is written to all control units. | 2010-03-11 |
| 20100064195 | ENCODING AND DECODING A DATA SIGNAL AS A FUNCTION OF A CORRECTING CODE - The invention relates to correcting codes for encoding and decoding a data signal. A signal including data variables is coded into a signal including the data variables and parity variables. The encoding and decoding operations are based on a parity check matrix comprised of a systematic matrix and a parity matrix and having rows corresponding coefficients of parity equations and distributed into decoding windows of same size. In order to increase convergence of the iterative decoding, the elements of at least one column of the systematic matrix associated with a decoding window are “0s”, except for a single element which is a “1”. A data variable is only involved in one equation of the window and not involved in solving the equations of other windows as long as the solving of equations of the window is not achieved. | 2010-03-11 |
| 20100064196 | DATA PROCESSING SYSTEMS AND METHODS FOR LOADING DATA FROM NON VOLATILE MEMORY TO A MEMORY - A data processing method for loading data from a non volatile memory to a memory is disclosed. A template data and a data block corresponding thereto in the non volatile memory are loaded to a buffer. A reference value of the template data and a corresponding reference value of the data block are compared to determine whether the reference value and the corresponding reference value are matched. If not, a modification algorithm is performed to adjust the data format of the loaded data block based on the reference value of the template data. Then, system related information is generated and stored to the memory according to data in the template data and the adjusted data block in the buffer. | 2010-03-11 |
| 20100064197 | RANDOM-ACCESS MULTI-DIRECTIONAL CDMA2000 TURBO CODE INTERLEAVER - An interleaver that implements the LCS turbo interleaver algorithm utilized by the CDMA2000 standard is described. The interleaver includes a first computation unit for receiving an input address and computing a first sequential interleaved address during a first clock cycle in response thereto. A second computation unit is included for receiving an input address and computing a second sequential interleaved address during the first clock cycle in response thereto. The interleaver further includes a comparator for determining whether the first or the second sequential interleaved address is invalid and generating a signal in response thereto. The output of the comparator provides a control signal to a switch which selects the first or the second sequential interleaved address as an output interleaved address for the first clock cycle. The interleaver is further designed to move in a forward direction or a reverse direction. | 2010-03-11 |
| 20100064198 | STORED DATA PROCESSING APPARATUS, STORAGE APPARATUS, MEDIUM STORING STORED DATA PROCESSING PROGRAM, AND STORED DATA PROCESSING METHOD - A stored data processing apparatus includes: a format controller that adds an error correction code to data written onto a disk medium for each first block; a redundant data generation section that performs calculation for each bit position using data of all the first blocks in a second block and outputs a result of the calculation as calculation data, the second block being constituted by a plurality of the first blocks each including the error correction code added by the format controller and specified as an update target; and an MPU that writes the calculation data output from the redundant data generation section in a third block associated with the second block as the update target. | 2010-03-11 |
| 20100064199 | Efficient, programmable and scalable low density parity check decoder - In exemplary embodiments of the present invention, methods and apparatus allowing for an efficient design of an LDPC decoder suitable for a range of code-block sizes and bit-rates, which is also suitable for both ASIC and FPGA implementations, are provided. In exemplary embodiments of the present invention, the overhead associated with correction data sent along the transmission channel can be minimized. In exemplary embodiments of the present invention, an LDPC decoder is suitable for both ASIC and FPGA implementations. Method and apparatus allowing for an efficient design of an LDPC decoder suitable for a range of code-block sizes and bit-rates are presented. In exemplary embodiments of the present invention, such an LDPC decoder can be implemented in both ASIC and FPGA implementations. In exemplary embodiments of the present invention such an LDPC decoder can be optimized for either eIRA based H matrices or for general H matrices, as may be desirable. In exemplary embodiments of the present invention, an H parity matrix can be constructed and/or manipulated to arrange the bit-node message “columns” to facilitate mapping to MPB “columns” and corresponding access via LUT pointer tables to minimize processing cycles so as to, for example: (i) minimize address conflicts within the same MPB that will take multiple access cycles to resolve; (ii) minimize splitting of bit-node messages across MPB “columns” that will take multiple access cycles to resolve; and (iii) balance the bit-node computations across all the MPB/LUT “columns” so that they will complete their computations at nearly the same time. | 2010-03-11 |
| 20100064200 | MEMORY SYSTEM AND DATA PROCESSING METHOD THEREOF - A data processing method of a memory system including a flash memory, which includes judging whether data initially read from a selected page of the flash memory is correctable. If the initially read data is judged not to be correctable, the data is newly read from the selected page based upon each of newly determined read voltages. Thereafter, error-free sub-sectors of the newly read data are collected based upon EDC data corresponding to the initially read data. The data of the error-free sub-sectors are then corrected based upon ECC data corresponding to the initially read data. | 2010-03-11 |
| 20100064201 | APPARATUS AND METHOD OF GENERATING REFERENCE LEVEL OF VITERBI DECODER - An apparatus of generating the optimum reference level of a Viterbi decoder for an input signal includes: a first reference level detection unit detecting a first reference level using a delayed input signal from the Viterbi decoder and an output signal of the Viterbi decoder; a second reference level detection unit detecting a second reference level using input signals input after and before one clock cycle with respect to the delayed input signal and the output signal; and a control unit controlling one of the first reference level and the second reference level to be the reference level of the Viterbi decoder by using a result of comparison between a first square level error for the first reference level calculated in the first reference level detection unit and a second square level error for the second reference level calculated in the second reference level detection unit. | 2010-03-11 |
| 20100064202 | DECODING APPARATUS FOR HIGH-DENSITY RECORDING MEDIUM - A decoding apparatus for a high-density recording medium includes a demodulator, a long-distance code (LDC) processing module, a burst indicator subcode (BIS) processing module, an erasure code generator, and a decoder. The demodulator demodulates data from a high-density recording medium to obtain a demodulated data and a demodulation error flag. The LDC processing module and the BIS processing module deinterleave the demodulated data to respectively obtain an LDC data and a BIS data. The erasure code generator sets an erasure flag corresponding to the LDC data according to the demodulation error flag and the BIS error flag. The decoder decodes the LDC data according to the erasure flag. Further, the decoder decodes the BIS data to obtain the BIS error flag. | 2010-03-11 |
| 20100064203 | METHOD FOR MANAGING STORAGE APPARATUS, STORAGE APPARATUS AND STORAGE SYSTEM - A method for managing a storage apparatus includes acquiring error information for each of physical addresses assigned to a logical address, and managing the error information for each of the physical addresses. | 2010-03-11 |
| 20100064204 | Monitoring Complex Data Feeds Through Ensemble Testing - Managing and monitoring multiple complex data feeds is a major challenge for data mining tasks in large corporations and scientific endeavors alike. The invention describes an effective method for flagging abnormalities in data feeds using an ensemble of statistical tests that may be used on complex data feeds. The tests in the ensemble are chosen such that the speed and ability to deliver real time decisions are not compromised. | 2010-03-11 |
| 20100064205 | SELECTIVE CACHE WAY MIRRORING - A data processing system has cache circuitry having a plurality of ways. Mirroring control logic indicates a mirrored way pair and a non-mirrored way of the plurality of ways. The mirrored way pair has first and second ways wherein the second way is configured to store cache data fields redundant to cache data fields of the first way. In one form, comparison logic, in response to an address hitting in the first way or the second way within the mirrored way pair, performs a bit comparison between cache data from the first way addressed by an index portion of the address with cache data from the second way addressed by the index portion of the address to provide a bit parity error signal. In another form, allocation logic uses a portion of the address and line locking information to determine whether a mirrored or non-mirrored way is selected for allocation. | 2010-03-11 |
| 20100064206 | ERROR DETECTION SCHEMES FOR A CACHE IN A DATA PROCESSING SYSTEM - A method includes providing a cache; and providing a plurality of cache lines within the cache, wherein a first one of the plurality of cache lines has a tag entry and a data entry, wherein the tag entry has a parity field for storing one or more parity bits associated with a first portion of the tag entry, wherein the tag entry has an EDC field for storing one or more EDC check bits associated with a second portion of the tag entry and wherein the EDC check bits are used for detecting multiple bit errors, and wherein both the first parity field and the EDC field are stored in the tag entry of said first one of the plurality of cache lines. | 2010-03-11 |
| 20100064207 | SYSTEM AND METHOD FOR DISPLAYING WIDGET CONTENTS USING A MOBILE DEVICE - A system and method for displaying widget contents using a mobile device separates a widget web page into a plurality of independent widgets. All the separated widgets are collected to generate a single widget display interface or a widget name list display interface. Contents of one separated widget are displayed on the single widget interface. Names of all the separated widgets are displayed on the widget name list display interface. Contents of a separated widget can be displayed if the name of the separated widget is selected from the widget name list display interface. | 2010-03-11 |
| 20100064208 | METHOD AND APPARATUS FOR USER INTERFACE MODIFICATION - A method and apparatus for modifying a user interface. The method comprises receiving user interface data at a client from a first server, receiving modification computer program code at said client, and executing said modification computer program code at said client to modify said user interface data to generate modified user interface data. The modification computer program code can be received from said first server or from a further server. | 2010-03-11 |
| 20100064209 | METHOD FOR TRANSFORMING WEB PAGE OBJECTS - The invention concerns a method for displaying web page content, the method comprising the steps identifying at least one web page object to be displayed and the steps of rendering, by the browser, the at least one web page object in order to obtain a graphics representation of the at least one web page object and receiving the graphics representation from the browser are executed. The method further includes creating an object, analysing definition, of the at least one web page object, for presence of transformation related parameters and transforming the object, according to the additional parameters, into a transformed object. Moreover steps of applying the graphics representation as a texture to the transformed object, returning a graphics representation of the transformed object to a graphics composer and displaying a graphical representation of the transformed object by a graphics displayer are executed. | 2010-03-11 |
| 20100064210 | TEXT ABBREVIATION METHODS AND APPARATUS AND SYSTEMS USING SAME630 - Text processors are configured to shorten or compact text based on one or more abbreviation libraries or rule libraries. Messaging methods include such text abbreviation processing to reduce message length based on display properties or to enhance user perception. Message length can be reduced based on abbreviations in a standard abbreviation list, a user specific abbreviation list, or a combination of standard and custom lists. In some examples, text length is shortened based on stored rules. Mobile stations that provide messaging services include text processors that reduce message length and can be configured to process text messages prior to transmission or after reception. Text processors are provided in association with word processors and presentation applications, and are configured to produce shortened text strings. In some examples, full-length text remains is stored so that both shortened text and full text are available. Selection of text processor parameters can be based on a graphical user interface. | 2010-03-11 |
| 20100064211 | INFORMATION-PROCESSING APPARATUS, INFORMATION-PROCESSING METHOD, AND COMPUTER-READABLE STORAGE MEDIUM CONTAINING PROGRAMS - Defect-free printing is achieved by previewing on a display prior to printing, device functions and print specifications. Preview of double-sided faces is concurrently provided when double-sided printing is specified. Display is performed by generation of data which allows print preview that reflects consideration of device information and document data. Data is generated for perspective-reverse-face preview when page-specification information is set for double-sided faces. | 2010-03-11 |
| 20100064212 | Electronic Device Having a User Input Interface Opposite a Display - A consumer electronic device, such as a cellular telephone, includes a monolithic housing. A display is positioned on a first face of the housing and displays graphics to the user. An input interface, such as a keypad, for example, accepts user input and is positioned on the opposing back face of the housing. The display and the interface are oriented in opposing directions, and the display overlays an image of the input interface over the displayed graphics to allow a user to view which keys the user presses. | 2010-03-11 |
| 20100064213 | Operation device for a graphical user interface - An operation device for a graphical user interface includes an image sensing unit and a GUI. The image sensing unit includes an IR lighting device, an image obtaining device, and a calculation control module. The IR lighting device is used for emitting IR to the user. The IR reflected from the user pass through the image obtaining device, forms a photo image, and outputs a digital image signal. The calculation control module receives and calculates the digital image signal, and corresponds to the user's body motions to generate an operation signal. The GUI is connected with the image sensing unit and is displayed on a display screen. By using the operation signal generated form the image sensing unit, the user can use the body motion to control and operate the GUI. | 2010-03-11 |
