IEEE Transactions on Microwave Theory and Techniques, 2003
This paper proposes a new design method for passive FET switches in the millimeter-wave (MMW) reg... more This paper proposes a new design method for passive FET switches in the millimeter-wave (MMW) regime. In contrast to the conventional resonant-type switch design method, this passive FET switch circuit utilizes impedance transformation to compensate the drain-source capacitance effect for the off state at high frequencies. By means of this new design concept, aand -band monolithic-microwave integrated-circuit single-pole double-throw (SPDT) switches using a GaAs pseudomorphic high electron-mobility-transistor process are demonstrated. The -band SPDT switch has a measured isolation better than 30 dB for the off state and 2-dB insertion loss for the on state from 38 to 45 GHz, while the -band switch also shows a measured isolation better than 30 dB for the off state and 4-dB insertion loss for the on state from 53 to 61 GHz. The obtained isolation performance using this design approach outmatches previously published FET switches in the MMW frequency range.
This paper presents a study and design of tunable concurrent dual-band receiver. Different system... more This paper presents a study and design of tunable concurrent dual-band receiver. Different system architectures and building blocks have been compared and analyzed. A tunable concurrent dual-band receiver front end has then been fabricated and characterized. It operates across a tri-tave 6-18 GHz bandwidth with a nominal 17-25 dB conversion gain, worst-case -15 dBm IIP3, and worst-case -24.5 dBm ICP 1 dB.
The noise figure (NF) of a front-end low-noise amplifier (LNA) places a lower bound on the sensit... more The noise figure (NF) of a front-end low-noise amplifier (LNA) places a lower bound on the sensitivity of a receiver. In a conventional LNA, there is a tradeoff between the intrinsic input capacitance of the input transistors and the achievable bandwidth (BW) of the amplifier. This makes it necessary to use smaller transistors at higher gate overdrive voltages to simultaneously achieve greater BW and better NF. Unfortunately, biasing the transistor in this fashion yields a power-inefficient design. Furthermore, the need for a smaller capacitance presents a challenge to electrostatic discharge (ESD) protection of the input due to its added capacitance.
This paper presents a scalable phased-array receiver system that covers a tritave bandwidth of 6-... more This paper presents a scalable phased-array receiver system that covers a tritave bandwidth of 6-to-18 GHz implemented in a 130 nm CMOS process. The single receiver element with a 10-bit phase shifting resolution achieves a maximum phase error of 2.5deg within a baseband amplitude variation of 1.5 dB for an arbitrary target angle. This dense interpolation provides excellent phase error/offset calibration capability in the array. A 4-element electrical array pattern is measured at 6 GHz, 13.5 GHz and 18 GHz, showing a worst case peak-to-null ratio of 21.5 dB. The EVM and phase noise improvements of the array compared with the single receiver element are also shown.
This paper reports a 6-to-18 GHz integrated phasedarray receiver implemented in 130-nm CMOS. The ... more This paper reports a 6-to-18 GHz integrated phasedarray receiver implemented in 130-nm CMOS. The receiver is easily scalable to build a very large-scale phased-array system. It concurrently forms four independent beams at two different frequencies from 6 to 18 GHz. The nominal conversion gain of the receiver ranges from 16 to 24 dB over the entire band while the worst-case cross-band and cross-polarization rejections are achieved 48 dB and 63 dB, respectively. Phase shifting is performed in the LO path by a digital phase rotator with the worst-case RMS phase error and amplitude variation of 0.5 and 0.4 dB, respectively, over the entire band. A four-element phased-array receiver system is implemented based on four receiver chips. The measured array patterns agree well with the theoretical ones with a peak-to-null ratio of over 21.5 dB.
This paper reports a 6-to-18 GHz integrated phasedarray receiver implemented in 130-nm CMOS. The ... more This paper reports a 6-to-18 GHz integrated phasedarray receiver implemented in 130-nm CMOS. The receiver is easily scalable to build a very large-scale phased-array system. It concurrently forms four independent beams at two different frequencies from 6 to 18 GHz. The nominal conversion gain of the receiver ranges from 16 to 24 dB over the entire band while the worst-case cross-band and cross-polarization rejections are achieved 48 dB and 63 dB, respectively. Phase shifting is performed in the LO path by a digital phase rotator with the worst-case RMS phase error and amplitude variation of 0.5 and 0.4 dB, respectively, over the entire band. A four-element phased-array receiver system is implemented based on four receiver chips. The measured array patterns agree well with the theoretical ones with a peak-to-null ratio of over 21.5 dB.
IEEE Transactions on Microwave Theory and Techniques, 2003
This paper proposes a new design method for passive FET switches in the millimeter-wave (MMW) reg... more This paper proposes a new design method for passive FET switches in the millimeter-wave (MMW) regime. In contrast to the conventional resonant-type switch design method, this passive FET switch circuit utilizes impedance transformation to compensate the drain-source capacitance effect for the off state at high frequencies. By means of this new design concept, aand -band monolithic-microwave integrated-circuit single-pole double-throw (SPDT) switches using a GaAs pseudomorphic high electron-mobility-transistor process are demonstrated. The -band SPDT switch has a measured isolation better than 30 dB for the off state and 2-dB insertion loss for the on state from 38 to 45 GHz, while the -band switch also shows a measured isolation better than 30 dB for the off state and 4-dB insertion loss for the on state from 53 to 61 GHz. The obtained isolation performance using this design approach outmatches previously published FET switches in the MMW frequency range.
This paper presents a study and design of tunable concurrent dual-band receiver. Different system... more This paper presents a study and design of tunable concurrent dual-band receiver. Different system architectures and building blocks have been compared and analyzed. A tunable concurrent dual-band receiver front end has then been fabricated and characterized. It operates across a tri-tave 6-18 GHz bandwidth with a nominal 17-25 dB conversion gain, worst-case -15 dBm IIP3, and worst-case -24.5 dBm ICP 1 dB.
The noise figure (NF) of a front-end low-noise amplifier (LNA) places a lower bound on the sensit... more The noise figure (NF) of a front-end low-noise amplifier (LNA) places a lower bound on the sensitivity of a receiver. In a conventional LNA, there is a tradeoff between the intrinsic input capacitance of the input transistors and the achievable bandwidth (BW) of the amplifier. This makes it necessary to use smaller transistors at higher gate overdrive voltages to simultaneously achieve greater BW and better NF. Unfortunately, biasing the transistor in this fashion yields a power-inefficient design. Furthermore, the need for a smaller capacitance presents a challenge to electrostatic discharge (ESD) protection of the input due to its added capacitance.
This paper presents a scalable phased-array receiver system that covers a tritave bandwidth of 6-... more This paper presents a scalable phased-array receiver system that covers a tritave bandwidth of 6-to-18 GHz implemented in a 130 nm CMOS process. The single receiver element with a 10-bit phase shifting resolution achieves a maximum phase error of 2.5deg within a baseband amplitude variation of 1.5 dB for an arbitrary target angle. This dense interpolation provides excellent phase error/offset calibration capability in the array. A 4-element electrical array pattern is measured at 6 GHz, 13.5 GHz and 18 GHz, showing a worst case peak-to-null ratio of 21.5 dB. The EVM and phase noise improvements of the array compared with the single receiver element are also shown.
This paper reports a 6-to-18 GHz integrated phasedarray receiver implemented in 130-nm CMOS. The ... more This paper reports a 6-to-18 GHz integrated phasedarray receiver implemented in 130-nm CMOS. The receiver is easily scalable to build a very large-scale phased-array system. It concurrently forms four independent beams at two different frequencies from 6 to 18 GHz. The nominal conversion gain of the receiver ranges from 16 to 24 dB over the entire band while the worst-case cross-band and cross-polarization rejections are achieved 48 dB and 63 dB, respectively. Phase shifting is performed in the LO path by a digital phase rotator with the worst-case RMS phase error and amplitude variation of 0.5 and 0.4 dB, respectively, over the entire band. A four-element phased-array receiver system is implemented based on four receiver chips. The measured array patterns agree well with the theoretical ones with a peak-to-null ratio of over 21.5 dB.
This paper reports a 6-to-18 GHz integrated phasedarray receiver implemented in 130-nm CMOS. The ... more This paper reports a 6-to-18 GHz integrated phasedarray receiver implemented in 130-nm CMOS. The receiver is easily scalable to build a very large-scale phased-array system. It concurrently forms four independent beams at two different frequencies from 6 to 18 GHz. The nominal conversion gain of the receiver ranges from 16 to 24 dB over the entire band while the worst-case cross-band and cross-polarization rejections are achieved 48 dB and 63 dB, respectively. Phase shifting is performed in the LO path by a digital phase rotator with the worst-case RMS phase error and amplitude variation of 0.5 and 0.4 dB, respectively, over the entire band. A four-element phased-array receiver system is implemented based on four receiver chips. The measured array patterns agree well with the theoretical ones with a peak-to-null ratio of over 21.5 dB.
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Papers by Yu-Jiu Wang