A) METODO MAPAS DE KARNAUGH

a)
OPERADORES NAND:

A B C D
12

11
3

b)
U135:A U135:B U135:D
7402 7402 7402

U136:A
1

13

1
2 12
13 U137:B U137:C
5 8
7427 4 10
U136:B 6 9
3
4 6 7402 7402
5 U138:B
5 F2
7427 4
U135:C 6
OPERADORES NOR: 8
10 7402
9 U137:D U138:A
11 2
7402 13 1
U137:A 12 3
2
1 7402 7402
3

7402
 c)
OPERADORES NAND:
A B C D E

U52 U51 U50 U49 U48

NAND_2 NAND_2 NAND_2 NAND_2 NAND_2

U53

NAND_3
U54

NAND_2
U55 U60 U61

NAND_3 NAND_5 NAND_2

U56

NAND_3
U57 U62
F3

NAND_3 NAND_3
U58

NAND_4
U59

NAND_3
QUARTUS II:
LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY PUNTO_A_ECGC IS

PORT(

A,B,C,D,E : IN STD_LOGIC;

F1,F2,F3 : OUT STD_LOGIC);

END PUNTO_A_ECGC;

ARCHITECTURE D7 OF PUNTO_A_ECGC IS

SIGNAL ABCD : STD_LOGIC_VECTOR (3 DOWNTO 0);

SIGNAL ABCDE : STD_LOGIC_VECTOR (4 DOWNTO 0);

BEGIN

ABCD<=A&B&C&D;

ABCDE<=A&B&C&D&E;

WITH ABCDE SELECT

F1<= '1' WHEN "00001",

'1' WHEN "00010",

'1' WHEN "00011",

'1' WHEN "00110",

'1' WHEN "00111",

'1' WHEN "01000",

'1' WHEN "01010",

'1' WHEN "01101",

'1' WHEN "01111",

'1' WHEN "10000",

'1' WHEN "10001",

'1' WHEN "10011",

'1' WHEN "10101",

'1' WHEN "10110",

'1' WHEN "11001",

'1' WHEN "11011",

'1' WHEN "11111",

'0' WHEN OTHERS;

WITH ABCD SELECT

F2<= '1' WHEN "0010",

'1' WHEN "0011",

'1' WHEN "0110",

'1' WHEN "0111",

'1' WHEN "1011",

'1' WHEN "1100",

'1' WHEN "1110",

'0' WHEN OTHERS;

F3<=(A AND (NOT B) AND E) OR (B AND C AND (NOT D)) OR ((NOT A) AND B AND C) OR ((NOT A) AND B AND E) OR (A AND D AND (NOT E))

OR (A AND (NOT C) AND (NOT D)) OR ((NOT A) AND (NOT B) AND C AND NOT(D)) OR (B AND C AND D AND E) OR (A AND (NOT C)
AND (NOT D) AND E);

END D7;

XILINX:
TEST-BENCH (VECTOR DE PRUEBA)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY TB IS

END TB;

ARCHITECTURE behavior OF TB IS

COMPONENT PUNTO_A_ECGC

PORT(

A : IN std_logic;

B : IN std_logic;

C : IN std_logic;

D : IN std_logic;

E : IN std_logic;

F1 : OUT std_logic;

F2 : OUT std_logic;

F3 : OUT std_logic

);

END COMPONENT;

signal A : std_logic := '0';

signal B : std_logic := '0';

signal C : std_logic := '0';

signal D : std_logic := '0';

signal E : std_logic := '0';

signal F1 : std_logic;

signal F2 : std_logic;

signal F3 : std_logic;

BEGIN

uut: PUNTO_A_ECGC PORT MAP (

A => A,

B => B,

C => C,

D => D,

E => E,

F1 => F1,

F2 => F2,
 F3 => F3

);

PROCESO1: process

begin

wait for 320 ns; A<=NOT A;

end process;

PROCESO2: process

begin

wait for 160 ns; B<=NOT B;

end process;

PROCESO3: process

begin

wait for 80 ns; C<=NOT C;

end process;

PROCESO4: process

begin

wait for 40 ns; D<=NOT D;

end process;

PROCESO5: process

begin

wait for 20 ns; E<=NOT E;

end process;

END;
WINCUPL:
Name PUNTO_A_ECGC ;
PartNo 00 ;
Date 14/9/2017 ;
Revision 01 ;
Designer Engineer ;
Company CRISREX ;
Assembly None ;
Location ;
Device g22v10 ;
/* *************** INPUT PINS *********************/
PIN 2 = A ; /* */
PIN 3 = B ; /* */
PIN 4 = C ; /* */
PIN 5 = D ; /* */
PIN 6 = E ; /* */

/* *************** OUTPUT PINS *********************/

PIN 18 = F_1 ; /* */
PIN 17 = F_2 ; /* */
PIN 16 = F_3 ; /* */

FIELD ENTRADA = A,B,C,D,E;

TABLE ENTRADA => F_1 {
'b'00000=>'b'0;
'b'00001=>'b'1;
'b'00010=>'b'1;
'b'00011=>'b'1;
'b'00100=>'b'0;
'b'00101=>'b'0;
'b'00110=>'b'1;
'b'00111=>'b'1;
'b'01000=>'b'1;
'b'01001=>'b'0;
'b'01010=>'b'1;
'b'01011=>'b'0;
 'b'01100=>'b'0;
'b'01101=>'b'1;
'b'01110=>'b'0;
'b'01111=>'b'1;
'b'10000=>'b'1;
'b'10001=>'b'1;
'b'10010=>'b'0;
'b'10011=>'b'1;
'b'10100=>'b'0;
'b'10101=>'b'1;
'b'10110=>'b'1;
'b'10111=>'b'0;
'b'11000=>'b'0;
'b'11001=>'b'1;
'b'11010=>'b'0;
'b'11011=>'b'1;
'b'11100=>'b'0;
'b'11101=>'b'0;
'b'11110=>'b'0;
'b'11111=>'b'1;
}
FIELD ENTRADA_1 = A,B,C,D;
TABLE ENTRADA_1 => F_2 {
'b'0000=>'b'0;
'b'0001=>'b'0;
'b'0010=>'b'1;
'b'0011=>'b'1;
'b'0100=>'b'0;
'b'0101=>'b'0;
'b'0110=>'b'1;
'b'0111=>'b'1;
'b'1000=>'b'0;
'b'1001=>'b'0;
'b'1010=>'b'0;
'b'1011=>'b'1;
'b'1100=>'b'1;
'b'1101=>'b'0;
'b'1110=>'b'1;
'b'1111=>'b'0;
}
F_3=(A&!B&E)#(B&C&!D)#(!A&B&C)#(!A&B&E)#(A&D&!E)#(A&!C&!D)#(!A&!B&C&!D)#(B&C&D&E)#(A&!C&!D&E);

B) OREX/NOREX
a) A B C D

13

11
5

9
U7:C U7:D U7:E U7:F
7404 7404 7404 7404

12

10

8
U65:A
1
3
U63 2

7408 U69:A
U65:B 1
4 3
XOR_2 6 2
5
7432
U64:A 7408 U69:C
U139 9 F1
8
10
U66
XOR_2 U69:B 7432
XOR_2 4
6
5
AND_3
7432
U140
XOR_2

U68

AND_3

A B C D
b)
13
5

U67:C U67:D
7404 7404
U70
6

12

U65:C
9
8
10 U69:D
XOR_2 12
U71 7408 11
U65:D 13
12
11 7432
13
XOR_2
7408 U75:A
U73 1
3
2

7432
AND_3
U75:C
U141 9 F2
XOR_2 8
10

7432

U72

U75:B
4
AND_3 6
U74 5

7432

AND_3
QUARTUS II:
LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY PUNTO_B_ECGC IS

PORT(

A,B,C,D : IN STD_LOGIC;

F1,F2 : OUT STD_LOGIC);

END PUNTO_B_ECGC;

ARCHITECTURE D7 OF PUNTO_B_ECGC IS

SIGNAL ABCD : STD_LOGIC_VECTOR (3 DOWNTO 0);

BEGIN

ABCD<=A&B&C&D;

WITH ABCD SELECT

F1<= '1' WHEN "0000",

'1' WHEN "0001",

'1' WHEN "0011",

'1' WHEN "0101",

'1' WHEN "1001",

'1' WHEN "1010",

'1' WHEN "1100",

'1' WHEN "1101",

'1' WHEN "1110",

'0' WHEN OTHERS;

WITH ABCD SELECT

F2<= '1' WHEN "0000",

'1' WHEN "0010",

'1' WHEN "0011",

'1' WHEN "0101",

'1' WHEN "0110",

'1' WHEN "1000",

'1' WHEN "1010",

'1' WHEN "1011",

'1' WHEN "1100",

'1' WHEN "1101",

'1' WHEN "1111",

'0' WHEN OTHERS;

END D7;
XILINX:
TEST-BENCH (VECTOR DE PRUEBA)
LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY TB IS

END TB;

ARCHITECTURE behavior OF TB IS

COMPONENT PUNTO_B_ECGC

PORT(

A : IN std_logic;

B : IN std_logic;

C : IN std_logic;

D : IN std_logic;
 F1 : OUT std_logic;

F2 : OUT std_logic

);

END COMPONENT;

signal A : std_logic := '0';

signal B : std_logic := '0';

signal C : std_logic := '0';

signal D : std_logic := '0';

signal F1 : std_logic;

signal F2 : std_logic;

BEGIN

uut: PUNTO_B_ECGC PORT MAP (

A => A,

B => B,

C => C,

D => D,

F1 => F1,

F2 => F2

);

PROCESO1: process

begin

wait for 160 ns; A<=NOT A;

end process;

PROCESO2: process

begin

wait for 80 ns; B<=NOT B;

end process;

PROCESO3: process

begin

wait for 40 ns; C<=NOT C;

end process;

PROCESO4: process

begin

wait for 20 ns; D<=NOT D;

end process;

END;
WINCUPL:
Name PUNTO_B_ECGC ;
PartNo 00 ;
Date 14/9/2017 ;
Revision 01 ;
Designer Engineer ;
Company CRISREX ;
Assembly None ;
Location ;
Device g22v10 ;

/* *************** INPUT PINS *********************/

PIN 2 = A ; /* */
PIN 3 = B ; /* */
PIN 4 = C ; /* */
PIN 5 = D ; /* */

/* *************** OUTPUT PINS *********************/

PIN 17 = F_1 ; /* */
PIN 18 = F_2 ; /* */

FIELD ENTRADA = A,B,C,D;

TABLE ENTRADA => F_1 {
'b'0000=>'b'1;
'b'0001=>'b'1;
'b'0010=>'b'0;
'b'0011=>'b'1;
'b'0100=>'b'0;
'b'0101=>'b'1;
'b'0110=>'b'0;
'b'0111=>'b'0;
'b'1000=>'b'0;
'b'1001=>'b'1;
'b'1010=>'b'1;
'b'1011=>'b'0;
'b'1100=>'b'1;
'b'1101=>'b'1;
'b'1110=>'b'1;
'b'1111=>'b'0;
}
TABLE ENTRADA => F_2 {
'b'0000=>'b'1;
'b'0001=>'b'0;
'b'0010=>'b'1;
 'b'0011=>'b'1;
'b'0100=>'b'0;
'b'0101=>'b'1;
'b'0110=>'b'1;
'b'0111=>'b'0;
'b'1000=>'b'1;
'b'1001=>'b'0;
'b'1010=>'b'1;
'b'1011=>'b'1;
'b'1100=>'b'1;
'b'1101=>'b'1;
'b'1110=>'b'0;
'b'1111=>'b'1;
}

C) QUINE McCLUSKEY
a) A B C D

F1:
13
1

U1:A U1:B U1:C U1:D

7404 7404 7404 7404
2

12

U2

OR_3
U3

U6
F1
OR_3
U4
AND_4

OR_3
U5

OR_3
 F2: A B C D E

13
9

5
U67:F U76:A U76:B U76:C U76:D
7404 7404 7404 7404 7404
U77

12
AND_3
U78 U84

AND_3 OR_3
U79

AND_4
U80

U86
F2
AND_4
U81 U85
OR_3

AND_4 OR_3
U82

AND_4
U83

AND_4

QUARTUS II:
LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY PUNTO_C_ECGC IS

PORT(

A,B,C,D,E : IN STD_LOGIC;

F1,F2 : OUT STD_LOGIC);

END PUNTO_C_ECGC;

ARCHITECTURE D7 OF PUNTO_C_ECGC IS

SIGNAL ABCD : STD_LOGIC_VECTOR (3 DOWNTO 0);

SIGNAL ABCDE : STD_LOGIC_VECTOR (4 DOWNTO 0);

BEGIN

ABCD<=A&B&C&D;

WITH ABCD SELECT

F1<= '1' WHEN "0000",

 '1' WHEN "0010",

'X' WHEN "0100",

'X' WHEN "0101",

'1' WHEN "0111",

'1' WHEN "1001",

'1' WHEN "1011",

'1' WHEN "1100",

'X' WHEN "1101",

'0' WHEN OTHERS;

ABCDE<=A&B&C&D&E;

WITH ABCDE SELECT

F2<= '1' WHEN "00000",

'1' WHEN "00100",

'1' WHEN "00101",

'1' WHEN "01001",

'1' WHEN "01010",

'1' WHEN "01101",

'1' WHEN "01110",

'1' WHEN "01111",

'1' WHEN "10001",

'1' WHEN "10011",

'1' WHEN "10100",

'1' WHEN "10110",

'1' WHEN "11001",

'1' WHEN "11010",

'1' WHEN "11101",

'1' WHEN "11110",

'0' WHEN OTHERS;

END D7;
XILINX:
TEST-BENCH (VECTOR DE PRUEBA)
LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY TB IS

END TB;

ARCHITECTURE behavior OF TB IS

COMPONENT PUNTO_C_ECGC

PORT(

A : IN std_logic;

B : IN std_logic;

C : IN std_logic;

D : IN std_logic;

E : IN std_logic;

F1 : OUT std_logic;

F2 : OUT std_logic

);

END COMPONENT;

signal A : std_logic := '0';

signal B : std_logic := '0';

signal C : std_logic := '0';

signal D : std_logic := '0';

signal E : std_logic := '0';

 signal F1 : std_logic;

signal F2 : std_logic;

BEGIN

uut: PUNTO_C_ECGC PORT MAP (

A => A,

B => B,

C => C,

D => D,

E => E,

F1 => F1,

F2 => F2

);

PROCESO1: process

begin

wait for 320 ns; A<=NOT A;

end process;

PROCESO2: process

begin

wait for 160 ns; B<=NOT B;

end process;

PROCESO3: process

begin

wait for 80 ns; C<=NOT C;

end process;

PROCESO4: process

begin

wait for 40 ns; D<=NOT D;

end process;

PROCESO5: process

begin

wait for 20 ns; E<=NOT E;

end process;

END;
WINCUPL:
Name PUNTO_C_ECGC ;
PartNo 00 ;
Date 16/9/2017 ;
Revision 01 ;
Designer Engineer ;
Company CRISREX ;
Assembly None ;
Location ;
Device g22v10 ;
/* *************** INPUT PINS *********************/
PIN 2 = A ; /* */
PIN 3 = B ; /* */
PIN 4 = C ; /* */
PIN 5 = D ; /* */
PIN 6 = E ; /* */
/* *************** OUTPUT PINS *********************/
PIN 17 = F_1 ; /* */
PIN 18 = F_2 ; /* */

FIELD ENTRADA = A,B,C,D;

TABLE ENTRADA => F_1 {
'b'0000=>'b'1;
'b'0001=>'b'0;
'b'0010=>'b'1;
'b'0011=>'b'0;
'b'0100=>'b'0;
'b'0101=>'b'0;
'b'0110=>'b'0;
'b'0111=>'b'1;
'b'1000=>'b'0;
'b'1001=>'b'1;
'b'1010=>'b'0;
 'b'1011=>'b'1;
'b'1100=>'b'1;
'b'1101=>'b'X;
'b'1110=>'b'0;
'b'1111=>'b'0;
}

FIELD ENTRADA_2 = A,B,C,D,E;

TABLE ENTRADA_2 => F_2 {
'b'00000=>'b'1;
'b'00001=>'b'0;
'b'00010=>'b'0;
'b'00011=>'b'0;
'b'00100=>'b'1;
'b'00101=>'b'1;
'b'00110=>'b'0;
'b'00111=>'b'0;
'b'01000=>'b'0;
'b'01001=>'b'1;
'b'01010=>'b'1;
'b'01011=>'b'0;
'b'01100=>'b'0;
'b'01101=>'b'1;
'b'01110=>'b'1;
'b'01111=>'b'1;
'b'10000=>'b'0;
'b'10001=>'b'1;
'b'10010=>'b'0;
'b'10011=>'b'1;
'b'10100=>'b'1;
'b'10101=>'b'0;
'b'10110=>'b'1;
'b'10111=>'b'0;
'b'11000=>'b'0;
'b'11001=>'b'1;
'b'11010=>'b'1;
'b'11011=>'b'0;
'b'11100=>'b'0;
'b'11101=>'b'1;
'b'11110=>'b'1;
'b'11111=>'b'0;
}
 A B C D

b)
11

3
MULTIFUNCIONES:
U1:E U1:F U7:A U7:B
7404 7404 7404 7404
U8
10

U10:A
1
AND_3 3
U9 2

7432

AND_4
U11:A
1
3
2

7408 U12
U11:B F1
4
6
5
OR_4
7408
U11:C
9
8
10

7408
U13

AND_3
U14
U17
F2

AND_3
U15
OR_5

AND_3
U16

AND_3
U11:D
12
11
13
U20
7408 F3
U18

OR_4

AND_3
U19

AND_3
QUARTUS II:
LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY PUNTO_C_ECGC IS

PORT(

A,B,C,D : IN STD_LOGIC;

F1,F2,F3 : OUT STD_LOGIC);

END PUNTO_C_ECGC;

ARCHITECTURE D7 OF PUNTO_C_ECGC IS

SIGNAL ABCD : STD_LOGIC_VECTOR (3 DOWNTO 0);

BEGIN

ABCD<=A&B&C&D;

WITH ABCD SELECT

F1<= '1' WHEN "0000",

'1' WHEN "0001",

'X' WHEN "0010",

'X' WHEN "0011",

'1' WHEN "0100",

'1' WHEN "0110",

'1' WHEN "0111",

'1' WHEN "1001",

'X' WHEN "1011",

'X' WHEN "1110",

'1' WHEN "1111",

'0' WHEN OTHERS;

WITH ABCD SELECT

F2<= '1' WHEN "0001",

'1' WHEN "0010",

'X' WHEN "0011",

'1' WHEN "0101",

'X' WHEN "1000",

'1' WHEN "1001",

'X' WHEN "1011",

'1' WHEN "1100",

'X' WHEN "1110",

'1' WHEN "1111",

'0' WHEN OTHERS;

WITH ABCD SELECT

F3<= '1' WHEN "0000",

'1' WHEN "0010",

'1' WHEN "0011",

'1' WHEN "0101",

'1' WHEN "1000",

'1' WHEN "1010",

'1' WHEN "1100",

'1' WHEN "1101",

'1' WHEN "1111",

'0' WHEN OTHERS;

END D7;
XILINX:
TEST-BENCH (VECTOR DE PRUEBA)
LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY TB IS

END TB;

ARCHITECTURE behavior OF TB IS

COMPONENT PUNTO_C_ECGC

PORT(

A : IN std_logic;

B : IN std_logic;

C : IN std_logic;

D : IN std_logic;

F1 : OUT std_logic;

F2 : OUT std_logic;

F3 : OUT std_logic

);

END COMPONENT;

signal A : std_logic := '0';

signal B : std_logic := '0';

signal C : std_logic := '0';

signal D : std_logic := '0';

signal F1 : std_logic;

signal F2 : std_logic;

signal F3 : std_logic;

BEGIN

uut: PUNTO_C_ECGC PORT MAP (

A => A,

B => B,

C => C,

D => D,

F1 => F1,

F2 => F2,
 F3 => F3

);

PROCESO1: process

begin

wait for 160 ns; A<=NOT A;

end process;

PROCESO2: process

begin

wait for 80 ns; B<=NOT B;

end process;

PROCESO3: process

begin

wait for 40 ns; C<=NOT C;

end process;

PROCESO4: process

begin

wait for 20 ns; D<=NOT D;

end process;

END;
WINCUPL:
Name PUNTO_C_ECGC ;
PartNo 00 ;
Date 16/9/2017 ;
Revision 01 ;
Designer Engineer ;
Company CRISREX ;
Assembly None ;
Location ;
Device g22v10 ;
/* *************** INPUT PINS *********************/
PIN 2=A ; /* */
PIN 3=B ; /* */
PIN 4=C ; /* */
PIN 5=D ; /* */
/* *************** OUTPUT PINS *********************/
PIN 17=F_1 ; /* */
PIN 18=F_2 ; /* */
PIN 19=F_3 ; /* */

FIELD ENTRADA = A,B,C,D;

TABLE ENTRADA => F_1 {
'b'0000=>'b'1;
'b'0001=>'b'1;
'b'0010=>'b'X;
'b'0011=>'b'X;
'b'0100=>'b'1;
'b'0101=>'b'0;
'b'0110=>'b'1;
'b'0111=>'b'1;
'b'1000=>'b'0;
'b'1001=>'b'1;
'b'1010=>'b'0;
'b'1011=>'b'X;
'b'1100=>'b'0;
'b'1101=>'b'0;
'b'1110=>'b'X;
'b'1111=>'b'1;
}
TABLE ENTRADA => F_2 {
'b'0000=>'b'0;
'b'0001=>'b'1;
'b'0010=>'b'1;
'b'0011=>'b'X;
'b'0100=>'b'0;
'b'0101=>'b'1;
'b'0110=>'b'0;
'b'0111=>'b'0;
'b'1000=>'b'X;
'b'1001=>'b'1;
'b'1010=>'b'0;
'b'1011=>'b'X;
'b'1100=>'b'1;
'b'1101=>'b'0;
'b'1110=>'b'X;
'b'1111=>'b'1;
}
TABLE ENTRADA => F_3 {
'b'0000=>'b'1;
 'b'0001=>'b'0;
'b'0010=>'b'1;
'b'0011=>'b'1;
'b'0100=>'b'0;
'b'0101=>'b'1;
'b'0110=>'b'0;
'b'0111=>'b'0;
'b'1000=>'b'1;
'b'1001=>'b'0;
'b'1010=>'b'1;
'b'1011=>'b'0;
'b'1100=>'b'1;
'b'1101=>'b'1;
'b'1110=>'b'0;
'b'1111=>'b'1;
}

D) VARIABLES BIFORMES
a)
A B C D E
11

U76:E U76:F U87:A U87:B U87:C

7404 7404 7404 7404 7404
U88
10

AND_3
U89 U95

AND_3 OR_3
U90

AND_3
U91
U97
F_A

AND_3
U92 U96 OR_3

AND_3 OR_3
U93

AND_4
U94

AND_4
 b) A B C D E
13

11

U87:D U87:E U87:F U98:A U98:B

7404 7404 7404 7404 7404
U99
12

10

AND_3
U100 U107

AND_3 OR_3
U101

AND_4
U102
U109
F_B

AND_4
U103 U108
OR_3

AND_4 OR_3
U105

U106
AND_3

AND_3

QUARTUS II:
LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY PUNTO_D_ECGC IS

PORT(

A,B,C,D,E : IN STD_LOGIC;

F1,F2 : OUT STD_LOGIC);

END PUNTO_D_ECGC;

ARCHITECTURE D7 OF PUNTO_D_ECGC IS

SIGNAL ABCDE : STD_LOGIC_VECTOR (4 DOWNTO 0);

BEGIN

ABCDE<=A&B&C&D&E;

WITH ABCDE SELECT

F1<= '1' WHEN "00000",

'1' WHEN "00001",

'1' WHEN "00100",

'1' WHEN "00101",

'1' WHEN "01001",

'1' WHEN "01010",

'1' WHEN "01100",

'1' WHEN "01101",

'1' WHEN "01110",

'1' WHEN "10011",

'1' WHEN "10101",

'1' WHEN "10111",

'1' WHEN "11000",

'1' WHEN "11001",

'1' WHEN "11100",

'1' WHEN "11101",

'0' WHEN OTHERS;

F2<=(A AND (NOT B) AND (NOT D) AND E) OR (B AND NOT(C) AND D AND (NOT E)) OR ((NOT A) AND (NOT B) AND C AND D) OR (A AND B
AND (NOT C) AND E)

OR ((NOT A) AND (NOT B) AND (NOT C) AND (NOT D) AND (NOT E)) OR (A AND (NOT B) AND (NOT C) AND D AND E) OR (A AND B
AND C AND (NOT D) AND E);

END D7;
XILINX:
TEST-BENCH (VECTOR DE PRUEBA)
LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY TB IS

END TB;

ARCHITECTURE behavior OF TB IS

COMPONENT PUNTO_D_ECGC

PORT(

A : IN std_logic;

B : IN std_logic;

C : IN std_logic;

D : IN std_logic;

E : IN std_logic;

F1 : OUT std_logic;
 F2 : OUT std_logic

);

END COMPONENT;

signal A : std_logic := '0';

signal B : std_logic := '0';

signal C : std_logic := '0';

signal D : std_logic := '0';

signal E : std_logic := '0';

signal F1 : std_logic;

signal F2 : std_logic;

BEGIN

uut: PUNTO_D_ECGC PORT MAP (

A => A,

B => B,

C => C,

D => D,

E => E,

F1 => F1,

F2 => F2

);

PROCESO1: process

begin

wait for 320 ns; A<=NOT A;

end process;

PROCESO2: process

begin

wait for 160 ns; B<=NOT B;

end process;

PROCESO3: process

begin

wait for 80 ns; C<=NOT C;

end process;

PROCESO4: process

begin

wait for 40 ns; D<=NOT D;

end process;

PROCESO5: process
 begin

wait for 20 ns; E<=NOT E;

end process;

END;

WINCUPL:
Name PUNTO_D_ECGC ;
PartNo 00 ;
Date 16/9/2017 ;
Revision 01 ;
Designer Engineer ;
Company CRISREX ;
Assembly None ;
Location ;
Device g22v10 ;
/* *************** INPUT PINS *********************/
PIN 2=A ; /* */
PIN 3=B ; /* */
PIN 4=C ; /* */
PIN 5=D ; /* */
PIN 6=E ; /* */
/* *************** OUTPUT PINS *********************/
PIN 17=F_1 ; /* */
PIN 18=F_2 ; /* */

FIELD ENTRADA = A,B,C,D,E;

TABLE ENTRADA => F_1 {
'b'00000=>'b'1;
'b'00001=>'b'1;
'b'00010=>'b'0;
'b'00011=>'b'0;
'b'00100=>'b'1;
'b'00101=>'b'1;
'b'00110=>'b'0;
'b'00111=>'b'0;
'b'01000=>'b'0;
'b'01001=>'b'1;
'b'01010=>'b'1;
'b'01011=>'b'0;
'b'01100=>'b'1;
'b'01101=>'b'1;
'b'01110=>'b'1;
'b'01111=>'b'0;
'b'10000=>'b'0;
'b'10001=>'b'0;
'b'10010=>'b'0;
'b'10011=>'b'1;
'b'10100=>'b'0;
'b'10101=>'b'1;
'b'10110=>'b'0;
'b'10111=>'b'1;
'b'11000=>'b'1;
'b'11001=>'b'1;
'b'11010=>'b'0;
'b'11011=>'b'0;
'b'11100=>'b'1;
'b'11101=>'b'1;
'b'11110=>'b'0;
'b'11111=>'b'0;
}

F_2=(A&!B&!D&E)#(B&!C&D&!E)#(!A&!B&C&D)#(A&B&!C&E)#(!A&!B&!C&!D&!E)#(A&!B&!C&D&E)#(A&B&C&!D&E);

A B C D

E) APLICACION MAPAS DE
13

11
5

KARNAUGH U98:C U98:D U98:E U98:F

7404 7404 7404 7404
U104
6

12

10

AND_3
U110 U115

AND_3 OR_3
U111

U117
F1
AND_3
U112
OR_3

AND_3
U113 U116

AND_3 OR_3
U114

AND_3
U118

U10:B
4
AND_3 6
U119 5

7432
U10:D
12 F2
AND_3 11
U120 13

7432
U10:C
9
AND_3 8
U121 10

7432

AND_3
QUARTUS II:
LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY PUNTO_E_ECGC IS

PORT(

A,B,C,D : IN STD_LOGIC;

F1,F2 : OUT STD_LOGIC);

END PUNTO_E_ECGC;

ARCHITECTURE D7 OF PUNTO_E_ECGC IS

SIGNAL ABCD : STD_LOGIC_VECTOR (3 DOWNTO 0);

BEGIN

ABCD<=A&B&C&D;

WITH ABCD SELECT

F1<= '1' WHEN "0001",

'1' WHEN "0010",

'1' WHEN "0011",

'1' WHEN "0100",

'1' WHEN "0101",

'1' WHEN "0110",

'1' WHEN "1000",

'1' WHEN "1001",

'1' WHEN "1010",

'1' WHEN "1100",

'0' WHEN OTHERS;

WITH ABCD SELECT

F2<= '1' WHEN "0111",

'1' WHEN "1011",

'1' WHEN "1101",

'1' WHEN "1110",

'1' WHEN "1111",

 '0' WHEN OTHERS;

END D7;

XILINX:
TEST-BENCH (VECTOR DE PRUEBA)
LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY TB IS

END TB;

ARCHITECTURE behavior OF TB IS

COMPONENT PUNTO_E_ECGC

PORT(

A : IN std_logic;
 B : IN std_logic;

C : IN std_logic;

D : IN std_logic;

F1 : OUT std_logic;

F2 : OUT std_logic

);

END COMPONENT;

signal A : std_logic := '0';

signal B : std_logic := '0';

signal C : std_logic := '0';

signal D : std_logic := '0';

signal F1 : std_logic;

signal F2 : std_logic;

BEGIN

uut: PUNTO_E_ECGC PORT MAP (

A => A,

B => B,

C => C,

D => D,

F1 => F1,

F2 => F2

);

PROCESO1: process

begin

wait for 160 ns; A<=NOT A;

end process;

PROCESO2: process

begin

wait for 80 ns; B<=NOT B;

end process;

PROCESO3: process

begin

wait for 40 ns; C<=NOT C;

end process;

PROCESO4: process

begin

wait for 20 ns; D<=NOT D;

 end process;

END;

WINCUPL:
Name PUNTO_E_ECGC ;
PartNo 00 ;
Date 16/9/2017 ;
Revision 01 ;
Designer Engineer ;
Company CRISREX ;
Assembly None ;
Location ;
Device g22v10 ;
/* *************** INPUT PINS *********************/
PIN 2=A ; /* */
PIN 3=B ; /* */
PIN 4=C ; /* */
PIN 5=D ; /* */
/* *************** OUTPUT PINS *********************/
PIN 17=F_1 ; /* */
PIN 18=F_2 ; /* */

FIELD ENTRADA = A,B,C,D;

TABLE ENTRADA => F_1 {
'b'0000=>'b'0;
'b'0001=>'b'1;
'b'0010=>'b'1;
'b'0011=>'b'1;
'b'0100=>'b'1;
'b'0101=>'b'1;
'b'0110=>'b'1;
'b'0111=>'b'0;
'b'1000=>'b'1;
'b'1001=>'b'1;
'b'1010=>'b'1;
'b'1011=>'b'0;
'b'1100=>'b'1;
'b'1101=>'b'0;
'b'1110=>'b'0;
'b'1111=>'b'0;
}
TABLE ENTRADA => F_2 {
'b'0000=>'b'0;
'b'0001=>'b'0;
'b'0010=>'b'0;
'b'0011=>'b'0;
'b'0100=>'b'0;
'b'0101=>'b'0;
'b'0110=>'b'0;
'b'0111=>'b'1;
'b'1000=>'b'0;
'b'1001=>'b'0;
'b'1010=>'b'0;
'b'1011=>'b'1;
'b'1100=>'b'0;
'b'1101=>'b'1;
'b'1110=>'b'1;
'b'1111=>'b'1;
}

F) APLICACION OREX/NOREX

A B C D
13
3

U125:B U125:D
7404 7404
O

U122
4

12

U129
U124 F1

XOR_2
U123
XOR_2
XOR_2

U125:A
1

XOR_2 7404

U126:A
2

1
3
2

U125:C 7408
U126:B U128:A
5 6 4 1 F2
O 7404
6 3
5 U126:C 2
9
7408 8 7432
10
U128:B
U126:D 7408 4
12 6
O
11 5
13 U127:A
1 7432
7408 3
2

7408
QUARTUS II:
LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY PUNTO_F_ECGC IS

PORT(

A,B,C,D : IN STD_LOGIC;

F1,F2 : OUT STD_LOGIC);

END PUNTO_F_ECGC;

ARCHITECTURE D7 OF PUNTO_F_ECGC IS

SIGNAL ABCD : STD_LOGIC_VECTOR (3 DOWNTO 0);

BEGIN

ABCD<=A&B&C&D;

WITH ABCD SELECT

F1<= '1' WHEN "0000",

'1' WHEN "0011",

'1' WHEN "0101",

'1' WHEN "0110",

'1' WHEN "1001",

'1' WHEN "1010",

'1' WHEN "1100",

'1' WHEN "1111",

'0' WHEN OTHERS;

WITH ABCD SELECT

F2<= '1' WHEN "0000",

'1' WHEN "0001",

'1' WHEN "0010",

'1' WHEN "0011",

'1' WHEN "0101",

'1' WHEN "1000",

'1' WHEN "1101",

'0' WHEN OTHERS;

END D7;
XILINX:
TEST-BENCH (VECTOR DE PRUEBA)
LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY TB IS

END TB;

ARCHITECTURE behavior OF TB IS

COMPONENT PUNTO_F_ECGC

PORT(

A : IN std_logic;

B : IN std_logic;

C : IN std_logic;

D : IN std_logic;

F1 : OUT std_logic;

F2 : OUT std_logic

);

END COMPONENT;

signal A : std_logic := '0';

signal B : std_logic := '0';

signal C : std_logic := '0';

signal D : std_logic := '0';

 signal F1 : std_logic;

signal F2 : std_logic;

BEGIN

uut: PUNTO_F_ECGC PORT MAP (

A => A,

B => B,

C => C,

D => D,

F1 => F1,

F2 => F2

);

PROCESO1: process

begin

wait for 160 ns; A<=NOT A;

end process;

PROCESO2: process

begin

wait for 80 ns; B<=NOT B;

end process;

PROCESO3: process

begin

wait for 40 ns; C<=NOT C;

end process;

PROCESO4: process

begin

wait for 20 ns; D<=NOT D;

end process;

END;
WINCUPL:
Name PUNTO_F_ECGC ;
PartNo 00 ;
Date 16/9/2017 ;
Revision 01 ;
Designer Engineer ;
Company CRISREX ;
Assembly None ;
Location ;
Device g22v10 ;
/* *************** INPUT PINS *********************/
PIN 2=A ; /* */
PIN 3=B ; /* */
PIN 4=C ; /* */
PIN 5=D ; /* */
/* *************** OUTPUT PINS *********************/
PIN 17=F_1 ; /* */
PIN 18=F_2 ; /* */

FIELD ENTRADA = A,B,C,D;

TABLE ENTRADA => F_1 {
'b'0000=>'b'1;
'b'0001=>'b'0;
'b'0010=>'b'0;
'b'0011=>'b'1;
'b'0100=>'b'0;
'b'0101=>'b'1;
'b'0110=>'b'1;
'b'0111=>'b'0;
'b'1000=>'b'0;
'b'1001=>'b'1;
'b'1010=>'b'1;
'b'1011=>'b'0;
'b'1100=>'b'1;
'b'1101=>'b'0;
'b'1110=>'b'0;
'b'1111=>'b'1;
}
TABLE ENTRADA => F_2 {
'b'0000=>'b'1;
'b'0001=>'b'1;
'b'0010=>'b'1;
'b'0011=>'b'1;
'b'0100=>'b'0;
'b'0101=>'b'1;
'b'0110=>'b'0;
'b'0111=>'b'0;
'b'1000=>'b'1;
'b'1001=>'b'0;
'b' 1010=>'b'0;
'b' 1011=>'b'0;
'b' 1100=>'b'0;
'b' 1101=>'b'1;
'b' 1110=>'b'0;
'b' 1111=>'b'0;
}
G) APLICACION QUINE McCLUSKEY
OPERADORES NAND:
A B C D
10

12

13
2

U142:A U142:B U142:C U142:D

7400 7400 7400 7400
3

11

1 U143:A
2
6
4
5
7420
9 U143:B
10
8
12 1 U145:A
13 2 F1
7420 6
1 U144:A 4
2 5
6 7420
4
5
7420
9 U144:B
10
8
12
13
7420
U146:A
1
2 12
13

7410
U146:B U148:B
3 3 F2
4 6 4 6
5 5

7410 7410
U147:A
1
3
2

7400
U147:B
4
6
5

7400
U146:C U148:C
9 9 F3
10 8 10 8
11 11

7410 7410
U148:A
1
2 12
13

7410
QUARTUS II:
LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY PUNTO_G_ECGC IS

PORT(

A,B,C,D : IN STD_LOGIC;

F1,F2,F3 : OUT STD_LOGIC);

END PUNTO_G_ECGC;

ARCHITECTURE D7 OF PUNTO_G_ECGC IS

SIGNAL ABCD : STD_LOGIC_VECTOR (3 DOWNTO 0);

BEGIN

ABCD<=A&B&C&D;

WITH ABCD SELECT

F1<= '1' WHEN "0000",

'1' WHEN "0101",

'1' WHEN "1010",

'1' WHEN "1111",

'0' WHEN OTHERS;

WITH ABCD SELECT

F2<= '1' WHEN "0100",

'1' WHEN "1000",

'1' WHEN "1001",

'1' WHEN "1100",

'1' WHEN "1101",

'1' WHEN "1110",

'0' WHEN OTHERS;

WITH ABCD SELECT

F3<= '1' WHEN "0001",

'1' WHEN "0010",

'1' WHEN "0011",

'1' WHEN "0110",

'1' WHEN "0111",

'1' WHEN "1011",

'0' WHEN OTHERS;

END D7;

XILINX:
TEST-BENCH (VECTOR DE PRUEBA)
LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY TB IS

END TB;

ARCHITECTURE behavior OF TB IS

COMPONENT PUNTO_G_ECGC

PORT(

A : IN std_logic;

B : IN std_logic;

C : IN std_logic;

D : IN std_logic;
 F1 : OUT std_logic;

F2 : OUT std_logic;

F3 : OUT std_logic

);

END COMPONENT;

signal A : std_logic := '0';

signal B : std_logic := '0';

signal C : std_logic := '0';

signal D : std_logic := '0';

signal F1 : std_logic;

signal F2 : std_logic;

signal F3 : std_logic;

BEGIN

uut: PUNTO_G_ECGC PORT MAP (

A => A,

B => B,

C => C,

D => D,

F1 => F1,

F2 => F2,

F3 => F3

);

PROCESO1: process

begin

wait for 160 ns; A<=NOT A;

end process;

PROCESO2: process

begin

wait for 80 ns; B<=NOT B;

end process;

PROCESO3: process

begin

wait for 40 ns; C<=NOT C;

end process;

PROCESO4: process

begin

wait for 20 ns; D<=NOT D;

 end process;

END;

WINCUPL:
Name PUNTO_G_ECGC ;
PartNo 00 ;
Date 16/9/2017 ;
Revision 01 ;
Designer Engineer ;
Company CRISREX ;
Assembly None ;
Location ;
Device g22v10 ;
/* *************** INPUT PINS *********************/
PIN 2=A ; /* */
PIN 3=B ; /* */
PIN 4=C ; /* */
PIN 5=D ; /* */
/* *************** OUTPUT PINS *********************/
PIN 16=F_1 ; /* */
PIN 17=F_2 ; /* */
PIN 18=F_3 ; /* */

FIELD ENTRADA = A,B,C,D;

TABLE ENTRADA => F_1 {
'b'0000=>'b'1;
'b'0001=>'b'0;
'b'0010=>'b'0;
'b'0011=>'b'0;
'b'0100=>'b'0;
'b'0101=>'b'1;
'b'0110=>'b'0;
'b'0111=>'b'0;
'b'1000=>'b'0;
'b'1001=>'b'0;
'b'1010=>'b'1;
'b'1011=>'b'0;
'b'1100=>'b'0;
'b'1101=>'b'0;
'b'1110=>'b'0;
'b'1111=>'b'1;
}
TABLE ENTRADA => F_2 {
'b'0000=>'b'0;
'b'0001=>'b'0;
'b'0010=>'b'0;
'b'0011=>'b'0;
'b'0100=>'b'1;
'b'0101=>'b'0;
'b'0110=>'b'0;
'b'0111=>'b'0;
'b'1000=>'b'1;
'b'1001=>'b'1;
'b'1010=>'b'0;
'b'1011=>'b'0;
'b'1100=>'b'1;
 'b'1101=>'b'1;
'b'1110=>'b'1;
'b'1111=>'b'0;
}
TABLE ENTRADA => F_3 {
'b'0000=>'b'0;
'b'0001=>'b'1;
'b'0010=>'b'1;
'b'0011=>'b'1;
'b'0100=>'b'0;
'b'0101=>'b'0;
'b'0110=>'b'1;
'b'0111=>'b'1;
'b'1000=>'b'0;
'b'1001=>'b'0;
'b'1010=>'b'0;
'b'1011=>'b'1;
'b'1100=>'b'0;
'b'1101=>'b'0;
'b'1110=>'b'0;
'b'1111=>'b'0;
}

H) APLICACION VARIABLES BIFORMES

A B C D
OPERADORES NOR:
12

11
9

U138:C U138:D U149:A U149:B

7402 7402 7402 7402
10

13

U150
F1

NOR_4
U151

U149:D U153:A
11 2 F2
NOR_3 13 1
U152 12 3

7402 7402

NOR_3
U154

NOR_3
U155

U157 U153:B
5 F3
NOR_3 4
U156 6

NOR_4 7402

NOR_3
U158

NOR_4
U153:C
8 F4
10
9

7402
QUARTUS II:
LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY PUNTO_H_ECGC IS

PORT(

A,B,C,D : IN STD_LOGIC;

F1,F2,F3,F4 : OUT STD_LOGIC);

END PUNTO_H_ECGC;

ARCHITECTURE D7 OF PUNTO_H_ECGC IS

SIGNAL ABCD : STD_LOGIC_VECTOR (3 DOWNTO 0);

BEGIN

ABCD<=A&B&C&D;

WITH ABCD SELECT

F1<= '1' WHEN "1111",

'0' WHEN OTHERS;

WITH ABCD SELECT

F2<= '1' WHEN "1010",

'1' WHEN "1011",

'1' WHEN "1110",

'0' WHEN OTHERS;

WITH ABCD SELECT

F3<= '1' WHEN "0110",

'1' WHEN "0111",

'1' WHEN "1001",

'1' WHEN "1011",

'1' WHEN "1101",

'1' WHEN "1110",

'0' WHEN OTHERS;

WITH ABCD SELECT

F4<= '1' WHEN "0101",

'1' WHEN "0111",

'1' WHEN "1101",

'1' WHEN "1111",

'0' WHEN OTHERS;

END D7;
XILINX:
TEST-BENCH (VECTOR DE PRUEBA)
LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY TB IS

END TB;

ARCHITECTURE behavior OF TB IS

COMPONENT PUNTO_H_ECGC

PORT(

A : IN std_logic;

B : IN std_logic;

C : IN std_logic;

D : IN std_logic;

F1 : OUT std_logic;

F2 : OUT std_logic;

F3 : OUT std_logic;

F4 : OUT std_logic

);

END COMPONENT;

signal A : std_logic := '0';

signal B : std_logic := '0';

signal C : std_logic := '0';

 signal D : std_logic := '0';

signal F1 : std_logic;

signal F2 : std_logic;

signal F3 : std_logic;

signal F4 : std_logic;

BEGIN

uut: PUNTO_H_ECGC PORT MAP (

A => A,

B => B,

C => C,

D => D,

F1 => F1,

F2 => F2,

F3 => F3,

F4 => F4

);

PROCESO1: process

begin

wait for 160 ns; A<=NOT A;

end process;

PROCESO2: process

begin

wait for 80 ns; B<=NOT B;

end process;

PROCESO3: process

begin

wait for 40 ns; C<=NOT C;

end process;

PROCESO4: process

begin

wait for 20 ns; D<=NOT D;

end process;
END;

WINCUPL:
Name PUNTO_H_ECGC ;
PartNo 00 ;
Date 16/9/2017 ;
Revision 01 ;
Designer Engineer ;
Company CRISREX ;
Assembly None ;
Location ;
Device g22v10 ;
/* *************** INPUT PINS *********************/
PIN 2=A ; /* */
PIN 3=B ; /* */
PIN 4=C ; /* */
PIN 5=D ; /* */
/* *************** OUTPUT PINS *********************/
PIN 16=F_1 ; /* */
PIN 17=F_2 ; /* */
PIN 18=F_3 ; /* */
PIN 19=F_4 ; /* */

FIELD ENTRADA = A,B,C,D;

TABLE ENTRADA => F_1 {
'b'0000=>'b'0;
'b'0001=>'b'0;
'b'0010=>'b'0;
'b'0011=>'b'0;
'b'0100=>'b'0;
'b'0101=>'b'0;
'b'0110=>'b'0;
'b'0111=>'b'0;
'b'1000=>'b'0;
'b'1001=>'b'0;
'b'1010=>'b'0;
'b'1011=>'b'0;
'b'1100=>'b'0;
'b'1101=>'b'0;
'b'1110=>'b'0;
'b'1111=>'b'1;
}
TABLE ENTRADA => F_2 {
'b'0000=>'b'0;
'b'0001=>'b'0;
'b'0010=>'b'0;
'b'0011=>'b'0;
'b'0100=>'b'0;
'b'0101=>'b'0;
'b'0110=>'b'0;
'b'0111=>'b'0;
'b'1000=>'b'0;
'b'1001=>'b'0;
'b'1010=>'b'1;
'b'1011=>'b'1;
'b'1100=>'b'0;
'b'1101=>'b'0;
'b'1110=>'b'1;
'b'1111=>'b'0;
}
TABLE ENTRADA => F_3 {
'b'0000=>'b'0;
'b'0001=>'b'0;
'b'0010=>'b'0;
'b'0011=>'b'0;
'b'0100=>'b'0;
'b'0101=>'b'0;
'b'0110=>'b'1;
'b'0111=>'b'1;
'b'1000=>'b'0;
'b'1001=>'b'1;
'b'1010=>'b'0;
'b'1011=>'b'1;
'b'1100=>'b'0;
'b'1101=>'b'1;
'b'1110=>'b'1;
'b'1111=>'b'0;
}
TABLE ENTRADA => F_4 {
'b'0000=>'b'0;
'b'0001=>'b'0;
'b'0010=>'b'0;
'b'0011=>'b'0;
'b'0100=>'b'0;
'b'0101=>'b'1;
'b'0110=>'b'0;
'b'0111=>'b'1;
'b'1000=>'b'0;
'b'1001=>'b'0;
'b'1010=>'b'0;
'b'1011=>'b'0;
'b'1100=>'b'0;
'b'1101=>'b'1;
'b'1110=>'b'0;
 'b'1111=>'b'1;
}

I) APORTE DEL ALUMNO

A B C D

U67:A
7404
F
2

QUARTUS II:
LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY PUNTO_I_ECGC IS

PORT(

A,B,C,D : IN STD_LOGIC;

F : OUT STD_LOGIC);

END PUNTO_I_ECGC;

ARCHITECTURE D7 OF PUNTO_I_ECGC IS

SIGNAL ABCD : STD_LOGIC_VECTOR (3 DOWNTO 0);

BEGIN
ABCD<=A&B&C&D;

WITH ABCD SELECT

F<= '1' WHEN "0000",

'1' WHEN "0010",

'1' WHEN "0100",

'1' WHEN "0110",

'1' WHEN "1000",

'1' WHEN "1010",

'1' WHEN "1100",

'1' WHEN "1110",

'0' WHEN OTHERS;

END D7;

XILINX:
TEST-BENCH (VECTOR DE PRUEBA)
LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY TB IS

END TB;

ARCHITECTURE behavior OF TB IS

COMPONENT PUNTO_I_ECGC

PORT(

A : IN std_logic;

B : IN std_logic;

C : IN std_logic;

D : IN std_logic;

F : OUT std_logic
 );

END COMPONENT;

signal A : std_logic := '0';

signal B : std_logic := '0';

signal C : std_logic := '0';

signal D : std_logic := '0';

signal F : std_logic;

BEGIN

uut: PUNTO_I_ECGC PORT MAP (

A => A,

B => B,

C => C,

D => D,

F => F

);

PROCESO1: process

begin

wait for 160 ns; A<=NOT A;

end process;

PROCESO2: process

begin

wait for 80 ns; B<=NOT B;

end process;

PROCESO3: process

begin

wait for 40 ns; C<=NOT C;

end process;

PROCESO4: process

begin

wait for 20 ns; D<=NOT D;

end process;

END;
WINCUPL:
Name PUNTO_I_ECGC ;
PartNo 00 ;
Date 16/9/2017 ;
Revision 01 ;
Designer Engineer ;
Company CRISREX ;
Assembly None ;
Location ;
Device g22v10 ;
/* *************** INPUT PINS *********************/
PIN 2=A ; /* */
PIN 3=B ; /* */
PIN 4=C ; /* */
PIN 5=D ; /* */
/* *************** OUTPUT PINS *********************/
PIN 17=F ; /* */

FIELD ENTRADA = A,B,C,D;

TABLE ENTRADA => F {
'b'0000=>'b'1;
'b'0001=>'b'0;
'b'0010=>'b'1;
'b'0011=>'b'0;
'b'0100=>'b'1;
'b'0101=>'b'0;
'b'0110=>'b'1;
'b'0111=>'b'0;
'b'1000=>'b'1;
'b'1001=>'b'0;
'b'1010=>'b'1;
'b'1011=>'b'0;
'b'1100=>'b'1;
'b'1101=>'b'0;
'b'1110=>'b'1;
'b'1111=>'b'0;
}