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mbedNoobNinjambedNoobNinja
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ports/renesas-ra: Add Ehternet support for VK-RA6M5.
Signed-off-by: mbedNoobNinja <novoltage@gmail.com>
1 parent 05cb140 commit 2646120

26 files changed

+1007
-21
lines changed

‎ports/renesas-ra/Makefile

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -24,7 +24,10 @@ include ../../py/mkenv.mk
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include $(BOARD_DIR)/mpconfigboard.mk
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USE_FSP_LPM ?= 1
27+
USE_FSP_OSPI ?= 0
2728
USE_FSP_QSPI ?= 0
29+
USE_FSP_SDHI ?= 0
30+
USE_FSP_ETH ?= 0
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FSP_BOARD_NAME ?= $(shell echo $(BOARD) | tr '[:upper:]' '[:lower:]')
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# Files that are generated and needed before the QSTR build.
@@ -328,6 +331,8 @@ SRC_C += \
328331
machine_rtc.c \
329332
machine_sdcard.c \
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modmachine.c \
334+
network_lan.c \
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eth.c \
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extint.c \
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usrsw.c \
333338
flash.c \
@@ -385,6 +390,11 @@ HAL_SRC_C += $(addprefix $(HAL_DIR)/ra/fsp/src/,\
385390
CFLAGS_FSP = -Wno-unused-variable -Wno-unused-function
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$(BUILD)/lib/fsp/ra/fsp/src/r_sci_uart/r_sci_uart.o: CFLAGS += $(CFLAGS_FSP)
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ifeq ($(USE_FSP_OSPI), 1)
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CFLAGS += -DUSE_FSP_OSPI
395+
HAL_SRC_C += $(HAL_DIR)/ra/fsp/src/r_ospi/r_ospi.c
396+
endif
397+
388398
ifeq ($(USE_FSP_QSPI), 1)
389399
CFLAGS += -DUSE_FSP_QSPI
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HAL_SRC_C += $(HAL_DIR)/ra/fsp/src/r_qspi/r_qspi.c
@@ -396,6 +406,13 @@ HAL_SRC_C += $(HAL_DIR)/ra/fsp/src/r_sdhi/r_sdhi.c \
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$(HAL_DIR)/ra/fsp/src/r_dtc/r_dtc.c
397407
endif
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409+
ifeq ($(USE_FSP_ETH), 1)
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CFLAGS += -DUSE_FSP_ETH
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HAL_SRC_C += $(HAL_DIR)/ra/fsp/src/r_ether_phy/targets/ICS1894/r_ether_phy_target_ics1894.c \
412+
$(HAL_DIR)/ra/fsp/src/r_ether_phy/r_ether_phy.c \
413+
$(HAL_DIR)/ra/fsp/src/r_ether/r_ether.c
414+
endif
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399416
ifeq ($(USE_FSP_LPM), 1)
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CFLAGS += -DUSE_FSP_LPM
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HAL_SRC_C += $(HAL_DIR)/ra/fsp/src/r_lpm/r_lpm.c
@@ -432,7 +449,10 @@ HAL_SRC_C += $(addprefix ra/,\
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ra_gpt.c \
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ra_utils.c \
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)
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endif
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454+
ifeq ($(MICROPY_SSL_MBEDTLS),1)
455+
LIB_SRC_C += mbedtls/mbedtls_port.c
436456
endif
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ifeq ($(MICROPY_HW_ENABLE_RNG),1)

‎ports/renesas-ra/boards/VK_RA6M5/board.json

Lines changed: 8 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2,16 +2,21 @@
22
"deploy": [
33
"../deploy.md"
44
],
5-
"docs": "",
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"docs": "https://vekatech.com/VK-RA6M5_docs/brochures/VK-RA6M5%20Flyer%20R2.pdf",
66
"features": [
7-
"DAC"
7+
"DAC",
8+
"USB",
9+
"microSD",
10+
"Ethernet",
11+
"External RAM",
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"External Flash"
813
],
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"images": [
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"VK-RA6M5.jpg"
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],
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"mcu": "ra6m5",
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"product": "VK-RA6M5",
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"thumbnail": "",
15-
"url": "https://vekatech.com/VK-RA6M5_docs/brochures/VK-RA6M5%20Flyer%20R2.pdf",
20+
"url": "https://vekatech.com",
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"vendor": "Vekatech"
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}

‎ports/renesas-ra/boards/VK_RA6M5/manifest.py

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,3 @@
1+
include("$(PORT_DIR)/boards/manifest.py")
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# Networking
3+
require("bundle-networking")

‎ports/renesas-ra/boards/VK_RA6M5/mpconfigboard.h

Lines changed: 8 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -10,18 +10,24 @@
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#define MICROPY_PY_BUILTINS_COMPLEX (1)
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#define MICROPY_PY_GENERATOR_PEND_THROW (1)
1212
#define MICROPY_PY_MATH (1)
13-
#define MICROPY_PY_UHEAPQ (1)
14-
#define MICROPY_PY_UTIMEQ (1)
13+
#define MICROPY_PY_HEAPQ (1)
1514
#define MICROPY_PY_THREAD (0) // disable ARM_THUMB_FP using vldr due to RA has single float only
15+
#define MICROPY_HW_ETH_MDC (1)
16+
#define MICROPY_PY_NETWORK (1)
17+
#define MICROPY_PY_NETWORK_HOSTNAME_DEFAULT MICROPY_HW_BOARD_NAME
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1719
// peripheral config
20+
#define MICROPY_HW_ENABLE_RNG (1)
1821
#define MICROPY_HW_ENABLE_RTC (1)
1922
#define MICROPY_HW_RTC_SOURCE (1) // 0: subclock
2023
#define MICROPY_HW_ENABLE_ADC (1)
2124
#define MICROPY_HW_HAS_FLASH (1)
25+
#define MICROPY_HW_ENABLE_USBDEV (1)
26+
#define MICROPY_HW_ENABLE_UART_REPL (1)
2227
#define MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE (1)
2328
#define MICROPY_HW_HAS_QSPI_FLASH (1)
2429
#define MICROPY_HW_HAS_SDHI_CARD (1)
30+
#define MICROPY_HW_HAS_OSPI_RAM (1)
2531

2632
// board config
2733

‎ports/renesas-ra/boards/VK_RA6M5/mpconfigboard.mk

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2,11 +2,22 @@ CMSIS_MCU = RA6M5
22
MCU_SERIES = m33
33
LD_FILES = boards/VK_RA6M5/vk_ra6m5.ld
44

5+
CFLAGS += -DCFG_TUH_MAX_SPEED=OPT_MODE_HIGH_SPEED \
6+
-DCFG_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED \
7+
-DCFG_TUSB_RHPORT0_MODE=OPT_MODE_DEVICE \
8+
-DCFG_TUSB_RHPORT1_MODE=0
9+
510
# MicroPython settings
611
MICROPY_VFS_FAT = 1
12+
MICROPY_HW_ENABLE_RNG = 1
13+
MICROPY_PY_LWIP = 1
14+
MICROPY_PY_SSL = 1
15+
MICROPY_SSL_MBEDTLS = 1
716

817
# FSP settings
18+
USE_FSP_OSPI = 1
919
USE_FSP_QSPI = 1
1020
USE_FSP_SDHI = 1
21+
USE_FSP_ETH = 1
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1223
CFLAGS+=-DDEFAULT_DBG_CH=9

‎ports/renesas-ra/boards/VK_RA6M5/ra_cfg/driver/r_ospi_cfg.h

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,5 @@
1+
/* generated configuration header file - do not edit */
2+
#ifndef R_OSPI_CFG_H_
3+
#define R_OSPI_CFG_H_
4+
#ifdef __cplusplus
5+
extern "C" {

‎ports/renesas-ra/boards/VK_RA6M5/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -77,7 +77,7 @@ extern "C" {
7777
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ | \
7878
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | \
7979
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \
80-
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* USBFS */ | \
80+
(((1 > 0) ? 0U : 1U) << 11) /* USBFS */ | \
8181
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \
8282
(((1 > 0) ? 0U : 1U) << 19) /* SPI0 */ | \
8383
(((1 > 0) ? 0U : 1U) << 22) /* SCI9 */ | \

‎ports/renesas-ra/boards/VK_RA6M5/ra_gen/bsp_clock_cfg.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,7 @@
1515
#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */
1616
#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* UCLK Src: PLL2 */
1717
#define BSP_CFG_U60CK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* U60CK Disabled */
18-
#define BSP_CFG_OCTA_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* OCTASPICLK Disabled */
18+
#define BSP_CFG_OCTA_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* OCTASPICLK Src: PLL */
1919
#define BSP_CFG_CANFDCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CANFDCLK Disabled */
2020
#define BSP_CFG_CECCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CECCLK Disabled */
2121
#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */

‎ports/renesas-ra/boards/VK_RA6M5/ra_gen/common_data.c

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Original file line numberDiff line numberDiff line change
@@ -1,5 +1,10 @@
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/* generated common source file - do not edit */
22
#include "common_data.h"
3+
sce_instance_ctrl_t sce_ctrl;
4+
const sce_cfg_t sce_cfg = { .lifecycle = SCE_SSD };
5+
#if SCE_USER_SHA_384_ENABLED
6+
uint32_t SCE_USER_SHA_384_FUNCTION(uint8_t *message, uint8_t *digest, uint32_t message_length);
7+
#endif
38
icu_instance_ctrl_t g_external_irq14_ctrl;
49
const external_irq_cfg_t g_external_irq14_cfg = { .channel = 14, .trigger =
510
EXTERNAL_IRQ_TRIG_RISING, .filter_enable = false, .pclk_div =

‎ports/renesas-ra/boards/VK_RA6M5/ra_gen/common_data.h

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Original file line numberDiff line numberDiff line change
@@ -3,11 +3,14 @@
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#define COMMON_DATA_H_
44
#include <stdint.h>
55
#include "bsp_api.h"
6+
#include "r_sce.h"
67
#include "r_icu.h"
78
#include "r_external_irq_api.h"
89
#include "r_ioport.h"
910
#include "bsp_pin_cfg.h"
1011
FSP_HEADER
12+
extern sce_instance_ctrl_t sce_ctrl;
13+
extern const sce_cfg_t sce_cfg;
1114
/** External IRQ on ICU Instance. */
1215
extern const external_irq_instance_t g_external_irq14;
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