diff --git a/devices/common_patches/g0_add_dma1_7ch.yaml b/devices/common_patches/g0_add_dma1_7ch.yaml
new file mode 100644
index 000000000..9c28c41f2
--- /dev/null
+++ b/devices/common_patches/g0_add_dma1_7ch.yaml
@@ -0,0 +1,935 @@
+_add:
+ DMA1:
+ description: DMA controller
+ groupName: DMA1
+ baseAddress: 0x40020000
+ addressBlock:
+ offset: 0x0
+ size: 0x400
+ usage: registers
+ registers:
+ ISR:
+ displayName: ISR
+ description: low interrupt status register
+ addressOffset: 0x0
+ size: 0x20
+ access: read-only
+ resetValue: 0x00000000
+ fields:
+ GIF1:
+ description: Channel 1 global interrupt flag
+ bitOffset: 0
+ bitWidth: 1
+ access: read-only
+ TCIF1:
+ description: Channel 1 transfer complete flag
+ bitOffset: 1
+ bitWidth: 1
+ access: read-only
+ HTIF1:
+ description: Channel 1 half transfer flag
+ bitOffset: 2
+ bitWidth: 1
+ access: read-only
+ TEIF1:
+ description: Channel 1 transfer error flag
+ bitOffset: 3
+ bitWidth: 1
+ access: read-only
+ GIF2:
+ description: Channel 2 global interrupt flag
+ bitOffset: 4
+ bitWidth: 1
+ access: read-only
+ TCIF2:
+ description: Channel 2 transfer complete flag
+ bitOffset: 5
+ bitWidth: 1
+ access: read-only
+ HTIF2:
+ description: Channel 2 half transfer flag
+ bitOffset: 6
+ bitWidth: 1
+ access: read-only
+ TEIF2:
+ description: Channel 2 transfer error flag
+ bitOffset: 7
+ bitWidth: 1
+ access: read-only
+ GIF3:
+ description: Channel 3 global interrupt flag
+ bitOffset: 8
+ bitWidth: 1
+ access: read-only
+ TCIF3:
+ description: Channel 3 transfer complete flag
+ bitOffset: 9
+ bitWidth: 1
+ access: read-only
+ HTIF3:
+ description: Channel 3 half transfer flag
+ bitOffset: 10
+ bitWidth: 1
+ access: read-only
+ TEIF3:
+ description: Channel 3 transfer error flag
+ bitOffset: 11
+ bitWidth: 1
+ access: read-only
+ GIF4:
+ description: Channel 4 global interrupt flag
+ bitOffset: 12
+ bitWidth: 1
+ access: read-only
+ TCIF4:
+ description: Channel 4 transfer complete flag
+ bitOffset: 13
+ bitWidth: 1
+ access: read-only
+ HTIF4:
+ description: Channel 4 half transfer flag
+ bitOffset: 14
+ bitWidth: 1
+ access: read-only
+ TEIF4:
+ description: Channel 4 transfer error flag
+ bitOffset: 15
+ bitWidth: 1
+ access: read-only
+ GIF5:
+ description: Channel 5 global interrupt flag
+ bitOffset: 16
+ bitWidth: 1
+ access: read-only
+ TCIF5:
+ description: Channel 5 transfer complete flag
+ bitOffset: 17
+ bitWidth: 1
+ access: read-only
+ HTIF5:
+ description: Channel 5 half transfer flag
+ bitOffset: 18
+ bitWidth: 1
+ access: read-only
+ TEIF5:
+ description: Channel 5 transfer error flag
+ bitOffset: 19
+ bitWidth: 1
+ access: read-only
+ GIF6:
+ description: Channel 6 global interrupt flag
+ bitOffset: 20
+ bitWidth: 1
+ access: read-only
+ TCIF6:
+ description: Channel 6 transfer complete flag
+ bitOffset: 21
+ bitWidth: 1
+ access: read-only
+ HTIF6:
+ description: Channel 6 half transfer flag
+ bitOffset: 22
+ bitWidth: 1
+ access: read-only
+ TEIF6:
+ description: Channel 6 transfer error flag
+ bitOffset: 23
+ bitWidth: 1
+ access: read-only
+ GIF7:
+ description: Channel 7 global interrupt flag
+ bitOffset: 24
+ bitWidth: 1
+ access: read-only
+ TCIF7:
+ description: Channel 7 transfer complete flag
+ bitOffset: 25
+ bitWidth: 1
+ access: read-only
+ HTIF7:
+ description: Channel 7 half transfer flag
+ bitOffset: 26
+ bitWidth: 1
+ access: read-only
+ TEIF7:
+ description: Channel 7 transfer error flag
+ bitOffset: 27
+ bitWidth: 1
+ access: read-only
+ IFCR:
+ displayName: IFCR
+ description: high interrupt status register
+ addressOffset: 0x4
+ size: 0x20
+ access: read-only
+ resetValue: 0x00000000
+ fields:
+ CGIF1:
+ description: Clear channel 1 global interrupt flag
+ bitOffset: 0
+ bitWidth: 1
+ CTCIF1:
+ description: Clear channel 1 transfer complete flag
+ bitOffset: 1
+ bitWidth: 1
+ CHTIF1:
+ description: Clear channel 1 half transfer flag
+ bitOffset: 2
+ bitWidth: 1
+ CTEIF1:
+ description: Clear channel 1 transfer error flag
+ bitOffset: 3
+ bitWidth: 1
+ CGIF2:
+ description: Clear channel 2 global interrupt flag
+ bitOffset: 4
+ bitWidth: 1
+ CTCIF2:
+ description: Clear channel 2 transfer complete flag
+ bitOffset: 5
+ bitWidth: 1
+ CHTIF2:
+ description: Clear channel 2 half transfer flag
+ bitOffset: 6
+ bitWidth: 1
+ CTEIF2:
+ description: Clear channel 2 transfer error flag
+ bitOffset: 7
+ bitWidth: 1
+ CGIF3:
+ description: Clear channel 3 global interrupt flag
+ bitOffset: 8
+ bitWidth: 1
+ CTCIF3:
+ description: Clear channel 3 transfer complete flag
+ bitOffset: 9
+ bitWidth: 1
+ CHTIF3:
+ description: Clear channel 3 half transfer flag
+ bitOffset: 10
+ bitWidth: 1
+ CTEIF3:
+ description: Clear channel 3 transfer error flag
+ bitOffset: 11
+ bitWidth: 1
+ CGIF4:
+ description: Clear channel 4 global interrupt flag
+ bitOffset: 12
+ bitWidth: 1
+ CTCIF4:
+ description: Clear channel 4 transfer complete flag
+ bitOffset: 13
+ bitWidth: 1
+ CHTIF4:
+ description: Clear channel 4 half transfer flag
+ bitOffset: 14
+ bitWidth: 1
+ CTEIF15:
+ description: Clear channel 4 transfer error flag
+ bitOffset: 15
+ bitWidth: 1
+ CGIF5:
+ description: Clear channel 5 global interrupt flag
+ bitOffset: 16
+ bitWidth: 1
+ CTCIF5:
+ description: Clear channel 5 transfer complete flag
+ bitOffset: 17
+ bitWidth: 1
+ CHTIF5:
+ description: Clear channel 5 half transfer flag
+ bitOffset: 18
+ bitWidth: 1
+ CTEIF5:
+ description: Clear channel 5 transfer error flag
+ bitOffset: 19
+ bitWidth: 1
+ CGIF6:
+ description: Clear channel 6 global interrupt flag
+ bitOffset: 20
+ bitWidth: 1
+ CTCIF6:
+ description: Clear channel 6 transfer complete flag
+ bitOffset: 21
+ bitWidth: 1
+ CHTIF6:
+ description: Clear channel 6 half transfer flag
+ bitOffset: 22
+ bitWidth: 1
+ CTEIF6:
+ description: Clear channel 6 transfer error flag
+ bitOffset: 23
+ bitWidth: 1
+ CGIF7:
+ description: Clear channel 7 global interrupt flag
+ bitOffset: 24
+ bitWidth: 1
+ CTCIF7:
+ description: Clear channel 7 transfer complete flag
+ bitOffset: 25
+ bitWidth: 1
+ CHTIF7:
+ description: Clear channel 7 half transfer flag
+ bitOffset: 26
+ bitWidth: 1
+ CTEIF7:
+ description: Clear channel 7 transfer error flag
+ bitOffset: 27
+ bitWidth: 1
+ CCR1:
+ displayName: CCR1
+ description: DMA channel 1 configuration register
+ addressOffset: 0x8
+ size: 0x20
+ access: read-write
+ resetValue: 0x00000000
+ fields:
+ EN:
+ description: Channel enable
+ bitOffset: 0
+ bitWidth: 1
+ TCIE:
+ description: Transfer complete interrupt enable
+ bitOffset: 1
+ bitWidth: 1
+ HTIE:
+ description: Half transfer interrupt enable
+ bitOffset: 2
+ bitWidth: 1
+ TEIE:
+ description: Transfer error interrupt enable
+ bitOffset: 3
+ bitWidth: 1
+ DIR:
+ description: Data transfer direction
+ bitOffset: 4
+ bitWidth: 1
+ CIRC:
+ description: Circular mode
+ bitOffset: 5
+ bitWidth: 1
+ PINC:
+ description: Peripherarl increment mode
+ bitOffset: 6
+ bitWidth: 1
+ MINC:
+ description: Memory increment mode
+ bitOffset: 7
+ bitWidth: 1
+ PSIZE:
+ description: Peripheral size
+ bitOffset: 8
+ bitWidth: 2
+ MSIZE:
+ description: Memory size
+ bitOffset: 10
+ bitWidth: 2
+ PL:
+ description: Channel priority level
+ bitOffset: 12
+ bitWidth: 2
+ MEM2MEM:
+ description: Memory to memory mode
+ bitOffset: 14
+ bitWidth: 1
+ CCR2:
+ displayName: CCR2
+ description: DMA channel 1 configuration register
+ addressOffset: 0x1C
+ size: 0x20
+ access: read-write
+ resetValue: 0x00000000
+ fields:
+ EN:
+ description: Channel enable
+ bitOffset: 0
+ bitWidth: 1
+ TCIE:
+ description: Transfer complete interrupt enable
+ bitOffset: 1
+ bitWidth: 1
+ HTIE:
+ description: Half transfer interrupt enable
+ bitOffset: 2
+ bitWidth: 1
+ TEIE:
+ description: Transfer error interrupt enable
+ bitOffset: 3
+ bitWidth: 1
+ DIR:
+ description: Data transfer direction
+ bitOffset: 4
+ bitWidth: 1
+ CIRC:
+ description: Circular mode
+ bitOffset: 5
+ bitWidth: 1
+ PINC:
+ description: Peripherarl increment mode
+ bitOffset: 6
+ bitWidth: 1
+ MINC:
+ description: Memory increment mode
+ bitOffset: 7
+ bitWidth: 1
+ PSIZE:
+ description: Peripheral size
+ bitOffset: 8
+ bitWidth: 2
+ MSIZE:
+ description: Memory size
+ bitOffset: 10
+ bitWidth: 2
+ PL:
+ description: Channel priority level
+ bitOffset: 12
+ bitWidth: 2
+ MEM2MEM:
+ description: Memory to memory mode
+ bitOffset: 14
+ bitWidth: 1
+ CCR3:
+ displayName: CCR3
+ description: DMA channel 1 configuration register
+ addressOffset: 0x30
+ size: 0x20
+ access: read-write
+ resetValue: 0x00000000
+ fields:
+ EN:
+ description: Channel enable
+ bitOffset: 0
+ bitWidth: 1
+ TCIE:
+ description: Transfer complete interrupt enable
+ bitOffset: 1
+ bitWidth: 1
+ HTIE:
+ description: Half transfer interrupt enable
+ bitOffset: 2
+ bitWidth: 1
+ TEIE:
+ description: Transfer error interrupt enable
+ bitOffset: 3
+ bitWidth: 1
+ DIR:
+ description: Data transfer direction
+ bitOffset: 4
+ bitWidth: 1
+ CIRC:
+ description: Circular mode
+ bitOffset: 5
+ bitWidth: 1
+ PINC:
+ description: Peripherarl increment mode
+ bitOffset: 6
+ bitWidth: 1
+ MINC:
+ description: Memory increment mode
+ bitOffset: 7
+ bitWidth: 1
+ PSIZE:
+ description: Peripheral size
+ bitOffset: 8
+ bitWidth: 2
+ MSIZE:
+ description: Memory size
+ bitOffset: 10
+ bitWidth: 2
+ PL:
+ description: Channel priority level
+ bitOffset: 12
+ bitWidth: 2
+ MEM2MEM:
+ description: Memory to memory mode
+ bitOffset: 14
+ bitWidth: 1
+ CCR4:
+ displayName: CCR4
+ description: DMA channel 1 configuration register
+ addressOffset: 0x44
+ size: 0x20
+ access: read-write
+ resetValue: 0x00000000
+ fields:
+ EN:
+ description: Channel enable
+ bitOffset: 0
+ bitWidth: 1
+ TCIE:
+ description: Transfer complete interrupt enable
+ bitOffset: 1
+ bitWidth: 1
+ HTIE:
+ description: Half transfer interrupt enable
+ bitOffset: 2
+ bitWidth: 1
+ TEIE:
+ description: Transfer error interrupt enable
+ bitOffset: 3
+ bitWidth: 1
+ DIR:
+ description: Data transfer direction
+ bitOffset: 4
+ bitWidth: 1
+ CIRC:
+ description: Circular mode
+ bitOffset: 5
+ bitWidth: 1
+ PINC:
+ description: Peripherarl increment mode
+ bitOffset: 6
+ bitWidth: 1
+ MINC:
+ description: Memory increment mode
+ bitOffset: 7
+ bitWidth: 1
+ PSIZE:
+ description: Peripheral size
+ bitOffset: 8
+ bitWidth: 2
+ MSIZE:
+ description: Memory size
+ bitOffset: 10
+ bitWidth: 2
+ PL:
+ description: Channel priority level
+ bitOffset: 12
+ bitWidth: 2
+ MEM2MEM:
+ description: Memory to memory mode
+ bitOffset: 14
+ bitWidth: 1
+ CCR5:
+ displayName: CCR5
+ description: DMA channel 1 configuration register
+ addressOffset: 0x58
+ size: 0x20
+ access: read-write
+ resetValue: 0x00000000
+ fields:
+ EN:
+ description: Channel enable
+ bitOffset: 0
+ bitWidth: 1
+ TCIE:
+ description: Transfer complete interrupt enable
+ bitOffset: 1
+ bitWidth: 1
+ HTIE:
+ description: Half transfer interrupt enable
+ bitOffset: 2
+ bitWidth: 1
+ TEIE:
+ description: Transfer error interrupt enable
+ bitOffset: 3
+ bitWidth: 1
+ DIR:
+ description: Data transfer direction
+ bitOffset: 4
+ bitWidth: 1
+ CIRC:
+ description: Circular mode
+ bitOffset: 5
+ bitWidth: 1
+ PINC:
+ description: Peripherarl increment mode
+ bitOffset: 6
+ bitWidth: 1
+ MINC:
+ description: Memory increment mode
+ bitOffset: 7
+ bitWidth: 1
+ PSIZE:
+ description: Peripheral size
+ bitOffset: 8
+ bitWidth: 2
+ MSIZE:
+ description: Memory size
+ bitOffset: 10
+ bitWidth: 2
+ PL:
+ description: Channel priority level
+ bitOffset: 12
+ bitWidth: 2
+ MEM2MEM:
+ description: Memory to memory mode
+ bitOffset: 14
+ bitWidth: 1
+ CCR6:
+ displayName: CCR6
+ description: DMA channel 1 configuration register
+ addressOffset: 0x6C
+ size: 0x20
+ access: read-write
+ resetValue: 0x00000000
+ fields:
+ EN:
+ description: Channel enable
+ bitOffset: 0
+ bitWidth: 1
+ TCIE:
+ description: Transfer complete interrupt enable
+ bitOffset: 1
+ bitWidth: 1
+ HTIE:
+ description: Half transfer interrupt enable
+ bitOffset: 2
+ bitWidth: 1
+ TEIE:
+ description: Transfer error interrupt enable
+ bitOffset: 3
+ bitWidth: 1
+ DIR:
+ description: Data transfer direction
+ bitOffset: 4
+ bitWidth: 1
+ CIRC:
+ description: Circular mode
+ bitOffset: 5
+ bitWidth: 1
+ PINC:
+ description: Peripherarl increment mode
+ bitOffset: 6
+ bitWidth: 1
+ MINC:
+ description: Memory increment mode
+ bitOffset: 7
+ bitWidth: 1
+ PSIZE:
+ description: Peripheral size
+ bitOffset: 8
+ bitWidth: 2
+ MSIZE:
+ description: Memory size
+ bitOffset: 10
+ bitWidth: 2
+ PL:
+ description: Channel priority level
+ bitOffset: 12
+ bitWidth: 2
+ MEM2MEM:
+ description: Memory to memory mode
+ bitOffset: 14
+ bitWidth: 1
+ CCR7:
+ displayName: CCR7
+ description: DMA channel 1 configuration register
+ addressOffset: 0x80
+ size: 0x20
+ access: read-write
+ resetValue: 0x00000000
+ fields:
+ EN:
+ description: Channel enable
+ bitOffset: 0
+ bitWidth: 1
+ TCIE:
+ description: Transfer complete interrupt enable
+ bitOffset: 1
+ bitWidth: 1
+ HTIE:
+ description: Half transfer interrupt enable
+ bitOffset: 2
+ bitWidth: 1
+ TEIE:
+ description: Transfer error interrupt enable
+ bitOffset: 3
+ bitWidth: 1
+ DIR:
+ description: Data transfer direction
+ bitOffset: 4
+ bitWidth: 1
+ CIRC:
+ description: Circular mode
+ bitOffset: 5
+ bitWidth: 1
+ PINC:
+ description: Peripherarl increment mode
+ bitOffset: 6
+ bitWidth: 1
+ MINC:
+ description: Memory increment mode
+ bitOffset: 7
+ bitWidth: 1
+ PSIZE:
+ description: Peripheral size
+ bitOffset: 8
+ bitWidth: 2
+ MSIZE:
+ description: Memory size
+ bitOffset: 10
+ bitWidth: 2
+ PL:
+ description: Channel priority level
+ bitOffset: 12
+ bitWidth: 2
+ MEM2MEM:
+ description: Memory to memory mode
+ bitOffset: 14
+ bitWidth: 1
+ CNDTR1:
+ displayName: CNDTR1
+ description: DMA channel 1 number of data tegister
+ addressOffset: 0xC
+ size: 0x20
+ access: read-write
+ resetValue: 0x00000000
+ fields:
+ NDT:
+ description: Number of data to transfer
+ bitOffset: 0
+ bitWidth: 16
+ CNDTR2:
+ displayName: CNDTR2
+ description: DMA channel 2 number of data tegister
+ addressOffset: 0x20
+ size: 0x20
+ access: read-write
+ resetValue: 0x00000000
+ fields:
+ NDT:
+ description: Number of data to transfer
+ bitOffset: 0
+ bitWidth: 16
+ CNDTR3:
+ displayName: CNDTR3
+ description: DMA channel 3 number of data tegister
+ addressOffset: 0x34
+ size: 0x20
+ access: read-write
+ resetValue: 0x00000000
+ fields:
+ NDT:
+ description: Number of data to transfer
+ bitOffset: 0
+ bitWidth: 16
+ CNDTR4:
+ displayName: CNDTR4
+ description: DMA channel 4 number of data tegister
+ addressOffset: 0x48
+ size: 0x20
+ access: read-write
+ resetValue: 0x00000000
+ fields:
+ NDT:
+ description: Number of data to transfer
+ bitOffset: 0
+ bitWidth: 16
+ CNDTR5:
+ displayName: CNDTR5
+ description: DMA channel 5 number of data tegister
+ addressOffset: 0x5C
+ size: 0x20
+ access: read-write
+ resetValue: 0x00000000
+ fields:
+ NDT:
+ description: Number of data to transfer
+ bitOffset: 0
+ bitWidth: 16
+ CNDTR6:
+ displayName: CNDTR6
+ description: DMA channel 6 number of data tegister
+ addressOffset: 0x70
+ size: 0x20
+ access: read-write
+ resetValue: 0x00000000
+ fields:
+ NDT:
+ description: Number of data to transfer
+ bitOffset: 0
+ bitWidth: 16
+ CNDTR7:
+ displayName: CNDTR7
+ description: DMA channel 7 number of data tegister
+ addressOffset: 0x84
+ size: 0x20
+ access: read-write
+ resetValue: 0x00000000
+ fields:
+ NDT:
+ description: Number of data to transfer
+ bitOffset: 0
+ bitWidth: 16
+ CPAR1:
+ displayName: CPAR1
+ description: DMA channel 1 peripheral address
+ addressOffset: 0x10
+ size: 0x20
+ access: read-write
+ resetValue: 0x00000000
+ fields:
+ PA:
+ description: Peripheral address
+ bitOffset: 0
+ bitWidth: 32
+ CPAR2:
+ displayName: CPAR2
+ description: DMA channel 2 peripheral address
+ addressOffset: 0x24
+ size: 0x20
+ access: read-write
+ resetValue: 0x00000000
+ fields:
+ PA:
+ description: Peripheral address
+ bitOffset: 0
+ bitWidth: 32
+ CPAR3:
+ displayName: CPAR3
+ description: DMA channel 3 peripheral address
+ addressOffset: 0x38
+ size: 0x20
+ access: read-write
+ resetValue: 0x00000000
+ fields:
+ PA:
+ description: Peripheral address
+ bitOffset: 0
+ bitWidth: 32
+ CPAR4:
+ displayName: CPAR4
+ description: DMA channel 4 peripheral address
+ addressOffset: 0x4C
+ size: 0x20
+ access: read-write
+ resetValue: 0x00000000
+ fields:
+ PA:
+ description: Peripheral address
+ bitOffset: 0
+ bitWidth: 32
+ CPAR5:
+ displayName: CPAR5
+ description: DMA channel 5 peripheral address
+ addressOffset: 0x60
+ size: 0x20
+ access: read-write
+ resetValue: 0x00000000
+ fields:
+ PA:
+ description: Peripheral address
+ bitOffset: 0
+ bitWidth: 32
+ CPAR6:
+ displayName: CPAR6
+ description: DMA channel 6 peripheral address
+ addressOffset: 0x74
+ size: 0x20
+ access: read-write
+ resetValue: 0x00000000
+ fields:
+ PA:
+ description: Peripheral address
+ bitOffset: 0
+ bitWidth: 32
+ CPAR7:
+ displayName: CPAR7
+ description: DMA channel 7 peripheral address
+ addressOffset: 0x88
+ size: 0x20
+ access: read-write
+ resetValue: 0x00000000
+ fields:
+ PA:
+ description: Peripheral address
+ bitOffset: 0
+ bitWidth: 32
+ CMAR1:
+ displayName: CMAR1
+ description: DMA channel 1 memory address
+ addressOffset: 0x14
+ size: 0x20
+ access: read-write
+ resetValue: 0x00000000
+ fields:
+ MA:
+ description: Memory address
+ bitOffset: 0
+ bitWidth: 32
+ CMAR2:
+ displayName: CMAR2
+ description: DMA channel 2 memory address
+ addressOffset: 0x28
+ size: 0x20
+ access: read-write
+ resetValue: 0x00000000
+ fields:
+ MA:
+ description: Memory address
+ bitOffset: 0
+ bitWidth: 32
+ CMAR3:
+ displayName: CMAR3
+ description: DMA channel 3 memory address
+ addressOffset: 0x3C
+ size: 0x20
+ access: read-write
+ resetValue: 0x00000000
+ fields:
+ MA:
+ description: Memory address
+ bitOffset: 0
+ bitWidth: 32
+ CMAR4:
+ displayName: CMAR4
+ description: DMA channel 4 memory address
+ addressOffset: 0x50
+ size: 0x20
+ access: read-write
+ resetValue: 0x00000000
+ fields:
+ MA:
+ description: Memory address
+ bitOffset: 0
+ bitWidth: 32
+ CMAR5:
+ displayName: CMAR5
+ description: DMA channel 5 memory address
+ addressOffset: 0x64
+ size: 0x20
+ access: read-write
+ resetValue: 0x00000000
+ fields:
+ MA:
+ description: Memory address
+ bitOffset: 0
+ bitWidth: 32
+ CMAR6:
+ displayName: CMAR6
+ description: DMA channel 6 memory address
+ addressOffset: 0x78
+ size: 0x20
+ access: read-write
+ resetValue: 0x00000000
+ fields:
+ MA:
+ description: Memory address
+ bitOffset: 0
+ bitWidth: 32
+ CMAR7:
+ displayName: CMAR7
+ description: DMA channel 7 memory address
+ addressOffset: 0x8C
+ size: 0x20
+ access: read-write
+ resetValue: 0x00000000
+ fields:
+ MA:
+ description: Memory address
+ bitOffset: 0
+ bitWidth: 32
+
+DMA1:
+ _cluster:
+ "CH%s":
+ description: "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"
+ "CCR?":
+ name: CR
+ "CNDTR?":
+ name: NDTR
+ "CPAR?":
+ name: PAR
+ "CMAR?":
+ name: MAR
diff --git a/devices/common_patches/g0_add_dma2_5ch.yaml b/devices/common_patches/g0_add_dma2_5ch.yaml
new file mode 100644
index 000000000..017d0537b
--- /dev/null
+++ b/devices/common_patches/g0_add_dma2_5ch.yaml
@@ -0,0 +1,678 @@
+_add:
+ DMA2:
+ description: DMA controller
+ groupName: DMA2
+ baseAddress: 0x40020400
+ addressBlock:
+ offset: 0x0
+ size: 0x400
+ usage: registers
+ registers:
+ ISR:
+ displayName: ISR
+ description: low interrupt status register
+ addressOffset: 0x0
+ size: 0x20
+ access: read-only
+ resetValue: 0x00000000
+ fields:
+ GIF1:
+ description: Channel 1 global interrupt flag
+ bitOffset: 0
+ bitWidth: 1
+ access: read-only
+ TCIF1:
+ description: Channel 1 transfer complete flag
+ bitOffset: 1
+ bitWidth: 1
+ access: read-only
+ HTIF1:
+ description: Channel 1 half transfer flag
+ bitOffset: 2
+ bitWidth: 1
+ access: read-only
+ TEIF1:
+ description: Channel 1 transfer error flag
+ bitOffset: 3
+ bitWidth: 1
+ access: read-only
+ GIF2:
+ description: Channel 2 global interrupt flag
+ bitOffset: 4
+ bitWidth: 1
+ access: read-only
+ TCIF2:
+ description: Channel 2 transfer complete flag
+ bitOffset: 5
+ bitWidth: 1
+ access: read-only
+ HTIF2:
+ description: Channel 2 half transfer flag
+ bitOffset: 6
+ bitWidth: 1
+ access: read-only
+ TEIF2:
+ description: Channel 2 transfer error flag
+ bitOffset: 7
+ bitWidth: 1
+ access: read-only
+ GIF3:
+ description: Channel 3 global interrupt flag
+ bitOffset: 8
+ bitWidth: 1
+ access: read-only
+ TCIF3:
+ description: Channel 3 transfer complete flag
+ bitOffset: 9
+ bitWidth: 1
+ access: read-only
+ HTIF3:
+ description: Channel 3 half transfer flag
+ bitOffset: 10
+ bitWidth: 1
+ access: read-only
+ TEIF3:
+ description: Channel 3 transfer error flag
+ bitOffset: 11
+ bitWidth: 1
+ access: read-only
+ GIF4:
+ description: Channel 4 global interrupt flag
+ bitOffset: 12
+ bitWidth: 1
+ access: read-only
+ TCIF4:
+ description: Channel 4 transfer complete flag
+ bitOffset: 13
+ bitWidth: 1
+ access: read-only
+ HTIF4:
+ description: Channel 4 half transfer flag
+ bitOffset: 14
+ bitWidth: 1
+ access: read-only
+ TEIF4:
+ description: Channel 4 transfer error flag
+ bitOffset: 15
+ bitWidth: 1
+ access: read-only
+ GIF5:
+ description: Channel 5 global interrupt flag
+ bitOffset: 16
+ bitWidth: 1
+ access: read-only
+ TCIF5:
+ description: Channel 5 transfer complete flag
+ bitOffset: 17
+ bitWidth: 1
+ access: read-only
+ HTIF5:
+ description: Channel 5 half transfer flag
+ bitOffset: 18
+ bitWidth: 1
+ access: read-only
+ TEIF5:
+ description: Channel 5 transfer error flag
+ bitOffset: 19
+ bitWidth: 1
+ access: read-only
+ IFCR:
+ displayName: IFCR
+ description: high interrupt status register
+ addressOffset: 0x4
+ size: 0x20
+ access: read-only
+ resetValue: 0x00000000
+ fields:
+ CGIF1:
+ description: Clear channel 1 global interrupt flag
+ bitOffset: 0
+ bitWidth: 1
+ CTCIF1:
+ description: Clear channel 1 transfer complete flag
+ bitOffset: 1
+ bitWidth: 1
+ CHTIF1:
+ description: Clear channel 1 half transfer flag
+ bitOffset: 2
+ bitWidth: 1
+ CTEIF1:
+ description: Clear channel 1 transfer error flag
+ bitOffset: 3
+ bitWidth: 1
+ CGIF2:
+ description: Clear channel 2 global interrupt flag
+ bitOffset: 4
+ bitWidth: 1
+ CTCIF2:
+ description: Clear channel 2 transfer complete flag
+ bitOffset: 5
+ bitWidth: 1
+ CHTIF2:
+ description: Clear channel 2 half transfer flag
+ bitOffset: 6
+ bitWidth: 1
+ CTEIF2:
+ description: Clear channel 2 transfer error flag
+ bitOffset: 7
+ bitWidth: 1
+ CGIF3:
+ description: Clear channel 3 global interrupt flag
+ bitOffset: 8
+ bitWidth: 1
+ CTCIF3:
+ description: Clear channel 3 transfer complete flag
+ bitOffset: 9
+ bitWidth: 1
+ CHTIF3:
+ description: Clear channel 3 half transfer flag
+ bitOffset: 10
+ bitWidth: 1
+ CTEIF3:
+ description: Clear channel 3 transfer error flag
+ bitOffset: 11
+ bitWidth: 1
+ CGIF4:
+ description: Clear channel 4 global interrupt flag
+ bitOffset: 12
+ bitWidth: 1
+ CTCIF4:
+ description: Clear channel 4 transfer complete flag
+ bitOffset: 13
+ bitWidth: 1
+ CHTIF4:
+ description: Clear channel 4 half transfer flag
+ bitOffset: 14
+ bitWidth: 1
+ CTEIF15:
+ description: Clear channel 4 transfer error flag
+ bitOffset: 15
+ bitWidth: 1
+ CGIF5:
+ description: Clear channel 5 global interrupt flag
+ bitOffset: 16
+ bitWidth: 1
+ CTCIF5:
+ description: Clear channel 5 transfer complete flag
+ bitOffset: 17
+ bitWidth: 1
+ CHTIF5:
+ description: Clear channel 5 half transfer flag
+ bitOffset: 18
+ bitWidth: 1
+ CTEIF5:
+ description: Clear channel 5 transfer error flag
+ bitOffset: 19
+ bitWidth: 1
+ CCR1:
+ displayName: CCR1
+ description: DMA channel 1 configuration register
+ addressOffset: 0x8
+ size: 0x20
+ access: read-write
+ resetValue: 0x00000000
+ fields:
+ EN:
+ description: Channel enable
+ bitOffset: 0
+ bitWidth: 1
+ TCIE:
+ description: Transfer complete interrupt enable
+ bitOffset: 1
+ bitWidth: 1
+ HTIE:
+ description: Half transfer interrupt enable
+ bitOffset: 2
+ bitWidth: 1
+ TEIE:
+ description: Transfer error interrupt enable
+ bitOffset: 3
+ bitWidth: 1
+ DIR:
+ description: Data transfer direction
+ bitOffset: 4
+ bitWidth: 1
+ CIRC:
+ description: Circular mode
+ bitOffset: 5
+ bitWidth: 1
+ PINC:
+ description: Peripherarl increment mode
+ bitOffset: 6
+ bitWidth: 1
+ MINC:
+ description: Memory increment mode
+ bitOffset: 7
+ bitWidth: 1
+ PSIZE:
+ description: Peripheral size
+ bitOffset: 8
+ bitWidth: 2
+ MSIZE:
+ description: Memory size
+ bitOffset: 10
+ bitWidth: 2
+ PL:
+ description: Channel priority level
+ bitOffset: 12
+ bitWidth: 2
+ MEM2MEM:
+ description: Memory to memory mode
+ bitOffset: 14
+ bitWidth: 1
+ CCR2:
+ displayName: CCR2
+ description: DMA channel 1 configuration register
+ addressOffset: 0x1C
+ size: 0x20
+ access: read-write
+ resetValue: 0x00000000
+ fields:
+ EN:
+ description: Channel enable
+ bitOffset: 0
+ bitWidth: 1
+ TCIE:
+ description: Transfer complete interrupt enable
+ bitOffset: 1
+ bitWidth: 1
+ HTIE:
+ description: Half transfer interrupt enable
+ bitOffset: 2
+ bitWidth: 1
+ TEIE:
+ description: Transfer error interrupt enable
+ bitOffset: 3
+ bitWidth: 1
+ DIR:
+ description: Data transfer direction
+ bitOffset: 4
+ bitWidth: 1
+ CIRC:
+ description: Circular mode
+ bitOffset: 5
+ bitWidth: 1
+ PINC:
+ description: Peripherarl increment mode
+ bitOffset: 6
+ bitWidth: 1
+ MINC:
+ description: Memory increment mode
+ bitOffset: 7
+ bitWidth: 1
+ PSIZE:
+ description: Peripheral size
+ bitOffset: 8
+ bitWidth: 2
+ MSIZE:
+ description: Memory size
+ bitOffset: 10
+ bitWidth: 2
+ PL:
+ description: Channel priority level
+ bitOffset: 12
+ bitWidth: 2
+ MEM2MEM:
+ description: Memory to memory mode
+ bitOffset: 14
+ bitWidth: 1
+ CCR3:
+ displayName: CCR3
+ description: DMA channel 1 configuration register
+ addressOffset: 0x30
+ size: 0x20
+ access: read-write
+ resetValue: 0x00000000
+ fields:
+ EN:
+ description: Channel enable
+ bitOffset: 0
+ bitWidth: 1
+ TCIE:
+ description: Transfer complete interrupt enable
+ bitOffset: 1
+ bitWidth: 1
+ HTIE:
+ description: Half transfer interrupt enable
+ bitOffset: 2
+ bitWidth: 1
+ TEIE:
+ description: Transfer error interrupt enable
+ bitOffset: 3
+ bitWidth: 1
+ DIR:
+ description: Data transfer direction
+ bitOffset: 4
+ bitWidth: 1
+ CIRC:
+ description: Circular mode
+ bitOffset: 5
+ bitWidth: 1
+ PINC:
+ description: Peripherarl increment mode
+ bitOffset: 6
+ bitWidth: 1
+ MINC:
+ description: Memory increment mode
+ bitOffset: 7
+ bitWidth: 1
+ PSIZE:
+ description: Peripheral size
+ bitOffset: 8
+ bitWidth: 2
+ MSIZE:
+ description: Memory size
+ bitOffset: 10
+ bitWidth: 2
+ PL:
+ description: Channel priority level
+ bitOffset: 12
+ bitWidth: 2
+ MEM2MEM:
+ description: Memory to memory mode
+ bitOffset: 14
+ bitWidth: 1
+ CCR4:
+ displayName: CCR4
+ description: DMA channel 1 configuration register
+ addressOffset: 0x44
+ size: 0x20
+ access: read-write
+ resetValue: 0x00000000
+ fields:
+ EN:
+ description: Channel enable
+ bitOffset: 0
+ bitWidth: 1
+ TCIE:
+ description: Transfer complete interrupt enable
+ bitOffset: 1
+ bitWidth: 1
+ HTIE:
+ description: Half transfer interrupt enable
+ bitOffset: 2
+ bitWidth: 1
+ TEIE:
+ description: Transfer error interrupt enable
+ bitOffset: 3
+ bitWidth: 1
+ DIR:
+ description: Data transfer direction
+ bitOffset: 4
+ bitWidth: 1
+ CIRC:
+ description: Circular mode
+ bitOffset: 5
+ bitWidth: 1
+ PINC:
+ description: Peripherarl increment mode
+ bitOffset: 6
+ bitWidth: 1
+ MINC:
+ description: Memory increment mode
+ bitOffset: 7
+ bitWidth: 1
+ PSIZE:
+ description: Peripheral size
+ bitOffset: 8
+ bitWidth: 2
+ MSIZE:
+ description: Memory size
+ bitOffset: 10
+ bitWidth: 2
+ PL:
+ description: Channel priority level
+ bitOffset: 12
+ bitWidth: 2
+ MEM2MEM:
+ description: Memory to memory mode
+ bitOffset: 14
+ bitWidth: 1
+ CCR5:
+ displayName: CCR5
+ description: DMA channel 1 configuration register
+ addressOffset: 0x58
+ size: 0x20
+ access: read-write
+ resetValue: 0x00000000
+ fields:
+ EN:
+ description: Channel enable
+ bitOffset: 0
+ bitWidth: 1
+ TCIE:
+ description: Transfer complete interrupt enable
+ bitOffset: 1
+ bitWidth: 1
+ HTIE:
+ description: Half transfer interrupt enable
+ bitOffset: 2
+ bitWidth: 1
+ TEIE:
+ description: Transfer error interrupt enable
+ bitOffset: 3
+ bitWidth: 1
+ DIR:
+ description: Data transfer direction
+ bitOffset: 4
+ bitWidth: 1
+ CIRC:
+ description: Circular mode
+ bitOffset: 5
+ bitWidth: 1
+ PINC:
+ description: Peripherarl increment mode
+ bitOffset: 6
+ bitWidth: 1
+ MINC:
+ description: Memory increment mode
+ bitOffset: 7
+ bitWidth: 1
+ PSIZE:
+ description: Peripheral size
+ bitOffset: 8
+ bitWidth: 2
+ MSIZE:
+ description: Memory size
+ bitOffset: 10
+ bitWidth: 2
+ PL:
+ description: Channel priority level
+ bitOffset: 12
+ bitWidth: 2
+ MEM2MEM:
+ description: Memory to memory mode
+ bitOffset: 14
+ bitWidth: 1
+ CNDTR1:
+ displayName: CNDTR1
+ description: DMA channel 1 number of data tegister
+ addressOffset: 0xC
+ size: 0x20
+ access: read-write
+ resetValue: 0x00000000
+ fields:
+ NDT:
+ description: Number of data to transfer
+ bitOffset: 0
+ bitWidth: 16
+ CNDTR2:
+ displayName: CNDTR2
+ description: DMA channel 2 number of data tegister
+ addressOffset: 0x20
+ size: 0x20
+ access: read-write
+ resetValue: 0x00000000
+ fields:
+ NDT:
+ description: Number of data to transfer
+ bitOffset: 0
+ bitWidth: 16
+ CNDTR3:
+ displayName: CNDTR3
+ description: DMA channel 3 number of data tegister
+ addressOffset: 0x34
+ size: 0x20
+ access: read-write
+ resetValue: 0x00000000
+ fields:
+ NDT:
+ description: Number of data to transfer
+ bitOffset: 0
+ bitWidth: 16
+ CNDTR4:
+ displayName: CNDTR4
+ description: DMA channel 4 number of data tegister
+ addressOffset: 0x48
+ size: 0x20
+ access: read-write
+ resetValue: 0x00000000
+ fields:
+ NDT:
+ description: Number of data to transfer
+ bitOffset: 0
+ bitWidth: 16
+ CNDTR5:
+ displayName: CNDTR5
+ description: DMA channel 5 number of data tegister
+ addressOffset: 0x5C
+ size: 0x20
+ access: read-write
+ resetValue: 0x00000000
+ fields:
+ NDT:
+ description: Number of data to transfer
+ bitOffset: 0
+ bitWidth: 16
+ CPAR1:
+ displayName: CPAR1
+ description: DMA channel 1 peripheral address
+ addressOffset: 0x10
+ size: 0x20
+ access: read-write
+ resetValue: 0x00000000
+ fields:
+ PA:
+ description: Peripheral address
+ bitOffset: 0
+ bitWidth: 32
+ CPAR2:
+ displayName: CPAR2
+ description: DMA channel 2 peripheral address
+ addressOffset: 0x24
+ size: 0x20
+ access: read-write
+ resetValue: 0x00000000
+ fields:
+ PA:
+ description: Peripheral address
+ bitOffset: 0
+ bitWidth: 32
+ CPAR3:
+ displayName: CPAR3
+ description: DMA channel 3 peripheral address
+ addressOffset: 0x38
+ size: 0x20
+ access: read-write
+ resetValue: 0x00000000
+ fields:
+ PA:
+ description: Peripheral address
+ bitOffset: 0
+ bitWidth: 32
+ CPAR4:
+ displayName: CPAR4
+ description: DMA channel 4 peripheral address
+ addressOffset: 0x4C
+ size: 0x20
+ access: read-write
+ resetValue: 0x00000000
+ fields:
+ PA:
+ description: Peripheral address
+ bitOffset: 0
+ bitWidth: 32
+ CPAR5:
+ displayName: CPAR5
+ description: DMA channel 5 peripheral address
+ addressOffset: 0x60
+ size: 0x20
+ access: read-write
+ resetValue: 0x00000000
+ fields:
+ PA:
+ description: Peripheral address
+ bitOffset: 0
+ bitWidth: 32
+ CMAR1:
+ displayName: CMAR1
+ description: DMA channel 1 memory address
+ addressOffset: 0x14
+ size: 0x20
+ access: read-write
+ resetValue: 0x00000000
+ fields:
+ MA:
+ description: Memory address
+ bitOffset: 0
+ bitWidth: 32
+ CMAR2:
+ displayName: CMAR2
+ description: DMA channel 2 memory address
+ addressOffset: 0x28
+ size: 0x20
+ access: read-write
+ resetValue: 0x00000000
+ fields:
+ MA:
+ description: Memory address
+ bitOffset: 0
+ bitWidth: 32
+ CMAR3:
+ displayName: CMAR3
+ description: DMA channel 3 memory address
+ addressOffset: 0x3C
+ size: 0x20
+ access: read-write
+ resetValue: 0x00000000
+ fields:
+ MA:
+ description: Memory address
+ bitOffset: 0
+ bitWidth: 32
+ CMAR4:
+ displayName: CMAR4
+ description: DMA channel 4 memory address
+ addressOffset: 0x50
+ size: 0x20
+ access: read-write
+ resetValue: 0x00000000
+ fields:
+ MA:
+ description: Memory address
+ bitOffset: 0
+ bitWidth: 32
+ CMAR5:
+ displayName: CMAR5
+ description: DMA channel 5 memory address
+ addressOffset: 0x64
+ size: 0x20
+ access: read-write
+ resetValue: 0x00000000
+ fields:
+ MA:
+ description: Memory address
+ bitOffset: 0
+ bitWidth: 32
+DMA2:
+ _cluster:
+ "CH%s":
+ description: "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"
+ "CCR?":
+ name: CR
+ "CNDTR?":
+ name: NDTR
+ "CPAR?":
+ name: PAR
+ "CMAR?":
+ name: MAR
diff --git a/devices/common_patches/g0_dma_7ch.yaml b/devices/common_patches/g0_dma_7ch.yaml
index db80a2465..b39ec581a 100644
--- a/devices/common_patches/g0_dma_7ch.yaml
+++ b/devices/common_patches/g0_dma_7ch.yaml
@@ -23,167 +23,167 @@ DMA:
CTCIF1:
name: CTCIF1
description: Clear channel 1 transfer complete flag
- CHTIF2:
+ CHTIF1:
name: CHTIF1
description: Clear channel 1 half transfer flag
- CTEIF3:
+ CTEIF1:
name: CTEIF1
description: Clear channel 1 transfer error flag
- CGIF4:
+ CGIF2:
name: CGIF2
description: Clear channel 2 global interrupt flag
- CTCIF5:
+ CTCIF2:
name: CTCIF2
description: Clear channel 2 transfer complete flag
- CHTIF6:
+ CHTIF2:
name: CHTIF2
description: Clear channel 2 half transfer flag
- CTEIF7:
+ CTEIF2:
name: CTEIF2
description: Clear channel 2 transfer error flag
- CGIF8:
+ CGIF3:
name: CGIF3
description: Clear channel 3 global interrupt flag
- CTCIF9:
+ CTCIF3:
name: CTCIF3
description: Clear channel 3 transfer complete flag
- CHTIF10:
+ CHTIF3:
name: CHTIF3
description: Clear channel 3 half transfer flag
- CTEIF11:
+ CTEIF3:
name: CTEIF3
description: Clear channel 3 transfer error flag
- CGIF12:
+ CGIF4:
name: CGIF4
description: Clear channel 4 global interrupt flag
- CTCIF13:
+ CTCIF4:
name: CTCIF4
description: Clear channel 4 transfer complete flag
- CHTIF14:
+ CHTIF4:
name: CHTIF4
description: Clear channel 4 half transfer flag
CTEIF15:
name: CTEIF4
description: Clear channel 4 transfer error flag
- CGIF16:
+ CGIF5:
name: CGIF5
description: Clear channel 5 global interrupt flag
- CTCIF17:
+ CTCIF5:
name: CTCIF5
description: Clear channel 5 transfer complete flag
- CHTIF18:
+ CHTIF5:
name: CHTIF5
description: Clear channel 5 half transfer flag
- CTEIF19:
+ CTEIF5:
name: CTEIF5
description: Clear channel 5 transfer error flag
- CGIF20:
+ CGIF6:
name: CGIF6
description: Clear channel 6 global interrupt flag
- CTCIF21:
+ CTCIF6:
name: CTCIF6
description: Clear channel 6 transfer complete flag
- CHTIF22:
+ CHTIF6:
name: CHTIF6
description: Clear channel 6 half transfer flag
- CTEIF23:
+ CTEIF6:
name: CTEIF6
description: Clear channel 6 transfer error flag
- CGIF24:
+ CGIF7:
name: CGIF7
description: Clear channel 7 global interrupt flag
- CTCIF25:
+ CTCIF7:
name: CTCIF7
description: Clear channel 7 transfer complete flag
- CHTIF26:
+ CHTIF7:
name: CHTIF7
description: Clear channel 7 half transfer flag
- CTEIF27:
+ CTEIF7:
name: CTEIF7
description: Clear channel 7 transfer error flag
ISR:
_modify:
- GIF0:
+ GIF1:
name: GIF1
description: Channel 1 global interrupt flag
TCIF1:
name: TCIF1
description: Channel 1 transfer complete flag
- HTIF2:
+ HTIF1:
name: HTIF1
description: Channel 1 half transfer flag
- TEIF3:
+ TEIF1:
name: TEIF1
description: Channel 1 transfer error flag
- GIF4:
+ GIF2:
name: GIF2
description: Channel 2 global interrupt flag
- TCIF5:
+ TCIF2:
name: TCIF2
description: Channel 2 transfer complete flag
- HTIF6:
+ HTIF2:
name: HTIF2
description: Channel 2 half transfer flag
- TEIF7:
+ TEIF2:
name: TEIF2
description: Channel 2 transfer error flag
- GIF8:
+ GIF3:
name: GIF3
description: Channel 3 global interrupt flag
- TCIF9:
+ TCIF3:
name: TCIF3
description: Channel 3 transfer complete flag
- HTIF10:
+ HTIF3:
name: HTIF3
description: Channel 3 half transfer flag
- TEIF11:
+ TEIF3:
name: TEIF3
description: Channel 3 transfer error flag
- GIF12:
+ GIF4:
name: GIF4
description: Channel 4 global interrupt flag
- TCIF13:
+ TCIF4:
name: TCIF4
description: Channel 4 transfer complete flag
- HTIF14:
+ HTIF4:
name: HTIF4
description: Channel 4 half transfer flag
- TEIF15:
+ TEIF4:
name: TEIF4
description: Channel 4 transfer error flag
- GIF16:
+ GIF5:
name: GIF5
description: Channel 5 global interrupt flag
- TCIF17:
+ TCIF5:
name: TCIF5
description: Channel 5 transfer complete flag
- HTIF18:
+ HTIF5:
name: HTIF5
description: Channel 5 half transfer flag
- TEIF19:
+ TEIF5:
name: TEIF5
description: Channel 5 transfer error flag
- GIF20:
+ GIF6:
name: GIF6
description: Channel 6 global interrupt flag
- TCIF21:
+ TCIF6:
name: TCIF6
description: Channel 6 transfer complete flag
- HTIF22:
+ HTIF6:
name: HTIF6
description: Channel 6 half transfer flag
- TEIF23:
+ TEIF6:
name: TEIF6
description: Channel 6 transfer error flag
- GIF24:
+ GIF7:
name: GIF7
description: Channel 7 global interrupt flag
- TCIF25:
+ TCIF7:
name: TCIF7
description: Channel 7 transfer complete flag
- HTIF26:
+ HTIF7:
name: HTIF7
description: Channel 7 half transfer flag
- TEIF27:
+ TEIF7:
name: TEIF7
description: Channel 7 transfer error flag
diff --git a/devices/stm32g050.yaml b/devices/stm32g050.yaml
new file mode 100644
index 000000000..9d776ccce
--- /dev/null
+++ b/devices/stm32g050.yaml
@@ -0,0 +1,7 @@
+_svd: ../svd/stm32g050.svd
+
+_modify:
+ name: STM32G050
+
+_include:
+ - ./common_patches/2_nvic_prio_bits.yaml
diff --git a/devices/stm32g051.yaml b/devices/stm32g051.yaml
new file mode 100644
index 000000000..2d5415af4
--- /dev/null
+++ b/devices/stm32g051.yaml
@@ -0,0 +1,13 @@
+_svd: ../svd/stm32g051.svd
+
+_modify:
+ name: STM32G051
+
+TIM1:
+ _modify:
+ _interrupts:
+ TIM1_BRK_UP_TRG_COM:
+ description: IM1 break, update, trigger and commutation interrupts
+
+_include:
+ - ./common_patches/2_nvic_prio_bits.yaml
diff --git a/devices/stm32g061.yaml b/devices/stm32g061.yaml
new file mode 100644
index 000000000..a760ce752
--- /dev/null
+++ b/devices/stm32g061.yaml
@@ -0,0 +1,13 @@
+_svd: ../svd/stm32g061.svd
+
+_modify:
+ name: STM32G061
+
+TIM1:
+ _modify:
+ _interrupts:
+ TIM1_BRK_UP_TRG_COM:
+ description: IM1 break, update, trigger and commutation interrupts
+
+_include:
+ - ./common_patches/2_nvic_prio_bits.yaml
diff --git a/devices/stm32g0b0.yaml b/devices/stm32g0b0.yaml
new file mode 100644
index 000000000..6de23993d
--- /dev/null
+++ b/devices/stm32g0b0.yaml
@@ -0,0 +1,15 @@
+_svd: ../svd/stm32g0b0.svd
+
+_modify:
+ name: STM32G0B0
+
+TIM1:
+ _modify:
+ _interrupts:
+ TIM1_BRK_UP_TRG_COM:
+ description: IM1 break, update, trigger and commutation interrupts
+
+_include:
+ - ./common_patches/2_nvic_prio_bits.yaml
+ - ./common_patches/g0_add_dma1_7ch.yaml
+ - ./common_patches/g0_add_dma2_5ch.yaml
diff --git a/devices/stm32g0b1.yaml b/devices/stm32g0b1.yaml
new file mode 100644
index 000000000..22f0ebcfb
--- /dev/null
+++ b/devices/stm32g0b1.yaml
@@ -0,0 +1,15 @@
+_svd: ../svd/stm32g0b1.svd
+
+_modify:
+ name: STM32G0B1
+
+TIM1:
+ _modify:
+ _interrupts:
+ TIM1_BRK_UP_TRG_COM:
+ description: IM1 break, update, trigger and commutation interrupts
+
+_include:
+ - ./common_patches/2_nvic_prio_bits.yaml
+ - ./common_patches/g0_add_dma1_7ch.yaml
+ - ./common_patches/g0_add_dma2_5ch.yaml
diff --git a/devices/stm32g0c1.yaml b/devices/stm32g0c1.yaml
new file mode 100644
index 000000000..baa237da9
--- /dev/null
+++ b/devices/stm32g0c1.yaml
@@ -0,0 +1,15 @@
+_svd: ../svd/stm32g0c1.svd
+
+_modify:
+ name: STM32G0C1
+
+TIM1:
+ _modify:
+ _interrupts:
+ TIM1_BRK_UP_TRG_COM:
+ description: IM1 break, update, trigger and commutation interrupts
+
+_include:
+ - ./common_patches/2_nvic_prio_bits.yaml
+ - ./common_patches/g0_add_dma1_7ch.yaml
+ - ./common_patches/g0_add_dma2_5ch.yaml
diff --git a/svd/vendor/en.stm32g0_svd.zip b/svd/vendor/en.stm32g0_svd.zip
index e3dfb8c47..b662cd04c 100644
Binary files a/svd/vendor/en.stm32g0_svd.zip and b/svd/vendor/en.stm32g0_svd.zip differ
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