diff --git a/devices/common_patches/g4_rcc.yaml b/devices/common_patches/g4_rcc.yaml
index b9bc2c6ed..87b30c2ed 100644
--- a/devices/common_patches/g4_rcc.yaml
+++ b/devices/common_patches/g4_rcc.yaml
@@ -1,4 +1,5 @@
 # Edits required to match RM0440.
+
 RCC:
   _modify:
     PLLSYSCFGR:
diff --git a/devices/stm32g431.yaml b/devices/stm32g431.yaml
index 156b161ef..fe0a085f1 100644
--- a/devices/stm32g431.yaml
+++ b/devices/stm32g431.yaml
@@ -19,3 +19,4 @@ _include:
  - ../peripherals/i2c/i2c_v2.yaml
  - ./common_patches/rename_USB_FS_peripheral_to_USB.yaml
  - ./common_patches/g4_usb.yaml
+ - ../peripherals/rcc/rcc_g4.yaml
diff --git a/devices/stm32g441.yaml b/devices/stm32g441.yaml
index 819894e72..1a03e47ca 100644
--- a/devices/stm32g441.yaml
+++ b/devices/stm32g441.yaml
@@ -19,3 +19,4 @@ _include:
  - ../peripherals/i2c/i2c_v2.yaml
  - ./common_patches/rename_USB_FS_peripheral_to_USB.yaml
  - ./common_patches/g4_usb.yaml
+ - ../peripherals/rcc/rcc_g4.yaml
diff --git a/devices/stm32g471.yaml b/devices/stm32g471.yaml
index 49ffcd5e7..f5f205bdb 100644
--- a/devices/stm32g471.yaml
+++ b/devices/stm32g471.yaml
@@ -19,3 +19,4 @@ _include:
  - ../peripherals/i2c/i2c_v2.yaml
  - ./common_patches/rename_USB_FS_peripheral_to_USB.yaml
  - ./common_patches/g4_usb.yaml
+ - ../peripherals/rcc/rcc_g4.yaml
diff --git a/devices/stm32g473.yaml b/devices/stm32g473.yaml
index eaccd64cc..4dd045c44 100644
--- a/devices/stm32g473.yaml
+++ b/devices/stm32g473.yaml
@@ -21,3 +21,4 @@ _include:
  - ../peripherals/i2c/i2c_v2.yaml
  - ./common_patches/rename_USB_FS_peripheral_to_USB.yaml
  - ./common_patches/g4_usb.yaml
+ - ../peripherals/rcc/rcc_g4.yaml
diff --git a/devices/stm32g474.yaml b/devices/stm32g474.yaml
index b0cf0fcb9..8a9b40a4f 100644
--- a/devices/stm32g474.yaml
+++ b/devices/stm32g474.yaml
@@ -21,3 +21,4 @@ _include:
  - ../peripherals/i2c/i2c_v2.yaml
  - ./common_patches/rename_USB_FS_peripheral_to_USB.yaml
  - ./common_patches/g4_usb.yaml
+ - ../peripherals/rcc/rcc_g4.yaml
diff --git a/devices/stm32g483.yaml b/devices/stm32g483.yaml
index fd9beda12..45142c514 100644
--- a/devices/stm32g483.yaml
+++ b/devices/stm32g483.yaml
@@ -22,3 +22,4 @@ _include:
  - ../peripherals/i2c/i2c_v2.yaml
  - ./common_patches/rename_USB_FS_peripheral_to_USB.yaml
  - ./common_patches/g4_usb.yaml
+ - ../peripherals/rcc/rcc_g4.yaml
diff --git a/devices/stm32g484.yaml b/devices/stm32g484.yaml
index e6f5b0f00..e95258bb0 100644
--- a/devices/stm32g484.yaml
+++ b/devices/stm32g484.yaml
@@ -21,3 +21,4 @@ _include:
  - ../peripherals/i2c/i2c_v2.yaml
  - ./common_patches/rename_USB_FS_peripheral_to_USB.yaml
  - ./common_patches/g4_usb.yaml
+ - ../peripherals/rcc/rcc_g4.yaml
diff --git a/devices/stm32g491.yaml b/devices/stm32g491.yaml
index 6aff1654c..88283dd30 100644
--- a/devices/stm32g491.yaml
+++ b/devices/stm32g491.yaml
@@ -30,3 +30,4 @@ _include:
  - ../peripherals/i2c/i2c_v2.yaml
  - ./common_patches/rename_USB_FS_peripheral_to_USB.yaml
  - ./common_patches/g4_usb.yaml
+ - ../peripherals/rcc/rcc_g4.yaml
diff --git a/peripherals/rcc/rcc_g4.yaml b/peripherals/rcc/rcc_g4.yaml
new file mode 100644
index 000000000..e34ce3fbe
--- /dev/null
+++ b/peripherals/rcc/rcc_g4.yaml
@@ -0,0 +1,360 @@
+RCC:
+  CR:
+    CSSON:
+      "Off": [0, "Clock security system disabled (clock detector OFF)"]
+      "On": [1, "Clock security system enable (clock detector ON if the HSE is ready, OFF if not)"]
+    HSEBYP:
+      NotBypassed: [0, "HSE crystal oscillator not bypassed"]
+      Bypassed: [1, "HSE crystal oscillator bypassed with external clock"]
+    "*RDY":
+      _read:
+        NotReady: [0, "Clock not ready"]
+        Ready: [1, "Clock ready"]
+    HSION,HSEON,PLLON,PLLI2SON,PLLSAION:
+      "Off": [0, "Clock Off"]
+      "On": [1, "Clock On"]
+
+  CFGR:
+    MCOPRE:
+      Div1: [0, "MCO divided by 1"]
+      Div2: [1, "MCO divided by 2"]
+      Div4: [2, "MCO divided by 4"]
+      Div8: [3, "MCO divided by 8"]
+      Div16: [4, "MCO divided by 16"]
+    MCOSEL:
+      None: [0, "MCO output disabled, no clock on MCO"]
+      SYSCLK: [1, "SYSCLK system clock selected"]
+      MSI: [2, "MSI clock selected"]
+      HSI: [3, "HSI clock selected"]
+      HSE: [4, "HSE clock selected"]
+      PLL: [5, "Main PLL clock selected"]
+      LSI: [6, "LSI clock selected"]
+      LSE: [7, "LSE clock selected"]
+      HSI48: [8, "Internal HSI48 clock selected"]
+    PPRE*:
+      Div1: [0, "HCLK not divided"] # Same for [0, 8]
+      Div2: [4, "HCLK divided by 2"]
+      Div4: [5, "HCLK divided by 4"]
+      Div8: [6, "HCLK divided by 8"]
+      Div16: [7, "HCLK divided by 16"]
+    HPRE:
+      Div1: [0, "SYSCLK not divided"] # Same for [0, 7]
+      Div2: [8, "SYSCLK divided by 2"]
+      Div4: [9, "SYSCLK divided by 4"]
+      Div8: [10, "SYSCLK divided by 8"]
+      Div16: [11, "SYSCLK divided by 16"]
+      Div64: [12, "SYSCLK divided by 64"]
+      Div128: [13, "SYSCLK divided by 128"]
+      Div256: [14, "SYSCLK divided by 256"]
+      Div512: [15, "SYSCLK divided by 512"]
+    SWS:
+      _read:
+        MSI: [0, "MSI oscillator used as system clock"]
+        HSI: [1, "HSI oscillator used as system clock"]
+        HSE: [2, "HSE used as system clock"]
+        PLL: [3, "PLL used as system clock"]
+    SW:
+      MSI: [0, "MSI selected as system clock"]
+      HSI: [1, "HSI selected as system clock"]
+      HSE: [2, "HSE selected as system clock"]
+      PLL: [3, "PLL selected as system clock"]
+
+  PLLCFGR:
+    PLLPDIV:
+      PLLP: [0, "pll_p_ck is controlled by PLLP"]
+      Div2: [2, "pll_p_ck = vco_ck / 2"]
+      Div3: [3, "pll_p_ck = vco_ck / 3"]
+      Div4: [4, "pll_p_ck = vco_ck / 4"]
+      Div5: [5, "pll_p_ck = vco_ck / 5"]
+      Div6: [6, "pll_p_ck = vco_ck / 6"]
+      Div7: [7, "pll_p_ck = vco_ck / 7"]
+      Div8: [8, "pll_p_ck = vco_ck / 8"]
+      Div9: [9, "pll_p_ck = vco_ck / 9"]
+      Div10: [10, "pll_p_ck = vco_ck / 10"]
+      Div11: [11, "pll_p_ck = vco_ck / 11"]
+      Div12: [12, "pll_p_ck = vco_ck / 12"]
+      Div13: [13, "pll_p_ck = vco_ck / 13"]
+      Div14: [14, "pll_p_ck = vco_ck / 14"]
+      Div15: [15, "pll_p_ck = vco_ck / 15"]
+      Div16: [16, "pll_p_ck = vco_ck / 16"]
+      Div17: [17, "pll_p_ck = vco_ck / 17"]
+      Div18: [18, "pll_p_ck = vco_ck / 18"]
+      Div19: [19, "pll_p_ck = vco_ck / 19"]
+      Div20: [20, "pll_p_ck = vco_ck / 20"]
+      Div21: [21, "pll_p_ck = vco_ck / 21"]
+      Div22: [22, "pll_p_ck = vco_ck / 22"]
+      Div23: [23, "pll_p_ck = vco_ck / 23"]
+      Div24: [24, "pll_p_ck = vco_ck / 24"]
+      Div25: [25, "pll_p_ck = vco_ck / 25"]
+      Div26: [26, "pll_p_ck = vco_ck / 26"]
+      Div27: [27, "pll_p_ck = vco_ck / 27"]
+      Div28: [28, "pll_p_ck = vco_ck / 28"]
+      Div29: [29, "pll_p_ck = vco_ck / 29"]
+      Div30: [30, "pll_p_ck = vco_ck / 30"]
+      Div31: [31, "pll_p_ck = vco_ck / 31"]
+    PLLR:
+      Div2: [0, "pll_r_ck = vco_ck / 2"]
+      Div4: [1, "pll_r_ck = vco_ck / 4"]
+      Div6: [2, "pll_r_ck = vco_ck / 6"]
+      Div8: [3, "pll_r_ck = vco_ck / 8"]
+    PLLQ:
+      Div2: [0, "pll_q_ck = vco_ck / 2"]
+      Div4: [1, "pll_q_ck = vco_ck / 4"]
+      Div6: [2, "pll_q_ck = vco_ck / 6"]
+      Div8: [3, "pll_q_ck = vco_ck / 8"]
+    PLLP:
+      Div7: [0, "pll_p_ck = vco_ck / 7"]
+      Div17: [1, "pll_p_ck = vco_ck / 17"]
+    PLLN:
+      Div8: [8, "pll_n_ck = vco_ck / 8"]
+      Div9: [9, "pll_n_ck = vco_ck / 9"]
+      Div10: [10, "pll_n_ck = vco_ck / 10"]
+      Div11: [11, "pll_n_ck = vco_ck / 11"]
+      Div12: [12, "pll_n_ck = vco_ck / 12"]
+      Div13: [13, "pll_n_ck = vco_ck / 13"]
+      Div14: [14, "pll_n_ck = vco_ck / 14"]
+      Div15: [15, "pll_n_ck = vco_ck / 15"]
+      Div16: [16, "pll_n_ck = vco_ck / 16"]
+      Div17: [17, "pll_n_ck = vco_ck / 17"]
+      Div18: [18, "pll_n_ck = vco_ck / 18"]
+      Div19: [19, "pll_n_ck = vco_ck / 19"]
+      Div20: [20, "pll_n_ck = vco_ck / 20"]
+      Div21: [21, "pll_n_ck = vco_ck / 21"]
+      Div22: [22, "pll_n_ck = vco_ck / 22"]
+      Div23: [23, "pll_n_ck = vco_ck / 23"]
+      Div24: [24, "pll_n_ck = vco_ck / 24"]
+      Div25: [25, "pll_n_ck = vco_ck / 25"]
+      Div26: [26, "pll_n_ck = vco_ck / 26"]
+      Div27: [27, "pll_n_ck = vco_ck / 27"]
+      Div28: [28, "pll_n_ck = vco_ck / 28"]
+      Div29: [29, "pll_n_ck = vco_ck / 29"]
+      Div30: [30, "pll_n_ck = vco_ck / 30"]
+      Div31: [31, "pll_n_ck = vco_ck / 31"]
+      Div32: [32, "pll_n_ck = vco_ck / 32"]
+      Div33: [33, "pll_n_ck = vco_ck / 33"]
+      Div34: [34, "pll_n_ck = vco_ck / 34"]
+      Div35: [35, "pll_n_ck = vco_ck / 35"]
+      Div36: [36, "pll_n_ck = vco_ck / 36"]
+      Div37: [37, "pll_n_ck = vco_ck / 37"]
+      Div38: [38, "pll_n_ck = vco_ck / 38"]
+      Div39: [39, "pll_n_ck = vco_ck / 39"]
+      Div40: [40, "pll_n_ck = vco_ck / 40"]
+      Div41: [41, "pll_n_ck = vco_ck / 41"]
+      Div42: [42, "pll_n_ck = vco_ck / 42"]
+      Div43: [43, "pll_n_ck = vco_ck / 43"]
+      Div44: [44, "pll_n_ck = vco_ck / 44"]
+      Div45: [45, "pll_n_ck = vco_ck / 45"]
+      Div46: [46, "pll_n_ck = vco_ck / 46"]
+      Div47: [47, "pll_n_ck = vco_ck / 47"]
+      Div48: [48, "pll_n_ck = vco_ck / 48"]
+      Div49: [49, "pll_n_ck = vco_ck / 49"]
+      Div50: [50, "pll_n_ck = vco_ck / 50"]
+      Div51: [51, "pll_n_ck = vco_ck / 51"]
+      Div52: [52, "pll_n_ck = vco_ck / 52"]
+      Div53: [53, "pll_n_ck = vco_ck / 53"]
+      Div54: [54, "pll_n_ck = vco_ck / 54"]
+      Div55: [55, "pll_n_ck = vco_ck / 55"]
+      Div56: [56, "pll_n_ck = vco_ck / 56"]
+      Div57: [57, "pll_n_ck = vco_ck / 57"]
+      Div58: [58, "pll_n_ck = vco_ck / 58"]
+      Div59: [59, "pll_n_ck = vco_ck / 59"]
+      Div60: [60, "pll_n_ck = vco_ck / 60"]
+      Div61: [61, "pll_n_ck = vco_ck / 61"]
+      Div62: [62, "pll_n_ck = vco_ck / 62"]
+      Div63: [63, "pll_n_ck = vco_ck / 63"]
+      Div64: [64, "pll_n_ck = vco_ck / 64"]
+      Div65: [65, "pll_n_ck = vco_ck / 65"]
+      Div66: [66, "pll_n_ck = vco_ck / 66"]
+      Div67: [67, "pll_n_ck = vco_ck / 67"]
+      Div68: [68, "pll_n_ck = vco_ck / 68"]
+      Div69: [69, "pll_n_ck = vco_ck / 69"]
+      Div70: [70, "pll_n_ck = vco_ck / 70"]
+      Div71: [71, "pll_n_ck = vco_ck / 71"]
+      Div72: [72, "pll_n_ck = vco_ck / 72"]
+      Div73: [73, "pll_n_ck = vco_ck / 73"]
+      Div74: [74, "pll_n_ck = vco_ck / 74"]
+      Div75: [75, "pll_n_ck = vco_ck / 75"]
+      Div76: [76, "pll_n_ck = vco_ck / 76"]
+      Div77: [77, "pll_n_ck = vco_ck / 77"]
+      Div78: [78, "pll_n_ck = vco_ck / 78"]
+      Div79: [79, "pll_n_ck = vco_ck / 79"]
+      Div80: [80, "pll_n_ck = vco_ck / 80"]
+      Div81: [81, "pll_n_ck = vco_ck / 81"]
+      Div82: [82, "pll_n_ck = vco_ck / 82"]
+      Div83: [83, "pll_n_ck = vco_ck / 83"]
+      Div84: [84, "pll_n_ck = vco_ck / 84"]
+      Div85: [85, "pll_n_ck = vco_ck / 85"]
+      Div86: [86, "pll_n_ck = vco_ck / 86"]
+      Div87: [87, "pll_n_ck = vco_ck / 87"]
+      Div88: [88, "pll_n_ck = vco_ck / 88"]
+      Div89: [89, "pll_n_ck = vco_ck / 89"]
+      Div90: [90, "pll_n_ck = vco_ck / 90"]
+      Div91: [91, "pll_n_ck = vco_ck / 91"]
+      Div92: [92, "pll_n_ck = vco_ck / 92"]
+      Div93: [93, "pll_n_ck = vco_ck / 93"]
+      Div94: [94, "pll_n_ck = vco_ck / 94"]
+      Div95: [95, "pll_n_ck = vco_ck / 95"]
+      Div96: [96, "pll_n_ck = vco_ck / 96"]
+      Div97: [97, "pll_n_ck = vco_ck / 97"]
+      Div98: [98, "pll_n_ck = vco_ck / 98"]
+      Div99: [99, "pll_n_ck = vco_ck / 99"]
+      Div100: [100, "pll_n_ck = vco_ck / 100"]
+      Div101: [101, "pll_n_ck = vco_ck / 101"]
+      Div102: [102, "pll_n_ck = vco_ck / 102"]
+      Div103: [103, "pll_n_ck = vco_ck / 103"]
+      Div104: [104, "pll_n_ck = vco_ck / 104"]
+      Div105: [105, "pll_n_ck = vco_ck / 105"]
+      Div106: [106, "pll_n_ck = vco_ck / 106"]
+      Div107: [107, "pll_n_ck = vco_ck / 107"]
+      Div108: [108, "pll_n_ck = vco_ck / 108"]
+      Div109: [109, "pll_n_ck = vco_ck / 109"]
+      Div110: [110, "pll_n_ck = vco_ck / 110"]
+      Div111: [111, "pll_n_ck = vco_ck / 111"]
+      Div112: [112, "pll_n_ck = vco_ck / 112"]
+      Div113: [113, "pll_n_ck = vco_ck / 113"]
+      Div114: [114, "pll_n_ck = vco_ck / 114"]
+      Div115: [115, "pll_n_ck = vco_ck / 115"]
+      Div116: [116, "pll_n_ck = vco_ck / 116"]
+      Div117: [117, "pll_n_ck = vco_ck / 117"]
+      Div118: [118, "pll_n_ck = vco_ck / 118"]
+      Div119: [119, "pll_n_ck = vco_ck / 119"]
+      Div120: [120, "pll_n_ck = vco_ck / 120"]
+      Div121: [121, "pll_n_ck = vco_ck / 121"]
+      Div122: [122, "pll_n_ck = vco_ck / 122"]
+      Div123: [123, "pll_n_ck = vco_ck / 123"]
+      Div124: [124, "pll_n_ck = vco_ck / 124"]
+      Div125: [125, "pll_n_ck = vco_ck / 125"]
+      Div126: [126, "pll_n_ck = vco_ck / 126"]
+      Div127: [127, "pll_n_ck = vco_ck / 127"]
+    PLLM:
+      Div1: [0, "pll_p_ck = vco_ck / 1"]
+      Div2: [1, "pll_p_ck = vco_ck / 2"]
+      Div3: [2, "pll_p_ck = vco_ck / 3"]
+      Div4: [3, "pll_p_ck = vco_ck / 4"]
+      Div5: [4, "pll_p_ck = vco_ck / 5"]
+      Div6: [5, "pll_p_ck = vco_ck / 6"]
+      Div7: [6, "pll_p_ck = vco_ck / 7"]
+      Div8: [7, "pll_p_ck = vco_ck / 8"]
+      Div9: [8, "pll_p_ck = vco_ck / 9"]
+      Div10: [9, "pll_p_ck = vco_ck / 10"]
+      Div11: [10, "pll_p_ck = vco_ck / 11"]
+      Div12: [11, "pll_p_ck = vco_ck / 12"]
+      Div13: [12, "pll_p_ck = vco_ck / 13"]
+      Div14: [13, "pll_p_ck = vco_ck / 14"]
+      Div15: [14, "pll_p_ck = vco_ck / 15"]
+      Div16: [15, "pll_p_ck = vco_ck / 16"]
+    PLLSRC:
+      None: [0, "No clock sent to PLL"]
+      HSI16: [2, "No clock sent to PLL"]
+      HSE: [3, "No clock sent to PLL"]
+
+  BDCR:
+    LSCOSEL:
+      LSI: [0, "LSI clock selected"]
+      LSE: [1, "LSE clock selected"]
+    LSCOEN:
+      Disabled: [0, "LSCO disabled"]
+      Enabled: [1, "LSCO enabled"]
+    BDRST:
+      Disabled: [0, "Reset not activated"]
+      Enabled: [1, "Reset the entire RTC domain"]
+    RTCEN:
+      Disabled: [0, "RTC clock disabled"]
+      Enabled: [1, "RTC clock enabled"]
+    LSERDY:
+      _read:
+        NotReady: [0, "LSE clock not ready"]
+        Ready: [1, "LSE clock ready"]
+    RTCSEL:
+      NoClock: [0, "No clock"]
+      LSE: [1, "LSE oscillator clock used as RTC clock"]
+      LSI: [2, "LSI oscillator clock used as RTC clock"]
+      HSE: [3, "HSE oscillator clock divided by a prescaler used as RTC clock"]
+    LSEON:
+      Disabled: [0, "LSE only enabled when requested by a peripheral or system function"]
+      Enabled: [1, "LSE enabled always generated by RCC"]
+    LSECSSD:
+      _read:
+        NoFailure: [0, "No failure detected on LSE (32 kHz oscillator)"]
+        Failure: [1, "Failure detected on LSE (32 kHz oscillator)"]
+    LSECSSON:
+      "Off": [0, "CSS on LSE (32 kHz external oscillator) OFF"]
+      "On": [1, "CSS on LSE (32 kHz external oscillator) ON"]
+    LSEDRV:
+      Lower: [0, "'Xtal mode' lower driving capability"]
+      MediumLow: [1, "'Xtal mode' medium low driving capability"]
+      MediumHigh: [2, "'Xtal mode' medium high driving capability"]
+      Higher: [3, "'Xtal mode' higher driving capability"]
+    LSEBYP:
+      NotBypassed: [0, "LSE crystal oscillator not bypassed"]
+      Bypassed: [1, "LSE crystal oscillator bypassed with external clock"]
+    LSERDY:
+      _read:
+        NotReady: [0, "LSE oscillator not ready"]
+        Ready: [1, "LSE oscillator ready"]
+    LSEON:
+      "Off": [0, "LSE oscillator Off"]
+      "On": [1, "LSE oscillator On"]
+
+  CSR:
+    "*RSTF":
+      _read:
+        NoReset: [0, "No reset has occured"]
+        Reset: [1, "A reset has occured"]
+    RMVF:
+      _write:
+        Clear: [1, "Clears the reset flag"]
+    LSIRDY:
+      _read:
+        NotReady: [0, "LSI oscillator not ready"]
+        Ready: [1, "LSI oscillator ready"]
+    LSION:
+      "Off": [0, "LSI oscillator Off"]
+      "On": [1, "LSI oscillator On"]
+
+  CCIPR:
+    "ADC*SEL":
+      None: [0, "No clock selected for ADC"]
+      PLLP: [1, "PLL 'P' clock selected for ADC"]
+      System: [2, "System clock selected for ADC"]
+    CLK48SEL:
+      HSI48: [0, "HSI48 clock selected as 48MHz clock"]
+      PLLQ: [2, "PLL 'Q' (PLL48M1CLK) clock selected as 48MHz clock"]
+    FDCANSEL:
+      HSE: [0, "HSE clock selected as FDCAN clock"]
+      PLLQ: [1, "PLL 'Q' clock selected as FDCAN clock"]
+      PCLK: [2, "PCLK clock selected as FDCAN clock"]
+    I2S23SEL:
+      System: [0, "System clock selected as I2S23 clock"]
+      PLLQ: [1, "PLL 'Q' clock selected as I2S23 clock"]
+      I2S_CKIN: [2, "Clock provided on I2S_CKIN pin is selected as I2S23 clock"]
+      HSI16: [3, "HSI16 clock selected as I2S23 clock"]
+    SAI1SEL:
+      System: [0, "System clock selected as SAI clock"]
+      PLLQ: [1, "PLL 'Q' clock selected as SAI clock"]
+      I2S_CKIN: [2, "Clock provided on I2S_CKIN pin is selected as SAI clock"]
+      HSI16: [3, "HSI16 clock selected as SAI clock"]
+    LPTIM1SEL:
+      PCLK: [0, "PCLK clock selected as LPTIM1 clock"]
+      LSI: [1, "LSI clock selected as LPTIM1 clock"]
+      HSI16: [2, "HSI16 clock selected as LPTIM1 clock"]
+      LSE: [3, "LSE clock selected as LPTIM1 clock"]
+    "I2C*SEL":
+      PCLK: [0, "PCLK clock selected as I2C clock"]
+      System: [1, "System clock (SYSCLK) selected as I2C clock"]
+      HSI16: [2, "HSI16 clock selected as I2C clock"]
+    "*UART*SEL":
+      PCLK: [0, "PCLK clock selected as UART clock"]
+      System: [1, "System clock (SYSCLK) selected as UART clock"]
+      HSI16: [2, "HSI16 clock selected as UART clock"]
+      LSE: [3, "LSE clock selected as UART clock"]
+
+  CCIPR2:
+    QSPISEL:
+      System: [0, "System clock selected as QUADSPI kernel clock"]
+      HSI16: [1, "HSI16 clock selected as QUADSPI kernel clock"]
+      PLLQ: [2, "PLL 'Q' clock selected as QUADSPI kernel clock"]
+    I2C4SEL:
+      PCLK: [0, "PCLK clock selected as I2C clock"]
+      System: [1, "System clock (SYSCLK) selected as I2C clock"]
+      HSI16: [2, "HSI16 clock selected as I2C clock"]

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