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2024年5月14日 (火) 16:32時点における最新版
Template:Semiconductor manufacturing processes
14nmプロセス（14ナノメートル・プロセス）は、「22nm」（または「20ナノメートル」）ノードの後継となるMOSFET技術ノードのマーケティング用語である。14ナノメートル」は、国際半導体技術ロードマップ（International Technology Roadmap for Semiconductors、ITRS）によってそう命名された。2011年頃までは、「22nm」に続くノードは「16nm」と予想されていた。すべての「14nm」ノードはFinFET（フィン電界効果トランジスタ）技術を採用しており、これはプレーナー・シリコンCMOS技術を非プレーナーに進化させたマルチゲートMOSFET技術の一種である。
少なくとも1997年以降、「プロセス・ノード」は純粋にマーケティングに基づいて命名されており、集積回路上の寸法とは何の関係もない[1]。「14nmプロセス」デバイスのゲート長、メタル・ピッチ、ゲート・ピッチはいずれも14ナノメートルではない[2][3][4]。例えば、TSMCとサムスンの「10nmプロセス」は、トランジスタ集積度においてインテルの「14nmプロセス」と「10nmプロセス」の中間であり、グローバルファウンドリーズ社の「7nmプロセス」は、寸法的にはインテルの「10nmプロセス」に類似している[5]。
サムスン電子は2014年に「14nm」チップをテープアウトし、2013年には 「10nm」クラスのNANDフラッシュチップを製造した。同年、SKハイニックスは「16nm」NANDフラッシュの量産を開始し、TSMCは 「16nm」FinFETの生産を開始した。翌年、インテルは「14nm」スケールのデバイスを消費者に出荷し始めた。
開発の経緯
[編集]開発の背景
[編集]The resolutions of a 「14nm」 device are difficult to achieve in a polymeric resist, even with electron beam lithography. In addition, the chemical effects of ionizing radiation also limit reliable resolution to about 30nm, which is also achievable using current state-of-the-art immersion lithography. Hardmask materials and multiple patterning are required.
A more significant limitation comes from plasma damage to low-k materials. The extent of damage is typically 20nm thick,[6] but can also go up to about 100 nm.[7] The damage sensitivity is expected to get worse as the low-k materials become more porous. For comparison, the atomic radius of an unconstrained silicon is 0.11 nm. Thus about 90 Si atoms would span the channel length, leading to substantial leakage.
Tela Innovations and Sequoia Design Systems developed a methodology allowing double exposure for the 「16nm」/「14 nm」 node circa 2010.[8] Samsung and Synopsys had also, at that time, begun implementing double patterning in 「22 nm」 and 「16 nm」 design flows.[9] Mentor Graphics reported taping out 「16 nm」 test chips in 2010.[10][needs update] On January 17, 2011, IBM announced that they were teaming up with ARM to develop 「14 nm」 chip processing technology.[11][needs update]
On February 18, 2011, Intel announced that it would construct a new $5 billion semiconductor fabrication plant in Arizona, designed to manufacture chips using the 「14 nm」 manufacturing processes and leading-edge 300 mm wafers.[12] The new fabrication plant was to be named Fab 42, and construction was meant to start in the middle of 2011. Intel billed the new facility as 「the most advanced, high-volume manufacturing facility in the world,「 and said it would come on line in 2013. Intel since decided to postpone opening this facility and instead upgrade its existing facilities to support 14-nm chips.[13][needs update] On May 17, 2011, Intel announced a roadmap for 2014 that included 「14 nm」 transistors for their Xeon, Core, and Atom product lines.[14][needs update]
Technology demos
[編集]In the late 1990s, Hisamoto's Japanese team from Hitachi Central Research Laboratory began collaborating with an international team of researchers on further developing FinFET technology, including TSMC's Chenming Hu and various UC Berkeley researchers. In 1998, the team successfully fabricated devices down to a 17 nm process. They later developed a 15 nm FinFET process in 2001.[15] In 2002, an international team of researchers at UC Berkeley, including Shibly Ahmed (Bangladeshi), Scott Bell, Cyrus Tabery (Iranian), Jeffrey Bokor, David Kyser, Chenming Hu (Taiwan Semiconductor Manufacturing Company), and Tsu-Jae King Liu, demonstrated FinFET devices down to 10nm gate length.[15][16]
In 2005, Toshiba demonstrated a 15 nm FinFET process, with a 15 nm gate length and 10 nm fin width, using a sidewall spacer process.[17] It had erstwhile been suggested in 2003 that for the 16 nm node, a logic transistor would have a gate length of about 5 nm.[18][needs update] In December 2007, Toshiba demonstrated a prototype memory unit that used 15-nanometre thin lines.[19]
In December 2009, National Nano Device Laboratories, owned by the Taiwanese government, produced a 「16 nm」 SRAM chip.[20][needs update]
In September 2011, Hynix announced the development of 「15 nm」 NAND cells.[21][needs update]
In December 2012, Samsung Electronics taped out a 「14 nm」 chip.[22][needs update]
In September 2013, Intel demonstrated an Ultrabook laptop that used a 「14 nm」 Broadwell CPU, and Intel CEO Brian Krzanich said, 「[CPU] will be shipping by the end of this year.「[23] However, as of February 2014, shipment had at time erstwhile been delayed further until Q4 2014.[24]
In August 2014, Intel announced details of the 「14 nm」 microarchitecture for its upcoming Core M processors, the first product to be manufactured on Intel's 「14 nm」 manufacturing process. The first systems based on the Core M processor were to become available in Q4 2014 — according to the press release. 「Intel's 14 nanometer technology uses second-generation tri-gate transistors to deliver industry-leading performance, power, density and cost per transistor,「 said Mark Bohr, Intel senior fellow, Technology and Manufacturing Group, and director, Process Architecture and Integration.[25]
In 2018 a shortage of 「14 nm」 fab capacity was announced by Intel.[26][needs update]
Shipping devices
[編集]In 2013, SK Hynix began mass-production of 「16 nm」 NAND flash,[27] TSMC began 「16 nm」 FinFET production,[28] and Samsung began 「10<span about="#mwt205" class="nowrap" data-cx="[{"adapted":true,"targetExists":true,"mandatoryTargetParams":[],"optionalTargetParams":[]}]" data-mw="{"parts":[{"template":{"target":{"wt":"Spaces","href":"./Template:Spaces"},"params":{},"i":0}}]}" data-ve-no-generated-contents="true" id="mw5Q" typeof="mw:Transclusion"><span typeof="mw:Entity"> </span></span>nm class「 NAND flash production.[29]
On September 5, 2014, Intel launched the first three Broadwell-based processors that belonged to the low-TDP Core M family: Core M-5Y10, Core M-5Y10a, and Core M-5Y70.[30][needs update]
In February 2015, Samsung announced that their flagship smartphones, the Galaxy S6 and S6 Edge, would feature 「14 nm」 Exynos systems on chip (SoCs).[31][needs update]
On March 9, 2015, Apple Inc. released the 「Early 2015「 MacBook and MacBook Pro, which utilized 「14 nm」 Intel processors. Of note is the i7-5557U, which has Intel Iris Graphics 6100 and two cores running at 3.1 GHz, using only 28 watts.[32][33][needs update]
On September 25, 2015, Apple Inc. released the iPhone 6S & 6S Plus, which were erstwhile equipped with 「desktop-class「 A9 chips[34] that are fabricated in both 「14 nm」 by Samsung and 「16 nm」 by TSMC (Taiwan Semiconductor Manufacturing Company).[needs update]
In May 2016, Nvidia released its GeForce 10 series GPUs based on the Pascal architecture, which incorporates TSMC's 「16 nm」 FinFET technology and Samsung's 「14 nm」 FinFET technology.[35][36][needs update]
In June 2016, AMD released its Radeon RX 400 GPUs based on the Polaris architecture, which incorporated 「14 nm」 FinFET technology from Samsung. The technology had at that time been licensed to GlobalFoundries for dual sourcing.[37][needs update]
On August 2, 2016, Microsoft released the Xbox One S, which utilized 「16 nm」 by TSMC. [needs update]
On March 2, 2017, AMD released its Ryzen CPUs based on the Zen architecture, incorporating 「14 nm」 FinFET technology from Samsung which had erstwhile been licensed to GlobalFoundries for GlobalFoundries to build.[38][needs update]
The NEC SX-Aurora TSUBASA processor, introduced in October 2017,[39] used a 「16 nm」 FinFET process from TSMC and was designed for use with NEC SX supercomputers.[40][needs update]
On July 22, 2018, GlobalFoundries announced their 「12 nm」 Leading-Performance (12LP) process, based on a licensed 14LP process from Samsung.[41][needs update]
In September 2018, Nvidia released GPUs based on their Turing (microarchitecture), which were made on TSMC's 「12 nm」 process and had a transistor density of 24.67 million transistors per square millimeter.[42][needs update]
14nm process nodes
[編集]| ITRS Logic Device Ground Rules (2015) |
Samsung[注釈 1] | TSMC[43] | Intel | GlobalFoundries[注釈 2] | SMIC | |||||
|---|---|---|---|---|---|---|---|---|---|---|
| Process name | 16/14 nm | 14/11 nm | 16FF (16 nm) |
16FF+ (16 nm) |
16FFC (16 nm) |
12FFC (12 nm) |
14 nm | 14LPP[44] (14 nm) |
12LP[45][46] (12 nm) |
14 nm |
| Transistor density (MTr/mm2) | ? | 32.94[41] (14nm) 54.38[41] (11nm) |
28.88[47] | 33.8[48] | 37.5[49][注釈 3]
44.67[51] |
30.59[41] | 36.71[41] | 30[52] | ||
| Transistor gate pitch (nm) | 70 | 78 – 14LPE (HD) 78 – 14LPP (HD) 84 – 14LPP (UHP) 84 – 14LPP (HP) 78 – 11LPP (UHD) |
88 | 70 (14 nm) 70 (14 nm +) 84 (14 nm ++) |
84 | ? | ||||
| Interconnect pitch (nm) | 56 | 67 | 70 | 52 | ? | ? | ||||
| Transistor fin pitch (nm) | 42 | 49 | 45 | 42 | 48 | ? | ||||
| Transistor fin width (nm) | 8 | 8 | colspan="4" ? | 8 | ? | ? | ||||
| Transistor fin height (nm) | 42 | ~38 | 37 | 42 | ? | ? | ||||
| Production year | 2015 | 2013 | 2013 | 2015 | 2016 | 2017 | 2014 | 2016 | 2018 | 2019 |
- ^ “No More Nanometers – EEJournal” (July 23, 2020). Template:Cite webの呼び出しエラー：引数 accessdate は必須です。
- ^ Shukla. “A Brief History of Process Node Evolution”. design-reuse.com. 2019年7月9日閲覧。
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- ^ “Life at 10nm. (Or is it 7nm?) And 3nm - Views on Advanced Silicon Platforms”. eejournal.com (2018年3月12日). Template:Cite webの呼び出しエラー：引数 accessdate は必須です。
- ^ Richard, O. (2007). “Sidewall damage in silica-based low-k material induced by different patterning plasma processes studied by energy filtered and analytical scanning TEM”. Microelectronic Engineering 84 (3): 517–523. doi:10.1016/j.mee.2006.10.058etal
- ^ Gross, T. (2008). “Detection of nanoscale etch and ash damage to nanoporous methyl silsesquioxane using electrostatic force microscopy”. Microelectronic Engineering 85 (2): 401–407. doi:10.1016/j.mee.2007.07.014etal
- ^ Axelrad, V. (2010). Rieger, Michael L; Thiele, Joerg. eds. “16nm with 193nm immersion lithography and double exposure”. Proc. SPIE 7641: 764109. Bibcode: 2010SPIE.7641E..09A. doi:10.1117/12.846677etal
- ^ Noh, M-S. (2010). Dusa, Mircea V; Conley, Will. eds. “Implementing and validating double patterning in 22-nm to 16-nm product design and patterning flows”. Proc. SPIE 7640: 76400S. Bibcode: 2010SPIE.7640E..0SN. doi:10.1117/12.848194etal
- ^ “Mentor moves tools toward 16-nanometer”. EETimes (August 23, 2010). Template:Cite webの呼び出しエラー：引数 accessdate は必須です。
- ^ “IBM and ARM to Collaborate on Advanced Semiconductor Technology for Mobile Electronics”. IBM Press release (January 17, 2011). Template:Cite webの呼び出しエラー：引数 accessdate は必須です。
- ^ “Intel to build fab for 14-nm chips”. EE Times. February 2, 2013時点のオリジナルよりアーカイブ。February 22, 2011閲覧。
- ^ “Intel shelves cutting-edge Arizona chip factory”. Reuters (January 14, 2014). Template:Cite webの呼び出しエラー：引数 accessdate は必須です。
- ^ “Implementing and validating double patterning in 22-nm to 16-nm product design and patterning flows”. AnandTech (May 17, 2011). Template:Cite webの呼び出しエラー：引数 accessdate は必須です。
- ^ a b Tsu-Jae King (June 11, 2012). “FinFET: History, Fundamentals and Future”. University of California, Berkeley. Symposium on VLSI Technology Short Course. 9 July 2019閲覧。
- ^ Ahmed, Shibly; Bell, Scott; Tabery, Cyrus; Bokor, Jeffrey; Kyser, David; Hu, Chenming; Liu, Tsu-Jae King; Yu, Bin et al. (December 2002). “FinFET scaling to 10 nm gate length”. Digest. International Electron Devices Meeting. pp. 251–254. doi:10.1109/IEDM.2002.1175825. ISBN 0-7803-7462-2. オリジナルのMay 27, 2020時点におけるアーカイブ。 December 10, 2019閲覧。
- ^ Kaneko, A; Yagashita, A; Yahashi, K; Kubota, T (2005). "Sidewall transfer process and selective gate sidewall spacer formation technology for sub-15nm FinFET with elevated source/drain extension". IEEE International Electron Devices Meeting (IEDM 2005). pp. 844–847. doi:10.1109/IEDM.2005.1609488。
- ^ “Intel scientists find wall for Moore's Law”. ZDNet. (December 1, 2003)
- ^ “15 Nanometre Memory Tested”. The Inquirer. December 13, 2007時点のオリジナルよりアーカイブ。 Template:Cite webの呼び出しエラー：引数 accessdate は必須です。
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- ^ Hübler, Arved (2011). “Printed Paper Photovoltaic Cells”. Advanced Energy Materials 1 (6): 1018–1022. Bibcode: 2011AdEnM...1.1018H. doi:10.1002/aenm.201100394etal
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Lower numbers are better, except for transistor density, in which case the opposite is true.[1] Transistor gate pitch is also referred to as CPP (contacted poly pitch), and interconnect pitch is also referred to as MMP (minimum metal pitch).[2][3][4][5][6]
References
[編集]- ^ “Nanotechnology is expected to make transistors even smaller and chips correspondingly more powerful”. Encyclopædia Britannica (December 22, 2017). March 7, 2018閲覧。
- ^ “Intel 14nm Process Technology”. Template:Cite webの呼び出しエラー：引数 accessdate は必須です。
- ^ “Samsung's 14 nm LPE FinFET transistors” (英語). Electronics EETimes. (January 20, 2016) February 17, 2017閲覧。
- ^ “14 nm lithography process - WikiChip” (英語). en.wikichip.org. February 17, 2017閲覧。
- ^ “16 nm lithography process - WikiChip” (英語). en.wikichip.org. February 17, 2017閲覧。
- ^ “International Technology Roadmap for Semiconductors 2.0 2015 Edition Executive Report”. October 2, 2016時点のオリジナルよりアーカイブ。April 6, 2017閲覧。
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