Shamks412

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Sep 20th, 2024
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SystemVerilog 2.72 KB | Source Code | 0 0
  1. module viterbi_tx_rx_tb();
  2.    reg clk;
  3.    reg rst;
  4.    reg encoder_i;
  5.    reg enable_encoder_i;
  6.    wire decoder_o;
  7.    wire [1:0] encoder_o;
  8.  
  9.    reg [1:0] corrupted_encoder_o;  // To hold the corrupted encoded output
  10.    reg [1:0] encoder_o_reg;
  11.    reg enable_decoder_in;
  12.  
  13.    integer error_counter = 0;       // To count the number of errors introduced
  14.    integer corrected_counter = 0;   // To count the number of errors corrected
  15.  
  16.    // Instantiate the DUT (Device Under Test)
  17.    viterbi_tx_rx vtr(
  18.       .clk(clk),
  19.       .rst(rst),
  20.       .encoder_i(encoder_i),
  21.       .enable_encoder_i(enable_encoder_i),
  22.       .decoder_o(decoder_o)
  23.    );
  24.  
  25.    // Generate a clock signal
  26.    always
  27.       #50 clk = ~clk;
  28.  
  29.    // Testbench stimulus
  30.    initial begin
  31.       clk = 1'b1;
  32.       rst = 1'b0;
  33.       encoder_i = 1'b0;
  34.       enable_encoder_i = 1'b0;
  35.       corrupted_encoder_o = 2'b00;   // Initialize the corrupted encoded output
  36.  
  37.       // Reset the system
  38.       #1000 rst = 1'b1;
  39.       enable_encoder_i = 1'b1;
  40.  
  41.       // Input sequence for the encoder
  42.       #100 encoder_i = 1'b1;
  43.       #100 encoder_i = 1'b0;
  44.       #100 encoder_i = 1'b1;
  45.       #100 encoder_i = 1'b1;
  46.       #100 encoder_i = 1'b0;
  47.       #100 encoder_i = 1'b1;
  48.  
  49.       // Stop the simulation after enough time
  50.       #1000000 $finish;
  51.    end
  52.  
  53.    // Simulate errors in the encoded output
  54.    always @(posedge clk) begin
  55.       if (rst && enable_encoder_i) begin
  56.          // Capture the encoder output
  57.          encoder_o_reg <= vtr.encoder_o;
  58.          
  59.          // Introduce an error in the encoder output every few cycles
  60.          if (error_counter % 10 == 0) begin
  61.             // Flip one bit to introduce an error
  62.             corrupted_encoder_o = {~encoder_o_reg[1], encoder_o_reg[0]};
  63.             error_counter = error_counter + 1;
  64.          end else begin
  65.             corrupted_encoder_o = encoder_o_reg;  // No error
  66.          end
  67.  
  68.          // Enable the decoder after capturing the encoded data
  69.          enable_decoder_in <= vtr.valid_encoder_o;
  70.       end
  71.    end
  72.  
  73.    // Monitor the decoder output and compare it with the original input
  74.    always @(posedge clk) begin
  75.       if (rst && enable_decoder_in) begin
  76.          // Check if the decoder output matches the original input
  77.          if (decoder_o != encoder_i) begin
  78.             corrected_counter = corrected_counter + 1;
  79.          end
  80.       end
  81.    end
  82.  
  83.    // Display the number of errors introduced and corrected
  84.    initial begin
  85.       $monitor("Time: %0t | Encoder Input: %b | Corrupted Encoder Output: %b | Decoder Output: %b | Errors Introduced: %d | Errors Corrected: %d",
  86.                $time, encoder_i, corrupted_encoder_o, decoder_o, error_counter, corrected_counter);
  87.    end
  88.  
  89. endmodule
  90.  
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