HCD-GRX20/RXD3

SERVICE MANUAL AEP Model

UK Model
HCD-RXD3

E Model
Australian Model
HCD-GRX20

HCD-GRX20/RXD3 is the tuner, deck, CD and PHOTO : HCD-RXD3

amplifier section in MHC-GRX20/RXD3.

Model Name Using Similar Mechanism NEW

CD CD Mechanism Type CX3
SECTION Base Unit Type KSM-213ECM
Optical Pick-up Type KSS-213ECM/C2NP
TAPE Model Name Using Similar Mechanism NEW
DECK
SECTION Tape Transport Mechanism Type CWL-44-FR

SPECIFICATIONS
Amplifier section Outputs DIGITAL OUT (OPTICAL)
European model MD OUT (phono jacks): (Square optical connector jack, rear panel)
DIN power output (Rated) 40 W + 40 W voltage 250 mV Wavelength 600 nm
(6 Ω at 1 kHz, DIN) impedance 1 kΩ Output Level –18 dBm
Continuous RMS power output (Reference) PHONES (stereo phone jack):
50 W + 50 W accepts headphones of 8 Tape deck section
(6 Ω at 1 kHz, 10% Ω or more. Recording system 4-track 2-channel stereo
THD) SPEAKER: accepts impedance of 6 Frequency response 40 – 13,000 Hz (±3 dB),
Music power output (Reference) to 16 Ω using Sony TYPE I
100 W + 100 W cassette
(6 Ω at 1 kHz, 10% CD player section Wow and flutter ±0.15% W. Peak(IEC)
THD) System Compact disc and digital 0.1% W. RMS(NAB)
Other models audio system ±0.2% W. Peak(DIN)
The following measured at AC 110, 220 V 60 Hz; Laser Semiconductor laser
DIN power output (Rated) 45 W + 45 W (λ = 780 nm) Tuner section
(6 Ω at 1 kHz, DIN) Emission duration: FM stereo, FM/AM superheterodyne tuner
Continuous RMS power output (Reference) continuous
50 W + 50 W Laser output Max. 44.6µW* FM tunr section
(6 Ω at 1 kHz, 10% *This output is the value Tuning range 87.5 – 108.0 MHz
THD) measured at a distance of Antenna FM lead antenna
The following measured at AC 120, 240 V 60 Hz; 200 mm from the Antenna terminals 75 Ω unbalanced
DIN power output (Rated) 50 W + 50 W objective lens surface on Intermediate frequency 10.7 MHz
(6 Ω at 1 kHz, DIN) the Optical Pick-up
Continuous RMS power output (Reference) Block with 7 mm — Continued on next page —
60 W + 60 W aperture.
(6 Ω at 1 kHz, 10% Frequency response 20Hz – 20kHz (±0.5 dB)
THD) Wavelength 780 – 790 nm
Inputs
MD IN (phono jack): voltage 450 mV,
impedance 47 kΩ

MINI Hi-Fi COMPONENT SYSTEM

MICROFILM
 HCD-GRX20/RXD3

6-4. SCHEMATIC DIAGRAM MAIN (1/3) SECTION • Refer to page 19 for Waveforms. • Refer to page 33 for IC Block Diagrams. • Refer to page 19 for Note on Schematic Diagram.

E,AUS,SP,TW MODEL

0.047µ
*
*

R167 2.2k
0.47µ

C107
* 220

68
0.047µ
25
16V

0.047µ mH

R136
L109 22µH 47
C167 C186 0.001µ
*
mH
R175

*
25

23
C100
0.001

22

23

* MARK :
C107 C135 C167 R105 R106

GRX20 NO MOUNT 0.022(T) NO MOUNT 220 5.6k

RXD3 0.01µ 560p(T) 10p 1k 100

21 21
HCD-GRX20/RXD3

6-5. SCHEMATIC DIAGRAM MAIN (2/3) SECTION • Refer to page 19 for Waveforms. • Refer to page 33 for IC Block Diagrams. • Refer to page 19 for Note on Schematic Diagram.

23
21

0.018µ

22µ

0.018 0.0012

0.0012 502

10

Q252

Q551

Q552

22 22
 HCD-GRX20/RXD3

6-6. SCHEMATIC DIAGRAM MAIN (3/3) SECTION • Refer to page 33 for IC Block Diagrams. • Refer to page 19 for Note on Schematic Diagram.

29

22
27

R333
47k

R341
470

R336
680 D302
UZ6.2B
C363
0.1

21

R358
470
C351
0.1

47µ

C352
0.1

23 23
 HCD-GRX20/RXD3

6-8. SCHEMATIC DIAGRAM FRONT PANEL SECTION • Refer to page 19 for Waveforms. • Refer to page 30 for IC Pin Function. • Refer to page 19 for Note on Schematic Diagram.

21 21

SPS-447-1

6.3V 0.022
150

2SA733

C622 10µ
0.1

82040

EXCEPT MX MODEL 0.01

0.01
AR,E,MX MODELS

EXCEPT MX MODEL

EXCEPT E,SP,TW,MX,AR MODELS

R612

100k

ROTARY
ENCODER

29

25 25
 HCD-GRX20/RXD3

6-10. SCHEMATIC DIAGRAM AMPLIFIER SECTION • Refer to page 19 for Note on Schematic Diagram.

R444
10
GRX20
MODEL
J475

RXD3
MODEL

-070E

RXD3
MODEL

J746
GRX20
MODEL

100µ 63V:AUS MODEL

100µ 63V:AUS MODEL

EXCEPT AUS MODEL

EXCEPT AUS MODEL

100µ 50V:
100µ 50V:
0.022 (CHASSIS)

23

* 100µ 50V :
EXCEPT AUS MODEL * 100µ 50V :
EXCEPT AUS MODEL
GRX20 : AUS, RXD3 MODELS
100µ 63V : AUS MODEL 100µ 63V : AUS MODEL

UZ-12BSA
T2A
UZ-8.2BSA

AC IN
C726
100µ
16V

UZ-27BSA-TA
FUSE F702 GRX20 : AR,E,SP,TW : 4.0A 250V
GRX20 : MX : 4.0A 125V
C701 C702
3300µ 50V : 3300µ 50V :
EXCEPT AUS MODEL EXCEPT AUS MODEL
3300µ 63V : 3300µ 63V : F703 GRX20 : AR,E,SP,TW MODEL
AUS MODEL AUS MODEL T2AL AC IN
250V

SW401

AC VOLTAGE
220 – 240 V

110 – 120 V

AC SWITCH
GRX20 : E,SP,TW,MX,AR MODELS

27 27
 HCD-GRX20/RXD3

6-12. SCHEMATIC DIAGRAM CD SECTION • Refer to page 19 for Waveforms. • Refer to page 31,32 for IC Block Diagrams. • Refer to page 19 for Note on Schematic Diagram.

25

23

29 29
HCD-GRX20/RXD3

6-13. IC PIN FUNCTION

IC601 CXP82040-108Q(SYSTEM CONTROL) FRONT BOARD
Pin No. Pin Name I/O Description Pin No. Pin Name I/O Description
1,2 2G,1G O FLD grid output. 51 TRAY C. SW I Tray close switch signal input.
3 NC — Not used. 52 VR UP I Volume up signal input.
4 SCOR I CXD2589Q SCOR input. 53 VR DN I Volume down signal input.
5 COUNT I CXD2589Q COUNT input. 54 CD ENCODER IN A I Not used.
6 POWER DOWN IN I Power data input. 55 CD ENCODER IN B I Not used.
7 FOK I FOK input. 56 SURROUND OUT O Not used.
8 REMOTE IN I Remote signal input. 57 DBFB NOR&HI OUT O Not used.
9 DATA IN I Data input.(DECK secton) 58 DBFB HI OUT O Not used.
10 S/L O S/L output.(DECK secton) 59 DOLBY NR OUT O Not used.
11 DECK,CD STB O STB output.(CD,DECK section) 60 2CH OUT O Not used.
12 LOCK O CXA1992BR LOCK output. 61 MD MUTE O Not used.
13 CLOCK O CXD2589Q CLOCK output. 62 TUNER MUTE OUT O Tuner Mute output.
14 MODE SW IN O Mode switch input. 63 SYSTEM MUTE OUT O System Mute output.
15 NC O Not used. 64 POWER SW OUT O POWER switch output.
16 CE O Not used. 65 P1 O FLD segment output.
17 CTRL O Function control output. 66 P2(MODE SW 1) O FLD segment output. Mode switch 1.
18 LATCH B O Not used. 67 P3(MODE SW 2) O FLD segment output. Mode switch 2.
19 LATCH A O LATCH output. 68 P4(MODE SW 3) O FLD segment output. Mode switch 3.
20 XLAT O CXD2589Q XLAT output. 69 P5(MODE SW 4) O FLD segment output. Mode switch 4.
21 CE O LC72131 CE output. 70 P6(MODE SW 5) O FLD segment output. Mode switch 5.
22 SQCK O CXD2589Q SQCK output. 71 P7(MODE SW 6) O FLD segment output. Mode switch 6.
23 SQSO O CXD2589Q SQSO output. 72 P8(MODE SW 7) O FLD segment output. Mode switch 7.
24 DATA O CXD2589Q DATA output. 73 P9(MODE SW 8) O FLD segment output. Mode switch 8.
25 S.CLOCK O S.CLOCK output. 74 P10(MODE SW 9) O FLD segment output. Mode switch 9.
26 S,DATA IN I S.DATA input. 75 P11(MODE SW 10) O FLD segment output. Mode switch 10.
27 S.DATA OUT O S.DATA output. 76 P12(MODE SW 11) O FLD segment output. Mode switch 11.
28 FM STEREO IN I FM Stereo input. 77 P13(MODE SW 12) O FLD segment output. Mode switch 12.
29 to 31 KEY IN O to 2 I Key input 0 to 2. 78 P14(MODE SW 13) O FLD segment output. Mode switch 13.
32 VACS IN I Not used. 79 P15(MODE SW 14) O FLD segment output. Mode switch 14.
33 to 36 SPEANA IN 1 to 4 I Not used. 80 to 85 P16 to 21 O FLD segment output.
37 ANS IN I AMS input. 86 NC — Not used.
38 RESET I RESET input. 87,88 15G,14G O FLD grid output.
39 EXTAL — X’TAL 10MHz 89 VDD — VDD.
40 XTAL — X’TAL 10MHz 90 to 100 13G to 3G O FLD grid output.
41 VSS — Ground.
42 SENS1 I CXD2589Q SENS1 input.
43 SENS2 I CXD2589Q SENS2 input.
44 VDD — VDD.
45 VFDP — VFDP.
46 PICK UP SW I Pick-up up switch signal input.
47 PICK DOWN SW I Pick-up down switch signal input.
48 DISC COUNT SW I Disc count switch signal input.
49 TURN TABLE SW I Turn Table switch signal input.
50 TRAY O. SW I Tray open switch signal input.

30 30
6-14. IC BLOCK DIAGRAMS

— CD DECORD SECTION —

IC701 CXA1992BR

RF M
RFTC

RF O
PD1

CC1

FOK
PD2

RF I

CC2
PD

LD

CP
CB
39 38 37 36 35 34 33 32 31 30 29 28 27

PD 2 PD 1 PD LD
I-V AMP I-V AMP AMP AMP RF SUMMING
AMP FOCUS OK
COMPARATOR

VCC
LASER
POWER
CONTROL
IFB1 – IFB6
PEAK/BOTTOM MIRR
HOLD COMPARATOR IIL
↓
FE PEAK/BOTTOM DEFECT TTL
40
BIAS HOLD AMP

FOCUS BIAS
FOCUS ERROR
WINDOW
VEE AMP
COMPARATOR

DFCT1
LDON

MIRR
LPCL

TGFL
LPC
FOH
FOL

CC1
F I-V
F 41
AMP
IIL 26 SENS2
E I-V TRACKING GAIN
TGH ↓ 25 SENS1
E 42 TGFL TTL
AMP WINDOW TGL 24 C. OUT
COMPARATOR
EI 43 BALH IIC DATA REGISTER, INPUT SHIFT REGISTER,
ADDRESS DECODER, SENSE SELECTOR,
VEE 44 VEE BALL 23 XRST
OUTPUT DECODER
TEO 45 TTL 22 DATA
ATSC
TOG1 – TOG4
BAL1 – BAL4

↓ 21 XLT
IIL 20 CLK
19 LOCK
TZC

FZC

E-F BALANCE
LPFI 46 WINDOW
TG1 – TG2

PS1 – PS4
FS1 – FS4
DFCTO

IFB1 – IFB6
BAL1 – BAL4
TOG1 – TOG4

TM1 – TM7

COMPARATOR VCC 18 VCC

TEI 47 VCC
ATSC
ATSC 48 WINDOW ISET 17 ISET
COMPARATOR TM6

TZC 16 SL O
TZC 49
COMPARATOR

TM1 15 SL M

DFCT TRACKING PHASE

–
COMPENSATION
TDFCT 50 14 SL P
TG1
+
TM5
VCC
TM2

CENTER VEE
VCC
VC 51 VOLTAGE
GENERATOR TM7
FZC
FZC 52 VCC TM4
COMPARATOR
VEE

FOCUS PHASE FS1

CHARGE UP
COMPENSATION
–
+

FS4 FS2
DFCT
FSET

TG2 TM3

VEE VEE
1 2 3 4 5 6 7 8 9 10 11 12 13
FSET
FEO

TA O
SRCH
FLB
FE O
FDFCT

TA M
TGU

TG2
FE M
FEI

FGD

31
IC702 CXD2589Q

PCMDI
EMPHI
PCMD
EMPH

SYSM
WFCK

LECKI
V16M
VPCO

XUGF

C2PO
XTSL

VCTL

LECK
VCKI

BCKI
BCK
GFS
51 25 26 27 28 47 49 54 56 50 39 41 43 55 40 42 44 62

24 TES1
23 TEST

79 XRST
C4M 52 Clock OSC
Error
Generator Corrector 3 RMUT
EFM 2 LMUT
demoduretor D/A Serial In
RF 35 Interface Interface

ASYI 37 70 XTAI
Asymmetry Timing
ASYO 38 Corrector 71 XTAO
16K Logic
BIAS 36
RAM Over Sampling
Digital Filter

XPCK 48
FILO 30
FILI 31 Digital Digital 3rd Order
PLL Sub Code OUT Noise Shaper
PCO 29
Processor
CLTV 33

PWM PWM

FOK 18 Servko
CPU Digital
SEIN 10 Auto
Interface CLV
CNIN 11 Sequencer

12 13 14 6 7 8 9 15 16 17 57 58 59 5 4 21 22 53 74 75 76 67 66 65
DATO
XLTO
CLKO

SENS
DATA
XTAL
CLOK
SPOA
SPOB
XLON
SCOR
SBSO
EXCK
SQSO
SQCK

MDP

PWMI

DOUT

LOUT2

AIN2
AOUT2

LOUT1

AIN1

AOUT1

IC703 BA5936S
MUTE IN

BIAS IN
OUT6–

OUT6+

OUT5+

OUT5–

OUT4+

OUT4–
IN6-R
IN6-F
GND

GND

GND

VCC

IN 4

IN 5

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
BIAS

D D VCC 100 D D D D
BIAS
MUTE
BIAS

100

LEVEL SHIFT 13.3K LEVEL SHIFT

LEVEL SHIFT

T.S.D

LEVEL SHIFT

LEVEL SHIFT 13.3K LEVEL SHIFT

10K
13.3K

100
BIAS

DETECTION
DF REG-OUT
CURRENT 10K
D D D D 100 VCC VCC D D
BIAS

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
OUT1–

OUT1+

OUT2–

OUT2+

IN2

IN1

VCC

VCC

REG-I

REG-B

REG OUT

IN3-R

IN3-F

OUT3+

OUT3–

GND

32
— MAIN BOARD —

IC103 LC72131

AOUT
XOUT

AMIN
FMIN
VDD
VSS

IFIN
AIN

IO2
PD
20 19 18 17 16 15 14 13 12 11

PHASE
DETECTOR
CHARGE PUMP

POWER
REFERENCE UNLOCK ON 1/2
DIVIDER DETECTOR RESET

SWALLOW COUNTER
1/16, 1/17 4BITS

12BITS
PROGRAMMABLE
DRIVER

CCB UNIVERSAL
DATA SHIFT REGISTER LATCH
INTERFACE COUNTER

1 2 3 4 5 6 7 8 9 10
XIN
CE

BO4
CL
DO

BO2
BO1
DI

BO3

IO1

IC201 TA8189N

METAL PRE TAPE A REC REC

CH2/A CH2/B NF OUT OUT /TAPE B VCC CG OUT NF IN ALC

24 23 22 21 20 19 18 17 16 15 14 13

CH2 –
– +
CH2
+

A/B

ALC
VREF1 IREF
VREF2

M/N

CH1 CH1
+ +
– –

GND GND
1 2 3 4 5 6 7 8 9 10 11 12
CH1/A CH1/B NF METAL PRE MIX GND1 M/H REC NF REC GND
OUT OUT OUT OUT IN

33
IC252 74HC165

PARALLEL INPUTS
CLOCK SERIAL OUTPUT
VCC INHIBIT D C B A INPUT QH
16 15 14 13 12 11 10 9

CLOCK D C B A SERIAL
INHIBIT IN

SHIFT/
QH
LOAD

CK E F G H QH

1 2 3 4 5 6 7 8
SHIFT/ CLOCK E F G H OUTPUT GND
LOAD QH
PARALLEL INPUTS

IC301 M62439SP

REC OUT2 INA2 INB2 INC2 IND2 TONEH2 TONEL2 OUT2 Vss CONT
20 19 18 17 16 15 14 13 12 11

CONTROL
LOGIC
VOLUME CONTROL
MONAURAL SW
REC OUT SW

INPUT SW

MUTE

Low boost
High boost

1 2 3 4 5 6 7 8 9 10
REC OUT1 INA1 INB1 INC1 IND1 TONEH1 TONEL1 OUT1 GND VDD

— FRONT BOARD —

IC602 BU2092
VDD

Q11
Q10
OE

Q9
Q8
Q7
Q6
Q5

18 17 16 15 14 13 12 11 10

12 BIT
CONTROL
SHIFT
CIRCUIT
REGISTER
OUTPUT
12 BIT BUFFER
STORAGE (OPEN DRAIN)
REGISTER

1 2 3 4 5 6 7 8 9
VSS
DATA

CLOCK

LCK

Q0
Q1
Q2
Q3
Q4

34