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    Bit Com Case

    Uploaded by

    Vishnu Priya
    bit

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as TXT, PDF, TXT or read online from Scribd

    Bit Com Case

    Uploaded by

    Vishnu Priya
    6 views1 page
    bit

    Copyright

    © Attribution Non-Commercial (BY-NC)

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    TXT, PDF, TXT or read online from Scribd

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    bit

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as TXT, PDF, TXT or read online from Scribd
    Download as txt, pdf, or txt
    6 views1 page

    Bit Com Case

    Uploaded by

    Vishnu Priya
    bit

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as TXT, PDF, TXT or read online from Scribd
    Download as txt, pdf, or txt
    You are on page 1of 1

    library ieee;

    use ieee.std_logic_1164.all;
    entity bitcomcase is
    port(a,b:in std_logic;
    c,d,e:out std_logic);
    end bitcomcase;
    architecture ar of bitcomcase is
    signal s:std_logic_vector(1 downto 0);
    begin
    s<=a&b;
    process(s)
    begin
    case s is
    when "00" =>
    c<='0';
    d<='1';
    e<='0';
    when "01" =>
    c<='1';
    d<='0';
    e<='0';
    when "10" =>
    c<='0';
    d<='0';
    e<='1';
    when "11" =>
    c<='0';
    d<='1';
    e<='0';
    when others =>
    c<='Z';
    d<='Z';
    e<='Z';
    end case;
    end process;
    end;

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