Apple Macbook Pro A1297 Cannaregio k20 Dvt1 051-7656 Rev31

8
1
CK
APPD
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
REV
SCHEM,CANNAREGIO,K20,DVT1
ZONE
ECN
ENG
APPD
DESCRIPTION OF CHANGE
DATE
31
657084
ENGINEERING RELEASED
DATE
12/12/08 ?
12/12/08
(.csa)
Date
Page
Contents
TABLE_TABLEOFCONTENTS_HEAD
TABLE_TABLEOFCONTENTS_ITEM
Sync
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
Table of Contents
K20_MLB
System Block Diagram
M98_MLB
2
3
Power Block Diagram
RXU_K20
Revision History
NA
4
5
BOM Configuration
(.csa)
04/01/2008
04/01/2008
07/24/2008
NA
04/01/2008
07/11/2008
09/24/2008
05/07/2008
09/24/2008
04/01/2008
04/01/2008
04/01/2008
04/01/2008
06/06/2008
06/06/2008
06/06/2008
K20_MLB
JTAG Scan Chain
BEN_K20
Functional / ICT Test
K20_MLB
Power Aliases
RXU_K20
Signal Aliases
K20_MLB
9
10
CPU FSB
M98_MLB
11
CPU Power & Ground
M98_MLB
12
CPU Decoupling & VID
M98_MLB
13
eXtended Debug Port(MiniXDP)
M98_MLB
14
MCP CPU Interface
T18_MLB
15
MCP Memory Interface
T18_MLB
MCP Memory Misc
T18_MLB
16
17
MCP PCIe Interfaces
06/06/2008
06/06/2008
06/06/2008
06/06/2008
06/06/2008
06/06/2008
04/01/2008
T18_MLB
18
MCP Ethernet & Graphics
T18_MLB
19
MCP PCI & LPC
T18_MLB
20
MCP SATA & USB
T18_MLB
21
MCP HDA & MISC
T18_MLB
22
MCP Power & Ground
T18_MLB
MCP Standard Decoupling
M98_MLB
25
26
MCP Graphics Support
04/01/2008
05/01/2008
10/15/2008
06/10/2008
07/14/2008
04/01/2008
05/01/2008
M98_MLB
28
SB Misc
M98_MLB
29
FSB/DDR3/FRAMEBUF Vref Margining
BEN_K20
31
DDR3 SO-DIMM Connector A
BEN_K20
32
DDR3 SO-DIMM Connector B
BEN_K20
33
DDR3 Support
M98_MLB
Right Clutch Connector
M98_MLB
34
35
ExpressCard Connector
10/15/2008
07/22/2008
07/15/2008
07/15/2008
04/01/2008
05/28/2008
07/14/2008
05/01/2008
07/14/2008
07/18/2008
06/06/2008
05/01/2008
BEN_K20
37
Ethernet PHY (RTL8211CL)
SUMA_K20
38
Ethernet & AirPort Support
SUMA_K20
39
Ethernet Connector
SUMA_K20
41
FireWire LLC/PHY (FW643)
M98_MLB
42
FireWire Port Power
YWU_K20
FireWire Ports
M98_MLB
43
45
SATA Connectors
M98_MLB
46
External USB Connectors
M98_MLB
48
Front Flex Support
CHANG_K20
49
SMC
T18_MLB
SMC Support
M98_MLB
50
51
LPC+SPI Debug Connector
05/28/2008
07/22/2008
08/20/2008
CHANG_K20
52
K20 SMBUS CONNECTIONS
BEN_K20
53
Current & Voltage Sensing
YWU_K20
Date
Page
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
Contents
(.csa)
Sync
54
Current Sensing
YWU_K20
Thermal Sensors
YWU_K20
55
56
Fan Connectors
M98_MLB
WELLSPRING 1
YMA_K20
57
58
WELLSPRING 2
08/12/2008
05/28/2008
04/01/2008
05/19/2008
09/24/2008
06/17/2008
05/01/2008
09/29/2008
09/29/2008
K20_MLB
59
Sudden Motion Sensor (SMS)
YWU_K20
61
SPI ROM
M98_MLB
62
AUDIO:CODEC
AUDIO_K20
AUDIO: LINE IN
AUDIO_K20
AUDIO: HEADPHONE AMP
AUDIO_K20
AUDIO:SPEAKER AMP
AUDIO_K20
AUDIO: JACKS
AUDIO_K20
AUDIO: JACK TRANSLATORS
AUDIO_K20
DC-In & Battery Connectors
RXU_K20
63
65
91
92
93
94
95
96
97
98
Date
Page
Contents
Sync
103
04/01/2008
MCP Constraints 2
M98_MLB
Ethernet Constraints
M98_MLB
FireWire Constraints
M98_MLB
SMC Constraints
M98_MLB
GPU (G96) Constraints
M98_MLB
Project Specific Constraints
M98_MLB
PCB Rule Definitions
M98_MLB
104
04/01/2008
105
04/01/2008
106
04/01/2008
107
05/01/2008
108
04/01/2008
109
04/01/2008
123
N/A
PROJECT SPECIFIC CONNS
N/A
09/29/2008
66
09/29/2008
67
09/29/2008
68
09/29/2008
69
05/21/2008
70
05/21/2008
PBus Supply & Battery Charger
RXU_K20
IMVP6 CPU VCore Regulator
RXU_K20
5V / 3.3V Power Supply
RXU_K20
1.5V DDR3 Supply
RXU_K20
5V_S0 / MCP CORE REGULATOR
RXU_K20
CPU VTT Power Supply
RXU_K20
Misc Power Supplies
RXU_K20
71
05/21/2008
72
05/21/2008
73
05/21/2008
75
05/21/2008
76
05/21/2008
77
05/21/2008
78
09/09/2008
Power Control
YMA_K20
Power FETs
YMA_K20
NV G96 PCI-E
M98_MLB
NV G96 CORE/FB POWER
M98_MLB
NV G96 FRAME BUFFER I/F
K20_MLB
GDDR3 Frame Buffer A (Bottom)
M98_MLB
GDDR3 Frame Buffer B (Bottom)
M98_MLB
NV G96 GPIO/MIO/MISC
K20_MLB
G96 GPIOs & Straps
M98_MLB
NV G96 Video Interfaces
K20_MLB
GPU (G96) CORE SUPPLY
RXU_K20
LVDS Display Connector
M98_MLB
GDDR3 Frame Buffer A (Top)
M99_MLB
GDDR3 Frame Buffer B (Top)
M88_MLB
79
05/19/2008
80
04/01/2008
81
04/01/2008
82
09/24/2008
84
04/01/2008
85
04/01/2008
86
09/24/2008
87
05/12/2008
88
09/24/2008
89
05/21/2008
90
07/14/2008
91
04/04/2008
92
11/01/2007
93
05/01/2008
Muxed Graphics Support
M98_MLB
DisplayPort Connector
K20_MLB
1.1V / 1V8 FB Power Supply
RXU_K20
Graphics MUX (GMUX)
T18_MXMGMUX
LCD BACKLIGHT DRIVER
KIRAN_K20
94
09/24/2008
95
05/21/2008
96
02/13/2008
97
12/03/2008
98
07/18/2008
LCD Backlight Support
YLEE_K20
Misc Power Supplies
RXU_K20
CPU/FSB Constraints
M98_MLB
Memory Constraints
M98_MLB
MCP Constraints 1
M98_MLB
99
05/07/2008
100
04/01/2008
101
04/01/2008
102
04/01/2008
DIMENSIONS ARE IN MILLIMETERS
APPLE INC.
METRIC
XX
X.XX
DRAFTER
Schematic / PCB #s
PART NUMBER
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
ENG APPD
MFG APPD
QA APPD
DESIGNER
RELEASE
SCALE
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
ANGLES
QTY
DESCRIPTION
REFERENCE DES
051-7656
SCHEM,CANNAREGIO,K20
SCH
CRITICAL
CRITICAL
820-2390
PCBF,CANNAREGIO,K20
PCB
CRITICAL
NOTICE OF PROPRIETARY PROPERTY
DESIGN CK
X.XXX
BOM OPTION
TITLE
DO NOT SCALE DRAWING
SCHEM,CANNAREGIO,K20
NONE
DRAWING
SIZE
TITLE=MLB
ABBREV=DRAWING
THIRD ANGLE PROJECTION
LAST_MODIFIED=Fri Dec 12 16:50:42 2008
MATERIAL/FINISH
NOTED AS
APPLICABLE
DRAWING NUMBER
REV.
051-7656
31
SHT
OF
123
U1000
U1300
INTEL CPU
XDP CONN
2.X OR 3.X GHZ
PG 12
PENRYN
PG 9
FSB
J6950
64-Bit
800/1067/1333 MHz
DC/BATT
POWER SUPPLY
PG 13
PG 60
J2900
2 UDIMMs
MAIN
FSB INTERFACE
GPIOs
DDR2-800MHZ
DDR3-1067/1333MHZ
MEMORY
DIMM
PG 14
U4900
PG 25,26
TEMP SENSOR
PG 41
Misc
CLK
PG 24
U6100
SYNTH
POWER SENSE
PG 45
SPI
Boot ROM
J4510
J5650,5600,5610,5611,5660,5720,5730,5750
FAN CONN AND CONTROL
SPI
SATA
PG 52
Conn
1.05V/3GHZ.
PG 48,49
PG 20
PG 38
HD
NVIDIA
J4520
J4900
B,0
SATA
Conn
Fan
Ser
Prt
SMC
LPC Conn
LPC
PG 19
PG 38
ADC
BSB
J5100
MCP79
SATA
1.05V/3GHZ.
ODD
Port80,serial
PG 41
PG 43
PG 18
U1400
J9000
PWR
LVDS
CONN
CTRL
LVDS OUT
PG 71
RGB OUT
J4700
J4720
DP OUT
IR
J3900,4635,4655
CAMERA
HDMI OUT
EXTERNAL
USB
Connectors
PG 40
PG 40
PG 40
PG 40
8
7
6
5
4
USB
PG 16
PCI-E
UP TO 20 LANES3
PG 17
PG 19
TMDS OUT
PG 39
DVI OUT
PG 71
J4710
J4710
TRACKPAD/
KEYBOARD
DISPLAY PORT
CONN
Bluetooth
(UP TO 12 DEVICES)
J9400
B
SMB
SMB
PG 20
CONN
RGMII
HDA
PCI
PG 44
DIMMs
(UP TO FOUR PORTS)

PG 17
PG 18
PG 20
U6200
Audio
Codec
PG 53
U6301
U6400
U6500
System Block Diagram
U6600,6605,6610,6620
U3700
GB
Line In
Line Out
Speaker
E-NET
Amp
Amp
Amp
Amps
PG 54
PG 55
PG 56
PG 57
HEADPHONE
SYNC_MASTER=M98_MLB
SYNC_DATE=04/01/2008
88E1116
PG 31

J3400
U3900
Mini PCI-E
J6800,6801,6802,6803
E-NET
AirPort
Conn
PG 28
Audio
SIZE
Conns
PG 33
PG 59
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7656
31
OF
2
123
7
K20 POWER SYSTEM ARCHITECTURE
PPDCIN_G3H
SMC PWRGD
D6905
R6905
SMC_RESET_L
NCP303LSN
U5000
(PAGE 42)
ENABLE
PPVIN_G3H_P3V42G3H
MIC5232-2.8YD5
3.425V G3HOT
D6905
PP3V42_G3H
LT3470A
PPBUS_G3H_VSENSE
U2801
VIN
PP3V3_G3_RTC
VOUT
U6990
J6900
F7040
SMC_TPAD_RST_L
D
SMC_ONOFF_L
R7020
DCIN(16.5V)
ADAPTER
PPVBAT_G3H_CHGR_REG
VIN
VOUT
F7041
ISL6258A
SMC_DCIN_ISENSE
8A FUSE
R7050
U5303
PPCPUVTT_S0
SMC_CPU_FSB_ISENSE
SC417
U7600
CPUVTTS0_PGOOD
PGOOD
(PAGE 65)
GPUVCORE_PGOOD
(PAGE 77)
CPU VCORE
SMC_CPU_HI_ISENSE
VOUT
R7505
MCP_CORE
MCPCORES0_EN
EN2
MCP79
PWRBTN#
IMVP_VR_ON
SMC_CPU_ISENSE
U7100
VR_PWRGOOD_DELAY
PGOOD
PWRGD_SB
(PAGE 61)
MCP_PS_PWRGD
SMC_MCP_CORE_ISENSE
PM_SLP_S3_L_R
5V
FSB_CPURST_L
PS_PWRGD
VOUT1
EN1
PM_SYSRST_DEBOUNCE_L
RSTBTN#
VR_ON
PPVCORE_S0_MCP
VOUT2
SMC_MCP_VSENSE
PPVCORE_S0_CPU
VIN
ISL9504B
CHGR_BGATE
SMC_CPU_VSENSE
U7100
R5388
PPVBAT_G3H_CHGR_R
(6 TO 8.4V)
1.05V
SMC_GPU_ISENSE
GPUVCORE_EN
Q7055
BATT_POS_GATE
VOUT
PGOOD
SMC_BATT_ISENSE
Q7056
EN_PSV
U8900
VR_ON
(PAGE 60)
PPVBATT_G3H_CONN
R7650
CPUVTTS0_EN
GPU VCORE
ISL6263C
U5001
VIN
PPVCORE_GPU
U5410
PBUS SUPPLY/
BATTERY CHARGER
J6950
VOUT
SMC_GPU_VSENSE
U7000
VIN
IN
2S4P
(PAGE 25)
PPBUS_G3H
F6905
6A FUSE
AC
(PAGE 59)
Q5315
CPU_RESET#
PP5V_S0
GMUX
VIN
PB16B
PB17A
U9600
PB17B
XP28
PB18A
EG_RAIL1_EN
P5V_RTS0_PGOOD
U1400
POK2
(PAGE 64)
R5445
MCPCORES0_PGOOD
EG_RAIL2_EN
P3V3GPU_EN
EG_RAIL3_EN
GPUVCORE_EN
EG_RAIL4_EN
P1V8_S0GPU_EN
S5
VOUT1
MEM_VTT_EN
R5413
1.103V(L/H)
P1V8_S0GPU_EN
VOUT2
EN2
RC
P3V3S5_EN
1.8V(R/H)
S3
RC
0.75V
VOUT2
PP0V9R0V75_S0_DDRVTT
CPU
TPS51116
U7300
SMC_GPU_1V8_ISENSE
U9500
PM_G2_P1V05S5_EN
P1V2_S0_EN
PP1V2_S0
RUN1
PM_ALL_GPU_PGOOD
POK2
(PAGE 83)
DELAY
RESET*
VIN
P1V1GPU_PGOOD
POK1
PWRGOOD
U1000
(PAGE 63)
ISL6236
SMC_PM_G2_EN
PP1V8R1V5_S0
MCPDDR_EN
PP1V8_S0GPU_ISNS
DELAY
U4900
P60
PP1V8R1V5_S3
VOUT1
PP1V1_S0GPU
VIN
EN1
SMC
PPMCPDDR_ISNS
VLDOIN
1.5V
DDRREG_EN
P1V1_GPU_EN
(PAGE 14~22)
SMC_MCP_DDR_ISENSE
PM_ALL_GPU_PGOOD
PL32A
U2850
Q7901
VIN
(PAGE 84)
POK1
U7500
P1V1GPU_EN
CPU_PWRGD
CPU_PWRGD
ISL6236
(PAGE 42)
VOUT1
LTC3547
U9900
P2V5S0_EN
(PAGE 10,11)
RUN2
VOUT2
PP2V5_S0
(PAGE 87)
VIN
EN1
5V
VOUT1
PP5V_S3
PM_ALL_GPU_PGOOD
(L/H)
PP3V3_S5
PM_SLP_RMGT_L
P3V3S5_EN
SLP_RMGT#(J17)
3.3V
EN2
PP3V3_S5
VOUT2
U7880
VIN
(R/H)
PP1V0_FW
R2870
RC
RUN1
TPS51220
U7201
MEM_VTT_EN
PP3V3_S3
VOUT1
LTC3547
(PAGE 62)
PGOOD1,2
DELAY
IMVP_VR_ON
IMVP_VR_ON(P16)
U7700
P1V8S0_EN
RUN2
RSMRST_PWRGD
PP1V8_S0
VOUT2
RSMRST_IN(P13)
PM_SYSRST_L
SYSRST(PA2)
SMC_ONOFF_L
PWR_BUTTON(P90)
PM_SLP_S4_L
PM_PWRBTN_L
P5V3V3_PGOOD
P17(BTN_OUT)
Q7930
P5VS3_EN
U9701
BKLT_PLT_RST_L
&&
LCD_BKLT_EN
ENA
VOUT
SMC_RESET_L
P5V3V3_PGOOD
P5V_RTS0_PGOOD
PP3V3_S0
PPVOUT_S0_LCDBKLT
(PAGE 85~86)
PM_SLP_S4_L
99ms DLY
PWRGD(P12)
(PAGE 66)
U1400
PM_RSMRST_L
RSMRST_OUT(P15)
ALL_SYS_PWRGD
P1V0FW_EN
DDRREG_EN
VIN
APP001
SMC
R0940
Q7910
PCI_RESET0#(R10)
R7894
PP3V3_S5
P5VS3_EN
MCP79
RES*
MCPCORES0_PGOOD
PM_SLP_S4_L
SLP_S5#(H17)
SLP_S5_L(P95)
PM_SLP_S3_L
Q4260
CPUVTTS0_PGOOD
Q7970
PM_SLP_S3_L
SLP_S3#(G17)
LTC1872
VIN
(PAGE 14~22)
U7790
PM_SLP_S4_L
SLP_S4_L(P94)
PP10V_FW
S0PGOOD_PWROK
PM_SLP_S3_L
PP3V3_S0GPU
SLP_S3_L(P93)
VOUT
VI
(PAGE 66)
TPS62202
P1V8_S0GPU_EN
P3V3GPU_EN
FW_PORTPWR_EN&&(SMC_ADAPTER_EN||PM_SLP_S3_L)
EN
Q3810
PP1V8_GPUIFPX
U7760
U4900
(PAGE 42)
PP3V3_S0
VOUT
(PAGE 66)
VCC
P3V3_ENET_PHY
R7878
PP1V8R1V5_S0
ADJ1
LTC2909
PM_SLP_S3_L_R
VIN
PM_SLP_RMGT_L
RC
RC
PM_G2_P1V05S5_EN
P1V8S0_EN
RC
MCPDDR_EN
(PAGE 67)
PGOOD
Q7953
P1V05_S5_PGOOD
PP1V05_S0
VDD
RSMRST_PWRGD
U7840
P1V05S0_EN
P2V5S0_EN
RESET*
PP3V3_S5
SENSE
MCPCORES0_EN

P1V2_S0_EN
Q3840
RC
RC
U7750
TRST = 200mS
PP3V42_G3H
DELAY
DELAY
ISL6269
EN
P1V05S0_EN
(PAGE 66)
RC
CPUVTTS0_EN
SYNC_MASTER=RXU_K20
DELAY
DELAY
RC
Power Block Diagram
PP1V2R1V05_S5
VOUT
DELAY
RST*
PP1V05_S0
ADJ2
1.05V AUX
U7870
TPS3808G
PP1V2R1V05_ENET
MR*
SIZE
(PAGE 67)
DELAY
DELAY
S5 PWRGD
APPLE INC.
P1V05_S5_PGOOD
PM_SLP_RMGT_L
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7656
31
OF
3
123
Proto:
See earlier schematics for info about proto changes
Pre-EVT:
See earlier schematics for info about Pre-EVT changes
EVT:
10/29/08
csa. 5 Added BKLT_PLL_NOT BOM option K20_COMMON2 BOM group. This stuffs R9713.
csa. 68 Changed net name on input to U6860 from PP3V3_S0_AUDIO to =PP3V3_S0_AUDIO.
See <rdar://problem/6327731> K20 PreEVT: iPhone headset detection test fail
csa. 97 Changed R9707 to 2.87K per <rdar://problem/6327135> Change R9707 to 2.87k, 1% resistor
10/29/08
csa. 9 Changed SH0924 to 870-1698 tall emi pogo pin.
11/5/08
csa. 4 Updated Revision History.
csa. 8 Tied =PP3V3_FW_FWPHY and =PP3V3_FW_P1V0FW aliases to PP3V3_S0.
csa. 9 Removed R0942 and R0943 which were for selecting from S0 or S3 for =PP3V3_FW_FWPHY.
Removed R0940 and R0941 which were for selecting from S0 or S3 for =PP3V3_FW_P1V0FW.
Tied =PP3V3_S3_GMUX alias to PP3V3_S3.
csa. 75 Changed U7500 from 353S2312 Intersil ISL6236 to 353S2203 TI SN0802043.
Changed TONSEL from GND to PP5V_S0_MCPREG_VCC.
This changes output frequencies to 200/300KHz for 5V/MCPCore.
Added C7562 330uF cap on =PPMCPCORE_S0_REG.

Changed snubber resistors R7598 and R7599 to 1/6W 0402, APN 114S0548.
csa. 87 Changed pulldown values to 10K on GPIO7_FBVDDQ_ALTVO, R8794.
Changed pulldowns R8792 and R8793 from 1K to 4.7K for power consumption.
csa. 90 Removed R9094. Replaced by R9678 on csa. 96 to tie to GMUX_S3_PD_GND.
csa. 96
Added Q9607 dual FET for disabling GMUX power sequence enable configuration pulldowns during S0.
Moved R9094 to R9678 and tied to GMUX_S3_PD_GND.

csa. 97 Changed R9707 to 2.67K 1%. This gives 22.5mA on LED current.
11/10/08
csa. 68 Changed R6885 from 0 ohms to 2.2K.
Changed C6885 from 470 pF to 0.0082 uF.
csa. 87 Changed R8792 and R8793 from 4.7K to 10K pulldowns on EG_LCD_PWR_EN and EG_BKLT_EN.
csa. 96 Changed R9678 pulldown on LCD_PWR_EN from 10K to 4.7K.
Removed BOM options on FET circuit for GMUX_S3_PD_GND.
Added R9684 NO STUFF 0 ohms to tie ALL_SYS_PWRGD to Q9607.
11/11/08
csa. 8 removed =PP3V3_S3_P1V0FW and =PP3V3_S3_BKL_VDDIO
csa. 41 changed R4160 from 274K to 200K <rdar://6292976>
csa. 68 changed R6885 from 0 ohm to 2.2K for Mic LPF
csa. 75 NO STUFF R7598, C7598, R7599, C7599 (snubbers)
csa. 87 changed R8795 from 1K to 10K pull down
csa. 96 NO STUFF R9677, C9695, STUFF R9684
11/12/08
csa. 5 removed MCP79 B01 from Module Parts table and added B03
csa. 39 added Bom table for J3900 (514-0636)
csa. 46 added Bom table for J4600, J4610 (514-0638)
csa. 94 added Bom table for J9400 (514-0637)
csa. 123 added Bom table for JC320 (514-0638)
11/13/08
csa. 1 change title to DVT
csa. 32 Added alternate table for J3200 (516S0709, Molex DIMM connector)
11/19/08
csa. 5 changed MCP79 B03 to 338S0710; change to binned G96 338S0714;
added PROD_DIGSMS and TPDT_DEBOUNCE to BOM groups
csa. 68 added bom option TPDT_BYPASS to R6865; TPDT_DEBOUNCE to U6860,C6861,R6860,R6862
csa. 97 changed Q9701 to 376S0757 <radr://6383480>
11/25/08
csa. 5 changed BOM option MCP_B02 to MCP_B03; added BOM option GMUX_1V8
added Mag Layer alternate 155S0457 to Murata 155S0329
csa. 93 added BOM table for 16 LVDS termination resistors to select GMUX_2V5 or GMUX_1V8
added BOM option GMUX_2V5 to 8 parallel resistors so theyll be NO STUFFed for GMUX_1V8
csa. 97 reverted Q9701 to 376S0678 due to parts availability
csa. 99 added BOM table for R9900 to select either 2.5V output or 1.8V output
DVT:
12/02/08
Start of PVT.
csa. 5 removed JTAG_ALLDEV bom option to remove U0600, R0601, C0601, C0602
added 516-0213 (Molex TH SODIMM CONN) as alternate to 516-0201 (Foxconn)
added GMUX_JTAG_CONN bom option to the bom table
csa. 6 added GMUX_JTAG_CONN bom option to J0600
csa. 99 moved OMIT from R9900 to R9901 to select either 150K (GMUX_2V5) or 237K (GMUX_1V8)
12/03/08
csa. 32 removed redundant alternate table for J3200
csa. 97 Per radar 6383480, Change the FET Q9701 from APN: 376S0678 to 376S0757
diode D9701 from APN: 371S0551 to 371S0572
12/09/08
csa. 1 changed title to DVT(1)
csa. 26 NO STUFF C2690, R2690
csa. 32 Refreshed symbol for J3200 for update to BGA SODIMM conn.
csa. 54 changed R5498 to 4.02K for 1.4x gain and R5493 to 2.87K <rdar://6423810>
csa. 89 changed L8920 to 152S0955 (25A Isat); R8900 to 7.15K for 24.6A OCP <rdar://6423810>
12/12/08
csa. 1 changed title to DVT1
csa. 4 removed pre-EVT check in notes from Rev. History
csa. 99 changed text note to reflect 2.5V to 1.8V GMUX rail change
31
SYNC_MASTER=NA
SYNC_DATE=NA

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
4
123
BOM Variants
Alternate Parts
TABLE_BOMGROUP_HEAD
BOM NUMBER
BOM NAME
BOM OPTIONS
630-9728
PCBA,BEST,2.66,512SAM_VRAM,K20
K20_COMMON,EEE_4CM,CPU_2_66GHZ,FB_512_SAMSUNG
630-9727
PCBA,BEST,2.66,512QIM_VRAM,K20
K20_COMMON,EEE_4CH,CPU_2_66GHZ,FB_512_QIMONDA
630-9730
PCBA,BEST,2.93,512SAM_VRAM,K20
K20_COMMON,EEE_4CQ,CPU_2_93GHZ,FB_512_SAMSUNG
TABLE_ALT_HEAD
PART NUMBER
ALTERNATE FOR
PART NUMBER
152S0476
BOM OPTION
REF DES
COMMENTS:
152S0276
ALL
Inductor alternate
353S1681
353S1294
ALL
TI alt to National
138S0603
138S0602
ALL
Murata alt to Samsung
152S0684
152S0368
ALL
Maglayers alt to Dale/Vishay
104S0023
104S0018
ALL
Cyntec alt to sense resistor
104S0024
104S0017
ALL
Panasonic alt to FW resistor
341S2367
341S2366
ALL
Macronix alt to SST
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
630-9729
PCBA,BEST,2.93,512QIM_VRAM,K20
K20_COMMON,EEE_4CP,CPU_2_93GHZ,FB_512_QIMONDA
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
152S0876
152S0782
ALL
Maglayer alt to Delta
157S0058
157S0055
ALL
Delta alt to TDK Magnetics
514-0612
514-0607
ALL
FOXLINK ALT TO FOXCONN XCVR
514-0613
514-0608
ALL
FOXLINK ALT TO FOXCONN RCVR
152S0684
152S0421
ALL
MAG LAYERS ALT TO VISHAY
152S0896
152S0518
ALL
MAG LAYERS ALT TO CYNTEC
152S0915
152S0796
ALL
MAG LAYERS ALT TO CYNTEC
516S0709
516S0706
ALL
MOLEX ALT TO FOXCONN
155S0457
155S0329
ALL
MAG LAYERS ALT TO MURATA
516-0213
516-0201
ALL
MOLEX ALT TO FOXCONN
TABLE_ALT_ITEM
TABLE_ALT_ITEM
K20 BOM GROUPS
TABLE_ALT_ITEM
TABLE_BOMGROUP_HEAD
BOM GROUP
BOM OPTIONS
K20_COMMON
ALTERNATE,COMMON,K20_COMMON1,K20_COMMON2,K20_DEBUG,K20_PROGPARTS
K20_COMMON1
ONEWIRE_PU,ISL6258,MEMRESET_HW,MEMRESET_MCP,MCP_B03,MCP_PROD,MCPSEQ_SMC,BMON_ENG,MCP_CS1_NO,FW_LVG_NEW,PROD_DIGSMS,TPDT_DEBOUNCE
K20_COMMON2
BOOT_MODE_USER,GPUVID_1P00V,MUXGFX,DPMUX_EN_S0,DP_ESD,EG_PWRSEQ_GMUX,DP_CA_DET_EG_PLD,BKLT_PLL_NOT,GMUX_1V8
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
K20_DEBUG
SMC_DEBUG_YES,XDP,XDP_CONN,LPCPLUS,VREFMRGN,TPAD_DEBUG,GMUX_JTAG_CONN
K20_PROGPARTS
GMUX_PROG,BOOTROM_PROG,SMC_PROG,TPAD_PROG
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
TABLE_BOMGROUP_HEAD
BOM GROUP
BOM OPTIONS
FB_1024_SAMSUNG
VRAM8,VRAM_1024_SAMSUNG
FB_1024_QIMONDA
VRAM8,VRAM_1024_QIMONDA
FB_512_SAMSUNG
VRAM4,VRAM_512_SAMSUNG
FB_512_QIMONDA
VRAM4,VRAM_512_QIMONDA
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
C Bar Code Labels / EEE #s

PART NUMBER
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION
826-4393
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEE:4CH]
CRITICAL
EEE_4CH
826-4393
[EEE:4CM]
CRITICAL
EEE_4CM
826-4393
[EEE:4CP]
CRITICAL
EEE_4CP
826-4393
[EEE:4CQ]
CRITICAL
EEE_4CQ
Module Parts
PART NUMBER
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION
337S3645
IC,PDC,QXXX,QS,2.66,25W,1066,E0,6M,BGA
U1000
CRITICAL
CPU_2_66GHZ
337S3644
U1000
CRITICAL
CPU_2_86GHZ
338S0714
IC,ASSP,GPU,NV G96-GS,LOWLKG,BGA969,LF
U8000
CRITICAL
338S0694
IC,RTL8251CA-VB-GR,GIGE TRANSCEIVER,48P LQFP
U3700
CRITICAL
338S0654
IC,FW643-E,1394B PHY/OHCI LINK/PCI-E,12
U4100
CRITICAL
338S0710
IC,MCP79XT-B3,35X35MM,BGA1437
U1400
CRITICAL
MCP_B03
338S0563
IC,SMC,HS8/2117,9MMX9MM,TLP
U4900
CRITICAL
SMC_BLANK
341S2355
IC,SMC,DEVELOPMENT,K20
U4900
CRITICAL
SMC_PROG
335S0610
IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP
U6100
CRITICAL
BOOTROM_BLANK
341S2356
IC,EFI ROM,DEVELOPMENT,K20
U6100
CRITICAL
BOOTROM_PROG
341S2384
IR,ENCORE II, CY7C63833-LFXC
U4800
CRITICAL
338S0603
IC,GMCP,MCP79-A01Q,35x35MM,BGA1437
U1400
CRITICAL
341S2383
IC,PSOC +W/USB,56PIN,MLF,M98
U5701
CRITICAL
MCP_A01Q
TPAD_PROG
337S3643
U1000
CRITICAL
CPU_2_93GHZ
337S3640
IC,PDC,SL3BX,PRQ,2.53,35W,1066,C0,6M,BGA
U1000
CRITICAL
CPU_2_53GHZ
337S3641
IC,PDC,SLB43.PRQ,2.80,35W,1066,E0,6M,BGA
U1000
CRITICAL
CPU_2_80GHZ
338S0635
IC,GMCP,MCP79-B02,35x35MM,BGA1437
U1400
CRITICAL
MCP_B02
333S0481
IC,SGRAM,GDDR3,32MX32,800MHZ,136 FBGA
U8400,U8450,U8500,U8550
CRITICAL
VRAM_512_SAMSUNG
333S0472
IC,SGRAM,GDDR3,32Mx32,900MHZ,136 FBGA
U8400,U8450,U8500,U8550
CRITICAL
VRAM_512_QIMONDA
333S0481
IC,SGRAM,GDDR3,32MX32,800MHZ,136 FBGA
U8400,U8450,U8500,U8550,U9100,U9150,U9200,U9250
CRITICAL
VRAM_1024_SAMSUNG
333S0472
IC,SGRAM,GDDR3,32Mx32,900MHZ,136 FBGA
U8400,U8450,U8500,U8550,U9100,U9150,U9200,U9250
CRITICAL
VRAM_1024_QIMONDA
BOM Configuration
SYNC_MASTER=K20_MLB

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
5
123
1.05V TO 3.3V LEVEL TRANSLATOR (M98: ON ICT FIXTURE)
=PP3V3_S0_XDP
13 8 6
y
r
a
n
i
m
il
U1000
CPU
From XDP connector

JTAG_ALLDEV
1
JTAG_ALLDEV
C0601
C0602
0.1UF
0.1UF
20%
10V
CERM
402
20%
10V
CERM
402
To XDP connector
and/or level translator
=PP1V05_S0_CPU
61 13 12 11 10 8
88 13 10 6
IN
88 13 10
IN
88 13 10 6
IN
88 13 10 6
IN
XDP_TCK
XDP_TDI
XDP_TMS
XDP_TRST_L
XDP
R0603
88 10
XDP_TDO
PLACEMENT_NOTE=Place near pin U1000.AB3

XDP_TDO_CONN
5%
1/16W
MF-LF
402
JTAG_ALLDEV
R0601 1
JTAG_ALLDEV
11
10K
5%
1/16W
MF-LF
402
From XDP connector

or via level translator
VCCA VCCB
U0600
NLSV4T244
XDP_TCK
88 13 10 6
2
3
NOSTUFF
R0602
0
5%
1/16W
MF-LF
402
XDP_TMS
XDP_TRST_L
88 13 10 6
88 13 10 6
4
5
A1
A2
A3
A4
UQFN
B1
B2
B3
B4
10
MAKE_BASE=TRUE
9
8
7
MAKE_BASE=TRUE
1
2
JTAG_LVL_TRANS_EN_L
12
R0606
OE*
10K
GND
5%
1/16W
MF-LF
2 402
JTAG_MCP_TCK
JTAG_MCP_TDI
JTAG_MCP_TMS
JTAG_MCP_TRST_L
13
OUT
XDP connector
U1400
MCP
13 21
XDP
13 21
R0604
13 21
13 21
21
JTAG_MCP_TDO
PLACEMENT_NOTE=Place near pin U1400.F19

JTAG_MCP_TDO_CONN
5%
1/16W
MF-LF
402
13
OUT
XDP connector
MAKE_BASE=TRUE
NOSTUFF
VCC
U0601
GPU_JTAG_TCK
GPU_JTAG_TDI
GPU_JTAG_TMS
GPU_JTAG_TRST_L
74LVC1G07
GMUX CPLD Programming Port
NC
NC
SOT886
NC
NC
GND
CRITICAL
M-RT-SM
7
GMUX_JTAG_CONN
2
3
4
=PP3V3_S0_XDP
6 8 13
TDO
TDI
TMS
TCK
U8000
GPU
75 74 8
=PP3V3_GPU_VDD33
10K
PLACEMENT_NOTE=Place close to U8000

GPU_JTAG_TMS
6 74
5%
1/16W
MF-LF
402
74
74
6 74
74
74
GPU_JTAG_TDO
TP_GPU_JTAG_TDO
MAKE_BASE=TRUE
J0600
1909782
R0605
e
r
JTAG_GMUX_TCK
JTAG_GMUX_TDI
JTAG_GMUX_TMS
U9600
GMUX
84
9 84
9 84
84 9
JTAG_GMUX_TDO
JTAG Scan Chain

SYNC_MASTER=BEN_K20

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
6
123
7
USB PORTS
Functional Test Points

J5650 (LEFT FAN CONN)
FUNC_TEST
=PP5V_S0_FAN_LT
TRUE
3 TPs
per Fan
8 48
I1038
TRUE
I1039
TRUE
I1040
TRUE
TRUE
PP5V_S3_RTUSB_A_F
USB2_LT1_N
USB2_LT1_P
GND
I1103
I1102
39
I1104
39 96
I1105
39 96
I1107
I1106
FAN_LT_PWM
FAN_LT_TACH
TRUE
TRUE
48
I1108
48
J5660 (RIGHT FAN CONN)

FAN_RT_PWM
FAN_RT_TACH
GND
TRUE
TRUE
TRUE
I1042
TRUE
I1043
TRUE
I1044
TRUE
TRUE
48
PP5V_S3_RTUSB_B_F
USB_LT2_N
USB_LT2_P
GND
39
I1109
39 96
I1110
39 96
I1111
I1112
48
I1113
5 TPs
per Fan
J6780 (MIC CONN)
I1046
TRUE
I1047
TRUE
I1048
TRUE
TRUE
PP5V_S3_RTUSB_C_F
USB_LT3_N
USB_LT3_P
GND
I1114
98
I1115
96 98
I1117
96 98
I1116
I1118
I557
TRUE
I558
TRUE
I559
TRUE
BI_MIC_LO
BI_MIC_SHIELD
BI_MIC_HI
57 58
I1120
57 58
J6781 (LEFT SPEAKER)

TRUE
I985
TRUE
I987
I986
TRUE
I988
TRUE
SPKRAMP_L1_OUT_P
SPKRAMP_L1_OUT_N
SPKRAMP_L2_OUT_P
SPKRAMP_L2_OUT_N
I990
TRUE
I992
TRUE
I991
TRUE
I994
TRUE
I993
TRUE
I1296
TRUE
I995
TRUE
I996
TRUE
I997
TRUE
I998
TRUE
I1000
TRUE
TRUE
I1004
TRUE
I1003
TRUE
TRUE
I1007
TRUE
I1006
TRUE
TRUE
I1008
TRUE
I1010
TRUE
I1011
TRUE
I1012
TRUE
I1014
TRUE
I1013
TRUE
I1015
TRUE
I1002
I1009
TRUE
I1016
TRUE
I1017
TRUE
I1018
TRUE
I1019
TRUE
I1053
TRUE
I1052
TRUE
I1054
TRUE
I1056
TRUE
I1055
TRUE
I1058
TRUE
I1057
TRUE
56 57 96
56 57 96
56 57 96
SPKRAMP_LFE_OUT_P
SPKRAMP_LFE_OUT_N
SPKRAMP_R1_OUT_P
SPKRAMP_R1_OUT_N
SPKRAMP_R2_OUT_P
SPKRAMP_R2_OUT_N
I1059
TRUE
I1061
TRUE
I1060
TRUE
I1063
TRUE
I1062
TRUE
I1064
TRUE
I1066
TRUE
I1065
TRUE
56 57 96
56 57 96
56 57 96
56 57 96
TRUE
I1020
TRUE
I1022
TRUE
I1021
TRUE
TRUE
I1067
BKL_SYNC
PP3V3_SW_LCD
=PP3V3_S0_DDC_LCD
PPVOUT_S0_LCDBKLT
LVDS_DDC_CLK
LVDS_DDC_DATA
LVDS_CONN_A_DATA_P<0>
LVDS_CONN_A_DATA_N<0>
LVDS_CONN_A_CLK_F_P
LVDS_CONN_A_CLK_F_N
LVDS_CONN_B_DATA_P<0>
LVDS_CONN_B_DATA_N<0>
LVDS_CONN_B_CLK_F_P
LVDS_CONN_B_CLK_F_N
LED_RETURN_1
LED_RETURN_2
LED_RETURN_3
LED_RETURN_4
LED_RETURN_5
LED_RETURN_6
GND
I1068
TRUE
I1069
TRUE
78
I1071
TRUE
8 75 78
I1070
TRUE
I1072
TRUE
78 81
I1074
TRUE
78 81
I1073
TRUE
78 85
2 TP needed
78 81 95
I1075
I1076
TRUE
78 81 95
I1077
TRUE
78 81 95
I1079
TRUE
78 81 95
I1078
I1081
TRUE
78 95
I1080
TRUE
78 95
I1082
TRUE
I1025
TRUE
I1028
TRUE
I1027
TRUE
I1029
TRUE
TRUE
PP5V_SW_ODD
SMC_ODD_DETECT
SATA_ODD_D2R_C_P
SATA_ODD_D2R_C_N
SATA_ODD_R2D_P
SATA_ODD_R2D_N
GND
78 81 95
I1083
TRUE
I1084
TRUE
78 81 95
78 81 95
I1085
78 81 95
I1086
78 81 95
I1087
78 95
I1273
78 95
I1089
78 85
I1088
78 85
I1090
78 85
I1091
78 85
I1098
78 85
I1097
78 85
I1095
I1096
I1094
I1099
38
I1100
38 41
I1101
38 90
38 90
I1131
38 90
I1132
TRUE
I1031
TRUE
I1033
TRUE
I1035
TRUE
I1034
TRUE
PP5V_S0_HDD_FLT
SATA_HDD_R2D_P
SATA_HDD_R2D_N
SATA_HDD_D2R_C_N
SATA_HDD_D2R_C_P
TRUE
GND
I1121
I1123
30 90
I1124
30 96
I1125
30 96
I1127
30
I1126
7 17 30 31
I1128
30
I1129
30
I1130
7 44 94
I1148
I1150
TRUE
I1149
TRUE
30 96
30 96
I1151
TRUE
I1152
TRUE
30 96
38
I1134
38 90
I1136
38 90
I1135
38 90
I1137
38 90
TRUE
J5815 (KBD BACKLIGHT CONN)

KBDLED_ANODE
TRUE
SMC_KDBLED_PRESENT_L
TRUE
50
I1140
50
I1142
GND
TRUE
I1141
I1143
LPC_AD<0..3>
19 41 43 84 91
I723
TRUE
SPI_ALT_MOSI
43
49
I725
TRUE
49
I726
TRUE
49
I727
TRUE
SPI_ALT_MISO
LPC_FRAME_L
PM_CLKRUN_L
I1154
TRUE
I1155
TRUE
49
I729
TRUE
41 42 43
TRUE
SMC_TMS
DEBUG_RESET_L
I728
49
I730
TRUE
SMC_TDO
41 42 43
49
I732
TRUE
SMC_TRST_L
41 43
I731
TRUE
49 50
49 50
TRUE
TRUE
SMC_MD1
41 43
TRUE
49
I734
TRUE
SMC_TX_L
39 41 42 43
I733
TRUE
SPIROM_USE_MLB
43
TRUE
TRUE
49
I735
TRUE
SPI_ALT_CLK
43
49
I736
TRUE
SPI_ALT_CS_L
43
TRUE
TRUE
49
I737
TRUE
LPC_SERIRQ
19 41 43
49
I739
TRUE
LPC_PWRDWN_L
19 41 43
49
I738
TRUE
41 42 43
49
I740
TRUE
SMC_TDI
SMC_TCK
49
I741
TRUE
49
I742
TRUE
49
I743
TRUE
TRUE
TRUE
LPCPLUS_GPIO
I751
TRUE
I752
TRUE
TRUE
ISSP_SCLK_P1_1
ISSP_SDATA_P1_0
SMC_ONOFF_L
I756
TRUE
PM_SYSRST_L
49
I1286
TRUE
BKL_FB
I1290
TRUE
BKL_GD
I1291
TRUE
BKL_SW
I1292
TRUE
BKLT_EN
I1293
TRUE
BKL_SCL
I1294
TRUE
BKL_SDA
I1288
TRUE
LCD_BKLT_PWM
40
40
49 50
49 50
49 50
49 50
49 50
TRUE
GND
TRUE
I1274
TRUE
I1275
TRUE
I1276
TRUE
49
10 14 88
10 14 88
10 14 88
10 14 88
10 14 88
FB_A_DQ<63..0>
FB_B_DQ<63..0>
FB_B_BA<1>
FB_B_CAS_L
FB_B_CS0_L
FB_B_MA<11>
TRUE
10 14 88
NO_TEST
I1297
10 14 88
TRUE
I762
10 14 88
TRUE
TRUE
I764
TRUE
I765
71 72 79 95
TRUE
I767
71 73 80 95
TRUE
I766
71 73 80 95
TRUE
I769
71 73 80 95
TRUE
I768
71 73 95
TRUE
I770
71 73 80 95
I774
LVDS NO_TESTs
NO_TEST
85
84 85
I1281
TRUE
I1280
TRUE
I1282
TRUE
I1283
TRUE
I1284
TRUE
I1285
TRUE
40 42
LVDS_A_DATA_N<0>
LVDS_A_DATA_P<0>
LVDS_B_CLK_P
LVDS_B_DATA_N<0>
LVDS_B_DATA_P<0>
LVDS_EG_A_DATA_N<2>
81 84 95
10
81 84 95
18
81 84 95
18
81 84 95
35
81 84 95
35
76 84 95
GND
16
15
47 96
15
47 96
16
NC NO_TESTs
I640
TRUE
I602
TRUE
I603
TRUE
I604
TRUE
I605
TRUE
I607
TRUE
I606
TRUE
PM_SLP_S3_L
21 33 36 41 67 82 84
PPBUS_G3H
PPBUS_CPU_IMVP_ISNS
PP3V42_G3H
PP5V_S3
PP5V_S0
PPVCORE_S0_CPU
I608
TRUE
PPVCORE_S0_MCP
I610
TRUE
I612
TRUE
I611
TRUE
PP3V3_S5
PP3V3_S3
PP3V3_S0
I613
TRUE
19
8 45
19
7 8 42
19
19
19
19
7 8
19
8 96
19
7 8
19
8 9 96
19
I600
TRUE
I625
TRUE
PP1V8_S0
19
19
PP1V8R1V5_S3
I623
TRUE
PP1V8R1V5_S0
I622
TRUE
PPMCPDDR_ISNS
7 8
TRUE
PP1V05_S0
I621
TRUE
PP1V2R1V05_S5
I618
TRUE
PPCPUVTT_S0
I617
TRUE
TRUE
PP1V2R1V05_ENET
I616
TRUE
PP3V3_ENET_PHY
I614
TRUE
I627
TRUE
I626
TRUE
PPVP_FW
PP1V0_FW
PP3V3_S0GPU
I639
TRUE
PP1V1_S0GPU
I638
TRUE
8
8
I637
TRUE
I636
TRUE
PP1V8_S0GPU_ISNS
PPVCORE_GPU
PP1V8_S0GPU_ISNS_R
I709
TRUE
PP3V3_S5_AVREF_SMC
41 42
I714
TRUE
PP18V5_S3
7 50
7 44 94
7 44 94
I1156
TRUE
I1157
TRUE
I1159
TRUE
I1160
TRUE
I1161
TRUE
PPDCIN_G3H
PPVCORE_S0_MCP
PPMCPDDR_ISNS
PPVTTDDR_S3
PP1V8_GPUIFPX
8
8
TP_PCI_AD<31..8>
TP_PCI_C_BE_L<3..0>
TP_PCI_CLK0
TP_PCI_CLK1
TP_PCI_DEVSEL_L
TP_PCI_FRAME_L
TP_PCI_GNT0_L
TP_PCI_GNT1_L
TP_PCI_INTW_L
TP_PCI_INTX_L
TP_PCI_INTY_L
TP_PCI_INTZ_L
TP_PCI_IRDY_L
TP_PCI_PAR
TP_PCI_PERR_L
TP_PCI_RESET1_L
TP_PCI_SERR_L
TP_PCI_STOP_L
TP_PCI_TRDY_L
TP_PCIE_CLK100M_PE4P
TP_PCIE_CLK100M_PE5N
TP_PCIE_PE4_D2RN
TP_PCIE_PE4_D2RP
TP_PE4_CLKREQ_L
TP_PEX_CLKREQ_L
TP_PSOC_P1_3
TP_SATA_C_D2RN
TP_SATA_C_D2RP
TP_SATA_C_R2D_CN
TP_SATA_C_R2D_CP
TP_SATA_D_D2RN
TP_SATA_D_D2RP
TP_SATA_D_R2D_CN
TP_SATA_D_R2D_CP
TP_SATA_E_D2RN
TP_SATA_E_D2RP
TP_SATA_E_R2D_CN
TP_SATA_E_R2D_CP
TP_SATA_F_D2RN
TP_SATA_F_D2RP
TP_SATA_F_R2D_CN
TP_SATA_F_R2D_CP
TP_SB_A20GATE
TP_SMC_P41
TP_USB_10P
TP_USB_11N
TP_USB_11P
TP_USB_EXTDN
TP_USB_EXTDP
TP_USB_MININ
TP_USB_MINIP
TP_XDP_OBSDATA_B2
TP_XDP_OBSDATA_B3
m
il
19
PP2V5_S0
PP1V2_S0
TRUE
16
NO_TEST
19
19
19
19
19
17
17
17
17
17
17
17
17
69
49
20
20
20
20
7 8
20
7 8
20
20
20
20
20
7 44 94
20
7 44 94
20
41 42 59
20
20
20
20
21
42
7 8 42
20
7 44 94
20
7 44 94
20
9
42 59
GND
13
GND
13
6 TPs
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
16
NC_PCI_AD<31..8>
NC_PCI_C_BE_L<3..0>
NC_PCI_CLK0
NC_PCI_CLK1
NC_PCI_DEVSEL_L
NC_PCI_FRAME_L
NC_PCI_GNT0_L
NC_PCI_GNT1_L
NC_PCI_INTW_L
NC_PCI_INTX_L
NC_PCI_INTY_L
NC_PCI_INTZ_L
NC_PCI_IRDY_L
NC_PCI_PAR
NC_PCI_PERR_L
NC_PCI_RESET1_L
NC_PCI_SERR_L
NC_PCI_STOP_L
NC_PCI_TRDY_L
NC_PCIE_CLK100M_PE4P
NC_PCIE_CLK100M_PE5N
NC_PCIE_CLK100M_PE6N
NC_PCIE_PE4_D2RN
NC_PCIE_PE4_D2RP
NC_PE4_CLKREQ_L
NC_PEX_CLKREQ_L
NC_PSOC_P1_3
NC_SATA_C_D2RN
NC_SATA_C_D2RP
NC_SATA_C_R2D_CN
NC_SATA_C_R2D_CP
NC_SATA_D_D2RN
NC_SATA_D_D2RP
NC_SATA_D_R2D_CN
NC_SATA_D_R2D_CP
NC_SATA_E_D2RN
NC_SATA_E_D2RP
NC_SATA_E_R2D_CN
NC_SATA_E_R2D_CP
NC_SATA_F_D2RN
NC_SATA_F_D2RP
NC_SATA_F_R2D_CN
NC_SATA_F_R2D_CP
NC_SB_A20GATE
NC_SMC_P41
NC_USB_10P
NC_USB_11N
NC_USB_11P
NC_USB_EXTDN
NC_USB_EXTDP
NC_USB_MININ
NC_USB_MINIP
NC_XDP_OBSDATA_B2
NC_XDP_OBSDATA_B3
TRUE
TRUE
I761
10 14 88
I771
40
MCPTHMSNS_D_P
MCPTHMSNS_D_N
y
r
10 14 88
I772
41 42 49
NC NO_TESTs
10 14 88
a
n
i
I1277
49
25 41
TRUE
TRUE
18 43
FUNC_TEST
NO_TEST
TRUE
I981
39 41 42 43
I744
49
I982
41 43
49
10 14 88
10 14 88
I763
41 42 43
49
FSB_A_L<31..3>
FSB_ADS_L
FSB_ADSTB_L<1..0>
FSB_D_L<63..0>
FSB_DBSY_L
FSB_DINV_L<3..0>
FSB_DRDY_L
FSB_DSTB_L_N<3..0>
FSB_DSTB_L_P<3..0>
FSB_HIT_L
FSB_HITM_L
FSB_LOCK_L
FSB_REQ_L<4..0>
FB NO_TESTs
41 42 43
SMC_RESET_L
SMC_NMI
SMC_RX_L
49
GND
J6995 (BAT LED CONN)

PP3V42_G3H
TRUE
SMBUS_SMC_BSA_SDA
TRUE
SMBUS_SMC_BSA_SCL
TRUE
SMC_BIL_BUTTON_DB_L
TRUE
TRUE
FUNC_TEST
I615
49 50
59
TRUE
25 43
49
e
r
50
59
TRUE
POWER RAILS
I620
49 50
59
TRUE
16
I624
49 50
TRUE
19 41 43 84 91
19 41 43
19
49 50
NO_TEST
43
49
40
7 50
49 50
CPU FSB NO_TESTs
J5502 (SENSOR CONN)
50
50
25 43 91
TRUE
49
PP3V42_G3H_LIDSWITCH_R
PP5V_S3_IR_R
SMC_LID_R
IR_RX_OUT
SYS_LED_ANODE
TRUE
30 96
40
I724
49
ICT Test Points
49
J4800 (FRONT CABLE CONN)
7 44 94
GND
J6950 (MAIN BATT CONN)

PPVBAT_G3H_CONN_F
TRUE
SMBUS_SMC_BSA_SCL
TRUE
SMBUS_SMC_BSA_SDA
TRUE
SMC_BS_ALRT_L
TRUE
49
7 8
30
J6900 (DC POWER CONN)

ADAPTER_SENSE
TRUE
PP18V5_DCIN_FUSE
TRUE
TRUE
J4501 (SATA HDD CONN)
I1146
I1122
30 90
PP1V5_S0_EXCARD_SWITCH
31
PCIE_WAKE_L
7 17 30 31
SMBUS_MCP_0_CLK
13 21 44 91
SMBUS_MCP_0_DATA
13 21 44 91
31
31
USB2_EXCARD_CONN_N
31 96
USB2_EXCARD_CONN_P
31 96
EXCARD_CPUSB_L
31
EXCARD_CLKREQ_CONN_L
31
EXCARD_CPPE_L
31
PLT_RESET_SWITCH_L
31
PCIE_EXCARD_D2R_P
17 31 90
PCIE_EXCARD_D2R_N
17 31 90
PCIE_EXCARD_R2D_P
31 90
PCIE_EXCARD_R2D_N
31 90
PCIE_CLK100M_EXCARD_CONN_P 31 96
PCIE_CLK100M_EXCARD_CONN_N 31 96
J5800 (IPD FLEX CONN)

PP3V3_S3_LDO
TRUE
PP18V5_S3
TRUE
TPAD_GND_F
TRUE
Z2_CS_L
TRUE
Z2_DEBUG3
TRUE
Z2_MISO
TRUE
Z2_BOOST_EN
TRUE
Z2_BOOT_CFG1
TRUE
Z2_CLKIN
TRUE
Z2_KEY_ACT_L
TRUE
Z2_RESET
TRUE
PSOC_F_CS_L
TRUE
PICKB_L
TRUE
PSOC_MISO
TRUE
PSOC_MOSI
TRUE
PSOC_SCLK
TRUE
SMBUS_SMC_A_S3_SCL
TRUE
SMBUS_SMC_A_S3_SDA
TRUE
38 90
5 TPs
I1032
TRUE
78 81 95
3 TPs
TRUE
TRUE
78 81 95
J4500 (SATA ODD CONN)
I1026
TRUE
78 81 95
I1093
I1024
TRUE
78 85
I1092
I1145
17 30 90
17 30 90
J3500 (EXPRESS CARD CONN)
56 57 96
4 TPs
PCIE_MINI_D2R_P
PCIE_MINI_D2R_N
PCIE_MINI_R2D_P
PCIE_MINI_R2D_N
PCIE_CLK100M_MINI_CONN_P
PCIE_CLK100M_MINI_CONN_N
MINI_CLKREQ_Q_L
PCIE_WAKE_L
MINI_RESET_CONN_L
PP5V_WLAN
PP5V_S3_BTCAMERA_F
SMBUS_SMC_A_S3_SDA
SMBUS_SMC_A_S3_SCL
USB_CAMERA_CONN_P
USB_CAMERA_CONN_N
CONN_USB2_BT_P
CONN_USB2_BT_N
56 57 96
J9000 (LVDS CONN)
I1005
TRUE
I1050
TRUE
I1001
I1051
56 57 96
J6782 (RIGHT & SUB SPEAKER)

TRUE
I989
I1119
J3401 (AIRPORT/BT/CAMERA CONN)

57 58
7 8 42
FUNC_TEST
SYS_LED_ANODE_R
TRUE
I720
LPC_CLK33M_LPCPLUS
TRUE
I722
5
J5713 (KEY BOARD CONN)
PP3V3_S3
TRUE
PP3V42_G3H
TRUE
WS_KBD1
TRUE
WS_KBD2
TRUE
WS_KBD3
TRUE
WS_KBD4
TRUE
WS_KBD5
TRUE
WS_KBD6
TRUE
WS_KBD7
TRUE
WS_KBD8
TRUE
WS_KBD9
TRUE
WS_KBD10
TRUE
WS_KBD11
TRUE
WS_KBD12
TRUE
WS_KBD13
TRUE
WS_KBD14
TRUE
WS_KBD15_CAP
TRUE
WS_KBD16_NUM
TRUE
WS_KBD17
TRUE
WS_KBD18
TRUE
WS_KBD19
TRUE
WS_KBD20
TRUE
WS_KBD21
TRUE
WS_KBD22
TRUE
WS_KBD23
TRUE
WS_KBD_ONOFF_L
TRUE
WS_LEFT_SHIFT_KBD
TRUE
WS_LEFT_OPTION_KBD
TRUE
WS_CONTROL_KBD
TRUE
16
16
16
16
16
16
16
16
15
16
16
16
16
16
16
16
16
16
16
21
21
74
75
75
75
75
74
75
19
75
75
75
9
9
9
21
17
21
20
TRUE
TRUE
TRUE
NC_SMC_FAN_3_TACH
NC_SMC_FAN_3_CTL
NC_SMC_FAN_2_TACH
NC_SMC_FAN_2_CTL
NC_FW2_TPBP
NC_FW2_TPBN
NC_FW2_TPBIAS
NC_FW2_TPAP
NC_FW2_TPAN
NC_FW0_TPBP
NC_FW0_TPBN
NC_FW0_TPAP
NC_ESTARLDO_EN
NC_ALS_GAIN
42
42
42
42
37
37
37
37
37
37
37
37
42
42
NC NO_TESTs
NO_TEST
NC_CPU_PECI_MCP
TRUE
MAKE_BASE=TRUE
NC_CPU_TEST3
TRUE
MAKE_BASE=TRUE
NC_ENET_INTR_L
TRUE
MAKE_BASE=TRUE
NC_ENET_PWRDWN_L
TRUE
MAKE_BASE=TRUE
NC_FW643_AVREG
TRUE
MAKE_BASE=TRUE
NC_FW643_TDI
TRUE
MAKE_BASE=TRUE
NC_MEM_A_A<15>
TRUE
MAKE_BASE=TRUE
NC_MEM_A_CKE<2>
TRUE
MAKE_BASE=TRUE
NC_MEM_A_CKE<3>
TRUE
MAKE_BASE=TRUE
NC_MEM_A_CLK2N
TRUE
MAKE_BASE=TRUE
NC_MEM_A_CLK2P
TRUE
MAKE_BASE=TRUE
NC_MEM_A_CLK3N
TRUE
MAKE_BASE=TRUE
NC_MEM_A_CLK3P
TRUE
MAKE_BASE=TRUE
NC_MEM_A_CLK4N
TRUE
MAKE_BASE=TRUE
NC_MEM_A_CLK4P
TRUE
MAKE_BASE=TRUE
NC_MEM_A_CLK5N
TRUE
MAKE_BASE=TRUE
NC_MEM_A_CLK5P
TRUE
MAKE_BASE=TRUE
NC_MEM_A_CS_L<2>
TRUE
MAKE_BASE=TRUE
NC_MEM_A_CS_L<3>
TRUE
MAKE_BASE=TRUE
NC_MEM_A_ODT<2>
TRUE
MAKE_BASE=TRUE
NC_MEM_A_ODT<3>
TRUE
MAKE_BASE=TRUE
NC_MEM_B_A<15>
TRUE
MAKE_BASE=TRUE
NC_MEM_B_CKE<2>
TRUE
MAKE_BASE=TRUE
NC_MEM_B_CLK2P
TRUE
MAKE_BASE=TRUE
NC_MEM_B_CLK3N
TRUE
MAKE_BASE=TRUE
NC_MEM_B_CLK3P
TRUE
MAKE_BASE=TRUE
NC_MEM_B_CLK4N
TRUE
MAKE_BASE=TRUE
NC_MEM_B_CLK4P
TRUE
MAKE_BASE=TRUE
NC_MEM_B_CLK5N
TRUE
MAKE_BASE=TRUE
NC_MEM_B_CLK5P
TRUE
MAKE_BASE=TRUE
NC_MEM_B_CS_L<2>
TRUE
MAKE_BASE=TRUE
NC_MEM_B_CS_L<3>
TRUE
MAKE_BASE=TRUE
NC_MEM_B_ODT<2>
TRUE
MAKE_BASE=TRUE
NC_MEM_B_ODT<3>
TRUE
MAKE_BASE=TRUE
NC_MLB_RAM_SIZE
TRUE
MAKE_BASE=TRUE
NC_MLB_RAM_VENDOR
TRUE
MAKE_BASE=TRUE
NC_GPU_BUFRST_L
TRUE
MAKE_BASE=TRUE
NC_GPU_GSTATE<0>
TRUE
MAKE_BASE=TRUE
NC_GPU_GSTATE<1>
TRUE
MAKE_BASE=TRUE
NC_GPU_MIOA_D<9..0>
TRUE
MAKE_BASE=TRUE
NC_GPU_MIOA_DE
TRUE
MAKE_BASE=TRUE
NC_GPU_PGOOD_OUT_L
TRUE
MAKE_BASE=TRUE
NC_GPU_VCORE_VID3
TRUE
MAKE_BASE=TRUE
NC_LPC_DRQ0_L
TRUE
MAKE_BASE=TRUE NC_LVDS_EG_B_CLK_N
TRUE
MAKE_BASE=TRUE
NC_LVDS_EG_B_CLK_P
TRUE
MAKE_BASE=TRUE
NC_LVDS_EG_BKL_PWM
TRUE
MAKE_BASE=TRUE
NC_LVDS_IG_B_CLKN
TRUE
MAKE_BASE=TRUE
NC_LVDS_IG_B_CLKP
TRUE
MAKE_BASE=TRUE
NC_LVDS_IG_BKL_PWM
TRUE
MAKE_BASE=TRUE
NC_MCP_BUF_SIO_CLK
TRUE
MAKE_BASE=TRUE
NC_MCP_GPIO_18
TRUE
MAKE_BASE=TRUE
NC_MCP_KBDRSTIN_L
TRUE
MAKE_BASE=TRUE
NC_MCP_SATALED_L
TRUE
MAKE_BASE=TRUE
TP_CPU_PECI_MCP
TP_CPU_TEST3
TP_ENET_INTR_L
TP_ENET_PWRDWN_L
TP_FW643_AVREG
TP_FW643_TDI
TP_MEM_A_A<15>
TP_MEM_A_CKE<2>
TP_MEM_A_CKE<3>
TP_MEM_A_CLK2N
TP_MEM_A_CLK2P
TP_MEM_A_CLK3N
TP_MEM_A_CLK3P
TP_MEM_A_CLK4N
TP_MEM_A_CLK4P
TP_MEM_A_CLK5N
TP_MEM_A_CLK5P
TP_MEM_A_CS_L<2>
TP_MEM_A_CS_L<3>
TP_MEM_A_ODT<2>
TP_MEM_A_ODT<3>
TP_MEM_B_A<15>
TP_MEM_B_CKE<2>
TP_MEM_B_CLK2P
TP_MEM_B_CLK3N
TP_MEM_B_CLK3P
TP_MEM_B_CLK4N
TP_MEM_B_CLK4P
TP_MEM_B_CLK5N
TP_MEM_B_CLK5P
TP_MEM_B_CS_L<2>
TP_MEM_B_CS_L<3>
TP_MEM_B_ODT<2>
TP_MEM_B_ODT<3>
TP_MLB_RAM_SIZE
TP_MLB_RAM_VENDOR
TP_GPU_BUFRST_L
TP_GPU_GSTATE<0>
TP_GPU_GSTATE<1>
TP_GPU_MIOA_D<9..0>
TP_GPU_MIOA_DE
TP_GPU_PGOOD_OUT_L
TP_GPU_VCORE_VID3
TP_LPC_DRQ0_L
TP_LVDS_EG_B_CLK_N
TP_LVDS_EG_B_CLK_P
TP_LVDS_EG_BKL_PWM
TP_LVDS_IG_B_CLKN
TP_LVDS_IG_B_CLKP
TP_LVDS_IG_BKL_PWM
TP_MCP_BUF_SIO_CLK
TP_MCP_GPIO_18
TP_MCP_KBDRSTIN_L
TP_MCP_SATALED_L
Functional / ICT Test


SIZE
DRAWING NUMBER
D
APPLE INC.
SYNC_MASTER=K20_MLB
REV.
051-7656
SCALE
SHT
NONE
31
OF
7
123
7
"G3Hot" (Always-Present) Rails
3.3V-2.5V Rails
PPBUS_G3H
=PPBUS_G3H
60
7 45
62
=PP3V3_S5_REG
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=6V
MAKE_BASE=TRUE
1.8V/DDR 1.5V Rails
PP3V3_S5
7 96
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
MAKE_BASE=TRUE
=PP1V8_S0_REG
66
500 mA max supply
190 mA
7
36
=PP3V3R1V8_S0_MCP_IFP_VDD
18 24
=PP1V8_S0_MCP_PLL_VLDO
66
63
67
=PP1V8R1V5_S0_MCP_FET
68
=PPVIN_S0GPU_P1V8P1V1
83
=PP3V3_S5_P1V05FET
68
=PPVIN_S0_DDRREG_LDO
63
59
=PP3V3_S5_MCP
22 23
=PP1V5_S3_MEM_A
27
66
=PP3V3_S5_MCP_GPIO
18 20
=PP1V5_S3_MEM_B
28
50
=PP3V3_FW_LATEVG_ACTIVE
36
=PP1V5_S3_MEMRESET
29
36
=PP3V3_S5_MCPPWRGD
25
=PPVIN_S0_CPUVTTS0
65
=PPBUS_S0_LCDBKLT
86
77
=PPVIN_S5_CPU_IMVP_ISNS_R
=PPVIN_S0_P5VRTS0_MCPCORE
45
64
=PPVBAT_G3H_P3V42G3H
=PPVIN_S0_P1V05S5
=PPVIN_S0_KBDLED
=PPVIN_S5_FWPWRSW
=PPVIN_S5_BKL
=PPVIN_PFWBOOST
29
68
78
63
=PPDDR_S3_REG
PP1V8R1V5_S3
68
68
=PP1V8R1V5_S0_FET
VOLTAGE=10V
MAKE_BASE=TRUE
PP1V8R1V5_S0
37
33
4771 mA
=PPMCPDDR_ISNS_R
46
=PP1V5_S0_CPU
=PPVIN_S5_CPU_IMVP_ISNS
PPBUS_CPU_IMVP_ISNS
11 12
=PP1V5_S0_VMON
67
82
59
=PP18V5_DCIN_CONN
VOLTAGE=18.5V
MAKE_BASE=TRUE
=PPDCIN_S5_CHGR
59
=PP3V42_G3H_REG
PP3V42_G3H
60
=PP3V3_S3_SMS
7 42
=PP3V3_S3_WLAN
=PP3V3_S3_MCP_GPIO
VOLTAGE=3.42V
MAKE_BASE=TRUE
=PP3V42_G3H_SMCUSBMUX
=PP3V42_G3H_SMBUS_SMC_BSA
=PP3V42_G3H_LIDSWITCH
=PP3V3_S5_SMC
=PP3V3_S5_LPCPLUS
=PPVIN_S5_SMCVREF
=PP3V42_G3H_PWRCTL
39
42
=PP3V42_G3H_CHGR
60
=PP3V3_S5_RTC_D
25
=PP3V42_G3H_BATT
59
31
68
=PP3V3_S0_FET
PP3V3_S0
7 9 96
46
=PP3V3_S0_XDP
6 8 13
e
r
=PPSPD_S0_MEM_A
77
=PPSPD_S0_MEM_B
39 98
=PP3V3_S0_GMUX
68
=PP3V3_S0_DPMUX
68
68
9
P
7 48
48
61
65
83
43
38
38
PPVCORE_S0_CPU
46
23 8
47
48
PP1V05_S0_MCP_PEX_AVDD
23
MAKE_BASE=TRUE
48
61
=PP1V05_S0_MCP_SATA_DVDD
23 8
67
7 75 78
PP1V05_S0_MCP_SATA_AVDD
23
6 8 13
=PPVCORE_S0_CPU
23
=PP1V05_S0_MCP_PEX_DVDD
8 23
8 23
=PP1V05_S0_MCP_HDMI_VDD
18 24
=PP1V05_S0_VMON
67
=PP1V05_S0_MCP_PLL_PEX_UF
23
66
=PP1V05_S5_MCP
=PP3V3_S0_MCP_PLL_UF
23
=PP3V3_S0_MCP_VPLL_UF
24
=PP3V3_S0_MCP_DAC_UF
24
=PP3V3_S0_MCP
21 22 23
63 26
38
=PPVTT_S3_DDR_BUF
63
=PPVTT_S0_DDR_LDO
47
=PP1V1_S0GPU_REG
=PP3V3_GPU_VDD33
=PP3V3_GPU_MIO
=PP2V5_S0_REG
47
87
=PP1V2_S0_REG
=PP3V3_GPU_PWRCTL
=PP3V3_GPU_VCORELOGIC
66
69
69
69
=PP1V1_GPU_PLLVDD
74
=PP1V05_S0_MCP_PEX_AVDD0
17
=PP1V1_GPU_H_PLLVDD
74
17
=PP1V1_GPU_VID_PLLVDD
74
=PP1V1_GPU_FBPLLAVDD
71
=PP1V1_GPU_IFPCD_IOVDD
76
20
20
(1.1V for A01)

7
66
=PP1V8_GPUIFPX_REG
PP1V8_GPUIFPX
0 mA
=PP1V05_S5_P1V05S0FET
=PP1V8_GPU_IFPX
PPCPUVTT_S0
1182 mA
76
68
VOLTAGE=1.05V
MAKE_BASE=TRUE
4500 mA
VOLTAGE=1.8V
MAKE_BASE=TRUE
46
=PP1V8_S0GPU_ISNS
=PP1V05_S0_CPU
6 10 11 12 13 61
=PP1V05_S0_SMC_LS
42
=PP1V05_S0_MCP_FSB
9 14 22 23
PPVTTDDR_S3
PP1V8_S0GPU_ISNS
VOLTAGE=1.8V
MAKE_BASE=TRUE
=PP1V8_GPU_FB_VDD
=PP1V8_GPU_FB_VDDQ
=PP1V8_GPU_FBVDDQ
=PP1V8_GPU_FBIO
72 73 79 80
9 72 73 79 80
70
71
VOLTAGE=0.75V
MAKE_BASE=TRUE
77 45
=PPVCORE_GPU_REG
PPVCORE_GPU
=PP0V75_S0_MEM_VTT_A
27
=PP0V75_S0_MEM_VTT_B
28
=PPVTT_S0_VTTCLAMP
68
VOLTAGE=1.2V
MAKE_BASE=TRUE
=PPVCORE_GPU
70
83
=PP1V8_GPU_REG
PP1V8_S0GPU_ISNS_R
VOLTAGE=1.25V
MAKE_BASE=TRUE
50
ENET Rails
66
33
=PP1V05_ENET_FET
=PP1V8_S0GPU_ISNS_R
PP1V2R1V05_ENET
46
VOLTAGE=1.05V
MAKE_BASE=TRUE
=PP1V05_ENET_MCP_PLL_MAC
23
=PP1V05_ENET_MCP_RMGT
=PP1V05_ENET_PHY
Power Aliases
18 23
SYNC_MASTER=RXU_K20
32

33
PP2V5_S0
=PP3V3_ENET_FET
PP3V3_ENET_PHY
VOLTAGE=3.3V
MAKE_BASE=TRUE

18 23
=PP3V3_ENET_PHY
32

84

SIZE
PP1V2_S0
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
84
REV.
051-7656
NONE
77
=PP1V1_GPU_PEX_PLLXVDD
OR 0.75V
66
=PP1V2_S0_GMUX
22 23 45
67
=PP1V1_GPU_PEX_IOVDD
VOLTAGE=1.2V
MAKE_BASE=TRUE
=PPVCORE_S0_MCP
81
PP1V1_S0GPU
44
35 37
=PP2V5_S0_GMUX
VOLTAGE=1.05V
MAKE_BASE=TRUE
74 75
=PP3V3_GPU_LVDS_DDC
31
VOLTAGE=2.5V
MAKE_BASE=TRUE
PPVCORE_S0_MCP
6 74 75
VOLTAGE=1.1V
MAKE_BASE=TRUE
MIN_LINE_WIDTH=2 mm
VOLTAGE=0.9V
MAKE_BASE=TRUE
44
81
=PP1V1_GPU_PEX_IOVDDQ
67
=PP3V3_S0_BATTCHARGERTMPSNSR
PP3V3_S0GPU
MIN_NECK_WIDTH=0.20MM
VOLTAGE=3.3V
MAKE_BASE=TRUE
17
PP1V2R1V05_S5
=PPCPUVTT_S0_REG
53 57 58
=PP3V3_S0_REMTHMSNS
=PP3V3_S0_EXCARD
=PP3V3_S0_LVDSDDCMUX
83
VOLTAGE=1.05V
MAKE_BASE=TRUE
5300 mA
18 19 21
35
17
=PP1V05_S0_MCP_SATA_AVDD0
241 mA max load
65
21 23
=PP1V0_FW_FWPHY
=PP1V05_S0_MCP_PEX_DVDD1
33
24
22 23
=PP3V3R1V5_S0_MCP_HDA
PP1V0_FW
VOLTAGE=1.0V
MAKE_BASE=TRUE
23 66
=PP1V05_ENET_P1V05ENETFET
=PP3V3_S0_HDCPROM
37
=PP1V05_S5_MCP_VDD_AUXC
=PP3V3_S0_MCP_GPIO
37
=PP3V3_GPU_P1V8S0
11 12 45
87
=PPMCPCORE_S0_REG
=PP1V05_S0_MCP_AVDD_UF
=PPVP_FW_PORT1
=PPVP_FW_PHY_CPS_FET
VOLTAGE=1.25V
MAKE_BASE=TRUE
64
139 mA/
87
PP1V05_S0
105 mA/241 mA
82
=PP3V3_FW_FWPHY
=PP3V3_FW_P1V0FW
46
44
=PP3V3_S0_P1V2P2V5
=PP3V3_GPU_SMBUS_SMC_0_S0
=PP3V3_S0_TPAD
28
=PPMCPDDR_ISNS
MAKE_BASE=TRUE
81
=PP3V3_S0_SMBUS_MCP_1
=PP1V5_S0_MEM_B
28
=PP3V3_S0_DPCONN
=PP3V3_S0_VMON
27
=PP1V05_S0_MCP_SATA_DVDD0
84
=PP3V3_S0_AUDIO
=PP3V3_S0_ODD
=PP1V5_S0_MEM_A
36
VOLTAGE=10V
MAKE_BASE=TRUE
"GPU" Rails
=PP3V3_S0GPU_FET
68
VOLTAGE=1.05V
47
27
=PP3V3_S0_SMBUS_MCP_0
50
MAKE_BASE=TRUE
46
=PP3V3_S0_MCPCOREISNS
VOLTAGE=5V
MAKE_BASE=TRUE
Chipset "VCore" Rails
44
63
30
PP5V_S0
m
il
PP1V05_S0_MCP_PLL_UF
40
42
=PP5V_S3_MCPDDRFET
=PP5V_S3_VTTCLAMP
=PP5V_S3_AUDIO_PWR
42
30
=PP5V_S3_TPAD
43
=PP3V3_S0_GPU1V8ISNS
=PP3V3_S0_CPUTHMSNS
=PP3V3_S0_GPUTHMSNS
=PP3V3_S0_FAN_LT
=PP3V3_S0_FAN_RT
=PP3V3_S0_IMVP
=PP3V3_S0_PWRCTL
=PP3V3_S0_DDC_LCD
=PP3V3_S0_XDP
VOLTAGE=1.05V
MAKE_BASE=TRUE
VOLTAGE=3.3V
MAKE_BASE=TRUE
45
PP5V_S3
=PP5V_S0_HDD
=PP1V05_S0_FET
68 66
66
=PP3V3_S0_MCPDDRISNS
=PP5V_S3_P1V05S0FET
=PP3V3_S3_EXCARD
49
=PP5V_S3_GPUVCORE
=PP5V_S3_RTUSB
=PPVCORE_S0_CPU_REG
44
45
=PP5V_S3_WLAN
=PP5V_S3_IR
=PP5V_S3_DDRREG
61
26
=PP3V42_G3H_BMON_ISNS
=PP5V_S0GPU_P1V1P1V8_GPU
=PP5V_S0_LPCPLUS
=PP5V_S0_ODD
PPMCPDDR_ISNS
49
=PP3V3_S3_SMBUS_SMC_MGMT
31
VOLTAGE=1.5V
MAKE_BASE=TRUE
21
=PP3V42_G3H_TPAD
=PP5V_S0_CPUVTTS0
=PP1V8R1V5_S0_MCP_MEM
23 16
8 51
30
=PP3V3_S0_LPCPLUS
=PP3V3_S0_SMC
=PP3V3_S0_SMBUS_SMC_B_S0
=PP5V_S0_FAN_LT
=PP5V_S0_FAN_RT
=PP5V_S0_CPU_IMVP
44
=PP3V3_S3_VREFMRGN
67
=PP5V_S3_BTCAMERA
=PP5V_S0_REG
66
43
=PP5V_S3_SYSLED
64
=PP1V5_S0_EXCARD
30
1034 mA
VOLTAGE=5V
MAKE_BASE=TRUE
a
n
i
84
41 42 51
5V Rails
=PP5V_S3_REG
VOLTAGE=1.5V
MAKE_BASE=TRUE
40
=PP3V42_G3H_CPUCOREISNS
62
PP1V5_EXP_S0
8 51
=PP3V3_S3_P1V5EXPS0
44
=PP1V0_FW_REG
66
=PP1V5_EXP_S0
66
=PP3V3_S3_GMUX
=PP3V3_S3_BT
=PP3V3_S3_P1V8S0
=PP3V3_S3_SMBUS_SMC_A_S3
=PP3V3_S3_SMS
=PP3V3_S3_TPAD
61
PPDCIN_G3H
VOLTAGE=3.3V
MAKE_BASE=TRUE
VOLTAGE=6V
MAKE_BASE=TRUE
=PPVIN_S5_CPU_IMVP
PP3V3_S3
=PPBOOST_FW_FWPWRSW_F
PPVP_FW
=PPBOOST_S5_FW_FET
y
r
VOLTAGE=1.5V
MAKE_BASE=TRUE
33
66
PP10V_FW
VOLTAGE=1.5V
MAKE_BASE=TRUE
68
500 mA
45
=PFWBOOST_REG
66
130 mA
=PP3V3_S3_FET
PPBUS_FW_FWBOOST
43 52
36
=PP3V3_FW_LATEVG
=PP3V3_S5_P1V05ENETFET
=PP3V3_S5_DP_PORT_PWR
68
=PPVOUT_FW_FWPWRSW
VOLTAGE=6V
MAKE_BASE=TRUE
=PPVIN_S3_DDRREG
62
"FW" (FireWire) Rails
PP1V8_S0
VOLTAGE=1.8V
MAKE_BASE=TRUE
=PP3V3_S5_ROM
=PP3V3_S5_MEMRESET
=PP3V3_S3_P3V3S3FET
=PP3V3_S0_LCD
=PP3V3_S0_P3V3S0FET
=PP3V3_GPU_P3V3GPUFET
=PP3V3_S5_PWRCTL
=PPVIN_S5_P5VP3V3
=PPVIN_GPU_GPUVCORE
31
OF
8
123
SH0902
Thermal Module Holes
TP_IMVP6_CLKEN_L
SM
ZT0984
61 88
STDOFF-4.5OD.98H-1.1-3.48-TH
ZT0983
ZT0980
STDOFF-4.5OD.98H-1.1-3.48-TH
CPU_BSEL<0..2>
88 10
=MCP_BSEL<0..2>
14
MEM_VTT_EN
25
=DDRVTT_EN
63 68
=SPI_CS1_R_L_USE_MLB
21 43
Right CPU
TM Hole
ZT0986
2.0DIA-TALL-EMI-MLB-M97-M98
SM
TP_USB_MININ
MAKE_BASE=TRUE
ZT0930
TP_MEM_A_A<15>
TP_MEM_B_A<15>
STDOFF-4.5OD.98H-1.1-3.48-TH
90 69
PEG_D2R_P<0..15>
90 69
PEG_D2R_N<0..15>
=PEG_D2R_P<0..15>
17
=PEG_D2R_N<0..15>
17
=PEG_R2D_C_P<0..15>
17
=PEG_R2D_C_N<0..15>
17
y
r
MAKE_BASE=TRUE
TP_CPU_PECI_MCP
90 69
PEG_R2D_C_P<0..15>
90 69
PEG_R2D_C_N<0..15>
MAKE_BASE=TRUE
TP_LVDS_IG_B_CLKP
TP_LVDS_IG_B_CLKN
GPU_FB_A_VREF_DIV
MAKE_BASE=TRUE
1%
1/16W
MF-LF
402
ZT0915
SH0910
26
1.4DIA-SHORT-EMI-MLB-M97-M98
SM
72
1%
1/16W
MF-LF
402
3R2P5
GND_CHASSIS_USB
26
=PP1V8_GPU_FB_VREF_B
DP_IG_ML_P<2..0>
18
=MCP_HDMI_TXC_N
18
=MCP_HDMI_TXD_P<0..2>
DP_IG_DDC_CLK
81 75
=MCP_HDMI_DDC_CLK
18
MAKE_BASE=TRUE
DP_IG_DDC_DATA
81 75
=MCP_HDMI_DDC_DATA
18
=MCP_HDMI_HPD
18
MAKE_BASE=TRUE
DP_IG_HPD
81
SM
3R2P5
=MCP_HDMI_TXD_N<0..2>
MAKE_BASE=TRUE
SM
ZT0932
DP_IG_ML_N<2..0>
90 81
SH0913
73
SH0912
MAKE_BASE=TRUE
GND_CHASSIS_RIGHTHS
GMUX ALIASES
PM_ALL_GPU_PGOOD
67
ALL_EG_PGOOD
84
MAKE_BASE=TRUE
ZT0960
SH0914
Extra FSB Pull-ups
SM
ZT0965
NO STUFF
3R2P5
R0970
GND_CHASSIS_CLUTCH
NO STUFF
1
ZT0940
R0950
220
3R2P5
5%
1/16W
MF-LF
2 402
GND_CHASSIS_LVDS
1%
1/16W
MF-LF
402 2
GND_CHASSIS_DIMM
88 61 14 10
88 14 10
OUT
88 14 13 10
OUT
88 14 10
OUT
88 14 10
OUT
OUT
R0980
SM
SH0916
150
SM
1%
1/16W
MF-LF
2 402
SH0917
e
r
P
ZT0958
4.0OD1.65H-M1.6X0.35
1
ZT0989
STDOFF-4.5OD.98H-1.1-3.48-TH
1
ZT0991
STDOFF-4.5OD.98H-1.1-3.48-TH
1
JTAG_GMUX_TDI
84 6
JTAG_GMUX_TMS
LVDS_IG_B_DATA_P<3>
18 90
LVDS_IG_B_DATA_N<3>
18 90
NO_TEST=TRUE
AUDIO ALIASES
53
HDA_BITCLK
HDA_BIT_CLK
84 6
XW0900
SM
69
=PP5V_S3_AUDIO_PWR
PP5V_S3_AUDIO
GMUX_JTAG_TDI
19
GMUX_JTAG_TMS
19
JTAG_GMUX_TDO
GMUX_INT
GMUX_JTAG_TDO
17
=DVI_HPD_GMUX_INT
PP5V_S3_AUDIO_AMP
LVDS_IG_BKL_ON
R0902
AUD_IPHS_SWITCH_EN
5%
1/16W
MF-LF
402
84
IG_LCD_PWR_EN
84
MAKE_BASE=TRUE
20
20
R0903
21
MCP_SPKR
33
SMC_MCP_SAFE_MODE
5%
1/16W
MF-LF
402
=P3V3ENET_EN
PM_SLP_RMGT_L
=P1V05ENET_EN
32
=PP3V3_ENET_PHY_VDDREG
32
=RTL8211_REGOUT
TP_PP3V3_ENET_PHY_VDDREG
MAKE_BASE=TRUE
NC_RTL8211_REGOUT
MAKE_BASE=TRUE
=RTL8211_ENSWREG
32
SM
SM
MCP79 PCIe PRSNT# Straps
SH0921
R0925
SM
66
SH0931
PCIE_FW_PRSNT_L
OUT
MAKE_BASE=TRUE
=P1V5_EXP_S0_EN
PP3V3_S0
17
5%
1/16W
MF-LF
402
7 8 96
NO STUFF
R0927
SM
PEG_PRSNT_L
OUT
MAKE_BASE=TRUE
SH0922
5%
1/16W
MF-LF
402
SM
17
R0926
0
EG_CLKREQ_OUT_L
IN
84
5%
1/16W
MF-LF
402
SH0932
SM
1
SH0934
SM
Signal Aliases
SYNC_MASTER=K20_MLB
SH0933
SM
MCP_MII_PD
SH0935
=MCP_MII_RXER

18
MAKE_BASE=TRUE
=MCP_MII_CRS
18
=MCP_MII_COL
18

SM
1
R0930
47K
5%
1/16W
MF-LF
402
Digital Ground

SIZE
GND
MIN_LINE_WIDTH=0.6MM
VOLTAGE=0V
DRAWING NUMBER
D
APPLE INC.
REV.
051-7656
SCALE
SHT
NONE
21
MAKE_BASE=TRUE
33
41
ETHERNET ALIASES
SH0919
19 58
MAKE_BASE=TRUE
IG_BKLT_EN
LVDS_IG_PANEL_PWR
10K
18
MAKE_BASE=TRUE
18
56
VOLTAGE=5V
XW0901
MAKE_BASE=TRUE
18
53 55
VOLTAGE=5V
SM
MAKE_BASE=TRUE
84
21 91
MAKE_BASE=TRUE
SM
4.0OD1.65H-M1.6X0.35
STDOFF-4.5OD.98H-1.1-3.48-TH
84 6
18 90
NO_TEST=TRUE
NC_LVDS_IG_B_DATAN<3>
MAKE_BASE=TRUE
SH0930
ZT0988
MAKE_BASE=TRUE
84
GPU_RESET_L
18 90
LVDS_IG_A_DATA_N<3>
ZT0957
NC_LVDS_IG_B_DATAP<3>
18
SH0918
STDOFF-4.0OD3.0H-SM
EG_RESET_L
LVDS_IG_A_DATA_P<3>
NO_TEST=TRUE
18
SM
Bosses for Flex Protector Bracket
ZT0931
18
NO_TEST=TRUE
MAKE_BASE=TRUE
CPU_DPRSTP_L
FSB_BREQ0_L
FSB_CPURST_L
CPU_INTR
CPU_NMI
STDOFF-4.0OD3.0H-SM
ZT0934
m
il
NO STUFF
1
R0960
5%
1/16W
MF-LF
2 402
3R2P5
1
150
5%
1/16W
MF-LF
402 2
NO STUFF
1
200
62
ZT0970
R0990
SH0924
NO STUFF
18 90
LVDS_IG_BKL_PWM
MAKE_BASE=TRUE
SM
=PP1V05_S0_MCP_FSB
LVDS_MUX_SEL_EG
MAKE_BASE=TRUE
NC_LVDS_IG_A_DATAN<3>
MAKE_BASE=TRUE
23 22 14 8
TP_LVDS_MUX_SEL_EG
NC_LVDS_IG_A_DATAP<3>
MAKE_BASE=TRUE
SH0923
GND_CHASSIS_TPAD
18 90
LVDS_IG_B_CLK_N
TP_LVDS_IG_BKL_PWM
MAKE_BASE=TRUE
84
Exist in MRB but not Intel designs. Here for CYA.

If found to be necessary, will move to page14.csa
3R2P5
a
n
i
=MCP_HDMI_TXC_P
MAKE_BASE=TRUE
MAKE_BASE=TRUE
ZT0945
DP_IG_ML_N<3>
MAKE_BASE=TRUE
GPU_FB_B_VREF_DIV
86
MAKE_BASE=TRUE
90 81
90 81
10
1
DP_IG_ML_P<3>
90 81
R0901
GND_BATT_CHGND
LVDS_BKL_ON
MAKE_BASE=TRUE
3R2P5
LCD_BKLT_EN
84
SM
=PP1V8_GPU_FB_VREF_A
LVDS_IG_B_CLK_P
MAKE_BASE=TRUE
SH0911
10
ZT0971
14
MAKE_BASE=TRUE
R0900
1
80 79 73 72 8 =PP1V8_GPU_FB_VDDQ
GND_CHASSIS_SATA
CPU_PECI_MCP
MAKE_BASE=TRUE
MAKE_BASE=TRUE
3R2P5
28
MAKE_BASE=TRUE
MAKE_BASE=TRUE
SM
27
MEM_B_A<15>
MAKE_BASE=TRUE
GPU signals
SH0920
MEM_A_A<15>
MAKE_BASE=TRUE
7
20 91
MAKE_BASE=TRUE
STDOFF-4.5OD.98H-1.1-3.48-TH
20 91
USB_MINI_N
SH0901
ZT0987
Frame Holes
USB_MINI_P
MAKE_BASE=TRUE
STDOFF-4.5OD.98H-1.1-3.48-TH
Bottom Left GPU

TM Hole
20 91
TP_USB_MINIP
TP_SPI_CS1_R_L_USE_MLB
SM
Left CPU
TM Hole
20 91
USB_EXTD_N
MAKE_BASE=TRUE
SH0903
STDOFF-4.5OD.98H-1.1-3.48-TH
USB_EXTD_P
MAKE_BASE=TRUE
MAKE_BASE=TRUE
Top GPU Right

TM Hole
TP_USB_EXTDN
MAKE_BASE=TRUE
SM
ZT0985
TP_USB_EXTDP
CPU_VID<0..6>
88 11
STDOFF-4.5OD.98H-1.1-3.48-TH
61
IMVP6_VID<0..6>
MAKE_BASE=TRUE
SH0900
STDOFF-4.5OD.98H-1.1-3.48-TH
VR_PWRGD_CLKEN_L
MAKE_BASE=TRUE
STDOFF-4.5OD.98H-1.1-3.48-TH
ZT0982
CPU signals
ZT0981
31
OF
9
123
OMIT
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14
BI
88 14
BI
88 14
BI
88 14
BI
88 14 7
BI
FSB_REQ_L<0>
FSB_REQ_L<1>
FSB_REQ_L<2>
FSB_REQ_L<3>
FSB_REQ_L<4>
K3
FSB_A_L<17>
FSB_A_L<18>
FSB_A_L<19>
FSB_A_L<20>
FSB_A_L<21>
FSB_A_L<22>
FSB_A_L<23>
FSB_A_L<24>
FSB_A_L<25>
FSB_A_L<26>
FSB_A_L<27>
FSB_A_L<28>
FSB_A_L<29>
FSB_A_L<30>
FSB_A_L<31>
FSB_A_L<32>
FSB_A_L<33>
FSB_A_L<34>
FSB_A_L<35>
FSB_ADSTB_L<1>
Y2
88 14
IN CPU_A20M_L
OUT CPU_FERR_L
88 14
IN
88 14
88 14
IN
88 14 9
IN
88 14 9
88 14
IN
IN
N2
J1
N3
P5
P2
L2
P4
P1
R1
M1
H2
K2
J3
L1
U5
R3
W6
U4
Y5
U1
R4
T5
T3
W2
W5
Y4
U2
V4
W3
AA4
AB2
AA3
V1
A6
A5
CPU_IGNNE_L
C4
CPU_STPCLK_L
CPU_INTR
CPU_NMI
CPU_SMI_L
TP_CPU_RSVD0
TP_CPU_RSVD1
TP_CPU_RSVD2
TP_CPU_RSVD3
TP_CPU_RSVD4
TP_CPU_RSVD5
TP_CPU_RSVD6
TP_CPU_RSVD7
TP_CPU_RSVD8
D5
C6
B4
A3
M4
N5
T2
V3
B2
F6
D2
D22
D3
REQ0*
REQ1*
REQ2*
REQ3*
REQ4*
=PP1V05_S0_CPU
DEFER*
DRDY*
DBSY*
E1
BR0*
F1
FSB_BREQ0_L
IN
BI
F21
IERR*
INIT*
D20
B3
CPU_IERR_L
CPU_INIT_L
LOCK*
H4
FSB_LOCK_L
RESET*
RS0*
RS1*
RS2*
TRDY*
C1
FSB_CPURST_L
FSB_RS_L<0>
FSB_RS_L<1>
FSB_RS_L<2>
FSB_TRDY_L
F3
F4
G3
G2
88
G6
BPM0*
BPM1*
BPM2*
BPM3*
PRDY*
PREQ*
TCK
TDI
TDO
TMS
TRST*
DBR*
AD4
RSVD0
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
BCLK0
BCLK1
XDP_TMS
54.9
54.9
E4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20
XDP_BPM_L<0>
XDP_BPM_L<1>
XDP_BPM_L<2>
XDP_BPM_L<3>
XDP_BPM_L<4>
XDP_BPM_L<5>
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST_L
XDP_DBRESET_L
R1002
6 8 10 11 12 13 61
PLACE TESTPOINT ON
FSB_IERR_L WITH A GND
0.1" AWAY
54.9
1%
1/16W
MF-LF
2 402
14 88
y
r
7 14 88
IN
9 13 14 88
IN
14 88
IN
14 88
IN
14 88
IN
14 88
BI
7 14 88
BI
7 14 88
BI
13 88
BI
13 88
BI
13 88
BI
13 88
=PP1V05_S0_CPU
54.9
1%
1/16W
MF-LF
402
13 88
B25
CPU_PROCHOT_L
CPU_THERMD_P
CPU_THERMD_N
C7
PM_THRMTRIP_L
D21
A24
A22
A21
54.9
1%
1/16W
MF-LF
402
R1022
54.9
XDP_TCK
R1023
649
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
BI
88 14 7
BI
BI
88 14 7
BI
88 14 7
BI
88 14 7
13 88
6 10 13 88
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
6 10 88
88 14 7
BI
IN
6 10 13 88
88 14 7
BI
IN
6 10 13 88
88 14 7
BI
OUT
OUT
13 25
88 14 7
R1004
OUT
OUT
47 96
OUT
47 96
OUT
14 42 88
IN
14 88
IN
14 88
6 8 10 11 12 13 61
14 42 61 88
BI
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
a
n
i
FSB_D_L<0>
FSB_D_L<1>
FSB_D_L<2>
FSB_D_L<3>
FSB_D_L<4>
FSB_D_L<5>
FSB_D_L<6>
FSB_D_L<7>
FSB_D_L<8>
FSB_D_L<9>
FSB_D_L<10>
FSB_D_L<11>
FSB_D_L<12>
FSB_D_L<13>
FSB_D_L<14>
FSB_D_L<15>
FSB_DSTB_L_N<0>
FSB_DSTB_L_P<0>
FSB_DINV_L<0>
E22
FSB_D_L<16>
FSB_D_L<17>
FSB_D_L<18>
FSB_D_L<19>
FSB_D_L<20>
FSB_D_L<21>
FSB_D_L<22>
FSB_D_L<23>
FSB_D_L<24>
FSB_D_L<25>
FSB_D_L<26>
FSB_D_L<27>
FSB_D_L<28>
FSB_D_L<29>
FSB_D_L<30>
FSB_D_L<31>
FSB_DSTB_L_N<1>
FSB_DSTB_L_P<1>
FSB_DINV_L<1>
N22
F24
E26
G22
F23
G25
E25
E23
K24
G24
J24
J23
H22
F26
K22
H23
J26
H26
H25
m
il
PM_THRMTRIP#
SHOULD CONNECT TO ICH AND
GMCH WITHOUT T (NO STUB)
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
e
r
=PP1V05_S0_CPU
88 14 7
6 10 13 88
IN
FSB_CLK_CPU_P
FSB_CLK_CPU_N
6 8 10 11 12 13 61
88 14 7
R1003 1
BI
IN
R1024
1
BI
9 14 88
BI
1%
1/16W
MF-LF
402
XDP_TDO
7 14 88
61 13 12 11 10 8 6
XDP_TRST_L
BI
H CLK
PLACEMENT_NOTE=Place R1024 near ITP connector (if present)
88 13 10 6
7 14 88
5%
1/16W
MF-LF
2 402
THERMTRIP*
STPCLK*
LINT0
LINT1
SMI*
FSB_HIT_L
FSB_HITM_L
HIT*
HITM*
PROCHOT*
THERMDA
THERMDC
1%
1/16W
MF-LF
402
88 13 10 6
14 88
BI
THERMAL
R1021
88 10 6
BI
68
A20M*
FERR*
IGNNE*
14 88
OMIT
A17*
A18*
A19*
A20*
A21*
A22*
A23*
A24*
A25*
A26*
A27*
A28*
A29*
A30*
A31*
A32*
A33*
A34*
A35*
ADSTB1*
XDP_TDI
14 88
BI
FSB_DEFER_L
FSB_DRDY_L
FSB_DBSY_L
R1020
88 13 10 6
7 14 88
BI
H5
88 13 10 6
BI
R1005
1K
1%
1/16W
MF-LF
402
R1006
2.0K
1%
1/16W
MF-LF
402 2
PLACE C1000 CLOSE TO CPU_TEST4

PIN. MAKE SURE CPU_TEST4 IS
REFERENCED TO GND
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
=PP1V05_S0_CPU
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
K25
P26
R23
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
T25
N25
L26
M26
N24
0.5" MAX LENGTH FOR CPU_GTLREF

88 26 CPU_GTLREF
CPU_TEST1
CPU_TEST2
7 TP_CPU_TEST3
CPU_TEST4
TP_CPU_TEST5
NOSTUFF
TP_CPU_TEST6
C1000
0.1uF
TP_CPU_TEST7
10%
16V
CPU_BSEL<0>
88
9
OUT
X5R
402
CPU_BSEL<1>
88 9
OUT
CPU_BSEL<2>
88 9
OUT
AD26
C23
D25
C24
AF26
AF1
A26
C3
B22
B23
C21
D0*
D1*
D2*
D3*
D4*
D5*
D6*
D7*
D8*
D9*
D10*
D11*
D12*
D13*
D14*
D15*
DSTBN0*
DSTBP0*
DINV0*
D16*
D17*
D18*
D19*
D20*
D21*
D22*
D23*
D24*
D25*
D26*
D27*
D28*
D29*
D30*
D31*
DSTBN1*
DSTBP1*
DINV1*
GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
BSEL0
BSEL1
BSEL2
U1000
PENRYN
FCBGA
2 OF 4
DATA GRP 2
BI
1 OF 4
FSB_ADS_L
FSB_BNR_L
FSB_BPRI_L
G5
DATA GRP 3
BI
88 14 7
M3
FCBGA
H1
E2
DATA GRP 0
88 14 7
K5
ADS*
BNR*
BPRI*
PENRYN
DATA GRP 1
BI
U1000
CONTROL
88 14 7
L4
A3*
A4*
A5*
A6*
A7*
A8*
A9*
A10*
A11*
A12*
A13*
A14*
A15*
A16*
ADSTB0*
XDP/ITP SIGNALS
BI
L5
ADDR GROUP0
88 14 7
FSB_A_L<3>
FSB_A_L<4>
FSB_A_L<5>
FSB_A_L<6>
FSB_A_L<7>
FSB_A_L<8>
FSB_A_L<9>
FSB_A_L<10>
FSB_A_L<11>
FSB_A_L<12>
FSB_A_L<13>
FSB_A_L<14>
FSB_A_L<15>
FSB_A_L<16>
FSB_ADSTB_L<0>
ADDR GROUP1
BI
ICH
BI
88 14 7
RESERVED
88 14 7
J4
D32*
D33*
D34*
D35*
D36*
D37*
D38*
D39*
D40*
D41*
D42*
D43*
D44*
D45*
D46*
D47*
DSTBN2*
DSTBP2*
DINV2*
Y22
D48*
D49*
D50*
D51*
D52*
D53*
D54*
D55*
D56*
D57*
D58*
D59*
D60*
D61*
D62*
D63*
DSTBN3*
DSTBP3*
DINV3*
AE24
COMP0
COMP1
COMP2
COMP3
MISC
DPRSTP*
DPSLP*
DPWR*
PWRGOOD
SLP*
PSI*
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20
R26
88
U26
88
AA1
88
Y1
E5
B5
D24
D6
D7
AE6
88
FSB_D_L<32>
FSB_D_L<33>
FSB_D_L<34>
FSB_D_L<35>
FSB_D_L<36>
FSB_D_L<37>
FSB_D_L<38>
FSB_D_L<39>
FSB_D_L<40>
FSB_D_L<41>
FSB_D_L<42>
FSB_D_L<43>
FSB_D_L<44>
FSB_D_L<45>
FSB_D_L<46>
FSB_D_L<47>
FSB_DSTB_L_N<2>
FSB_DSTB_L_P<2>
FSB_DINV_L<2>
FSB_D_L<48>
FSB_D_L<49>
FSB_D_L<50>
FSB_D_L<51>
FSB_D_L<52>
FSB_D_L<53>
FSB_D_L<54>
FSB_D_L<55>
FSB_D_L<56>
FSB_D_L<57>
FSB_D_L<58>
FSB_D_L<59>
FSB_D_L<60>
FSB_D_L<61>
FSB_D_L<62>
FSB_D_L<63>
FSB_DSTB_L_N<3>
FSB_DSTB_L_P<3>
FSB_DINV_L<3>
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
LAYOUT NOTE:
COMP0,2 CONNECT WITH ZO=27.4OHM,
MAKE TRACE LENGTH SHORTER THAN 0.5".
COMP1,3 CONNECT WITH ZO=55OHM,
MAKE TRACE LENGTH SHORTER THAN 0.5".
R1016
1
1%
1/16W
MF-LF
402
CPU_COMP<0>
CPU_COMP<1>
CPU_COMP<2>
CPU_COMP<3>
CPU_DPRSTP_L
CPU_DPSLP_L
FSB_DPWR_L
CPU_PWRGD
FSB_CPUSLP_L
CPU_PSI_L
54.9
R1019
1
IN
9 14 61 88
IN
14 88
IN
14 88
IN
13 14 88
IN
14 88
OUT
R1018
1
54.9
1%
1/16W
MF-LF
402
R1017
1
27.4
27.4
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
61
NOSTUFF
R1030
0
1
NOSTUFF
R1012
2
5%
1/16W
MF-LF
402
NOSTUFF
1
1K
5%
1/16W
MF-LF
402
R1007
1K
5%
1/16W
MF-LF
402
CPU FSB
SYNC_MASTER=M98_MLB

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
10
123
A4
P6
A8
(CPU CORE POWER)

8 11 12 45
Standard Voltage:
A7
AB20
OMIT
A9
A10
AB7
AC7
U1000
A12
AC9
PENRYN
A13
Low Voltage:
44.0 A (Design Target)
Ultra Low Voltage:
41.0 A (HFM)
30.4 A (LFM)
25.5 A (SuperLFM)
TBD
TBD
U1000
A16
PENRYN
P24
R2
R5
FCBGA
A19
21.0 A (HFM)
18.7 A (LFM)
TBD A (SuperLFM)
A14
P21
A (HFM)
A (LFM)
R22
4 OF 4
A23
R25
AF2
T1
AC13
3 OF 4
A17
AC15
T4
B8
T23
B11
A18
AC17
27.4 A (Auto-Halt/Stop-Grant HFM)

17.0 A (Auto-Halt/Stop-Grant SuperLFM)
TBD
TBD
A (Auto-Halt/Stop-Grant HFM)
A (Auto-Halt/Stop-Grant SuperLFM)
TBD
TBD
A (Auto-Halt/Stop-Grant HFM)
A (Auto-Halt/Stop-Grant LFM)
27.4 A (Sleep HFM)

16.8 A (Sleep SuperLFM)
TBD
TBD
A (Sleep HFM)
A (Sleep SuperLFM)
TBD
TBD
A (Sleep HFM)
A (Sleep LFM)
T26
25.0 A (Deep Sleep HFM)

16.0 A (Deep Sleep SuperLFM)
TBD
TBD
A (Deep Sleep HFM)

A (Deep Sleep SuperLFM)
TBD
TBD
A (Deep Sleep HFM)

A (Deep Sleep LFM)
B13
U3
B16
U6
B19
A20
AC18
B7
AD7
B9
AD9
B10
AD10
U21
B21
U24
B24
V2
C5
V5
C8
V22
C11
B12
AD12
B14
AD14
B15
AD15
B17
AD17
11.5 A (Deeper Sleep)

9.4 A (Enhanced Deeper Sleep)
TBD
A (Deeper Sleep)
TBD
A (Deeper Sleep)
TBD
A (Enhanced Deeper Sleep)
TBD
A (Enhanced Deeper Sleep)
V25
C14
a
n
i
C16
C19
C2
AD18
B18
C22
B20
VCC
C9
AE9
C25
AE10
D1
C10
AE12
C12
AE13
C13
AE15
C15
AE17
D4
D8
D11
D13
C17
AE18
D16
C18
AE20
D19
AF9
D9
D23
AF10
D10
D26
D12
AF12
D14
AF14
D15
AF15
VCC
AF17
D17
D18
AF18
E7
AF20
E10
G21
E12
V6
E13
J6
E17
M6
E18
J21
E20
K21
VCCP
M21
N21
F9
N6
F10
R21
F12
F14
R6
F15
T21
T6
F17
W21
F20
(CPU INTERNAL PLL POWER 1.5V)

=PP1V5_S0_CPU
AA7
8 12
B26
AA9
e
r
V21
F18
AA10
VCCA
130 mA
C26
AA12
AA13
AA15
AA17
AA18
AA20
AB9
AC10
VID0
VID1
VID2
VID3
VID4
VID5
VID6
AD6
AF5
AE5
AF4
AE3
AF3
AE2
CPU_VID<0>
CPU_VID<1>
CPU_VID<2>
CPU_VID<3>
CPU_VID<4>
CPU_VID<5>
CPU_VID<6>
AB10
AB12
AB14
VCCSENSE
AF7
CPU_VCCSENSE_P
AB15
AB17
AB18
m
il
4500 mA (before VCC stable)

2500 mA (after VCC stable)
K6
E15
F7
6 8 10 12 13 61
VSSSENSE
AE7
CPU_VCCSENSE_N
OUT
9 88
OUT
9 88
OUT
9 88
OUT
9 88
OUT
9 88
OUT
9 88
OUT
9 88
=PPVCORE_S0_CPU
R1100
100
1%
1/16W
MF-LF
402
8 11 12 45
PLACEMENT_NOTE=Place within 1 inch of CPU, no stub.
OUT
OUT
61 88
61 88
R1101
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA19
E6
AA25
E8
AB1
VSS
VSS
AA16
AA22
E14
=PP1V05_S0_CPU
E9
W1
E3
E11
(CPU IO POWER 1.05V)
y
r
B6
AC12
FCBGA
A15
OMIT
A11
=PPVCORE_S0_CPU
AB4
AB8
E16
AB11
E19
AB13
E21
AB16
E24
AB19
F5
AB23
F8
AB26
F11
AC3
F13
AC6
F16
AC8
F19
AC11
F2
AC14
F22
AC16
F25
AC19
G4
AC21
G1
AC24
G23
AD2
G26
AD5
H3
AD8
H6
AD11
H21
AD13
H24
AD16
J2
AD19
J5
AD22
J22
AD25
J25
AE1
K1
AE4
K4
AE8
K23
AE11
K26
AE14
L3
AE16
L6
AE19
L21
AE23
L24
AE26
M2
A2
M5
AF6
M22
AF8
M25
AF11
N1
AF13
100
1%
1/16W
MF-LF
2 402
PLACEMENT_NOTE=Place within 1 inch of CPU, no stub.
N4
AF16
N23
AF19
N26
AF21
P3
A25
B1
AF25
CPU Power & Ground

SYNC_MASTER=M98_MLB

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
Current numbers from Merom for Santa Rosa EMTS, doc #22221.
REV.
051-7656
31
OF
11
123
y
r
CPU VCORE HF AND BULK DECOUPLING

45 11 8
=PPVCORE_S0_CPU
a
n
i
4x 330uF, 20x 22uF 0805
CRITICAL
C1250
CRITICAL
1
C1251
330UF
20%
2.0V
POLY-TANT
D2T-SM2
CRITICAL
1
20%
2.0V
POLY-TANT
D2T-SM2
CRITICAL
CRITICAL
C1200
22UF
330UF
C1201
20%
6.3V
X5R-CERM
603
22UF
20%
6.3V
X5R-CERM
603
C1203
CRITICAL
C1204
22UF
20%
6.3V
X5R-CERM
603
CRITICAL
CRITICAL
C1202
22UF
C1205
22UF
20%
6.3V
X5R-CERM
603
20%
6.3V
X5R-CERM
603
CRITICAL
1
22UF
CRITICAL
1
22UF
20%
6.3V
X5R-CERM
603
C1206
20%
6.3V
X5R-CERM
603
C1207
CRITICAL
1
22UF
2
20%
6.3V
X5R-CERM
603
CRITICAL
C1208
22UF
2
C1209
22UF
20%
6.3V
X5R-CERM
603
20%
6.3V
X5R-CERM
603
PLACEMENT_NOTE=Place in CPU center cavity.

CRITICAL
C1252
C1253
330UF
20%
2.0V
POLY-TANT
D2T-SM2
CRITICAL
CRITICAL
1
22UF
330UF
2
20%
2.0V
POLY-TANT
D2T-SM2
C1211
C1212
22UF
20%
6.3V
X5R-CERM
603
CRITICAL
CRITICAL
CRITICAL
C1210
22UF
20%
6.3V
X5R-CERM
603
22UF
20%
6.3V
X5R-CERM
603
CRITICAL
CRITICAL
C1213
C1214
C1215
22UF
20%
6.3V
X5R-CERM
603
CRITICAL
1
22UF
20%
6.3V
X5R-CERM
603
CRITICAL
1
22UF
20%
6.3V
X5R-CERM
603
C1216
20%
6.3V
X5R-CERM
603
C1217
CRITICAL
1
22UF
2
20%
6.3V
X5R-CERM
603
CRITICAL
C1218
22UF
2
C1219
22UF
20%
6.3V
X5R-CERM
603
20%
6.3V
X5R-CERM
603

VCCP (CPU I/O) DECOUPLING

61 13 11 10 8 6
=PP1V05_S0_CPU
m
il
1x 470uF, 6x 0.1uF 0402
CRITICAL
C1235
20%
2.5V
POLY
D2T
C1236
0.1UF
470UF
2
20%
10V
CERM
402
C1237
0.1UF
2
20%
10V
CERM
402
C1238
0.1UF
2
C1239
0.1UF
20%
10V
CERM
402
20%
10V
CERM
402
C1240
0.1UF
2
20%
10V
CERM
402
C1241
0.1UF
20%
10V
CERM
402
WF: Consider sharing bulk cap with NB Vtt?
e
r
VCCA (CPU AVdd) DECOUPLING
B
11 8
=PP1V5_S0_CPU
1x 10uF, 1x 0.01uF
C1280
10uF
20%
6.3V
X5R
603
C1281
0.01UF
10%
16V
CERM
402
PLACEMENT_NOTE=Place near CPU pin B26.
CPU Decoupling & VID

SYNC_MASTER=M98_MLB

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
12
123
Mini-XDP Connector
NOTE: This is not the standard XDP pinout.
Use with 920-0620 adapter board to support CPU, MCP debugging.
y
r
MCP79-specific pinout
8 6
61 12 11 10 8 6
=PP3V3_S0_XDP
=PP1V05_S0_CPU
XDP
CRITICAL
XDP_CONN
R1315 1
54.9
88 10
BI
88 10
BI
88 10
BI
LTH-030-01-G-D-NOPEGS
F-ST-SM
2
XDP_BPM_L<5>
XDP_BPM_L<4>
OBSFN_A0
OBSFN_A1
XDP_BPM_L<3>
XDP_BPM_L<2>
OBSDATA_A0
OBSDATA_A1
10
12
11
14
13
16
15
18
17
20
19
22
21
24
23
26
25
28
27
30
29
32
31
34
33
36
35
88 10
IN
88 10
IN
88 10
IN
XDP_BPM_L<1>
XDP_BPM_L<0>
OBSDATA_A2
OBSDATA_A3
TP_XDP_OBSFN_B0
TP_XDP_OBSFN_B1
OBSFN_B0
OBSFN_B1
TP_XDP_OBSDATA_B0
TP_XDP_OBSDATA_B1
7
XDP
OBSDATA_B0
OBSDATA_B1
TP_XDP_OBSDATA_B2
TP_XDP_OBSDATA_B3
OBSDATA_B2
OBSDATA_B3
88 14 10
IN
CPU_PWRGD
XDP_PWRGD
XDP_OBS20
5%
1/16W
MF-LF
402
19
21 6
IN
OUT
91 44 21 7
BI
91 44 21 7
BI
88 10 6
OUT
OBSFN_C0
OBSFN_C1
PM_LATRIGGER_L
JTAG_MCP_TCK
SMBUS_MCP_0_DATA
SMBUS_MCP_0_CLK
PWRGD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
SDA
SCL
TCK1
TCK0
XDP_TCK
NC
38
37
40
39
42
41
44
43
46
45
48
47
50
49
52
51
54
53
56
55
58
57
60
59
e
r
0.1uF
10%
16V
X5R
402
IN
OUT
6 21
MCP_DEBUG<0>
MCP_DEBUG<1>
BI
19 91
BI
19 91
OBSDATA_C2
OBSDATA_C3
MCP_DEBUG<2>
MCP_DEBUG<3>
BI
19 91
OBSFN_D0
OBSFN_D1
JTAG_MCP_TDI
JTAG_MCP_TMS
OUT
6 21
OUT
6 21
OBSDATA_D0
OBSDATA_D1
MCP_DEBUG<4>
MCP_DEBUG<5>
BI
19 91
BI
19 91
OBSDATA_D2
OBSDATA_D3
MCP_DEBUG<6>
MCP_DEBUG<7>
BI
19 91
BI
19 91
FSB_CLK_ITP_P
ITPCLK/HOOK4
FSB_CLK_ITP_N
ITPCLK#/HOOK5
VCC_OBS_CD
88 XDP_CPURST_L
RESET#/HOOK6
XDP_DBRESET_L
DBR#/HOOK7
NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.
XDP_TDO_CONN
TDO
XDP_TRST_L
TRSTn
XDP_TDI
TDI
XDP_TMS
TMS
XDP_PRESENT#
XDP
XDP
C1300
JTAG_MCP_TDO_CONN
JTAG_MCP_TRST_L
OBSDATA_C0
OBSDATA_C1
m
il
R1399
1K
a
n
i
J1300
1%
1/16W
MF-LF
402 2
BI
19 91
IN
14 88
IN
14 88
OUT
10 25
IN
XDP
R1303
1
1K
5%
1/16W
MF-LF
402
FSB_CPURST_L
IN
9 10 14 88
PLACEMENT_NOTE=Place close to CPU to minimize stub.
OUT
6 10 88
OUT
6 10 88
OUT
6 10 88
C1301
0.1uF
10%
16V
X5R
402
998-1571
Direction of XDP module
Please avoid any obstructions

on even-numbered side of J1300
eXtended Debug Port(MiniXDP)

SYNC_MASTER=M98_MLB

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
13
123
OMIT
U1400
MCP79-TOPO-B
BGA
(1 OF 11)
BI
88 10 7
BI
88 10 7
88 10 7
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10
BI
88 10
BI
88 10
BI
88 10 7
88 10 7
R1410 1
R1415 1
54.9
62
1%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
BI
BI
88 10 7
BI
BI
88 10
IN
IN
88 10 7
88 10
88 10 9
PM_THRMTRIP_L
CPU_FERR_L
88 10 7
BI
BI
BI
R1420
IN
IN
IN
=MCP_BSEL<2>
=MCP_BSEL<1>
=MCP_BSEL<0>
NO STUFF
R1421
1K
1K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
NO STUFF
R1422
1K
5%
1/16W
MF-LF
402
R1430
R1435
49.9
49.9
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
NO STUFF
IN
88 10
OUT
OUT
88 61 42 10
OUT
FSB_DSTB_L_P<3>
FSB_DSTB_L_N<3>
FSB_DINV_L<3>
M39
V35
L36
N35
M41
J41
AC34
AE38
AE34
AC37
AE37
AE35
AB35
AF35
AG35
AG39
AE33
AG37
AG38
AG34
AN38
AL39
AG33
AL33
AJ33
AN36
AJ35
AJ37
AJ36
AJ38
AL37
AL34
AN37
AJ34
FSB_ADS_L
FSB_BNR_L
FSB_BREQ0_L
FSB_BREQ1_L
FSB_DBSY_L
FSB_DRDY_L
FSB_HIT_L
FSB_HITM_L
FSB_LOCK_L
FSB_TRDY_L
88 10
OUT
88 10
OUT
88 10
OUT
23
AL35
AN34
AR39
AN35
AE36
AK35
AC38
AA33
AC39
AC33
AC35
AD42
AD43
AE40
AL32
AD39
AD41
AB42
AD40
AC43
AE41
E41
AJ41
AG43
AH40
F42
88
D42
F41
49.9
1%
1/16W
MF-LF
402
CPU_DSTBP1#
CPU_DSTBN1#
CPU_DBI1#
CPU_DSTBP2#
CPU_DSTBN2#
CPU_DBI2#
CPU_DSTBP3#
CPU_DSTBN3#
CPU_DBI3#
CPU_A3#
CPU_A4#
CPU_A5#
CPU_A6#
CPU_A7#
CPU_A8#
CPU_A9#
CPU_A10#
CPU_A11#
CPU_A12#
CPU_A13#
CPU_A14#
CPU_A15#
CPU_A16#
CPU_A17#
CPU_A18#
CPU_A19#
CPU_A20#
CPU_A21#
CPU_A22#
CPU_A23#
CPU_A24#
CPU_A25#
CPU_A26#
CPU_A27#
CPU_A28#
CPU_A29#
CPU_A30#
CPU_A31#
CPU_A32#
CPU_A33#
CPU_A34#
CPU_A35#
CPU_D0#
CPU_D1#
CPU_D2#
CPU_D3#
CPU_D4#
CPU_D5#
CPU_D6#
CPU_D7#
CPU_D8#
CPU_D9#
CPU_D10#
CPU_D11#
CPU_D12#
CPU_D13#
CPU_D14#
CPU_D15#
CPU_D16#
CPU_D17#
CPU_D18#
CPU_D19#
CPU_D20#
CPU_D21#
CPU_D22#
CPU_D23#
CPU_D24#
CPU_D25#
CPU_D26#
CPU_D27#
CPU_D28#
CPU_D29#
CPU_D30#
CPU_D31#
CPU_D32#
CPU_D33#
CPU_D34#
CPU_D35#
CPU_D36#
CPU_D37#
CPU_D38#
CPU_D39#
CPU_D40#
CPU_D41#
CPU_D42#
CPU_D43#
CPU_D44#
CPU_D45#
CPU_D46#
CPU_D47#
CPU_D48#
CPU_D49#
CPU_D50#
CPU_D51#
CPU_D52#
CPU_D53#
CPU_D54#
CPU_D55#
CPU_D56#
CPU_D57#
CPU_D58#
CPU_D59#
CPU_D60#
CPU_D61#
CPU_D62#
CPU_D63#
FSB_D_L<0>
FSB_D_L<1>
FSB_D_L<2>
FSB_D_L<3>
FSB_D_L<4>
FSB_D_L<5>
FSB_D_L<6>
FSB_D_L<7>
FSB_D_L<8>
FSB_D_L<9>
FSB_D_L<10>
FSB_D_L<11>
FSB_D_L<12>
FSB_D_L<13>
FSB_D_L<14>
FSB_D_L<15>
FSB_D_L<16>
FSB_D_L<17>
FSB_D_L<18>
FSB_D_L<19>
FSB_D_L<20>
FSB_D_L<21>
FSB_D_L<22>
FSB_D_L<23>
FSB_D_L<24>
FSB_D_L<25>
FSB_D_L<26>
FSB_D_L<27>
FSB_D_L<28>
FSB_D_L<29>
FSB_D_L<30>
FSB_D_L<31>
FSB_D_L<32>
FSB_D_L<33>
FSB_D_L<34>
FSB_D_L<35>
FSB_D_L<36>
FSB_D_L<37>
FSB_D_L<38>
FSB_D_L<39>
FSB_D_L<40>
FSB_D_L<41>
FSB_D_L<42>
FSB_D_L<43>
FSB_D_L<44>
FSB_D_L<45>
FSB_D_L<46>
FSB_D_L<47>
FSB_D_L<48>
FSB_D_L<49>
FSB_D_L<50>
FSB_D_L<51>
FSB_D_L<52>
FSB_D_L<53>
FSB_D_L<54>
FSB_D_L<55>
FSB_D_L<56>
FSB_D_L<57>
FSB_D_L<58>
FSB_D_L<59>
FSB_D_L<60>
FSB_D_L<61>
FSB_D_L<62>
FSB_D_L<63>
Y43
W42
Y40
W41
Y39
V42
Y41
Y42
P42
U41
R42
T39
T42
T41
R41
T43
W35
AA37
W33
W34
AA36
AA38
AA35
U38
U36
U35
U33
U34
W38
R33
U37
N34
N33
R34
R35
P35
R39
R37
R38
L37
L39
CPU_ADSTB0#
CPU_ADSTB1#
CPU_REQ0#
CPU_REQ1#
CPU_REQ2#
CPU_REQ3#
CPU_REQ4#
CPU_ADS#
CPU_BNR#
CPU_BR0#
CPU_BR1#
CPU_DBSY#
CPU_DRDY#
CPU_HIT#
CPU_HITM#
CPU_LOCK#
CPU_TRDY#
CPU_PECI
CPU_PROCHOT#
CPU_THERMTRIP#
CPU_FERR#
CPU_BSEL2
CPU_BSEL1
CPU_BSEL0
CPU_BPRI#
CPU_DEFER#
N36
N38
J39
J38
J37
L42
M42
P41
N41
N40
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
y
r
a
n
i
AA34
L38
BI
M40
H40
K42
H41
L41
H43
H42
K41
J40
H39
M43
AA41
AA40
BCLK_OUT_CPU_P
BCLK_OUT_CPU_N
G42
BCLK_OUT_ITP_P
BCLK_OUT_ITP_N
AL43
BCLK_OUT_NB_P
BCLK_OUT_NB_N
AL41
88
AK42
88
BCLK_IN_N
BCLK_IN_P
AK41
G41
AL42
FSB_BPRI_L
FSB_DEFER_L
OUT
10 88
OUT
10 88
FSB_CLK_CPU_P
FSB_CLK_CPU_N
OUT
10 88
OUT
10 88
FSB_CLK_ITP_P
FSB_CLK_ITP_N
OUT
13 88
OUT
13 88
FSB_CLK_MCP_P
FSB_CLK_MCP_N
Loop-back clock for delay matching.
FSB_RS_L<0>
FSB_RS_L<1>
FSB_RS_L<2>
AC41
AB41
AC42
CPU_RS0#
CPU_RS1#
CPU_RS2#
PP1V05_S0_MCP_PLL_FSB
270 mA (A01)
88
CPU_DSTBP0#
CPU_DSTBN0#
CPU_DBI0#
m
il
AL38
(MCP_BSEL<2>)
(MCP_BSEL<1>)
(MCP_BSEL<0>)
88
1%
1/16W
MF-LF
402
N37
W37
206
20
29
15
mA
mA
mA
mA
MCP_BCLK_VML_COMP_VDD
MCP_BCLK_VML_COMP_GND
AG27
AH27
AG28
AH28
AM39
AM40
MCP_CPU_COMP_VCC
MCP_CPU_COMP_GND
AM43
AM42
R1436
49.9
FSB_DSTB_L_P<2>
FSB_DSTB_L_N<2>
FSB_DINV_L<2>
CPU_PECI_MCP
CPU_PROCHOT_L
88
R1431 1
W39
e
r
5%
1/16W
MF-LF
402
88
88 42 10
V41
FSB_DSTB_L_P<1>
FSB_DSTB_L_N<1>
FSB_DINV_L<1>
FSB_REQ_L<0>
FSB_REQ_L<1>
FSB_REQ_L<2>
FSB_REQ_L<3>
FSB_REQ_L<4>
BI
BI
U40
FSB_ADSTB_L<0>
FSB_ADSTB_L<1>
BI
88 10 7
88 10 7
R1416
62
BI
88 10 7
T40
FSB_A_L<3>
FSB_A_L<4>
FSB_A_L<5>
FSB_A_L<6>
FSB_A_L<7>
FSB_A_L<8>
FSB_A_L<9>
FSB_A_L<10>
FSB_A_L<11>
FSB_A_L<12>
FSB_A_L<13>
FSB_A_L<14>
FSB_A_L<15>
FSB_A_L<16>
FSB_A_L<17>
FSB_A_L<18>
FSB_A_L<19>
FSB_A_L<20>
FSB_A_L<21>
FSB_A_L<22>
FSB_A_L<23>
FSB_A_L<24>
FSB_A_L<25>
FSB_A_L<26>
FSB_A_L<27>
FSB_A_L<28>
FSB_A_L<29>
FSB_A_L<30>
FSB_A_L<31>
FSB_A_L<32>
FSB_A_L<33>
FSB_A_L<34>
FSB_A_L<35>
BI
88 10 7
88 10 7
=PP1V05_S0_MCP_FSB
BI
BI
88 10
23 22 14 9 8
BI
88 10 7
88 10 7
FSB_DSTB_L_P<0>
FSB_DSTB_L_N<0>
FSB_DINV_L<0>
FSB
88 10 7
+V_DLL_DLCELL_AVDD
+V_PLL_MCLK
+V_PLL_FSB
+V_PLL_CPU
BCLK_VML_COMP_VDD
BCLK_VML_COMP_GND
CPU_COMP_VCC
CPU_COMP_GND
CPU_A20M#
CPU_IGNNE#
CPU_INIT#
CPU_INTR
CPU_NMI
CPU_SMI#
CPU_PWRGD
CPU_RESET#
CPU_SLP#
CPU_DPSLP#
CPU_DPWR#
CPU_STPCLK#
CPU_DPRSTP#
AJ40
AF41
AH39
AH42
AF42
AG41
AH41
AH43
H38
AM33
AN33
AM32
AG42
AN32
CPU_A20M_L
CPU_IGNNE_L
CPU_INIT_L
CPU_INTR
CPU_NMI
CPU_SMI_L
CPU_PWRGD
FSB_CPURST_L
FSB_CPUSLP_L
CPU_DPSLP_L
FSB_DPWR_L
CPU_STPCLK_L
CPU_DPRSTP_L
OUT
10 88
OUT
10 88
OUT
10 88
OUT
9 10 88
OUT
9 10 88
OUT
10 88
=PP1V05_S0_MCP_FSB
8 9 14 22 23
NO STUFF
1
R1440
150
OUT
OUT
9 10 13 88
OUT
10 88
OUT
10 88
OUT
10 88
OUT
10 88
OUT
9 10 61 88
MCP CPU Interface
5%
1/16W
MF-LF
402
SYNC_MASTER=T18_MLB
10 13 88

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
REV.
051-7656
31
OF
14
123
OMIT
U1400
MCP79-TOPO-B
MCP79-TOPO-B
BGA
BGA
(2 OF 11)
BI
89 27
BI
89 27
BI
89 27
BI
89 27
BI
89 27
BI
89 27
BI
89 27
BI
89 27
BI
89 27
BI
89 27
BI
BI
89 27
BI
89 27
BI
89 27
BI
89 27
BI
89 27
BI
89 27
BI
89 27
BI
89 27
BI
89 27
BI
89 27
BI
89 27
BI
89 27
BI
89 27
BI
89 27
BI
89 27
BI
89 27
BI
89 27
BI
89 27
BI
89 27
BI
89 27
BI
89 27
BI
89 27
BI
89 27
BI
89 27
89 27
89 27
BI
BI
BI
89 27
BI
89 27
BI
89 27
BI
89 27
BI
89 27
BI
89 27
BI
89 27
BI
89 27
BI
89 27
BI
89 27
BI
89 27
BI
89 27
89 27
BI
89 27
BI
89 27
BI
89 27
BI
89 27
BI
89 27
BI
89 27
BI
89 27
BI
89 27
BI
89 27
BI
89 27
BI
89 27
BI
89 27
BI
89 27
BI
89 27
BI
89 27
OUT
89 27
OUT
89 27
OUT
89 27
OUT
89 27
OUT
89 27
OUT
89 27
OUT
89 27
OUT
MEM_A_DQ<63>
MEM_A_DQ<62>
MEM_A_DQ<61>
MEM_A_DQ<60>
MEM_A_DQ<59>
MEM_A_DQ<58>
MEM_A_DQ<57>
MEM_A_DQ<56>
MEM_A_DQ<55>
MEM_A_DQ<54>
MEM_A_DQ<53>
MEM_A_DQ<52>
MEM_A_DQ<51>
MEM_A_DQ<50>
MEM_A_DQ<49>
MEM_A_DQ<48>
MEM_A_DQ<47>
MEM_A_DQ<46>
MEM_A_DQ<45>
MEM_A_DQ<44>
MEM_A_DQ<43>
MEM_A_DQ<42>
MEM_A_DQ<41>
MEM_A_DQ<40>
MEM_A_DQ<39>
MEM_A_DQ<38>
MEM_A_DQ<37>
MEM_A_DQ<36>
MEM_A_DQ<35>
MEM_A_DQ<34>
MEM_A_DQ<33>
MEM_A_DQ<32>
MEM_A_DQ<31>
MEM_A_DQ<30>
MEM_A_DQ<29>
MEM_A_DQ<28>
MEM_A_DQ<27>
MEM_A_DQ<26>
MEM_A_DQ<25>
MEM_A_DQ<24>
MEM_A_DQ<23>
MEM_A_DQ<22>
MEM_A_DQ<21>
MEM_A_DQ<20>
MEM_A_DQ<19>
MEM_A_DQ<18>
MEM_A_DQ<17>
MEM_A_DQ<16>
MEM_A_DQ<15>
MEM_A_DQ<14>
MEM_A_DQ<13>
MEM_A_DQ<12>
MEM_A_DQ<11>
MEM_A_DQ<10>
MEM_A_DQ<9>
MEM_A_DQ<8>
MEM_A_DQ<7>
MEM_A_DQ<6>
MEM_A_DQ<5>
MEM_A_DQ<4>
MEM_A_DQ<3>
MEM_A_DQ<2>
MEM_A_DQ<1>
MEM_A_DQ<0>
AL8
AL9
AP9
AN9
AL6
AL7
AN6
AN7
AR6
AR7
AV6
AW5
AN10
AR5
AU6
AV5
AU7
AU8
AW9
AP11
AW6
AY5
AU9
AV9
AU11
AV11
AV13
AW13
AR11
AT11
AR14
AU13
AR26
AU25
AT27
AU27
AP25
AR25
AP27
AR27
AP29
AR29
AP31
AR31
AV27
AN29
AV29
AN31
AU31
AR33
AV37
AW37
AT31
AV31
AT37
AU37
AW39
AV39
AR37
AR38
AV38
AW38
AR35
AP35
MEM_A_DM<7>
MEM_A_DM<6>
MEM_A_DM<5>
MEM_A_DM<4>
MEM_A_DM<3>
MEM_A_DM<2>
MEM_A_DM<1>
MEM_A_DM<0>
AN5
AU5
AR10
AN13
AN27
AW29
AV35
AR34
MDQ0_63
MDQ0_62
MDQ0_61
MDQ0_60
MDQ0_59
MDQ0_58
MDQ0_57
MDQ0_56
MDQ0_55
MDQ0_54
MDQ0_53
MDQ0_52
MDQ0_51
MDQ0_50
MDQ0_49
MDQ0_48
MDQ0_47
MDQ0_46
MDQ0_45
MDQ0_44
MDQ0_43
MDQ0_42
MDQ0_41
MDQ0_40
MDQ0_39
MDQ0_38
MDQ0_37
MDQ0_36
MDQ0_35
MDQ0_34
MDQ0_33
MDQ0_32
MDQ0_31
MDQ0_30
MDQ0_29
MDQ0_28
MDQ0_27
MDQ0_26
MDQ0_25
MDQ0_24
MDQ0_23
MDQ0_22
MDQ0_21
MDQ0_20
MDQ0_19
MDQ0_18
MDQ0_17
MDQ0_16
MDQ0_15
MDQ0_14
MDQ0_13
MDQ0_12
MDQ0_11
MDQ0_10
MDQ0_9
MDQ0_8
MDQ0_7
MDQ0_6
MDQ0_5
MDQ0_4
MDQ0_3
MDQ0_2
MDQ0_1
MDQ0_0
MDQM0_7
MDQM0_6
MDQM0_5
MDQM0_4
MDQM0_3
MDQM0_2
MDQM0_1
MDQM0_0
(3 OF 11)
MDQS0_7_P
MDQS0_7_N
MDQS0_6_P
MDQS0_6_N
MDQS0_5_P
MDQS0_5_N
MDQS0_4_P
MDQS0_4_N
MDQS0_3_P
MDQS0_3_N
MDQS0_2_P
MDQS0_2_N
MDQS0_1_P
MDQS0_1_N
MDQS0_0_P
MDQS0_0_N
MEMORY PARTITION 0
89 27
OMIT
U1400
MEM_A_DQS_P<7>
MEM_A_DQS_N<7>
MEM_A_DQS_P<6>
MEM_A_DQS_N<6>
MEM_A_DQS_P<5>
MEM_A_DQS_N<5>
MEM_A_DQS_P<4>
MEM_A_DQS_N<4>
MEM_A_DQS_P<3>
MEM_A_DQS_N<3>
MEM_A_DQS_P<2>
MEM_A_DQS_N<2>
MEM_A_DQS_P<1>
MEM_A_DQS_N<1>
MEM_A_DQS_P<0>
MEM_A_DQS_N<0>
AL10
AL11
AR8
AR9
AW7
AW8
AP13
AR13
AV25
AW25
AU30
AU29
AT35
AU35
AU39
AT39
BI
27 89
89 28
BI
BI
27 89
89 28
BI
BI
27 89
89 28
BI
27 89
89 28
BI
BI
27 89
89 28
BI
BI
27 89
89 28
BI
BI
27 89
89 28
BI
BI
27 89
89 28
BI
BI
27 89
89 28
BI
BI
27 89
89 28
BI
27 89
89 28
BI
BI
27 89
89 28
BI
BI
27 89
89 28
BI
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L
AV17
AP17
AR17
27 89
89 28
BI
27 89
89 28
BI
BI
27 89
89 28
BI
89 28
BI
OUT
27 89
OUT
27 89
OUT
27 89
MA0_14
MA0_13
MA0_12
MA0_11
MA0_10
MA0_9
MA0_8
MA0_7
MA0_6
MA0_5
MA0_4
MA0_3
MA0_2
MA0_1
MA0_0
MEM_A_BA<2>
MEM_A_BA<1>
MEM_A_BA<0>
AP23
AP19
AW17
AU15
AN23
AW21
AN19
AV21
AR22
AU21
AP21
AR21
AN21
AV19
AU19
AT19
AR19
AV33
BA24
MCLK0A_0_P
MCLK0A_0_N
BB20
MCS0A_1#
MCS0A_0#
TP_MEM_A_CLK2P
TP_MEM_A_CLK2N
AW33
MCLK0A_1_P
MCLK0A_1_N
AY24
BC20
AT15
P
MODT0A_1
MODT0A_0
MCKE0A_1
MCKE0A_0
AR18
AP15
AV15
AU23
AT23
OUT
27 89
OUT
27 89
OUT
27 89
OUT
27 89
OUT
27 89
OUT
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
OUT
27 89
OUT
27 89
OUT
27 89
OUT
27 89
OUT
27 89
OUT
27 89
OUT
m
il
27 89
OUT
27 89
OUT
27 89
OUT
27 89
7
7
MEM_A_CLK_P<1>
MEM_A_CLK_N<1>
OUT
27 89
OUT
27 89
MEM_A_CLK_P<0>
MEM_A_CLK_N<0>
OUT
27 89
OUT
27 89
MEM_A_CS_L<1>
MEM_A_CS_L<0>
MEM_A_ODT<1>
MEM_A_ODT<0>
MEM_A_CKE<1>
MEM_A_CKE<0>
OUT
27 89
OUT
27 89
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
27 89
BI
AT4
AT3
AV2
AV3
AR4
AR3
AU2
AU3
AY4
AY3
BB3
BC3
AW4
AW3
BA3
BB2
BB5
BA5
MDQ1_63
MDQ1_62
MDQ1_61
MDQ1_60
MDQ1_59
MDQ1_58
MDQ1_57
MDQ1_56
MDQ1_55
MDQ1_54
MDQ1_53
MDQ1_52
MDQ1_51
MDQ1_50
MDQ1_49
MDQ1_48
MDQ1_47
MDQ1_46
MDQ1_45
MDQ1_44
MDQ1_43
MDQ1_42
MDQ1_41
MDQ1_40
MDQ1_39
MDQ1_38
MDQ1_37
MDQ1_36
MDQ1_35
MDQ1_34
MDQ1_33
MDQ1_32
MDQ1_31
MDQ1_30
MDQ1_29
MDQ1_28
MDQ1_27
MDQ1_26
MDQ1_25
MDQ1_24
MDQ1_23
MDQ1_22
MDQ1_21
MDQ1_20
MDQ1_19
MDQ1_18
MDQ1_17
MDQ1_16
MDQ1_15
MDQ1_14
MDQ1_13
MDQ1_12
MDQ1_11
MDQ1_10
MDQ1_9
MDQ1_8
MDQ1_7
MDQ1_6
MDQ1_5
MDQ1_4
MDQ1_3
MDQ1_2
MDQ1_1
MDQ1_0
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
OUT
89 28
OUT
89 28
OUT
OUT
27 89
89 28
OUT
OUT
27 89
89 28
OUT
89 28
OUT
OUT
27 89
89 28
OUT
OUT
27 89
89 28
OUT
BA8
BC8
BB4
BC4
BA7
AY8
BA9
BB10
BB12
AW12
BB8
BB9
AY12
BA12
BC32
AW32
BA35
AY36
BA32
BB32
BA34
AY35
BC36
AW36
BA39
AY40
BA36
BB36
BA38
AY39
BB40
AW40
AV42
AV41
BA40
BC40
AW42
AW41
AT40
AT41
AP41
AN40
AU40
AU41
AR41
AP42
MEM_B_DM<7>
MEM_B_DM<6>
MEM_B_DM<5>
MEM_B_DM<4>
MEM_B_DM<3>
MEM_B_DM<2>
MEM_B_DM<1>
MEM_B_DM<0>
AT5
BA2
AY7
BA11
BB34
BB38
AY43
AR42
MDQS1_7_P
MDQS1_7_N
MDQS1_6_P
MDQS1_6_N
MDQS1_5_P
MDQS1_5_N
MDQS1_4_P
MDQS1_4_N
MDQS1_3_P
MDQS1_3_N
MDQS1_2_P
MDQS1_2_N
MDQS1_1_P
MDQS1_1_N
MDQS1_0_P
MDQS1_0_N
MEM_B_DQS_P<7>
MEM_B_DQS_N<7>
MEM_B_DQS_P<6>
MEM_B_DQS_N<6>
MEM_B_DQS_P<5>
MEM_B_DQS_N<5>
MEM_B_DQS_P<4>
MEM_B_DQS_N<4>
MEM_B_DQS_P<3>
MEM_B_DQS_N<3>
MEM_B_DQS_P<2>
MEM_B_DQS_N<2>
MEM_B_DQS_P<1>
MEM_B_DQS_N<1>
MEM_B_DQS_P<0>
MEM_B_DQS_N<0>
AT2
AT1
AY2
AY1
BB6
BA6
BA10
y
r
a
n
i
27 89
e
r
MEMORY
CONTROL
0A
MCLK0A_2_P
MCLK0A_2_N
27 89
OUT
MEM_A_A<14>
MEM_A_A<13>
MEM_A_A<12>
MEM_A_A<11>
MEM_A_A<10>
MEM_A_A<9>
MEM_A_A<8>
MEM_A_A<7>
MEM_A_A<6>
MEM_A_A<5>
MEM_A_A<4>
MEM_A_A<3>
MEM_A_A<2>
MEM_A_A<1>
MEM_A_A<0>
AR23
OUT
BI
89 28
89 28
MBA0_2
MBA0_1
MBA0_0
BI
BI
89 28
MRAS0#
MCAS0#
MWE0#
BI
MEM_B_DQ<63>
MEM_B_DQ<62>
MEM_B_DQ<61>
MEM_B_DQ<60>
MEM_B_DQ<59>
MEM_B_DQ<58>
MEM_B_DQ<57>
MEM_B_DQ<56>
MEM_B_DQ<55>
MEM_B_DQ<54>
MEM_B_DQ<53>
MEM_B_DQ<52>
MEM_B_DQ<51>
MEM_B_DQ<50>
MEM_B_DQ<49>
MEM_B_DQ<48>
MEM_B_DQ<47>
MEM_B_DQ<46>
MEM_B_DQ<45>
MEM_B_DQ<44>
MEM_B_DQ<43>
MEM_B_DQ<42>
MEM_B_DQ<41>
MEM_B_DQ<40>
MEM_B_DQ<39>
MEM_B_DQ<38>
MEM_B_DQ<37>
MEM_B_DQ<36>
MEM_B_DQ<35>
MEM_B_DQ<34>
MEM_B_DQ<33>
MEM_B_DQ<32>
MEM_B_DQ<31>
MEM_B_DQ<30>
MEM_B_DQ<29>
MEM_B_DQ<28>
MEM_B_DQ<27>
MEM_B_DQ<26>
MEM_B_DQ<25>
MEM_B_DQ<24>
MEM_B_DQ<23>
MEM_B_DQ<22>
MEM_B_DQ<21>
MEM_B_DQ<20>
MEM_B_DQ<19>
MEM_B_DQ<18>
MEM_B_DQ<17>
MEM_B_DQ<16>
MEM_B_DQ<15>
MEM_B_DQ<14>
MEM_B_DQ<13>
MEM_B_DQ<12>
MEM_B_DQ<11>
MEM_B_DQ<10>
MEM_B_DQ<9>
MEM_B_DQ<8>
MEM_B_DQ<7>
MEM_B_DQ<6>
MEM_B_DQ<5>
MEM_B_DQ<4>
MEM_B_DQ<3>
MEM_B_DQ<2>
MEM_B_DQ<1>
MEM_B_DQ<0>
MDQM1_7
MDQM1_6
MDQM1_5
MDQM1_4
MDQM1_3
MDQM1_2
MDQM1_1
MDQM1_0
MEMORY PARTITION 1
AY11
BB33
BA33
BB37
BA37
BA43
AY42
AT42
AT43
MRAS1#
MCAS1#
MWE1#
AW16
MBA1_2
MBA1_1
MBA1_0
BB29
MA1_14
MA1_13
MA1_12
MA1_11
MA1_10
MA1_9
MA1_8
MA1_7
MA1_6
MA1_5
MA1_4
MA1_3
MA1_2
MA1_1
MA1_0
BA29
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
BA15
BA16
MEM_B_BA<2>
MEM_B_BA<1>
MEM_B_BA<0>
BB18
BB17
MEM_B_A<14>
MEM_B_A<13>
MEM_B_A<12>
MEM_B_A<11>
MEM_B_A<10>
MEM_B_A<9>
MEM_B_A<8>
MEM_B_A<7>
MEM_B_A<6>
MEM_B_A<5>
MEM_B_A<4>
MEM_B_A<3>
MEM_B_A<2>
MEM_B_A<1>
MEM_B_A<0>
BA14
AW28
BC28
BA17
BB28
AY28
BA28
AY27
BA27
BA26
BB26
BA25
BB25
BA18
BI
28 89
BI
28 89
BI
28 89
BI
28 89
BI
28 89
BI
28 89
BI
28 89
BI
28 89
BI
28 89
BI
28 89
BI
28 89
BI
28 89
BI
28 89
BI
28 89
BI
28 89
BI
28 89
OUT
28 89
OUT
28 89
OUT
28 89
OUT
28 89
OUT
28 89
OUT
28 89
OUT
28 89
OUT
28 89
OUT
28 89
OUT
28 89
OUT
28 89
OUT
28 89
OUT
28 89
OUT
28 89
OUT
28 89
OUT
28 89
OUT
28 89
OUT
28 89
OUT
28 89
OUT
28 89
OUT
28 89
MEMORY
CONTROL
1A
MCLK1A_2_P
MCLK1A_2_N
BA42
MCLK1A_1_P
MCLK1A_1_N
BB22
MCLK1A_0_P
MCLK1A_0_N
BA19
MCS1A_1#
MCS1A_0#
BB14
MODT1A_1
MODT1A_0
BB13
MCKE1A_1
MCKE1A_0
AY31
TP_MEM_B_CLK2P
TP_MEM_B_CLK2N
BB42
BA22
AY19
BB16
AY15
BB30
MEM_B_CLK_P<1>
MEM_B_CLK_N<1>
OUT
28 89
OUT
28 89
MEM_B_CLK_P<0>
MEM_B_CLK_N<0>
OUT
28 89
OUT
28 89
MEM_B_CS_L<1>
MEM_B_CS_L<0>
OUT
28 89
OUT
28 89
MEM_B_ODT<1>
MEM_B_ODT<0>
OUT
28 89
OUT
28 89
MEM_B_CKE<1>
MEM_B_CKE<0>
OUT
28 89
OUT
28 89
MCP Memory Interface

SYNC_MASTER=T18_MLB

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
15
123
OMIT
U1400
MCP79-TOPO-B
BGA
7
7
7
7
7
7
7
7
7
7
23 16 8
23
AU33
TP_MEM_A_CLK4P
TP_MEM_A_CLK4N
BB24
TP_MEM_A_CLK3P
TP_MEM_A_CLK3N
BA21
TP_MEM_A_CS_L<2>
TP_MEM_A_CS_L<3>
AU17
TP_MEM_A_ODT<2>
TP_MEM_A_ODT<3>
AN17
TP_MEM_A_CKE<2>
TP_MEM_A_CKE<3>
AV23
AU34
BC24
BB21
AR15
AN15
AN25
MCLK0B_1_P
MCLK0B_1_N
MCLK0B_0_P
MCLK0B_0_N
MCS0B_0#
MCS0B_1#
MODT0B_0
MODT0B_1
MCKE0B_0
MCKE0B_1
17
12
19
39
R1610 1
40.2
89
mA
mA
mA
mA
T27
U28
U27
T28
+V_PLL_XREF_XS
+V_PLL_DP
+V_PLL_CORE
+V_VPLL
MCP_MEM_COMP_VDD
MCP_MEM_COMP_GND
AN41
AM41
40.2
AA22
AP12
2
G30
P10
T10
T6
V10
V34
AY23
MCLK1B_0_P
MCLK1B_0_N
BA20
MCS1B_0#
MCS1B_1#
BC16
MODT1B_0
MODT1B_1
AY16
MCKE1B_0
MCKE1B_1
BA30
MRESET0#
AY32
TP_MEM_B_CLK4P
TP_MEM_B_CLK4N
BA23
TP_MEM_B_CLK3P
TP_MEM_B_CLK3N
AY20
TP_MEM_B_CS_L<2>
TP_MEM_B_CS_L<3>
BA13
TP_MEM_B_ODT<2>
TP_MEM_B_ODT<3>
BC13
TP_MEM_B_CKE<2>
TP_MEM_B_CKE<3>
AA39
AB22
AB7
AD22
AE20
AF24
AG24
AH35
AK7
AM28
AT25
AP30
AR36
e
r
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
GND21
GND22
GND23
GND24
GND25
GND26
GND27
GND28
GND29
GND30
GND31
GND32
GND33
GND34
GND35
GND36
GND37
GND38
GND39
GND40
GND41
GND42
GND43
GND44
GND45
GND46
GND47
GND48
GND49
GND50
GND51
GND52
GND53
GND54
y
r
7
7
7
7
7
7
a
n
i
BA31
MCP_MEM_RESET_L
OUT
29
TP or NC for DDR2.
+VDD_MEM1
+VDD_MEM2
+VDD_MEM3
+VDD_MEM4
+VDD_MEM5
+VDD_MEM6
+VDD_MEM7
+VDD_MEM8
+VDD_MEM9
+VDD_MEM10
+VDD_MEM11
+VDD_MEM12
+VDD_MEM13
+VDD_MEM14
+VDD_MEM15
+VDD_MEM16
+VDD_MEM17
+VDD_MEM18
+VDD_MEM19
+VDD_MEM20
+VDD_MEM21
+VDD_MEM22
+VDD_MEM23
+VDD_MEM24
+VDD_MEM25
+VDD_MEM26
+VDD_MEM27
+VDD_MEM28
+VDD_MEM29
+VDD_MEM30
+VDD_MEM31
+VDD_MEM32
+VDD_MEM33
+VDD_MEM34
+VDD_MEM35
+VDD_MEM36
+VDD_MEM37
+VDD_MEM38
+VDD_MEM39
+VDD_MEM40
+VDD_MEM41
+VDD_MEM42
+VDD_MEM43
+VDD_MEM44
+VDD_MEM45
AM17
AM19
AM21
AM23
AM25
AM27
AM29
AN16
BC29
AN20
8 16 23
4771 mA (A01, DDR3)
m
il
W5
MCLK1B_1_P
MCLK1B_1_N
TP_MEM_B_CLK5P
TP_MEM_B_CLK5N
BB41
MEM_COMP_VDD
MEM_COMP_GND
R1611 1
1%
1/16W
MF-LF
402
BA41
2
89
MCLK1B_2_P
MCLK1B_2_N
PP1V05_S0_MCP_PLL_CORE
87 mA (A01)
1%
1/16W
MF-LF
402
MCLK0B_2_P
MCLK0B_2_N
MEMORY CONTROL 1B
TP_MEM_A_CLK5P
TP_MEM_A_CLK5N
MEMORY CONTROL 0B
(4 OF 11)
7
AU10
F28
BC21
AY9
BC9
D34
F24
G32
H31
K7
M38
M5
M6
M7
M9
N39
N8
P33
P34
P37
P4
P40
P7
R36
R40
R43
R5
T18
T20
AK11
T24
T26
GND55
GND56
GND57
GND58
GND59
GND60
GND61
GND62
GND63
GND64
AN24
AT17
AP16
AN22
AP20
AP24
AV16
AR16
AR20
AR24
AW15
AP22
AP18
AU16
AN18
AU24
AT21
AY29
AV24
AU20
AU22
AW27
BC17
AV20
AY17
AY18
AM15
AU18
AY25
AY26
AW19
AW24
BC25
AL30
AM31
T33
T34
T35
T37
T38
T7
MCP Memory Misc
T9
U18
SYNC_MASTER=T18_MLB
U20
U22

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
16
123
OMIT
U1400
MCP79-TOPO-B
BGA
(5 OF 11)
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
9
9
IN
=PEG_D2R_P<0>
=PEG_D2R_N<0>
=PEG_D2R_P<1>
=PEG_D2R_N<1>
=PEG_D2R_P<2>
=PEG_D2R_N<2>
=PEG_D2R_P<3>
=PEG_D2R_N<3>
=PEG_D2R_P<4>
=PEG_D2R_N<4>
=PEG_D2R_P<5>
=PEG_D2R_N<5>
=PEG_D2R_P<6>
=PEG_D2R_N<6>
=PEG_D2R_P<7>
=PEG_D2R_N<7>
=PEG_D2R_P<8>
=PEG_D2R_N<8>
=PEG_D2R_P<9>
=PEG_D2R_N<9>
=PEG_D2R_P<10>
=PEG_D2R_N<10>
=PEG_D2R_P<11>
=PEG_D2R_N<11>
=PEG_D2R_P<12>
=PEG_D2R_N<12>
=PEG_D2R_P<13>
=PEG_D2R_N<13>
=PEG_D2R_P<14>
=PEG_D2R_N<14>
=PEG_D2R_P<15>
=PEG_D2R_N<15>
IN
IN
IN
30
IN
35
IN
IN
31
IN
31
IN
58
IN
84
OUT
C7
E6
F6
E5
F5
E4
E3
C3
D3
G5
H5
J7
J6
J5
J4
L11
L10
L9
L8
L7
L6
N11
N10
N9
P9
N7
N6
N5
N4
C9
PEB_CLKREQ#/GPIO_49
PEB_PRSNT# Int PU
FW_CLKREQ_L
PCIE_FW_PRSNT_L
E8
PEC_CLKREQ#/GPIO_50
C10
90 30 7
IN
90 35
IN
90 35
IN
90 31 7
IN
90 31 7
PCIE_FW_D2R_P
PCIE_FW_D2R_N
PCIE_EXCARD_D2R_P
PCIE_EXCARD_D2R_N
IN
TP_PCIE_PE4_D2RP
TP_PCIE_PE4_D2RN
57 mA (A01, DVDD0 & 1)
Int PU
PED_CLKREQ#/GPIO_51
B10
PED_PRSNT# Int PU
L16
PEE_CLKREQ#/GPIO_16
L18
PEE_PRSNT#/GPIO_46
M16
PEF_CLKREQ#/GPIO_17
PEF_PRSNT#/GPIO_47
Int PU
Int PU
Int PU
B4
A4
A3
B3
B2
C1
D1
D2
E1
E2
F2
F3
F4
G3
H4
H3
H2
H1
J2
J3
K2
K3
L4
L3
M4
M3
M2
M1
PE0_REFCLK_P
PE0_REFCLK_N
E11
PE1_REFCLK_P
PE1_REFCLK_N
G11
PE2_REFCLK_P
PE2_REFCLK_N
J11
D11
F11
J10
PE3_REFCLK_P
PE3_REFCLK_N
G13
PE4_REFCLK_P
PE4_REFCLK_N
J13
PE5_REFCLK_P
PE5_REFCLK_N
L14
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
F13
H13
K14
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
PEG_CLK100M_P
PEG_CLK100M_N
OUT
69 90
OUT
69 90
PCIE_CLK100M_MINI_P
PCIE_CLK100M_MINI_N
OUT
30 90
OUT
30 90
PCIE_CLK100M_FW_P
PCIE_CLK100M_FW_N
OUT
35 90
OUT
35 90
PCIE_CLK100M_EXCARD_P
PCIE_CLK100M_EXCARD_N
OUT
31 90
OUT
31 90
PE6_REFCLK_P
PE6_REFCLK_N
M14
F17
Int PU
PE_WAKE# Int PU (S5)
PEX_RST0#
K11
PCIE_RESET_L
OUT
25
PE1_RX0_P
PE1_RX0_N
PE1_TX0_P
PE1_TX0_N
D8
PCIE_MINI_R2D_C_P
PCIE_MINI_R2D_C_N
OUT
30 90
OUT
30 90
PE1_RX1_P
PE1_RX1_N
PE1_TX1_P
PE1_TX1_N
B8
PCIE_FW_R2D_C_P
PCIE_FW_R2D_C_N
OUT
35 90
OUT
35 90
PE1_RX2_P
PE1_RX2_N
PE1_TX2_P
PE1_TX2_N
A7
PCIE_EXCARD_R2D_C_P
PCIE_EXCARD_R2D_C_N
OUT
31 90
OUT
31 90
PE1_RX3_P
PE1_RX3_N
PE1_TX3_P
PE1_TX3_N
B6
G9
F9
E9
H7
G7
C8
A8
B7
C6
W19
U17
V19
W16
W17
W18
U16
+DVDD0_PEX1
+DVDD0_PEX2
+DVDD0_PEX3
+DVDD0_PEX4
+DVDD0_PEX5
+DVDD0_PEX6
+DVDD0_PEX7
+DVDD0_PEX8
T19
U19
+DVDD1_PEX1
+DVDD1_PEX2
T16
+V_PLL_PEX
A11
PEX_CLK_COMP
+AVDD0_PEX1
+AVDD0_PEX2
+AVDD0_PEX3
+AVDD0_PEX4
+AVDD0_PEX5
+AVDD0_PEX6
+AVDD0_PEX7
+AVDD0_PEX8
+AVDD0_PEX9
+AVDD0_PEX10
+AVDD0_PEX11
+AVDD0_PEX12
+AVDD0_PEX13
Y12
+AVDD1_PEX1
+AVDD1_PEX2
+AVDD1_PEX3
M13
7
7
TP_PCIE_PE4_R2D_CP
TP_PCIE_PE4_R2D_CN
T17
206 mA (A01, AVDD0 & 1)
AA12
AB12
Minimum 1.025V for Gen2 support
M12
P12
R12
N12
T12
U12
AC12
AD12
V12
W12
N13
MCP PCIe Interfaces
P13
NO STUFF
1
SYNC_MASTER=T18_MLB
R1710
If PE0 interface is not used, ground DVDD0_PEX and AVDD0_PEX.

If PE1 interface is not used, ground DVDD1_PEX and AVDD1_PEX.
2.37K
PEG_CLKREQ#/GPIO_18
PEG_PRSNT#/GPIO_48
H9
y
r
M19
J9
MCP_PEX_CLK_COMP
OUT
a
n
i
J1
Int PU
84 mA (A01)
90
C4
K9
PP1V05_S0_MCP_PLL_PEX
23
D4
Int PU
=PEG_R2D_C_P<0>
=PEG_R2D_C_N<0>
=PEG_R2D_C_P<1>
=PEG_R2D_C_N<1>
=PEG_R2D_C_P<2>
=PEG_R2D_C_N<2>
=PEG_R2D_C_P<3>
=PEG_R2D_C_N<3>
=PEG_R2D_C_P<4>
=PEG_R2D_C_N<4>
=PEG_R2D_C_P<5>
=PEG_R2D_C_N<5>
=PEG_R2D_C_P<6>
=PEG_R2D_C_N<6>
=PEG_R2D_C_P<7>
=PEG_R2D_C_N<7>
=PEG_R2D_C_P<8>
=PEG_R2D_C_N<8>
=PEG_R2D_C_P<9>
=PEG_R2D_C_N<9>
=PEG_R2D_C_P<10>
=PEG_R2D_C_N<10>
=PEG_R2D_C_P<11>
=PEG_R2D_C_N<11>
=PEG_R2D_C_P<12>
=PEG_R2D_C_N<12>
=PEG_R2D_C_P<13>
=PEG_R2D_C_N<13>
=PEG_R2D_C_P<14>
=PEG_R2D_C_N<14>
=PEG_R2D_C_P<15>
=PEG_R2D_C_N<15>
C5
N14
M17
PEC_PRSNT# Int PU
PE0_TX0_P
PE0_TX0_N
PE0_TX1_P
PE0_TX1_N
PE0_TX2_P
PE0_TX2_N
PE0_TX3_P
PE0_TX3_N
PE0_TX4_P
PE0_TX4_N
PE0_TX5_P
PE0_TX5_N
PE0_TX6_P
PE0_TX6_N
PE0_TX7_P
PE0_TX7_N
PE0_TX8_P
PE0_TX8_N
PE0_TX9_P
PE0_TX9_N
PE0_TX10_P
PE0_TX10_N
PE0_TX11_P
PE0_TX11_N
PE0_TX12_P
PE0_TX12_N
PE0_TX13_P
PE0_TX13_N
PE0_TX14_P
PE0_TX14_N
PE0_TX15_P
PE0_TX15_N
m
il
PCIE_WAKE_L
PCIE_MINI_D2R_P
PCIE_MINI_D2R_N
Int PU
M15
M18
e
r
IN
Int PU
D9
TP_MCP_GPIO_18
GMUX_JTAG_TDO
IN
90 30 7
Int PU
PE0_PRSNT_16#
D5
AUD_IP_PERIPHERAL_DET
GMUX_JTAG_TCK_L
IN
PE0_RX0_P
PE0_RX0_N
PE0_RX1_P
PE0_RX1_N
PE0_RX2_P
PE0_RX2_N
PE0_RX3_P
PE0_RX3_N
PE0_RX4_P
PE0_RX4_N
PE0_RX5_P
PE0_RX5_N
PE0_RX6_P
PE0_RX6_N
PE0_RX7_P
PE0_RX7_N
PE0_RX8_P
PE0_RX8_N
PE0_RX9_P
PE0_RX9_N
PE0_RX10_P
PE0_RX10_N
PE0_RX11_P
PE0_RX11_N
PE0_RX12_P
PE0_RX12_N
PE0_RX13_P
PE0_RX13_N
PE0_RX14_P
PE0_RX14_N
PE0_RX15_P
PE0_RX15_N
MINI_CLKREQ_L
PCIE_MINI_PRSNT_L
TP_PE4_CLKREQ_L
TP_PE4_PRSNT_L
31 30 7
D7
EXCARD_CLKREQ_L
PCIE_EXCARD_PRSNT_L
7
E7
PEG_PRSNT_L
IN
30
F7
PCI EXPRESS
1%
1/16W
MF-LF
402

PLACEMENT_NOTE=Place within 12.7mm of U1400

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
17
123
OMIT
U1400
MCP79-TOPO-B
BGA
(6 OF 11)
23 18 8
92 32
IN
92 32
IN
92 32
IN
92 32
IN
92 32
IN
92 32
IN
IN
IN
IN
R1810 1
ENET_RXD<0>
ENET_RXD<1>
ENET_RXD<2>
ENET_RXD<3>
E24
A24
RGMII_RXD0
RGMII_RXD1
RGMII_RXD2
RGMII_RXD3
ENET_CLK125M_RXCLK
ENET_RX_CTRL
A23
RGMII_RXC/MII_RXCLK
C22
RGMII_RXCTL/MII_RXDV
=MCP_MII_RXER
=MCP_MII_COL
=MCP_MII_CRS
F23
MII_RXER/GPIO_36
MII_COL/GPIO_20/MSMB_DATA
MII_CRS/GPIO_21/MSMB_CLK
B26
B22
J22
5 mA (A01)
K24
+V_DUAL_RMGT1
+V_DUAL_RMGT2
U23
MII_VREF
E28
MCP_MII_VREF
RGMII_TXD0
RGMII_TXD1
RGMII_TXD2
RGMII_TXD3
B24
ENET_TXD<0>
ENET_TXD<1>
ENET_TXD<2>
ENET_TXD<3>
RGMII_TXC/MII_TXCLK
D24
RGMII_TXCTL/MII_TXEN
C26
RGMII_MDC
RGMII_MDIO
D21
RGMII_PWRDWN/GPIO_37
RGMII_INTR/GPIO_35
T23
+V_DUAL_MACPLL
C27
MII_COMP_VDD
MII_COMP_GND
92
MCP_MII_COMP_VDD
MCP_MII_COMP_GND
B27
20 8
90 24
OUT
90 24
OUT
47K
5%
1/16W
MF-LF
402
43 7
24
IN
24
OUT
E36
A35
Interface Mode
MCP Signal
TMDS/HDMI
DisplayPort
=MCP_HDMI_TXC_P/N
=MCP_HDMI_TXD_P/N<0>
=MCP_HDMI_DDC_CLK
=MCP_HDMI_DDC_DATA
=MCP_HDMI_HPD
DP_IG_AUX_CH_P/N
TMDS_IG_TXC_P/N
TMDS_IG_TXD_P/N<0>
TMDS_IG_TXD_P/N<1>
TMDS_IG_TXD_P/N<2>
TMDS_IG_DDC_CLK
TMDS_IG_DDC_DATA
TMDS_IG_HPD
TP_DP_IG_AUX_CHP/N
DP_IG_ML_P/N<3>
DP_IG_ML_P/N<2>
DP_IG_ML_P/N<1>
DP_IG_ML_P/N<0>
DP_IG_DDC_CLK
DP_IG_DDC_DATA
DP_IG_HPD
DP_IG_AUX_CH_P/N
NOTE: 1M pull-down required on DP_IG_CA_DET if DP not used.

NOTE: 20K pull-down required on DP_HPD_DET.
NOTE: 1K pull-down required on DP_IG_AUX_CH_N if DP is used.
NOTE: HDMI port requires level-shifting. IFP interface can
be used to provide HDMI or dual-channel TMDS without
level-shifters.
LVDS:
Power +VDD_IFPx at 1.8V
Dual-channel TMDS: Power +VDD_IFPx at 3.3V
32 92
OUT
32 92
OUT
32 92
ENET_CLK125M_TXCLK
ENET_TX_CTRL
OUT
32 92
OUT
32 92
OUT
32 92
C21
ENET_MDC
ENET_MDIO
G23
TP_ENET_PWRDWN_L
BUF_25MHZ
E23
MCP_CLK25M_BUF0_R
MII_RESET#
J23
ENET_RESET_L
C25
D25
a
n
i
TV_DAC_RSET
TV_DAC_VREF
C38
D38
LPCPLUS_GPIO
DP_IG_CA_DET
BI
IN
OUT
OUT
OUT
OUT
OUT
9
9
OUT
OUT
OUT
OUT
OUT
90 81
OUT
OUT
IN
P
9
IN
24 8
24
24 8
90 24
90 24
(See below)
=MCP_HDMI_TXD_P<0>
=MCP_HDMI_TXD_N<0>
=MCP_HDMI_TXD_P<1>
=MCP_HDMI_TXD_N<1>
=MCP_HDMI_TXD_P<2>
=MCP_HDMI_TXD_N<2>
DP_IG_AUX_CH_P
DP_IG_AUX_CH_N
=DVI_HPD_GMUX_INT
=MCP_HDMI_HPD
GPIO_6/FERR*/IGPU_GPIO_6
B15
GPIO_7/NFERR*/IGPU_GPIO_7
G39
F40
=MCP_HDMI_TXC_P
=MCP_HDMI_TXC_N
(See below)
XTALIN_TV
XTALOUT_TV
E16
E37
e
r
OUT
90 81
LVDS_IG_BKL_PWM
LVDS_IG_BKL_ON
LVDS_IG_PANEL_PWR
D35
E35
G35
F35
F33
G33
J33
H33
D43
C43
C31
F31
LCD_BKL_CTL/GPIO_57
LCD_BKL_ON/GPIO_59
LCD_PANEL_PWR/GPIO_58
HDMI_TXC_P/ML0_LANE3_P
HDMI_TXC_N/ML0_LANE3_N
HDMI_TXD0_P/ML0_LANE2_P
HDMI_TXD0_N/ML0_LANE2_N
DP_AUX_CH0_P
DP_AUX_CH0_N
HPLUG_DET2/GPIO_22
HPLUG_DET3
190 mA (A01, 1.8V)
M27
M26
PP3V3_S0_MCP_VPLL
16 mA (A01)
95 mA (A01)
MCP_HDMI_RSET
OUT
MCP_HDMI_VPROBE
OUT
8 mA
8 mA
TV
C
Y
Comp
J32
K32
B31
RGB_DAC_RED
RGB_DAC_GREEN
RGB_DAC_BLUE
B39
RGB_DAC_HSYNC
RGB_DAC_VSYNC
Component
Pr
TV_DAC_RED
Y
TV_DAC_GREEN
Pb
TV_DAC_BLUE
A40
TV_DAC_HSYNC/GPIO_44
TV_DAC_VSYNC/GPIO_45
D36
IFPA_TXC_P
IFPA_TXC_N
B35
IFPA_TXD0_P
IFPA_TXD0_N
IFPA_TXD1_P
IFPA_TXD1_N
IFPA_TXD2_P
IFPA_TXD2_N
IFPA_TXD3_P
IFPA_TXD3_N
B32
IFPB_TXC_P
IFPB_TXC_N
L31
IFPB_TXD4_P
IFPB_TXD4_N
IFPB_TXD5_P
IFPB_TXD5_N
IFPB_TXD6_P
IFPB_TXD6_N
IFPB_TXD7_P
IFPB_TXD7_N
J29
DDC_CLK2/GPIO_23
DDC_DATA2/GPIO_24
C30
DDC_CLK3
DDC_DATA3
D31
IFPAB_RSET
IFPAB_VPROBE
E32
/
/
/
/
103 mA
103 mA
M28
M29
+VDD_IFPA
+VDD_IFPB
+V_PLL_IFPAB
+V_PLL_HDMI
T25
+VDD_HDMI
J31
HDMI_RSET
HDMI_VPROBE
J30
TP_MCP_RGB_RED
TP_MCP_RGB_GREEN
TP_MCP_RGB_BLUE
A39
B40
TP_MCP_RGB_HSYNC
TP_MCP_RGB_VSYNC
A41
CRT_IG_R_C_PR
CRT_IG_G_Y_Y
CRT_IG_B_COMP_PB
A36
B36
C36
C37
C35
32 92
OUT
33 92
OUT
32 92
24
206 mA (A01)
A32
D32
C32
D33
C33
B34
C34
Network Interface Select

Interface
ENET_TXD<0>
RGMII
MII
NOTE: All Apple products set strap to

MII, RGMII products will enable
feature via software. This
avoids a leakage issue since
MCP79 requires a S5 pull-up.
=PP3V3_S0_MCP_GPIO
R1860 1
100K
5%
1/16W
MF-LF
402
8 19 21
R1861
100K
5%
1/16W
MF-LF
402
RGB DAC Disable:
24
Okay to float all RGB_DAC signals.

DDC_CLK0/DDC_DATA0 pull-ups still required.
24
24
24
24
OUT
24 90
OUT
24 90
OUT
24 90
CRT_IG_HSYNC
CRT_IG_VSYNC
OUT
24 90
OUT
24 90
LVDS_IG_A_CLK_P
LVDS_IG_A_CLK_N
OUT
84 90
OUT
84 90
OUT
84 90
OUT
84 90
OUT
84 90
OUT
84 90
OUT
84 90
OUT
84 90
OUT
9 90
OUT
9 90
OUT
9 90
OUT
9 90
OUT
84 90
OUT
84 90
OUT
84 90
OUT
84 90
OUT
84 90
OUT
84 90
OUT
9 90
OUT
9 90
LVDS_IG_DDC_CLK
LVDS_IG_DDC_DATA
OUT
81
=MCP_HDMI_DDC_CLK
=MCP_HDMI_DDC_DATA
OUT
MCP_IFPAB_RSET
MCP_IFPAB_VPROBE
OUT
24 90
OUT
24 90
LVDS_IG_A_DATA_P<0>
LVDS_IG_A_DATA_N<0>
LVDS_IG_A_DATA_P<1>
LVDS_IG_A_DATA_N<1>
LVDS_IG_A_DATA_P<2>
LVDS_IG_A_DATA_N<2>
LVDS_IG_A_DATA_P<3>
LVDS_IG_A_DATA_N<3>
TV DAC Disable:
Okay to float all TV_DAC signals.
Okay to float XTALIN_TV and XTALOUT_TV.
DDC_CLK0/DDC_DATA0 pull-ups still required.
WF: IFP is capable of LVDS (1.8V) or TMDS (3.3V), need aliases

LVDS_IG_B_CLK_P
LVDS_IG_B_CLK_N
K31
LVDS_IG_B_DATA_P<0>
LVDS_IG_B_DATA_N<0>
LVDS_IG_B_DATA_P<1>
LVDS_IG_B_DATA_N<1>
LVDS_IG_B_DATA_P<2>
LVDS_IG_B_DATA_N<2>
LVDS_IG_B_DATA_P<3>
LVDS_IG_B_DATA_N<3>
H29
L29
K29
L30
K30
N30
M30
B30
E31
G31
BI
BI
81
9
9
R1850
10K
GPIOs 57-59 (if LCD panel is used):

In MCP79 these pins have undocumented internal
pull-ups (~10K to 3.3V S0). To ensure pins are low
by default, pull-downs (1K or stronger) must be used.
BI
MCP_DDC_CLK0
MCP_DDC_DATA0
A31
m
il
MCP_CLK27M_XTALIN
MCP_CLK27M_XTALOUT
81
MCP_TV_DAC_RSET
MCP_TV_DAC_VREF
=PP3V3_S5_MCP_GPIO
R1820
32 92
DDC_CLK0
DDC_DATA0
RGB ONLY
B38
DACS
24
RGB_DAC_RSET
RGB_DAC_VREF
y
r
23
OUT
+V_RGB_DAC
+V_TV_DAC
FLAT PANEL
24
C39
IN
OUT
C24
PP3V3_S0_MCP_DAC
TP_MCP_RGB_DAC_RSET
TP_MCP_RGB_DAC_VREF
8 23
131 mA (A01)
V23
49.9
1%
1/16W
MF-LF
402
8 18 23
83 mA (A01)
PP1V05_ENET_MCP_PLL_MAC
23
92
R1811
B23
TP_ENET_INTR_L
49.9
1%
1/16W
MF-LF
402
C23
J24
+3.3V_DUAL_RMGT2
LAN
+3.3V_DUAL_RMGT1
5%
1/16W
MF-LF
402
MCP Ethernet & Graphics

SYNC_MASTER=T18_MLB

=DVI_HPD_GMUX_INT:
Alias to DVI_HPD for systems using IFP for DVI.
Alias to GMUX_INT for systems with GMUX.
Alias to HPLUG_DET2 for other systems.
Pull-down (20k) required in all cases.

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
18
123
OMIT
U1400
21 18 8
=PP3V3_S0_MCP_GPIO
MCP79-TOPO-B
BGA
(7 OF 11)
19
58 9
OUT
OUT
19
IN
91 13
BI
91 13
BI
91 13
BI
91 13
BI
91 13
BI
91 13
BI
91 13
BI
91 13
BI
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
43 41 7
35
IN
BI
TP_PCI_INTW_L
TP_PCI_INTX_L
TP_PCI_INTY_L
TP_PCI_INTZ_L
TP_PCI_TRDY_L
PM_CLKRUN_L
IN
7
43 41 7
MCP_DEBUG<0>
MCP_DEBUG<1>
MCP_DEBUG<2>
MCP_DEBUG<3>
MCP_DEBUG<4>
MCP_DEBUG<5>
MCP_DEBUG<6>
MCP_DEBUG<7>
TP_PCI_AD<8>
TP_PCI_AD<9>
TP_PCI_AD<10>
TP_PCI_AD<11>
TP_PCI_AD<12>
TP_PCI_AD<13>
TP_PCI_AD<14>
TP_PCI_AD<15>
TP_PCI_AD<16>
TP_PCI_AD<17>
TP_PCI_AD<18>
TP_PCI_AD<19>
TP_PCI_AD<20>
TP_PCI_AD<21>
TP_PCI_AD<22>
TP_PCI_AD<23>
TP_PCI_AD<24>
TP_PCI_AD<25>
TP_PCI_AD<26>
TP_PCI_AD<27>
TP_PCI_AD<28>
TP_PCI_AD<29>
TP_PCI_AD<30>
TP_PCI_AD<31>
T2
V9
T3
U9
T4
AC3
AE10
AC4
AE11
AB3
AC6
AB2
AC7
AC8
AA2
AC9
AC10
AC11
AA1
AA5
Y5
W3
W6
W4
W7
V3
W8
V2
W9
U3
W11
U2
U5
U1
U6
T5
U7
P2
N3
N2
N1
Y3
AD11
FW_PME_L
TP_LPC_DRQ0_L
LPC_SERIRQ
AE2
AE1
AE6
PCI_REQ0#
PCI_REQ1#/FANRPM2
PCI_REQ2#/GPIO_40/RS232_DSR#
PCI_REQ3#/GPIO_38/RS232_CTS#
PCI_REQ4#/GPIO_52/RS232_SIN#
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_CBE0#
PCI_CBE1#
PCI_CBE2#
PCI_CBE3#
PCI_DEVSEL#
PCI_FRAME#
PCI_IRDY#
PCI_PAR
PCI_PERR#/GPIO_43/RS232_DCD#
PCI_SERR#
PCI_STOP#
PCI_CLKRUN#/GPIO_42
LPC_DRQ1#/GPIO_19 Int PU
Int PU
LPC_DRQ0#
LPC_SERIRQ Int PU
PCI_PME#/GPIO_30
Int PU (S5)
PCI_RESET0#
PCI_RESET1#
PCI_CLK0
PCI_CLK1
PCI_CLK2
TP_PCI_GNT0_L
TP_PCI_GNT1_L
GMUX_JTAG_TMS
GMUX_JTAG_TDI
MCP_RS232_SOUT_L
R3
U10
R4
U11
P3
TP_PCI_C_BE_L<0>
TP_PCI_C_BE_L<1>
TP_PCI_C_BE_L<2>
TP_PCI_C_BE_L<3>
AA3
AA6
AA11
W10
Y2
TP_PCI_DEVSEL_L
TP_PCI_FRAME_L
TP_PCI_IRDY_L
TP_PCI_PAR
TP_PCI_PERR_L
TP_PCI_SERR_L
TP_PCI_STOP_L
T1
PM_LATRIGGER_L
R10
MEM_VTT_EN_R
TP_PCI_RESET1_L
AA9
Y4
AA10
Y1
AB9
AA7
R11
R6
R7
R8
91
U39
U4
U8
V16
V17
V18
V20
V22
V24
V26
V27
V28
V33
V37
V4
V40
V7
W20
W22
W24
W36
W40
W43
Y16
Y17
Y18
Y19
Y20
Y22
Y24
Y25
GND65
GND66
GND67
GND68
GND69
GND70
GND71
GND72
GND73
GND74
GND75
GND76
GND77
GND78
GND79
GND80
GND81
GND82
GND83
GND84
GND85
GND86
GND87
GND88
GND89
GND90
GND91
GND92
GND93
GND94
GND95
GND96
GND97
7
91 19
OUT
OUT
OUT
19
OUT
13
OUT
25
19
19
PCI_CLKIN
LPC_FRAME#
LPC_PWRDWN#/GPIO_54/EXT_NMI#
R9
AE5
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
AD3
GND98
GND99
GND100
GND101
GND102
GND103
GND104
GND105
GND106
GND107
GND108
GND109
GND110
GND111
GND112
GND113
GND114
GND115
GND116
GND117
GND118
GND119
GND120
GND121
GND122
GND123
GND124
GND125
GND126
GND127
GND128
GND129
GND130
AD2
AD1
AD5
AE9
Y26
43
H34
AB20
AB21
AB23
AB24
AB25
AB26
AB27
AB28
AB34
AB37
AB4
LPC_FRAME_R_L
LPC_PWRDWN_L
LPC_AD_R<0>
LPC_AD_R<1>
LPC_AD_R<2>
LPC_AD_R<3>
8.2K
R1990
R1991
R1992
R1994
8.2K
8.2K
8.2K
8.2K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
y
r
7
7
7
7
7
7
7
7
7
a
n
i
7
7
R1910
5%
1/16W
MF-LF
402
PLACEMENT_NOTE=Place close to pin R8
R1960
22
LPC_RESET_L
R1950
R1951
R1952
R1953
22
22
22
22
LPC_CLK33M_SMC_R
LPC_FRAME_L
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>
OUT
7 41 43 84 91
OUT
7 41 43
OUT
25 84 91
BI
7 41 43 84 91
BI
7 41 43 84 91
BI
7 41 43 84 91
BI
402
OUT
7 41 43 84 91
25 91
R1961
10K
e
r
Y27
AB18
PCI_CLK33M_MCP
R1989
PCI_REQ0_L
PCI_REQ1_L
CRTMUX_SEL_TV_L
MCP_RS232_SIN_L
m
il
AD4
AE12
LPC_RESET0#
LPC_CLK0
91
MCP_RS232_SOUT_L
GND
U26
91 19
22
U24
TP_PCI_CLK0
TP_PCI_CLK1
PCI_CLK33M_MCP_R
PCI_INTW#
PCI_INTX#
PCI_INTY#
PCI_INTZ#
PCI_TRDY#
19
PCI_GNT0#
PCI_GNT1#/FANCTL2
PCI_GNT2#/GPIO_41/RS232_DTR#
PCI_GNT3#/GPIO_39/RS232_RTS#
PCI_GNT4#/GPIO_53/RS232_SOUT#
PCI
91 19
PCI_REQ0_L
PCI_REQ1_L
CRTMUX_SEL_TV_L
AUD_IPHS_SWITCH_EN
MCP_RS232_SIN_L
LPC
91 19
5%
1/16W
MF-LF
402
Strap for Boot ROM Selection (See HDA_SDOUT)
AB40
AC22
AC36
AC40
AB33
AC5
AD16
AD17
AD18
AD19
AD20
AD24
AD25
AD26
AD27
MCP PCI & LPC
AD28
AD33
SYNC_MASTER=T18_MLB
AD34

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
19
123
OMIT
U1400
MCP79-TOPO-B
BGA
(8 OF 11)
90 38
90 38
SATA_HDD_R2D_C_P
SATA_HDD_R2D_C_N
OUT
OUT
90 38
IN
90 38
IN
AJ7
SATA_HDD_D2R_N
SATA_HDD_D2R_P
AJ6
AJ5
AJ4
SATA_A0_TX_P
SATA_A0_TX_N
USB0_P
USB0_N
SATA_A0_RX_N
SATA_A0_RX_P
USB1_P
USB1_N
USB2_P
USB2_N
OUT
90 38
OUT
90 38
90 38
SATA_ODD_R2D_C_P
SATA_ODD_R2D_C_N
AJ10
SATA_ODD_D2R_N
SATA_ODD_D2R_P
IN
IN
AJ9
AK9
TP_SATA_C_R2D_CP
TP_SATA_C_R2D_CN
7
7
AK2
AJ3
TP_SATA_C_D2RN
TP_SATA_C_D2RP
7
7
AJ2
AJ1
TP_SATA_D_R2D_CP
TP_SATA_D_R2D_CN
7
7
AM4
AL3
TP_SATA_D_D2RN
TP_SATA_D_D2RP
7
7
AJ11
AL4
AK3
TP_SATA_E_R2D_CP
TP_SATA_E_R2D_CN
7
7
AN1
TP_SATA_E_D2RN
TP_SATA_E_D2RP
AM1
7
7
AM2
AM3
TP_SATA_F_R2D_CP
TP_SATA_F_R2D_CN
7
7
AP3
SATA_B1_RX_N
SATA_B1_RX_P
SATA_C0_TX_P
SATA_C0_TX_N
AP2
AN3
AN2
TP_MCP_SATALED_L
PP1V05_S0_MCP_PLL_SATA
23
84 mA (A01)
43 mA (A01, DVDD0 & 1)
e
r
127 mA (A01, AVDD0 & 1)
P
9
90
B28
F29
SATA_C1_TX_P
SATA_C1_TX_N
SATA_C1_RX_N
SATA_C1_RX_P
E12
AE16
AF19
AG16
AG17
AG19
AH17
AH19
AJ12
AN11
AK12
AK13
AL12
AM11
AM12
AN12
AL13
SATA_LED#
+V_PLL_SATA
+DVDD0_SATA1
+DVDD0_SATA2
+DVDD0_SATA3
+DVDD0_SATA4
+DVDD1_SATA1
+DVDD1_SATA2
+AVDD0_SATA1
+AVDD0_SATA2
+AVDD0_SATA3
+AVDD0_SATA4
+AVDD0_SATA5
+AVDD0_SATA6
+AVDD0_SATA7
+AVDD0_SATA8
+AVDD0_SATA9
AN14
AL14
AM13
AM14
AE3
+AVDD1_SATA1
+AVDD1_SATA2
+AVDD1_SATA3
+AVDD1_SATA4
SATA_TERMP
39 91
BI
39 91
BI
9 91
BI
9 91
External D
USB_EXTD_P
USB_EXTD_N
BI
9 91
BI
9 91
USB_CAMERA_P
USB_CAMERA_N
BI
30 91
BI
USB4_P
USB4_N
K27
30 91
USB_IR_P
USB_IR_N
BI
40 91
BI
USB5_P
USB5_N
J26
40 91
Geyser Trackpad/Keyboard
USB_TPAD_P
USB_TPAD_N
BI
49 91
BI
USB6_P
USB6_N
F27
49 91
Bluetooth
USB_BT_P
USB_BT_N
BI
30 91
BI
30 91
External B
USB_EXTB_P
USB_EXTB_N
BI
39 91
BI
39 91
ExpressCard
USB_EXCARD_P
USB_EXCARD_N
BI
31 91
BI
31 91
External C
USB_EXTC_P
USB_EXTC_N
BI
91 96 98
BI
91 96 98
G29
USB7_P
USB7_N
USB8_P
USB8_N
USB9_P
USB9_N
L27
J27
G27
y
r
a
n
i
D27
E27
K25
L25
H25
J25
USB10_P
USB10_N
F25
USB11_P
USB11_N
K23
USB_OC0#/GPIO_25
USB_OC1#/GPIO_26
USB_OC2#/GPIO_27/MGPIO
USB_OC3#/GPIO_28/MGPIO
L21
+V_PLL_USB
L28
G25
L23
SATA_C0_RX_N
SATA_C0_RX_P
MCP_SATA_TERMP
A28
USB3_P
USB3_N
USB_RBIAS_GND
D28
BI
AirPort (PCIe Mini-Card)

USB_MINI_P
USB_MINI_N
IR
SATA_B0_TX_P
SATA_B0_TX_N
SATA_B1_TX_P
SATA_B1_TX_N
C28
External A
USB_EXTA_P
USB_EXTA_N
Camera
SATA_A1_RX_N
SATA_A1_RX_P
SATA_B0_RX_N
SATA_B0_RX_P
D29
K21
J21
H21
m
il
TP_SATA_F_D2RN
TP_SATA_F_D2RP
SATA_A1_TX_P
SATA_A1_TX_N
SATA
USB
90 38
C29
GND131
GND132
GND133
GND134
GND135
GND136
GND137
GND138
GND139
GND140
GND141
GND142
GND143
GND144
GND145
GND146
GND147
GND148
GND149
GND150
GND151
GND152
GND153
GND154
GND155
GND156
GND157
GND158
GND159
GND160
A27
AD35
AD37
AD38
TP_USB_10P
TP_USB_10N
TP_USB_11P
TP_USB_11N
R2050
7
7
PP3V3_S0_MCP_PLL_USB
=PP3V3_S5_MCP_GPIO
R2051
8.2K
R2053
8.2K
5%
1/16W
MF-LF
402
R2052
8.2K
8.2K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
8 18
5%
1/16W
MF-LF
402
USB_EXTA_OC_L
USB_EXTB_OC_L
USB_EXTC_OC_L
EXCARD_OC_L
IN
39
IN
39
IN
98
IN
31 42
23
19 mA (A01)
91
MCP_USB_RBIAS_GND
R2060 1
806
1%
1/16W
MF-LF
402
AE22
AE24
AE39
AE4
AD6
AF16
AF17
AF18
AF20
AF22
AF26
AF27
AF28
AF33
AF34
AF37
AF40
AG18
AG20
AG22
AG26
AG36
AG40
AH18
AH20
AH22
AH24
R2010
2.49K
1%
1/16W
MF-LF
402
If all SATA_Ax & Bx pins are not used, ground DVDD0_SATA and AVDD0_SATA.
If all SATA_Cx pins are not used, ground DVDD1_SATA and AVDD1_SATA.
MCP SATA & USB

SYNC_MASTER=T18_MLB

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
20
123
OMIT
U1400
MCP79-TOPO-B
8 21 23
7 mA (A01)
BGA
(9 OF 11)
HDA
+V_DUAL_HDA1
+V_DUAL_HDA2
D
91 53
HDA_SDIN0
IN
TP_MLB_RAM_SIZE
J14
TP_MLB_RAM_VENDOR
23 21 8
G15
J15
(MXM_OK for MXM systems)

1
HDA_SDATA_IN0
Int PD
HDA_SDATA_OUT
HDA_SDATA_IN1/GPIO_2/PS2_KB_CLK
Int PD
HDA_BITCLK
43 9
49.9K
1%
1/16W
MF-LF
402
OUT
IN
R2121
49.9K
E15
91 21
22
HDA_RESET#
K15
91 21
L15
91 21
22
HDA_BIT_CLK_R
22
22
HDA_RST_L
5%
1/16W
MF-LF
402
HDA_SYNC
MCP_HDA_PULLDN_COMP
A15
1%
1/16W
MF-LF
402
7
41
IN
41
IN
HDA_PULLDN_COMP
HDA_DOCK_EN#/GPIO_4/PS2_MS_CLK
HDA_DOCK_RST#/GPIO_5/PS2_MS_DATA
K17
SLP_S3#
SLP_RMGT#
SLP_S5#
G17
THERM_DIODE_P
THERM_DIODE_N
B11
a
n
i
MCP_GPIO_4
AUD_I2C_INT_L
L17
PP1V05_S0_MCP_PLL_NV
20 mA
17 mA
SMC_ADAPTER_EN
AE18
AE17
+V_PLL_NV_H
+V_PLL_SP_SPREF
L24
GPIO_1/PWRDN_OK/SPI_CS1
L26
GPIO_12/SUS_STAT#/ACCLMTR
TP_SB_A20GATE
TP_MCP_KBDRSTIN_L
SMC_WAKE_SCI_L
SMC_RUNTIME_SCI_L
K13
C18
Int PU
A20GATE
KBRDRSTIN# Int PU
SIO_PME#
Int PU (S5)
EXT_SMI/GPIO_32# Int PU (S5)
SM_INTRUDER_L
B20
INTRUDER#
L13
C19
21
IN
PM_SLP_S3_L
PM_SLP_RMGT_L
PM_SLP_S4_L
J17
H17
MCP_THMDIODE_P
MCP_THMDIODE_N
C11
21 58
OUT
7 33 36 41 67 82 84
OUT
OUT
39 41 42 67
OUT
47 96
OUT
47 96
OUT
21 64
OUT
21 64
OUT
21 64
IN
IN
PM_DPRSLPVR
M22
CPU_DPRSLPVR
41
IN
C16
25
IN
PM_PWRBTN_L
D16
PWRBTN# Int PU (S5)

RSTBTN# Int PU
RTC_RST_L
C20
RTC_RST#
MCP_VID0/GPIO_13
MCP_VID1/GPIO_14
MCP_VID2/GPIO_15
L20
M21
MCP_VID<0>
MCP_VID<1>
MCP_VID<2>
SPKR
C13
MCP_SPKR
SMB_CLK0
SMB_DATA0
SMB_CLK1/MSMB_CLK
SMB_DATA1/MSMB_DATA
SMB_ALERT#/GPIO_64
L19
SMBUS_MCP_0_CLK
SMBUS_MCP_0_DATA
SMBUS_MCP_1_CLK
SMBUS_MCP_1_DATA
AP_PWR_EN
FANRPM0/GPIO_60
FANCTL0/GPIO_61
FANRPM1/GPIO_63
FANCTL1/GPIO_62
B12
C12
MEM_EVENT_L
ODD_PWR_EN_L
SMC_IG_THROTTLE_L
ARB_DETECT
CPUVDD_EN
D17
MCP_CPUVDD_EN
SPI_CS0/GPIO_10
SPI_CLK/GPIO_11
SPI_DI/GPIO_8
SPI_DO/GPIO_9
C14
SPI_CS0_R_L
SPI_CLK_R
SPI_MISO
SPI_MOSI_R
M20
25
IN
E20
25
IN
MCP_CPU_VLD
C17
CPU_VLD
JTAG_MCP_TDI
JTAG_MCP_TDO
JTAG_MCP_TMS
JTAG_MCP_TRST_L
JTAG_MCP_TCK
E19
JTAG_TDI Int PU
JTAG_TDO
JTAG_TMS Int PU
JTAG_TRST#
JTAG_TCK
IN
IN
OUT
13 6
IN
13 6
IN
13 6
IN
B
25
IN
25
OUT
25
IN
25
OUT
J19
J18
G19
MCP_CLK25M_XTALIN
MCP_CLK25M_XTALOUT
A16
B16
RTC_CLK32K_XTALIN
RTC_CLK32K_XTALOUT
A19
B19
10K
HDA_RST_R_L
HDA_SYNC_R
C2170
C2172
10PF
10PF
5%
50V
CERM
402
5%
50V
CERM
402
C2171
21 91
21 91
21 91
21 91
XTALIN
XTALOUT
XTALIN_RTC
XTALOUT_RTC
100K
5%
1/16W
MF-LF
402
R2140
R2141
SUS_CLK/GPIO_34
BUF_SIO_CLK
TEST_MODE_EN
PKG_TEST
10PF
5%
50V
CERM
402
5%
50V
CERM
402
F21
M23
A12
D12
D13
C15
B14
OUT
BI
OUT
BI
OUT
IN
OUT
53 91
LPC_FRAME#
PCI
SPI0
SPI1
SPI0 = SPI_CS0_L, SPI1 = SPI_CS1_L

R1961 and R2160 selects SPI0 ROM by
default, LPC+ debug card pulls
LPC_FRAME# high for SPI1 ROM override.
NOTE: MCP79 does not support FWH, only
LPC ROMs. So Apple designs will
not use LPC for BootROM override.
NOTE: MCP79 rev A01 does not support
SPI1 option. Rev B01 will.
8 22 23
IN
=PP3V3_S0_MCP_GPIO
7 13 44 91
Frequency
9
10K
7 13 44 91
44 91
21 30 33
R2142
OUT
14.31818 MHz
10K
10K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
MCP_GPIO_4
AUD_I2C_INT_L
MEM_EVENT_L
SMC_IG_THROTTLE_L
ARB_DETECT
USER mode: Normal

SAFE mode: For ROMSIP
recovery
SPI Frequency Select
Connects to SMC for

automatic recovery.
Frequency
38
SPI_DO
SPI_CLK
42 MHz
25 MHz
1 MHz
31 MHz
21 42
25
OUT
43 91
OUT
43 91
IN
43 91
OUT
43 91
OUT
25 91
NOTE: Straps not provided on this page.
B
7
MCP_TEST_MODE_EN
K22
L22
R2163
R2190
1K
5%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
8 18 19
R2143
10K
5%
1/16W
MF-LF
402
R2154
100K
5%
1/16W
MF-LF
402
AP_PWR_EN
21
21 30 33
21 58
MCP HDA & MISC
21 27 28 41
MCP_VID<0>
MCP_VID<1>
MCP_VID<2>
21 42
21
R2147
R2155
R2156
100K
22K
22K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
21 64
SYNC_MASTER=T18_MLB
21 64

R2157
22K
21 64
5%
1/16W
MF-LF
402

SIZE
DRAWING NUMBER
D
APPLE INC.
REV.
051-7656
SCALE
SHT
NONE
HDA_SYNC
24 MHz
21 27 28 41
=PP3V3_S3_MCP_GPIO
1
R2181
44 91
BUF_SIO_CLK Frequency
5%
1/16W
MF-LF
402
21
PM_CLK32K_SUSCLK_R
TP_MCP_BUF_SIO_CLK
B18
AE7
C2173
10PF
G21
10K
5%
1/16W
MF-LF
402
K19
(MGPIO2)
10K
OUT
HDA_SDOUT
LPC
10K
OUT
m
il
R2151
P
5%
1/16W
MF-LF
402
53 91
I/F
BOOT_MODE_USER
e
r
F19
R2150 1
HDA_SDOUT_R
HDA_BIT_CLK_R
D20
R2180
(MGPIO3)
PWRGD_SB
PS_PWRGD
13 6
For EMI Reduction on HDA interface
LID# Int PU (S5)

LLB# Int PU (S5)
PM_RSMRST_L
MCP_PS_PWRGD
41
HDA Output Caps
M24
OUT
BIOS Boot Select
BOOT_MODE_SAFE
MISC
41
88 61
M25
9 91
=PP3V3_S0_MCP
TP_MCP_LID_L
PM_BATLOW_L
53 91
y
r
OUT
R2172
1
OUT
HDA_BIT_CLK
HDA_RST_R_L
HDA_SYNC_R
HDA_SDOUT
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
HDA_SDATA_IN2/GPIO_3/PS2_KB_DATA
Int PD
R2170
HDA_SDOUT_R
5%
1/16W
MF-LF
402
42 41 36 33
91 21
R2173
PP3V3_G3_RTC
F15
5%
1/16W
MF-LF
402
R2171
HDA_SYNC
37 mA (A01)
8.2K
1%
1/16W
MF-LF
402
23
R2120
R2160
R2110
91
25 22
K16
49.9
J16
31
OF
21
123
7
OMIT
U1400
MCP79-TOPO-B
MCP79-TOPO-B
AH37
AH38
AJ39
AJ8
AK10
AK33
AK34
AK37
AK4
AK40
AL36
AL40
AL5
AM10
AM16
AM18
AM20
AM22
AM24
AM26
AM30
AM34
AM35
AM37
AM38
AM5
AM6
AM7
AM9
AP26
AN28
AN30
AN39
AN4
Y7
AP10
AU26
AP14
AU14
AP28
AP32
AP34
AP36
AP37
AP4
AP40
AP7
AW23
AR28
AR32
AR40
AT10
AR12
AT13
AT29
AT33
AT6
AT7
AT9
AY21
AY22
L12
AU12
AU28
AP33
AU32
AR30
AU36
AU38
AU4
G28
F20
AV28
AV32
AV36
AV4
AV7
AW11
G20
AR43
AW43
AY10
AV12
AY30
AY33
AY34
AY37
AY38
AY41
GND253
GND254
GND255
GND256
GND257
GND258
GND259
GND260
GND261
GND262
GND263
GND264
GND265
GND266
GND267
GND268
GND269
GND270
GND271
GND272
GND273
GND274
GND275
GND276
GND277
GND278
GND279
GND280
GND281
GND282
GND283
GND284
GND285
GND286
GND287
GND288
GND289
GND290
GND291
GND292
GND293
GND294
GND295
GND296
GND297
GND298
GND299
GND300
GND301
GND302
GND303
GND304
GND305
GND306
GND307
GND308
GND309
GND310
GND311
GND312
GND313
GND314
GND315
GND316
GND317
GND318
GND319
GND320
GND321
GND322
GND323
GND324
GND325
GND326
GND327
GND328
GND329
GND330
GND331
GND332
GND333
GND334
GND335
GND336
GND337
GND338
GND339
GND340
GND341
GND342
GND343
45 23 8
AV40
BGA
(10 OF 11)
=PPVCORE_S0_MCP
AA25
23065 mA (A01, 1.2V)

16996 mA (A01, 1.0V)
BA1
AC23
BA4
U25
AW31
AH12
AY6
AG10
L35
AG5
BC33
Y21
BC37
Y23
BC41
AA16
AY14
AA26
BC5
AA27
C2
AA28
D10
AC16
D14
AC17
D15
AC18
D18
AC19
D19
AC20
D22
AC21
D23
AA17
D26
AC24
D30
AC25
D37
AC26
D6
AC27
E13
AC28
E17
AD21
E21
AD23
E25
W27
E29
V25
E33
AA18
F12
AE19
F16
AE21
F32
AE23
F8
AE25
G10
AE26
G12
AE27
G14
AE28
G16
AF10
BC12
AF11
G22
AA19
G24
AF2
AW20
AF21
AF25
G4
G43
AF3
G6
AF4
G8
AF7
H11
AH23
H15
AF9
AW35
AA20
H23
AG11
AN8
AG12
G40
AG21
J12
AG23
J8
AG25
e
r
K12
K18
K26
K37
K4
K40
K8
AU1
L40
L43
L5
M10
M34
M35
M37
Y28
Y33
Y34
Y35
Y37
Y38
AB17
AB16
AN26
AD7
M11
AA4
AB19
AY13
P11
Y6
T11
V11
=PP1V05_S0_MCP_FSB
+VTT_CPU1
+VTT_CPU2
+VTT_CPU3
+VTT_CPU4
+VTT_CPU5
+VTT_CPU6
+VTT_CPU7
+VTT_CPU8
+VTT_CPU9
+VTT_CPU10
+VTT_CPU11
+VTT_CPU12
+VTT_CPU13
+VTT_CPU14
+VTT_CPU15
+VTT_CPU16
+VTT_CPU17
+VTT_CPU18
+VTT_CPU19
+VTT_CPU20
+VTT_CPU21
+VTT_CPU22
+VTT_CPU23
+VTT_CPU24
+VTT_CPU25
+VTT_CPU26
+VTT_CPU27
+VTT_CPU28
+VTT_CPU29
+VTT_CPU30
+VTT_CPU31
+VTT_CPU32
+VTT_CPU33
+VTT_CPU34
+VTT_CPU35
+VTT_CPU36
+VTT_CPU37
+VTT_CPU38
+VTT_CPU39
+VTT_CPU40
+VTT_CPU41
+VTT_CPU42
+VTT_CPU43
+VTT_CPU44
+VTT_CPU45
+VTT_CPU46
+VTT_CPU47
+VTT_CPU48
+VTT_CPU49
+VTT_CPU50
+VTT_CPU51
+VTT_CPU52
R32
1139 mA
AG3
AG4
AA21
AG6
AG7
AG8
AG9
AH1
AH10
AH11
W26
AH2
AA23
W28
AH25
AH21
AH3
AH4
AH5
AH6
AH7
AH9
AA24
W21
W23
W25
AF12
25 21
PP3V3_G3_RTC
10 uA (G3)
80 uA (S0)
A20
+VBAT
8 9 14 23
1182 mA (A01)
AC32
E40
J36
N32
T32
U32
V32
y
r
W32
P31
AF32
AE32
AH32
AJ32
AK31
AK32
AD32
AL31
AB32
B41
a
n
i
B42
C40
C41
C42
D39
D40
D41
E38
E39
F37
F38
F39
G36
G37
G38
H35
H37
J34
J35
K33
K34
m
il
AF23
G34
K10
+VDD_CORE1
+VDD_CORE2
+VDD_CORE3
+VDD_CORE4
+VDD_CORE5
+VDD_CORE6
+VDD_CORE7
+VDD_CORE8
+VDD_CORE9
+VDD_CORE10
+VDD_CORE11
+VDD_CORE12
+VDD_CORE13
+VDD_CORE14
+VDD_CORE15
+VDD_CORE16
+VDD_CORE17
+VDD_CORE18
+VDD_CORE19
+VDD_CORE20
+VDD_CORE21
+VDD_CORE22
+VDD_CORE23
+VDD_CORE24
+VDD_CORE25
+VDD_CORE26
+VDD_CORE27
+VDD_CORE28
+VDD_CORE29
+VDD_CORE30
+VDD_CORE31
+VDD_CORE32
+VDD_CORE33
+VDD_CORE34
+VDD_CORE35
+VDD_CORE36
+VDD_CORE37
+VDD_CORE38
+VDD_CORE39
+VDD_CORE40
+VDD_CORE41
+VDD_CORE42
+VDD_CORE43
+VDD_CORE44
+VDD_CORE45
+VDD_CORE46
+VDD_CORE47
+VDD_CORE48
+VDD_CORE49
+VDD_CORE50
+VDD_CORE51
+VDD_CORE52
+VDD_CORE53
+VDD_CORE54
+VDD_CORE55
+VDD_CORE56
+VDD_CORE57
+VDD_CORE58
+VDD_CORE59
+VDD_CORE60
+VDD_CORE61
+VDD_CORE62
+VDD_CORE63
+VDD_CORE64
+VDD_CORE65
+VDD_CORE66
+VDD_CORE67
+VDD_CORE68
+VDD_CORE69
+VDD_CORE70
+VDD_CORE71
+VDD_CORE72
+VDD_CORE73
+VDD_CORE74
+VDD_CORE75
+VDD_CORE76
+VDD_CORE77
+VDD_CORE78
+VDD_CORE79
+VDD_CORE80
+VDD_CORE81
POWER
AH34
GND161
GND162
GND163
GND164
GND165
GND166
GND167
GND168
GND169
GND170
GND171
GND172
GND173
GND174
GND175
GND176
GND177
GND178
GND179
GND180
GND181
GND182
GND183
GND184
GND185
GND186
GND187
GND188
GND189
GND190
GND191
GND192
GND193
GND194
GND195
GND196
GND197
GND198
GND199
GND200
GND201
GND202
GND203
GND204
GND205
GND206
GND207
GND208
GND209
GND210
GND211
GND212
GND213
GND214
GND215
GND216
GND217
GND218
GND219
GND220
GND221
GND222
GND223
GND224
GND225
GND226
GND227
GND228
GND229
GND230
GND231
GND232
GND233
GND234
GND235
GND236
GND237
GND238
GND239
GND240
GND241
GND242
GND243
GND244
GND245
GND246
GND247
GND248
GND249
GND250
GND251
GND252
GND
BGA
(11 OF 11)
AH33
OMIT
U1400
AH26
K35
L32
L33
L34
M31
M32
M33
N31
P32
Y32
AA32
+VTT_CPUCLK
AG32
+3.3V_1
+3.3V_2
+3.3V_3
+3.3V_4
+3.3V_5
+3.3V_6
+3.3V_7
+3.3V_8
AD10
43 mA
=PP3V3_S0_MCP
8 21 23
450 mA (A01)
AE8
AB10
AD9
Y10
AB11
AA8
Y9
=PP3V3_S5_MCP
+3.3V_DUAL1
+3.3V_DUAL2
+3.3V_DUAL3
+3.3V_DUAL4
G18
+3.3V_DUAL_USB1
+3.3V_DUAL_USB2
+3.3V_DUAL_USB3
+3.3V_DUAL_USB4
G26
+VDD_AUXC1
+VDD_AUXC2
+VDD_AUXC3
T21
16 mA
8 23
266 mA (A01)
H19
J20
K20
250 mA
H27
J28
K28
8 23
105 mA (A01)
MCP Power & Ground
U21
V21
SYNC_MASTER=T18_MLB

Y11
AH16
T22

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
22
123
8
MCP Core Power
45 22 8
NV: 1x 10uF 0805, 2x 4.7uF 0402, 3x 1uF 0402, 9x 0.1uF 0402 (23.3 uF)
Apple: 4x 4.7uF 0402, 4x 1uF 0402, 6x 0.1uF 0402 (23.4 uF)
=PPVCORE_S0_MCP
23065 mA (A01, 1.2V)
16996 mA (A01, 1.0V)
(No IG vs. EG data)
C2500
C2501
C2502
C2503
4.7UF
4.7UF
4.7UF
4.7UF
20%
4V
X5R
402
20%
4V
X5R
402
20%
4V
X5R
402
20%
4V
X5R
402
C2504
C2506
C2507
C2508
C2509
C2510
C2511
C2512
1UF
1UF
1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
10%
10V
X5R
402-1
10%
10V
X5R
402-1
10%
10V
X5R
402-1
10%
10V
X5R
402-1
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
MCP PCIE (DVDD) Power

8
C2505
1UF
C2513
0.1UF
20%
10V
CERM
402
MCP SATA (DVDD) Power
57 mA (A01)
43 mA (A01)
30-OHM-5A
=PP1V05_S0_MCP_AVDD_UF
333 mA (A01)
y
r
2
0603
C2515
4.7UF
20%
4V
X5R
402
C2516
1UF
C2517
1UF
10%
10V
X5R
402-1
C2518
C2519
0.1uF
10%
10V
X5R
402-1
C2520
0.1uF
20%
10V
CERM
402
20%
4V
X5R
402
MCP 1.05V AUX Power

22 8
C2521
4.7UF
20%
10V
CERM
402
0.1uF
2
20%
6.3V
CERM
402-LF
a
n
i
1
131 mA (A01)
0603
C2525
C2526
0.1uF
2
MCP FSB (VTT) Power

22 14 9 8
C2528
0.1uF
20%
10V
CERM
402
20%
4V
X5R
402
C2529
4.7uF
20%
10V
CERM
402
0.1uF
NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)

Apple: 7x 2.2uF 0402 (15.4 uF)
=PP1V05_S0_MCP_FSB
C2530
C2531
2.2UF
2
2.2UF
20%
6.3V
CERM
402-LF
2.2UF
20%
6.3V
CERM
402-LF
C2532
20%
6.3V
CERM
402-LF
C2533
2.2UF
C2534
2.2UF
20%
6.3V
CERM
402-LF
20%
6.3V
CERM
402-LF
C2535
2.2UF
2
C2536
=PP1V05_S0_MCP_PLL_PEX_UF
2.2UF
20%
6.3V
CERM
402-LF
20%
6.3V
CERM
402-LF
20%
4V
X5R
402
m
il
66 8
4.7UF
20%
4V
X5R
402
MCP 3.3V Power

=PP3V3_S0_MCP
C2541
C2542
C2543
C2544
0.1UF
0.1UF
0.1UF
0.1UF
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
C2550
C2551
C2552
2.2UF
2.2UF
2.2UF
20%
6.3V
CERM
402-LF
20%
6.3V
CERM
402-LF
20%
6.3V
CERM
402-LF
20%
6.3V
CERM
402-LF
e
r
C2553
2.2UF
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

Apple: 1x 2.2uF 0402 (2.2 uF)
83 mA (A01)
C2560
20%
6.3V
CERM
402-LF
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

Apple: 1x 2.2uF 0402 (2.2 uF)
7 mA (A01)
1
C2562
2.2UF
20%
6.3V
CERM
402-LF
L2595
30-OHM-1.7A
=PP1V05_ENET_MCP_PLL_MAC
5 mA (A01)
PP1V05_ENET_MCP_PLL_MAC
VOLTAGE=1.05V
2
0402
C2595
4.7UF
20%
4V
X5R
402
VOLTAGE=3.3V
0402
0.2
1%
1/6W
MF
402-HF
C2580
C2574
2.2UF
20%
6.3V
CERM
402-LF
20%
6.3V
CERM
402-LF
C2576
2.2UF
20%
6.3V
CERM
402-LF
17
84 mA (A01)
C2583
20%
6.3V
CERM
402-LF
2 16V
X5R
14
270 mA (A01)
C2581
2.2UF
4.7UF
10%
603
L2584
30-OHM-1.7A
PP1V05_S0_MCP_PLL_SATA
VOLTAGE=1.05V
2
0402
C2584
C2555
4.7UF
20%
4V
X5R
402
20%
6.3V
CERM
402-LF
20
84 mA (A01)
C2585
2.2UF
20%
6.3V
CERM
402-LF
B
L2586
30-OHM-1.7A
1
PP1V05_S0_MCP_PLL_CORE
C2586
4.7UF
20%
6.3V
CERM
402-LF
20%
4V
X5R
402
16
VOLTAGE=1.05V
2
0402
C2564
87 mA (A01)
C2587
2.2UF
20%
6.3V
CERM
402-LF
L2588
30-OHM-1.7A
1
PP1V05_S0_MCP_PLL_NV
C2588
4.7UF
20%
4V
X5R
402
21
VOLTAGE=1.05V
2
0402
C2589
2.2UF
2
20%
6.3V
CERM
402-LF
37 mA (A01)
C2590
0.1UF
20%
10V
CERM
402
R2591 1
MCP Standard Decoupling
1.47K
1%
1/16W
MF-LF
402
SYNC_MASTER=M98_MLB
2
MCP_MII_VREF
OUT
18

5 mA (A01)
R2590 1
1.47K
1%
1/16W
MF-LF
402 2
20%
6.3V
CERM
402-LF
18
C2596
C2591
0.1UF
2
20%
10V
CERM
402

SIZE
DRAWING NUMBER
D
APPLE INC.
REV.
051-7656
SCALE
SHT
NONE
206 mA (A01)
127 mA (A01)
PP1V05_S0_MCP_PLL_FSB
2.2UF
C2573
2.2UF
20%
6.3V
CERM
402-LF
VOLTAGE=1.05V
VOLTAGE=1.05V
19 mA (A01)
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

Apple: 1x 2.2uF 0402 (2.2 uF)
C2572
2.2UF
20%
4V
X5R
402
MCP79 Ethernet VRef
23 18 8
R2580
2.2UF
2.2UF
2
20%
10V
CERM
402
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

Apple: 1x 2.2uF 0402 (2.2 uF)
PP3V3_S0_MCP_PLL_USB
20
MCP 3.3V Ethernet Power
23 18 8
2.2UF
C2549
0.1UF
30-OHM-1.7A
19 mA (A01)
20%
10V
CERM
402
L2555
266 mA (A01)
21 8
C2548
0.1UF
MCP 3.3V/1.5V HDA Power
C2547
0.1UF
20%
10V
CERM
402
=PP3V3_S5_MCP
C2546
0.1UF
20%
10V
CERM
402
NV: 1x 4.7uF 0603, 4x 0.1uF 0402 (5.1 uF)

Apple: 4x 2.2uF 0402 (8.8 uF)
22 8
C2545
0.1UF
450 mA (A01)
MCP 3.3V AUX/USB Power
562 mA (A01)
2.2UF
PP1V05_S0_MCP_PLL_PEX
4.7UF
20%
6.3V
CERM
402-LF
VOLTAGE=1.05V
C2582
4771 mA (A01, DDR3)
C2540
0402
MCP Memory Power
22 21 8
20%
6.3V
CERM
402-LF
30-OHM-1.7A
16 8
C2575
L2582
1182 mA (A01)
2.2UF
2.2UF
20%
10V
CERM
402
C2571
VOLTAGE=1.05V
NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)

Apple: 2x 2.2uF 0402 (4.4 uF)
PP1V05_S0_MCP_SATA_AVDD
8
L2575
30-OHM-5A
18 8
105 mA (A01)
C2570
2.2UF
20%
10V
CERM
402
MCP 1.05V RMGT Power
NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 1uF 0402, 2x 0.1uF 0402 (16.9 uF)
Apple: 5x 2.2uF 0402 (11 uF)
PP1V05_S0_MCP_PEX_AVDD
L2570
31
OF
25
123
WF: Checklist says 0-ohm resistor placeholder for ferrite bead.

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
Apple: 1x 2.2uF 0402 (2.2 uF)
NO STUFF
18 8
190 mA (A01, 1.8V)
30-OHM-1.7A
=PP3V3_S0_MCP_DAC_UF
1
206 mA (A01)
1
NV: 1x 4.7uF 0603, 2x 0.1uF 0402 (4.9 uF)

Apple: 2x 2.2uF 0402 (4.4 uF)
PP3V3_S0_MCP_DAC
L2650
C2610
2.2UF
NO STUFF
1
20%
6.3V
CERM
402-LF
C2650
R2651
0
5%
1/16W
MF-LF
2 402
20%
6.3V
CERM
402-LF
95 mA (A01)
C2615
4.7UF
20%
4V
X5R
402
C2616
2.2UF
a
n
i
20%
6.3V
CERM
402-LF
18
TP_MCP_RGB_RED
18
TP_MCP_RGB_GREEN
18
18
MCP_HDMI_RSET
MCP_HDMI_VPROBE
90 18
90 18
90 18
90 18
NO STUFF
C2620
20%
10V
CERM
402
C2630
1K
1%
1/16W
MF-LF
402
20%
10V
CERM
402
=PP3V3_S0_MCP_VPLL_UF
VOLTAGE=3.3V
C2640
4.7UF
HDCP ROM
WF: Open question on which packge option(s) nVidia can support.
=PP3V3_S0_HDCPROM
20%
10V
CERM
402
NO STUFF
NO STUFF
AT24C08
A0
A1
3
A2
SOIC
1
2
P
5%
1/16W
MF-LF
402
VCC
U2695
R2690 1
NO STUFF
10K
SDA
SCL
5
6
=I2C_HDCPROM_SDA
=I2C_HDCPROM_SCL
WP
HDCPROM_WP
GND
4
1K
1%
1/16W
MF-LF
402
90 18
m
il
BI
IN
16 mA (A01)
C2641
44
44
20%
6.3V
CERM
402-LF
TP_MCP_RGB_HSYNC
TP_MCP_RGB_VSYNC
CRT_IG_R_C_PR
CRT_IG_G_Y_Y
NC_MCP_RGB_RED
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_MCP_RGB_GREEN
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_MCP_RGB_BLUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_MCP_RGB_HSYNC
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_MCP_RGB_VSYNC
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_CRT_IG_R_C_PR
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_CRT_IG_G_Y_Y
MAKE_BASE=TRUE
NO_TEST=TRUE
90 18
CRT_IG_B_COMP_PB
NC_CRT_IG_B_COMP_PB
90 18
CRT_IG_HSYNC
NC_CRT_IG_HSYNC
90 18
CRT_IG_VSYNC
NC_CRT_IG_VSYNC
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
18
TP_MCP_RGB_DAC_RSET
NC_MCP_RGB_DAC_RSET
18
TP_MCP_RGB_DAC_VREF
NC_MCP_RGB_DAC_VREF
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
90 18
MCP_TV_DAC_RSET
NC_MCP_TV_DAC_RSET
90 18
MCP_TV_DAC_VREF
NC_MCP_TV_DAC_VREF
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
18
MCP_CLK27M_XTALIN
NC_MCP_CLK27M_XTALIN
18
MCP_CLK27M_XTALOUT
NC_MCP_CLK27M_XTALOUT
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
e
r
R2630
2.2UF
20%
6.3V
CERM
603
0.1UF
90 18
0.1UF
0402
C2690
WF: Checklist says 0-ohm resistor placeholder for ferrite bead.

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
L2640
Apple: ???
30-OHM-1.7A
PP3V3_S0_MCP_VPLL
18
16 mA (A01)
NO STUFF
NO STUFF
R2620
0.1UF
18
MCP_IFPAB_RSET
MCP_IFPAB_VPROBE
TP_MCP_RGB_BLUE
y
r
18 8
206 mA (A01)
2.2UF
2
18
VOLTAGE=3.3V
2
0402
MCP Graphics Support

SYNC_MASTER=M98_MLB

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
Current numbers from email Xiaowei Lin provided 11/12/2007 3:22pm (no official document number).
REV.
051-7656
31
OF
26
123
RTC Power Sources
R2803
1
2
5%
1/16W
MF-LF
402
RTC_PS_YES
VIN
LPC Reset (Unbuffered)
U2801
R2881
MIC5232-2.8YD5
TSOT-23-5
3
EN
91 84 19
CRITICAL VOUT
PP3V3_G3_RTC
IN
LPC_RESET_L
33
C2802
NO STUFF1
R2801
C28011
10
5%
1/16W
MF-LF
402
1UF
10%
6.3V
CERM
402
NO STUFF
R2802
2
1.0M
2%
3.3V
XHHG
SM
CRITICAL
21
IN
21
OUT
10M
Y2810
5%
1/16W
MF-LF
402 2
7X1.5X1.4-SM
32.768K
C2811
CRITICAL
4
R2811
RTC_CLK32K_XTALOUT_R
5%
1/16W
MF-LF
402
2
5%
50V
CERM
402
R2810
NO STUFF
a
n
i
12pF
1
12pF
1
RTC_CLK32K_XTALIN
2
5%
50V
CERM
402
MCP 25MHz Crystal

21
IN
C2815
12pF
1
MCP_CLK25M_XTALOUT
CRITICAL
21
OUT
Y2815
5%
1/16W
MF-LF
402 2
25.0000M
1M
m
il
5%
1/16W
MF-LF
402
SM-3.2X2.5MM
R2816
MCP_CLK25M_XTALOUT_R
NO STUFF
2
5%
50V
CERM
402
R2815
1
NC
NC
C2816
12pF
1
MCP_CLK25M_XTALIN
2
5%
50V
CERM
402
e
r
MCP S0 PWRGD & CPU_VLD

8
=PP3V3_S5_MCPPWRGD
MCPSEQ_SMC
1
C2850
0.1UF
20%
10V
CERM
402
MCPSEQ_SMC
84 67 41
IN
ALL_SYS_PWRGD
IN
VR_PWRGOOD_DELAY
5 TC7SZ08AFEAPE
SOT665
U2850 Y
61
B
3
S0_AND_IMVP_PGOOD
MCPSEQ_SMC
R2853
0
R2851
0
5%
1/16W
MF-LF
402
21
IN
MCP_CPUVDD_EN
OUT
41
FW_RESET_L
OUT
35
MCP_PS_PWRGD
OUT
21
5%
1/16W
MF-LF
402
MCP_CPU_VLD
OUT
21
19
91 19
IN
IN
IN
PCIE_RESET_L
5%
1/16W
MF-LF
402
R2890
0
GMUX_PCIE_RESET_L
MAKE_BASE=TRUE
5%
1/16W
MF-LF
402
=GMUX_PCIE_RESET_L
84
R2893
0
PCA9557D_RESET_L
OUT
26
OUT
86
5%
1/16W
MF-LF
402
BKLT_PLT_RST_L
5%
1/16W
MF-LF
402
R2894
0
1
MINI_RESET_L
OUT
30
OUT
31
OUT
LPC_CLK33M_SMC
OUT
41 91
LPC_CLK33M_LPCPLUS
OUT
7 43 91
5%
1/16W
MF-LF
402
R2895
1
EXCARD_RESET_L
5%
1/16W
MF-LF
402
R2870
33
1
MEM_VTT_EN
2
5%
1/16W
MF-LF
402
R2825
33
5%
1/16W
MF-LF
402
R2826
33
1
R2827
1
33
2
5%
1/16W
MF-LF
402
LPC_CLK33M_GMUX
OUT
84
OUT
41 91
5%
1/16W
MF-LF
402
R2829
91 21
IN
22
PM_CLK32K_SUSCLK_R
1
PM_CLK32K_SUSCLK
2
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
Reset Button
MCPSEQ_SMC
R2850
1
41 7
IN
PM_SYSRST_L
XDP
R2896
5%
1/16W
MF-LF
402
13 10
IN
XDP_DBRESET_L
0
5%
1/16W
MF-LF
402
R2899
OMIT
R2897 1
33
10K pull-up to 3.3V S0 inside MCP

5%
1/16W
MF-LF
402
SB Misc
OUT
21
NO STUFF
5%
1/16W
MF-LF
402
SYNC_MASTER=M98_MLB
C2899
1UF
MCPSEQ_MIX is cross between MLB and internal power sequencing, which

results in earlier ROMSIP and MCP FSB I/O interface initialization.
10%
10V
X5R
402

SILK_PART=FP SYS RESET
SMC 99ms delay from ALL_SYS_PWRGD to IMVP_VR_ON plus IMVP6 delay for
VR_PWRGOOD_DELAY should guarantee CPU_VLD does not go high before
CPUVDD_EN (which is 40-100ms after PS_PWRGD assertion).

SIZE
DRAWING NUMBER
NOTE: If CPU_VLD deasserts during S0 MCP79 will take system to S5 immediately.
APPLE INC.
REV.
051-7656
SCALE
SHT
NONE
OUT
R2891
MEM_VTT_EN_R
LPC_CLK33M_SMC_R
R2852
MCPSEQ_SMC represents MCP79 MLB power sequencing connections,

but results in MCP79 ROMSIP sequence happening after CPU powers up.
MCPSEQ_MIX
SMC_LRESET_L
5%
1/16W
MF-LF
402
MCPSEQ_MIX
R2892
17
C2810
RTC_CLK32K_XTALOUT
7 43
PCIE Reset (Unbuffered)
5%
1/10W
MF-LF
603
RTC Crystal
OUT
y
r
C2800
0.08F SUPERCAP_YES
RTC_DISCHARGE_R
33
SUPERCAP_YES
5%
1/16W
MF-LF
402
PP3V3_G3_SUPERCAP
2
DEBUG_RESET_L
R2883
1
R2800
100
GND
1UF
10%
10V
X5R
402
NC
5%
1/16W
MF-LF
402
21 22
VOLTAGE=3.3V
NO STUFF
Platform Reset Connections
=PP3V3_S5_RTC_D
1
31
OF
28
123
Page Notes
MEM A VREF DQ
Power aliases required by this page:
MEM A VREF CA
MEM B VREF DQ
MEM B VREF CA
CPU FSB VREF
FRAME BUFFER VREF
- =PP3V3_S3_VREFMRGN
DAC channel
- =PP3V3_S5_VREFMRGN
Min DAC code
0x00
0x00
0x00
0x00
0x00
Max DAC code
0x87
0x87
0x87
0x87
0x55
0x00
- =PPVTT_S3_DDR_BUF
Signal aliases required by this page:
Max sink I
-3.75 mA
-3.75 mA
-3.75 mA
-3.75 mA
- =I2C_VREFDACS_SCL
Max source I
5 mA
5 mA
5 mA
5 mA
- =I2C_VREFDACS_SDA
Nominal Vref
0.75 V
0.75 V
0.75 V
0.75 V
- =I2C_PCA9557D_SCL
Min Vref
0.375 V
0.375 V
0.375 V
0.375 V
- =I2C_PCA9557D_SDA
Max Vref
1.250 V
1.250 V
1.250 V
1.250 V
Vref Stepping
6.5 mV
6.5 mV
6.5 mV
6.5 mV
0xFF
-0.91 mA
-59.04 mA
0.52 mA
51.15 mA
0.70 V
1.248 V
0.091 V
1.042 V
1.044 V
1.426 V
SO-DIMM A and SO-DIMM B Vref settings should be margined separately

(i.e. not simultaneously) due to current limitation of TPS51116 regulator.
=PPVTT_S3_DDR_BUF
63 8
11.2 mV
1.5 mV
BOM options provided by this page:
10mA max load
(per DAC LSB)

VREFMRGN
y
r
R2903
NO_VREFMRGN
VREFMRGN
200
B1
VREFMRGN
1
A2
C2903
V+
0.1UF
R2918
SHORT2
1
=PP3V3_S3_VREFMRGN
8
PP3V3_S3_VREFMRGN_DAC
U2902
A3
UCSP
A1
V-
26 VREFMRGN_DQ_SODIMMA_EN
VREFMRGN
a
n
i
0.1UF
20%
6.3V
CERM
402-LF
100K
20%
10V
CERM
402
B1
C2
V+
VREFMRGN
C3
VDD
44
IN
=I2C_VREFDACS_SCL
BI
=I2C_VREFDACS_SDA
6 SCL
7 SDA
9 A0
ADDR=0x98(WR)/0x99(RD)
UCSP
C1
VOUTA
VREFMRGN_DQ_SODIMM
VOUTB
VREFMRGN_CA_SODIMM
VOUTC
VREFMRGN_CPUFSB
VOUTD
VREFMRGN_FRAMEBUF
VREFMRGN_DQ_SODIMMB_BUF
C4
V-
26 VREFMRGN_DQ_SODIMMB_EN
B4
MSOP
DAC5574
44
5%
1/16W
MF-LF
402
VREFMRGN
MAX4253
VREFMRGN
U2900
U2902
R2902
100K
10 A1
5%
1/16W
MF-LF
402
B1
VREFMRGN
1
GND
3
A2
C2904
V+
0.1UF
2
MAX4253
UCSP
VREFMRGN
20%
10V
CERM
402
A3
VREFMRGN
U2903
A1
VREFMRGN_CA_SODIMMA_BUF
R2909
SHORT2
PP3V3_S3_VREFMRGN_CTRL
NONE
NONE
NONE
402
CRITICAL
VREFMRGN
C2902
16
0.1UF
2
20%
10V
CERM
402
VREFMRGN
VCC
P
U2901
PCA9557
QFN
4
5
44
44
IN
=I2C_PCA9557D_SCL
BI
=I2C_PCA9557D_SDA
1
2
A0
A1
A2
SCL
SDA
THRM
17
PAD
A
Required zero ohm resistors when no VREF margining circuit stuffed
PART NUMBER
116S0004
QTY
1
DESCRIPTION
REFERENCE DES
R2903
RES,MTL FILM,0,5%,0402,SM,LF
RESET*
GND
NC
7
9
10
11
12
13
14
15
B1
V+
U2904
100
1
A1
26
C3
5%
1/16W
MF-LF
402
B4
VREFMRGN_DQ_SODIMMA_EN
26
VREFMRGN_CA_SODIMMB_EN
VREFMRGN
2
1
1
GPU_FB_A_VREF_DIV
OUT
OUT
OUT
10 88
Place close to U8400, U8450
49.9
1%
1/16W
MF-LF
402
VREFMRGN
GPU_FB_B_VREF_DIV
Place close to U8500, U8550
R2914
MAX4253
UCSP
VREFMRGN
100
1
VREFMRGN_CPUFSB_BUF
CPU_GTLREF
2
1%
1/16W
MF-LF
402
26 VREFMRGN_CPUFSB_EN
5%
1/16W
MF-LF
402
26
R2916
VREFMRGN
C4
V-
Place close to J3200.126
R2917
100K
C1
1%
1/16W
MF-LF
402
26 VREFMRGN_FRAMEBUF_EN
U2904
28
49.9
100K
VREFMRGN_CA_SODIMMA_EN
100
VREFMRGN
VREFMRGN_FRAMEBUF_BUF
R2915
B1
PP0V75_S3_MEM_VREFCA_B
R2912
V+
VREFMRGN
1%
1/16W
MF-LF
402
B4
VREFMRGN
200
1%
1/16W
MF-LF
402
R2913
VREFMRGN_CPUFSB_EN
VREFMRGN
A4
C2
R2911
1
UCSP
V-
2
1%
1/16W
MF-LF
402
MAX4253
VREFMRGN
A3
27
VREFMRGN
100K
A2
PP0V75_S3_MEM_VREFCA_A
R2910
Place close to U1000.AD26
VREFMRGN
26
VREFMRGN_DQ_SODIMMB_EN
26
VREFMRGN_FRAMEBUF_EN
26
NC
PCA9557D_RESET_L
IN
25
ADDR=0x30(WR)/0x31(RD)
P0
P1
P2
P3
P4
P5
P6
P7
VREFMRGN_CA_SODIMMB_BUF
5%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
26 VREFMRGN_CA_SODIMMB_EN
R2908
C2905
20%
10V
CERM
402
C1
VREFMRGN
200
C4
B4
0.1UF
UCSP
V-
VREFMRGN
MAX4253
VREFMRGN
C3
R2919
V+
5%
1/16W
MF-LF
402
28
e
r
C2
U2903
100
VREFMRGN
m
il
VREFMRGN
B1
PP0V75_S3_MEM_VREFDQ_B
1%
1/16W
MF-LF
402
B4
100K
VREFMRGN
R2906
26 VREFMRGN_CA_SODIMMA_EN
R2907
200
1%
1/16W
MF-LF
402
A4
V-
R2905
R2901
C2901
2.2UF
C2900
1%
1/16W
MF-LF
402
VREFMRGN
1
27
VREFMRGN
100
VREFMRGN_DQ_SODIMMA_BUF
A4
B4
NONE
NONE
NONE
402
PP0V75_S3_MEM_VREFDQ_A
R2904
MAX4253
VREFMRGN
20%
10V
CERM
402
1%
1/16W
MF-LF
402
CRITICAL
CRITICAL
FSB/DDR3/FRAMEBUF Vref Margining

SYNC_MASTER=BEN_K20

BOM OPTION

NO_VREFMRGN
116S0004
R2905
CRITICAL
NO_VREFMRGN
116S0004
R2909
CRITICAL
NO_VREFMRGN
116S0004
R2911
CRITICAL
NO_VREFMRGN
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
29
123
DDR3 PLANE STITCHING CAPS (SPACE EVENLY ACROSS PLANE SPLIT)
Page Notes
8
=PP1V5_S0_MEM_A
=PP1V5_S3_MEM_A

- =PP1V5_S0_MEM_A
- =PP1V5_S3_MEM_A
- =PP0V75_S0_MEM_VTT_A
- =PPSPD_S0_MEM_A (2.5 - 3.3V)
- =I2C_SODIMMA_SCL
C3111
C3112
C3113
C3114
C3115
C3116
C3117
C3118
C3119
C3120
C3121
C3122
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
C3123
0.1UF
20%
10V
CERM
402
C3101
10UF
20%
6.3V
X5R
603
20%
6.3V
X5R
603
26 PP0V75_S3_MEM_VREFDQ_A
(NONE)
C3130
0.1UF
20%
6.3V
2
20%
10V
2
CERM
402-LF
CERM
402
1
73
MEM_A_CKE<0>
NC
89 15
MEM_A_BA<2>
79
89 15
IN
MEM_A_A<12>
81
83
89 15
IN
MEM_A_A<9>
85
IN
MEM_A_A<8>
87
89
89 15
IN
MEM_A_A<5>
91
89 15
IN
MEM_A_A<3>
93
95
89 15
IN
MEM_A_A<1>
89 15
IN
MEM_A_CLK_P<0>
89 15
IN
MEM_A_CLK_N<0>
89 15
IN
MEM_A_A<10>
89 15
IN
MEM_A_BA<0>
89 15
IN
MEM_A_WE_L
89 15
IN
MEM_A_CAS_L
89 15
IN
MEM_A_A<13>
IN
MEM_A_CS_L<1>
89 15
IN
75
77
89 15
97
99
101
103
105
107
109
111
113
115
117
119
121
123
NC
89 15
BI
MEM_A_DQ<33>
89 15
BI
MEM_A_DQ<32>
89 15
BI
MEM_A_DQS_N<4>
89 15
BI
MEM_A_DQS_P<4>
89 15
BI
MEM_A_DQ<34>
89 15
BI
MEM_A_DQ<35>
125
127
129
131
133
135
137
139
141
143
145
BI
MEM_A_DQ<44>
89 15
BI
MEM_A_DQ<41>
89 15
IN
MEM_A_DM<5>
89 15
BI
MEM_A_DQ<45>
89 15
BI
MEM_A_DQ<42>
89 15
BI
MEM_A_DQ<52>
89 15
BI
MEM_A_DQ<51>
89 15
147
149
151
153
155
157
159
161
163
165
167
89 15
BI
MEM_A_DQS_N<6>
89 15
BI
MEM_A_DQS_P<6>
169
171
173
89 15
89 15
BI
MEM_A_DQ<55>
BI
MEM_A_DQ<54>
BI
MEM_A_DQ<61>
89 15
BI
MEM_A_DQ<60>
89 15
IN
MEM_A_DM<7>
181
183
185
187
189
89 15
BI
MEM_A_DQ<58>
89 15
BI
MEM_A_DQ<59>
191
193
195
MEM_A_SA<0>
8 =PPSPD_S0_MEM_A
MEM_A_SA<1>
197
199
201
203
1
1
C3140
10K
2.2UF
20%
6.3V
2
CERM
402-LF
R3140
R3141
10K
5%
5%
1/16W
1/16W
MF-LF
MF-LF
402
402
J3100
74
MEM_A_CKE<1>
IN
15 89
76
78
MEM_A_A<15>
IN
80
MEM_A_A<14>
IN
15 89
89 15
89 15
BI
BI
89 15
IN
MEM_A_A<11>
IN
15 89
89 15
BI
MEM_A_A<7>
IN
15 89
89 15
BI
MEM_A_DQ<2>
MEM_A_A<6>
MEM_A_A<4>
IN
15 89
94
96
MEM_A_A<2>
IN
15 89
MEM_A_A<0>
IN
MEM_A_CLK_P<1>
MEM_A_CLK_N<1>
98
100
102
104
106
108
110
112
114
116
118
120
122
BI
MEM_A_DQ<9>
89 15
BI
MEM_A_DQ<13>
89 15
BI
MEM_A_DQS_N<1>
15 89
89 15
BI
MEM_A_DQS_P<1>
IN
15 89
89 15
BI
MEM_A_DQ<11>
IN
15 89
89 15
BI
MEM_A_DQ<14>
MEM_A_BA<1>
IN
15 89
89 15
BI
MEM_A_DQ<16>
MEM_A_RAS_L
IN
15 89
89 15
BI
MEM_A_DQ<18>
MEM_A_CS_L<0>
IN
15 89
89 15
BI
MEM_A_DQS_N<2>
MEM_A_ODT<0>
IN
15 89
89 15
BI
MEM_A_DQS_P<2>
MEM_A_ODT<1>
IN
15 89
89 15
BI
MEM_A_DQ<23>
IN
126
128
136
138
140
142
144
146
148
150
89 15
89 15
MEM_A_DQ<36>
MEM_A_DQ<37>
MEM_A_DM<4>
MEM_A_DQ<38>
MEM_A_DQ<39>
MEM_A_DQ<47>
MEM_A_DQ<40>
152
154
156
158
160
162
164
166
MEM_A_DQS_N<5>
MEM_A_DQS_P<5>
MEM_A_DQ<46>
MEM_A_DQ<43>
MEM_A_DQ<48>
MEM_A_DQ<53>
168
170
172
174
176
178
180
182
184
186
188
MEM_A_DM<6>
MEM_A_DQ<50>
BI
15 89
BI
15 89
IN
15 89
BI
15 89
BI
15 89
BI
15 89
BI
15 89
BI
15 89
BI
15 89
BI
15 89
BI
15 89
BI
15 89
IN
15 89
BI
15 89
MEM_A_DQ<57>
BI
15 89
MEM_A_DQ<56>
BI
15 89
MEM_A_DQS_N<7>
MEM_A_DQ<24>
BI
MEM_A_DQ<30>
IN
MEM_A_DM<3>
89 15
BI
MEM_A_DQ<27>
89 15
BI
MEM_A_DQ<25>
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
PP0V75_S3_MEM_VREFCA_A
C3135
2.2UF
4
6
MEM_A_DQ<4>
MEM_A_DQ<5>
8
10
MEM_A_DQS_N<0>
51
53
55
57
59
61
63
65
67
69
71
12
MEM_A_DQS_P<0>
14
16
MEM_A_DQ<6>
18
MEM_A_DQ<7>
20
22
MEM_A_DQ<8>
24
MEM_A_DQ<12>
26
28
MEM_A_DM<1>
30
32
MEM_RESET_L
34
MEM_A_DQ<15>
BI
15 89
BI
15 89
BI
15 89
BI
15 89
BI
15 89
BI
15 89
BI
15 89
BI
15 89
IN
15 89
IN
28 29
BI
15 89
BI
15 89
MEM_A_DQ<21>
BI
15 89
MEM_A_DQ<20>
BI
15 89
46
MEM_A_DM<2>
IN
48
50
MEM_A_DQ<17>
BI
15 89
MEM_A_DQ<22>
BI
15 89
MEM_A_DQ<29>
BI
15 89
MEM_A_DQ<28>
BI
15 89
MEM_A_DQS_N<3>
BI
15 89
MEM_A_DQS_P<3>
BI
15 89
MEM_A_DQ<26>
BI
15 89
MEM_A_DQ<31>
BI
15 89
36
38
MEM_A_DQ<10>
40
42
44
52
54
56
58
60
62
64
66
68
70
72
15 89
KEY
516-0201
15 89
BI
15 89
MEM_A_DQ<62>
BI
15 89
MEM_A_DQ<63>
BI
15 89
C3136
20%
10V
CERM
402-LF
MEM_A_DQS_P<7>
26
0.1UF
20%
6.3V
BI
J3100
15 89
BI
MEM_A_DQ<49>
17
MEM_A_DQ<19>
BI
89 15
15 89
BI
BI
VREFDQ
VSS
VSS
DQ4
DQ5
DQ0
CRITICAL
VSS
DQ1
VSS
DQS0*
DQS0
DM0
F-RT-THB
VSS
VSS
DQ2
DQ6
DQ3
DQ7
VSS
VSS
DQ12
DQ8
DQ13
DQ9
VSS
VSS
DQS1*
DM1
RESET*
DQS1
VSS
VSS
DQ14
DQ10
DQ15
DQ11
VSS
VSS
DQ20
DQ16
DQ17
DQ21
VSS
VSS
DQS2*
DM2
DQS2
VSS
DQ22
VSS
DQ18
DQ23
VSS
DQ19
DQ28
VSS
DQ24
DQ29
VSS
DQ25
DQS3*
VSS
DQS3
DM3
VSS
VSS
DQ30
DQ26
DQ31
DQ27
VSS
VSS
a
n
i
13
15
m
il
NC
132
134
89 15
89 15
124
130
15 89
11
MEM_A_DM<0>
86
92
7
9
MEM_A_DQ<1>
MEM_A_DQ<3>
88
90
3
5
MEM_A_DQ<0>
82
84
e
r
P
175
177
179
89 15
CKE0
CKE1
VDD
VDD
NC
A15
BA2
A14
F-RT-THB
VDD
VDD
A12/BC*
A11
A9
A7
VDD
VDD
A8
A6
A5
A4
VDD
VDD
A3
A2
A1
A0
VDD
VDD
CK1
CK0
CK0*
CK1*
VDD
VDD
A10/AP
BA1
RAS*
BA0
VDD
VDD
WE*
S0*
CAS*
ODT0
VDD
VDD
ODT1
A13
S1*
NC
VDD
VDD
TEST
VREFCA
VSS
VSS
DQ32
DQ36
DQ33
DQ37
VSS
VSS
DM4
DQS4*
DQS4
VSS
DQ38
VSS
DQ39
DQ34
DQ35
VSS
VSS
DQ44
DQ45
DQ40
DQ41
VSS
VSS
DQS5*
DM5
DQS5
VSS
VSS
DQ42
DQ46
DQ43
DQ47
VSS
VSS
DQ48
DQ52
DQ49
DQ53
VSS
VSS
DQS6*
DM6
VSS
DQS6
DQ54
VSS
DQ50
DQ55
DQ51
VSS
VSS
DQ60
DQ56
DQ61
DQ57
VSS
VSS
DQS7*
DM7
DQS7
VSS
VSS
DQ58
DQ62
DQ59
DQ63
VSS
VSS
SA0
EVENT*
VDDSPD
SDA
SCL
SA1
VTT
VTT
(SYMBOL 2 OF 2)
IN
DDR3-SODIMM-DUAL-M97-3
89 15
KEY
y
r
C3131
2.2UF
(SYMBOL 1 OF 2)
DDR3-SODIMM-DUAL-M97-3
C3100
10UF
- =I2C_SODIMMA_SDA
C3110
CERM
402
190
192
194
196
198
200
=I2C_SODIMMA_SDA
BI
202
=I2C_SODIMMA_SCL
IN
MEM_EVENT_L
OUT
21 28 41
"Factory" (top) slot
44
44
204
=PP0V75_S0_MEM_VTT_A
DDR3 SO-DIMM Connector A

SYNC_MASTER=BEN_K20
516-0201
SPD ADDR=0xA0(WR)/0xA1(RD)

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
31
123
DDR3 PLANE STITCHING CAPS (SPACE EVENLY ACROSS PLANE SPLIT)
Page Notes
8
=PP1V5_S0_MEM_B
=PP1V5_S3_MEM_B

- =PP1V5_S0_MEM_B
- =PP1V5_S3_MEM_B
- =PP0V75_S0_MEM_VTT_B
- =PPSPD_S0_MEM_B (2.5 - 3.3V)
C3200
- =I2C_SODIMMB_SCL
C3211
C3212
C3213
C3214
C3215
C3216
C3217
C3218
C3219
C3220
C3221
C3222
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
C3223
0.1UF
20%
10V
CERM
402
C3201
10UF
20%
6.3V
X5R
603
20%
6.3V
X5R
603
26 PP0V75_S3_MEM_VREFDQ_B
(NONE)
C3230
0.1UF
20%
10V
20%
6.3V
2
CERM
CERM
402
402-LF
1
73
203
CKE0
CKE1
VDD
VDD
NC
A15
A14
BA2
VDD F-RT-BGA3 VDD
A11
A12/BC*
A9
A7
VDD
VDD
A8
A6
A5
A4
VDD
VDD
A3
A2
A1
A0
VDD
VDD
CK1
CK0
CK0*
CK1*
VDD
VDD
A10/AP
BA1
RAS*
BA0
VDD
VDD
S0*
WE*
CAS*
ODT0
VDD
VDD
ODT1
A13
S1*
NC
VDD
VDD
TEST
VREFCA
VSS
VSS
DQ36
DQ32
DQ37
DQ33
VSS
VSS
DQS4*
DM4
DQS4
VSS
VSS
DQ38
DQ34
DQ39
DQ35
VSS
DQ44
VSS
DQ40
DQ45
DQ41
VSS
VSS
DQS5*
DM5
DQS5
VSS
VSS
DQ42
DQ46
DQ47
DQ43
VSS
VSS
DQ52
DQ48
DQ53
DQ49
VSS
VSS
DQS6*
DM6
DQS6
VSS
VSS
DQ54
DQ50
DQ55
DQ51
VSS
VSS
DQ60
DQ56
DQ61
DQ57
VSS
DQS7*
VSS
DM7
DQS7
VSS
VSS
DQ58
DQ62
DQ59
DQ63
VSS
VSS
EVENT*
SA0
VDDSPD
SDA
SA1
SCL
VTT
VTT
205
207
MTG PIN
MTG PIN
209
211
MTG PIN
MTG PIN
75
77
89 15
79
89 15
IN
MEM_B_A<12>
81
83
89 15
IN
MEM_B_A<9>
85
IN
MEM_B_A<8>
87
89
89 15
IN
MEM_B_A<5>
91
89 15
IN
MEM_B_A<3>
93
95
89 15
IN
MEM_B_A<1>
89 15
IN
MEM_B_CLK_P<0>
89 15
IN
MEM_B_CLK_N<0>
89 15
IN
MEM_B_A<10>
89 15
IN
MEM_B_BA<0>
89 15
IN
MEM_B_WE_L
89 15
IN
MEM_B_CAS_L
89 15
IN
MEM_B_A<13>
IN
MEM_B_CS_L<1>
89 15
IN
MEM_B_BA<2>
89 15
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
89 15
BI
MEM_B_DQ<32>
89 15
BI
MEM_B_DQ<37>
89 15
BI
MEM_B_DQS_N<4>
89 15
BI
MEM_B_DQS_P<4>
89 15
BI
MEM_B_DQ<34>
89 15
BI
MEM_B_DQ<35>
129
131
133
135
137
139
141
143
145
BI
MEM_B_DQ<41>
89 15
BI
MEM_B_DQ<40>
89 15
IN
MEM_B_DM<5>
89 15
BI
MEM_B_DQ<43>
89 15
BI
MEM_B_DQ<42>
89 15
BI
MEM_B_DQ<55>
89 15
BI
MEM_B_DQ<49>
89 15
147
149
151
153
155
157
159
161
163
165
167
89 15
BI
MEM_B_DQS_N<6>
89 15
BI
MEM_B_DQS_P<6>
169
171
173
89 15
89 15
BI
MEM_B_DQ<52>
BI
MEM_B_DQ<51>
R3240
BI
MEM_B_DQ<56>
89 15
BI
MEM_B_DQ<57>
89 15
MEM_B_DM<7>
IN
5%
1/16W
89 15
BI
MEM_B_DQ<63>
89 15
BI
MEM_B_DQ<59>
MF-LF
402
185
187
189
10K
181
183
191
193
195
MEM_B_SA<0>
8 =PPSPD_S0_MEM_B
MEM_B_SA<1>
1
1
C3240
5%
20%
6.3V
2
R3241
10K
2.2UF
1/16W
MF-LF
CERM
402-LF
402
197
199
201
74
MEM_B_CKE<1>
76
78
MEM_B_A<15>
80
MEM_B_A<14>
IN
MTG PINS
MTG PIN
MTG PIN
MTG PIN
MTG PIN
89 15
15 89
IN
IN
15 89
BI
89 15
BI
MEM_B_DQ<1>
89 15
IN
MEM_B_DM<0>
MEM_B_A<11>
IN
15 89
89 15
BI
MEM_B_DQ<2>
86
MEM_B_A<7>
IN
15 89
89 15
BI
MEM_B_DQ<3>
88
90
MEM_B_A<6>
92
MEM_B_A<4>
IN
15 89
94
96
MEM_B_A<2>
IN
15 89
MEM_B_A<0>
IN
MEM_B_CLK_P<1>
MEM_B_CLK_N<1>
98
100
102
104
106
108
110
112
114
116
118
120
122
BI
MEM_B_DQ<28>
89 15
BI
MEM_B_DQ<24>
89 15
BI
MEM_B_DQS_N<3>
15 89
89 15
BI
MEM_B_DQS_P<3>
IN
15 89
89 15
BI
MEM_B_DQ<31>
IN
15 89
89 15
BI
MEM_B_DQ<30>
MEM_B_BA<1>
IN
15 89
89 15
BI
MEM_B_DQ<9>
MEM_B_RAS_L
IN
15 89
89 15
BI
MEM_B_DQ<8>
MEM_B_CS_L<0>
IN
15 89
89 15
BI
MEM_B_DQS_N<1>
MEM_B_ODT<0>
IN
15 89
89 15
BI
MEM_B_DQS_P<1>
MEM_B_ODT<1>
IN
15 89
89 15
BI
MEM_B_DQ<15>
IN
126
128
136
138
140
142
144
146
148
150
89 15
89 15
MEM_B_DQ<33>
MEM_B_DQ<36>
MEM_B_DM<4>
MEM_B_DQ<38>
MEM_B_DQ<39>
MEM_B_DQ<44>
MEM_B_DQ<45>
152
154
156
158
160
162
164
166
MEM_B_DQS_N<5>
MEM_B_DQS_P<5>
MEM_B_DQ<47>
MEM_B_DQ<46>
MEM_B_DQ<48>
MEM_B_DQ<54>
168
170
172
174
176
178
180
182
184
186
188
MEM_B_DM<6>
MEM_B_DQ<53>
BI
15 89
BI
15 89
IN
BI
15 89
BI
15 89
BI
15 89
BI
15 89
BI
15 89
BI
15 89
BI
15 89
BI
15 89
BI
15 89
BI
15 89
IN
MEM_B_DQ<21>
BI
MEM_B_DQ<17>
IN
MEM_B_DM<2>
89 15
BI
MEM_B_DQ<18>
89 15
BI
MEM_B_DQ<22>
15 89
15 89
MEM_B_DQ<60>
BI
15 89
MEM_B_DQ<61>
BI
15 89
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
4
6
8
10
MEM_B_DQ<4>
MEM_B_DQ<5>
MEM_B_DQS_N<0>
BI
15 89
BI
15 89
BI
15 89
12
MEM_B_DQS_P<0>
BI
15 89
14
16
MEM_B_DQ<6>
BI
15 89
18
MEM_B_DQ<7>
BI
15 89
20
22
MEM_B_DQ<29>
BI
15 89
24
MEM_B_DQ<25>
26
28
MEM_B_DM<3>
30
32
34
MEM_RESET_L
MEM_B_DQ<26>
BI
15 89
IN
15 89
IN
27 29
BI
15 89
BI
15 89
MEM_B_DQ<13>
BI
15 89
MEM_B_DQ<12>
BI
15 89
46
MEM_B_DM<1>
IN
48
50
MEM_B_DQ<14>
BI
15 89
MEM_B_DQ<11>
BI
15 89
MEM_B_DQ<20>
BI
15 89
MEM_B_DQ<16>
BI
15 89
MEM_B_DQS_N<2>
BI
15 89
MEM_B_DQS_P<2>
BI
15 89
MEM_B_DQ<19>
BI
15 89
MEM_B_DQ<23>
BI
15 89
36
38
40
42
44
52
54
56
58
60
62
64
66
68
70
72
MEM_B_DQ<27>
15 89
KEY
516s0706
PP0V75_S3_MEM_VREFCA_B
C3235
2.2UF
15 89
BI
15 89
MEM_B_DQ<58>
BI
15 89
MEM_B_DQ<62>
BI
15 89
C3236
20%
10V
CERM
402-LF
MEM_B_DQS_P<7>
26
0.1UF
20%
6.3V
BI
J3200
a
n
i
11
MEM_B_DQ<10>
BI
VREFDQ
VSS
VSS
DQ4
DQ5
DQ0
CRITICAL
DQ1
VSS
VSS
DQS0*
DM0
DQS0
F-RT-BGA3
VSS
VSS
DQ2
DQ6
DQ3
DQ7
VSS
VSS
DQ8
DQ12
DQ9
DQ13
VSS
VSS
DQS1*
DM1
DQS1
RESET*
VSS
VSS
DQ14
DQ10
DQ11
DQ15
VSS
VSS
DQ16
DQ20
DQ17
DQ21
VSS
VSS
DQS2*
DM2
DQS2
VSS
DQ22
VSS
DQ18
DQ23
VSS
DQ19
VSS
DQ28
DQ29
DQ24
VSS
DQ25
DQS3*
VSS
DM3
DQS3
VSS
VSS
DQ26
DQ30
DQ27
DQ31
VSS
VSS
15 89
BI
MEM_B_DQS_N<7>
BI
89 15
15 89
BI
MEM_B_DQ<50>
7
9
m
il
NC
132
134
89 15
89 15
124
130
15 89
3
5
MEM_B_DQ<0>
82
84
e
r
P
175
177
179
89 15
J3200
(2 OF 2)
MEM_B_CKE<0>
IN
DDR3-SODIMM
89 15
KEY
y
r
C3231
2.2UF
(1 OF 2)
DDR3-SODIMM
10UF
- =I2C_SODIMMB_SDA
C3210
CERM
402
190
192
194
196
198
200
=I2C_SODIMMB_SDA
BI
202
=I2C_SODIMMB_SCL
IN
MEM_EVENT_L
OUT
21 27 41
204
44
"Expansion" (bottom) slot

44
=PP0V75_S0_MEM_VTT_B
DDR3 SO-DIMM Connector B
206
208
SYNC_MASTER=BEN_K20
210
212

516s0706
SPD ADDR=0xA2(WR)/0xA3(RD)

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
32
123
y
r
a
n
i
DDR3 RESET Support
MCP79 cannot control this signal directly since it must be high in sleep and MCP MEM rails are not powered in sleep.
=PP1V5_S3_MEMRESET
3.3V input must be stable before
before 1.5V starts to rise to
avoid glitch on MEM_RESET_L.
=PP3V3_S5_MEMRESET
1K
MEMRESET_HW
R3310
R3305
5%
1/16W
MF-LF
402
MEM_RESET_L
20K
MEMRESET_HW
R3300 1
MEM_RESET
10K
5%
1/16W
MF-LF
402
MEMRESET_HW
3
R3301 1
Q3305
MMDT3904-X-G
C3300
0.1UF
2
2
R3309
0
MMDT3904-X-G
1
27 28
5%
1/16W
MF-LF
402
m
il
MEMRESET_HW
1
20K
IN
Q3305
SOT-363-LF
MEMRESET_HW
16
MEMRESET_HW
6
2
OUT
MEMRESET_MCP
SOT-363-LF
MEM_RESET_RC_L
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
20%
10V
CERM
402
MCP_MEM_RESET_L
e
r
DDR3 Support
SYNC_MASTER=M98_MLB

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
33
123
7
17
OUT
PCIE_MINI_PRSNT_L
3
Q3401
SSM6N15FEAPE
SOT563
AP_PWR_EN
21 33
IN
5V S3 WLAN FET
Q3401
CHANNEL
P-TYPE
RDS(ON)
y
r
26 mOhm @4.5V
SSM6N15FEAPE
SOT563
LOADING
0.8 A (EDP)
a
n
i
L3404
20347-325E-12
10%
10%
0.1uF
IN
17 90
IN
17 90
PP5V_WLAN
PCIE_MINI_D2R_P
PCIE_MINI_D2R_N
1
2
OUT
7 17 90
OUT
7 17 90
90 7
90 7
PCIE_MINI_R2D_P
PCIE_MINI_R2D_N
96 7
96 7
7
11
SYM_VER-1
IN
17 90
PCIE_CLK100M_MINI_N
IN
17 90
OUT
7 17 31
12
13
m
il
14
15
16
NC
17
18
19
PP5V_S3_BTCAMERA_F
I2C_ALS_SDA
I2C_ALS_SCL
96 7
22
96 7
BI
IN
44
VOLTAGE=5V
96 7
25
96 7
ALS
CAMERA
44
L3402
90-OHM
CONN_USB2_BT_P
CONN_USB2_BT_N
DLP0NS
SYM_VER-1
27
1
28
30
32
USB_CAMERA_N
OUT
20 91
SYM_VER-1
P
=PP3V3_S3_WLAN
TC7SZ08AFEAPE 5
SOT665
MINI_RESET_CONN_L
U3401
USB_BT_P
BI
20 91
USB_BT_N
BI
20 91
PLACEMENT_NOTE=Place close to J3401.
PP5V_WLAN_F
U3402
74LVC1G17DRL
SOT-553
4
20%
10V
X5R
805
C3451
10%
16V
X5R
402
C3450
0.1UF
2
R3451
10K
0.033UF
R3450
P5VWLAN_SS
100K
5%
1/16W
MF-LF
402
PM_WLAN_EN_L
IN
33
5%
1/16W
MF-LF
402
10%
16V
X5R
402
L3406
PP3V3_S3_BT_F
VOLTAGE=3.3V
=PP5V_S3_BTCAMERA
VOLTAGE=5V
=PP3V3_S3_BT
C3462
VOLTAGE=3.3V
FERR-120-OHM-1.5A
0402-LF
0.1uF
20%
10V
CERM 2
402
30
R3453
5%
1/16W
MF-LF
402
R3455
WLAN_SMIT_RC
NC
NC
10UF
VOLTAGE=5V
33K
WLAN_SMIT_BUF
MINI_RESET_L
20%
10V
CERM
402
20 91
DLP0NS
C3420
=PP5V_S3_WLAN
1
BLUETOOTH
L3403
90-OHM
0402-LF
0.1uF
OUT
29
C3452
USB_CAMERA_P
e
r
26
FERR-120-OHM-1.5A
USB_CAMERA_CONN_P
USB_CAMERA_CONN_N
23
24
L3405
275 mA peak
206 mA nominal max
20
21
MIN_LINE_WIDTH=1 mm
VOLTAGE=5V
SOT-6
PLACEMENT_NOTE=Place close to Q3450.
MINI_CLKREQ_Q_L
PCIE_WAKE_L
PP5V_WLAN_R
Q3450
FDC606P_G
PLACEMENT_NOTE=Place close to Q3450.
PCIE_CLK100M_MINI_P
9
10
20%
10V
CERM
402
5%
1/10W
MF-LF
603
DLP11S
4
L3401
90-OHM-100MA
PP5V_WLAN_F
0.1uF
20%
10V
CERM
402
AIRPORT
3
4
C3421
0.1uF
31
30
MIN_LINE_WIDTH=1 mm
VOLTAGE=5V
C3422
C3430
F-RT-SM
R3404
MIN_LINE_WIDTH=1 mm
VOLTAGE=5V
16V X5R 402
5 6
1000 mA peak
750 mA nominal max
PCIE_MINI_R2D_C_P
PCIE_MINI_R2D_C_N
0.1uF
16V X5R 402
0402-LF
C3431
J3401
FERR-120-OHM-1.5A
CRITICAL
518S0610
FDC606P
OUT
MOSFET
17
MINI_CLKREQ_L
C3453
IN
25
1
5%
1/16W
MF-LF
402
WLAN_SMIT_RC_FET
Q3402
3
SSM3K15FV
Right Clutch Connector
SOD-VESM-HF
62K
1UF
10%
6.3V
CERM
402
R3454
2
2
SYNC_MASTER=M98_MLB
5%
1/16W
MF-LF
402
G 1

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
34
123
EXPRESSCARD/34 FLEX CONNECTOR
y
r
L3502
90-OHM
DLP0NS
CRITICAL
SYM_VER-1
91 20
BI
USB_EXCARD_N
91 20
BI
USB_EXCARD_P
USB2_EXCARD_CONN_N
7 31 96
USB2_EXCARD_CONN_P
7 31 96
J3500
502250-8627
F-RT-SM
29
INPUT DECOUPLING
27
PLACEMENT_NOTE=Place close to J3500
26
25
31 8
L3503
90-OHM-100MA
=PP3V3_S3_EXCARD
1
C3530
10uF
20%
10V
CERM
402
20%
6.3V
X5R
603
a
n
i
90 17 7
DLP11S
C3531
0.1uF
SYM_VER-1
90 17
IN
90 17
IN
PCIE_CLK100M_EXCARD_CONN_N
7 31 96
PCIE_CLK100M_EXCARD_CONN_P
7 31 96
96 31 7
31 7
31 7
31 7
31 7
31 8
=PP1V5_S0_EXCARD
44
C3571
1
C3534
C3535
0.1uF
2
20%
10V
CERM
402
10uF
20%
6.3V
X5R
603
90 17
IN
90 17
IN
PCIE_EXCARD_R2D_C_N
PCIE_EXCARD_R2D_C_P
1
10%
0.1uF
10%
PCIE_EXCARD_R2D_N
PCIE_EXCARD_R2D_P
0.1uF
16V X5R 402
7 31 90
7 31 90
96 31 7
16V X5R 402
R3504
31 8
=PP3V3_S3_EXCARD
SHORT
NONE
NONE
NONE
402
R3503
31 8
=PP3V3_S0_EXCARD
m
il
SHORT
NONE
NONE
NONE
402
R3502
31 8
=PP1V5_S0_EXCARD
SHORT
OUTPUT DECOUPLING
NONE
NONE
NONE
402
VOLTAGE=3.3V
MIN_LINE_WIDTH=.3mm
MIN_NECK_WIDTH=0.2mm
U3500
TPS2231
17
AUXIN
QFN
VIN3P3
VIN1P5
2
12
AUXOUT
15
e
r
VOUT3P3
VOUT1P5
VOLTAGE=3.3V
11
MIN_LINE_WIDTH=.6mm
41
IN
25
IN
42 20
IN
SMC_EXCARD_PWR_EN
TP_EXCARD_STBY_L
EXCARD_RESET_L
EXCARD_OC_L
R3500
MF-LF
1
402
EXCARD_SHDN_L_R
5%
1/16W
20
1
6
NC
NC
NC
NC
NC
SHDN*
PERST*
STBY*
SYSRST*
CPPE*
CPUSB*
10
RCLKEN
18 EXCARD_RCLKEN
OC*
19
4
NC0
5
13
NC1
NC2
14
NC3
16
NC4
=PP3V3_S3_EXCARD
31 7
EXCARD_CPUSB_L
74HC1G00GWDG
SC70-5
U3551
31 7
EXCARD_CPPE_L
THRML_PAD
SMC_EXCARD_CP
31
MIN_LINE_WIDTH=.6mm
31 8
VOLTAGE=1.5V
GND
C3500
OUT
21
31 8
7 31
C3503
0.1uF
CRITICAL
PP3V3_S3_EXCARD_R
PP3V3_S0_EXCARD_R
PP1V5_S0_EXCARD_R
10uF
20%
10V
CERM
402
C3501
20
19
18
17
16
15
14
13
12
11
9
NC
MF-LF
USB2_EXCARD_CONN_P
7 31 96
28
518S0647
1
402
PCIE_EXCARD_PRSNT_L
5%
1/16W
17
7 31
20%
6.3V
X5R
603
PLT_RESET_SWITCH_L
EXCARD_CPPE_L
EXCARD_CPUSB_L
7 31
7 31
7 31
ExpressCard Connector
1
5
100K
1%
1/16W
MF-LF
402
41 42
31
EXCARD_RCLKEN
EXCARD_CLKREQ_CONN
74HC1G00GWDG
SYNC_MASTER=BEN_K20
SC70-5
U3560
EXCARD_CLKREQ_L
OUT
17
B1
C2
BGA

U3561
SN74LVC1G04YZPR
C3560
0.1uF
20%
10V
CERM
402

2
SIZE
DRAWING NUMBER
D
APPLE INC.
REV.
051-7656
SCALE
SHT
NONE
44
10uF
10%
16V
X5R
402
A2
BI
C3505
C1
7 17 30
7 31
=PP3V3_S0_EXCARD
R3561
31 7
OUT
=SMBUS_EXCARD_SCL
7 31
20%
6.3V
X5R
603
C3502
0.1uF
20%
10V
CERM
402
7 31
NC
C3550
7 17 90
7 31
10
R3501
EXCARD_CPPE_L
OUT
7 31 96
10uF
10%
16V
X5R
402
0.1uF
31 7
7 31 90
PCIE_EXCARD_D2R_N
EXCARD_CPPE_L
PLT_RESET_SWITCH_L
PCIE_WAKE_L
7 31
1
EXCARD_CPUSB_L
USB2_EXCARD_CONN_N
21
C3504
0.1uF
=SMBUS_EXCARD_SDA
PCIE_EXCARD_R2D_P
23
22
20%
6.3V
X5R
603
BI
31 7
C3570
24
PCIE_EXCARD_R2D_N
OUT PCIE_EXCARD_D2R_P
90 31 7
31
OF
35
123
=PP1V05_ENET_PHY
C3710
C3711
0.1UF
8
10%
16V
X5R
402
=PP3V3_ENET_PHY
0.1UF
10%
16V
X5R
402
CRITICAL
L3705
FERR-120-OHM-1.5A
C3700
C3701
L3715
FERR-120-OHM-1.5A
C3702
0.1UF
0.1UF
0.1UF
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
PP1V05_ENET_PHYAVDD
C3714
0402-LF
C3715
0.1UF
0.1UF
10%
16V
X5R
402
10%
16V
X5R
402
C3705
0.1UF
2
10%
16V
X5R
402
C3706
0.1UF
VOLTAGE=1.05V
0.1UF
10%
16V
X5R
402
a
n
i
PP3V3_ENET_PHYAVDD
VOLTAGE=3.3V
C3716
10%
16V
X5R
402
y
r
CRITICAL
2
(221mA typ - 1000base-T)

( 7mA typ - Energy Detect)
WF: Marvell numbers, update for Realtek
0402-LF
(43mA typ - 1000base-T)

(19mA typ - Energy Detect)
WF: Marvell numbers, update for Realtek
=PP3V3_ENET_PHY_VDDREG
If internal switcher is used, must place 1x 22uF &

1x 0.1uF caps within 5mm of U3700 pins 44 & 45.
NOTE: VDDREG rise time must be >1ms to avoid damage to switcher.
5%
1/16W
MF-LF
402 2
=RTL8211_ENSWREG
39
IN
ENSWREG
22
ENET_CLK125M_TXCLK_R
IN
ENET_TX_CTRL
92 18
IN
92 18
BI
ENET_MDC
ENET_MDIO
IN
92 18
IN
92 18
92 18
92 18
IN
IN
ENET_RESET_L
e
r
RTL8211_RSET
NO STUFF
C3725
0.1UF
20%
10V
CERM
402
RTL8211_CLK125
R3730 1
2.49K
1%
1/16W
MF-LF
402
R37311
92 33
IN
22
2
5%
1/16W
MF-LF
402
23
24
25
26
27
30
31
29
RTL8211_PHYRST_L
5%
1/16W
402
MF-LF
10
36
40
RXC
19
RTL8211_CLK25M_CKXTAL1
TP_RTL8211_CKXTAL2
14
m
il
R3724
92 18
REGOUT
46
32
TXD[0]
TXD[1]
TXD[2]
TXD[3]
RGMII/MII
TXCTL
MDC
MDIO
PHYRSTB*
RSET
RXCTL
43
17
18
13
MDI+[1]
MDI-[1]
MDI+[2]
MDI-[2]
MDI+[3]
MDI-[3]
11
LED0/PHYAD0
LED1/PHYAD1
LED2/RXDLY
34
RESET MEDIA DEPENDENT
REFERENCE
16
MDI+[0]
MDI-[0]
MANAGEMENT
4.7K
4.7K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
=RTL8211_REGOUT
If internal switcher is used, must place inductor within 5mm

of U3700, and 1x 22uF & 1x 0.1uF caps within 5mm of inductor.
92
92
92
92
92
R3790
ENET_CLK125M_RXCLK_R
R3791
R3792
R3793
R3794
ENET_RXD_R<0>
ENET_RXD_R<1>
ENET_RXD_R<2>
ENET_RXD_R<3>
R3795
ENET_RXCTL_R
12
ENET_MDI_P<0>
ENET_MDI_N<0>
BI
34 92
BI
34 92
ENET_MDI_P<1>
ENET_MDI_N<1>
BI
34 92
BI
34 92
ENET_MDI_P<2>
ENET_MDI_N<2>
BI
34 92
BI
34 92
ENET_MDI_P<3>
ENET_MDI_N<3>
BI
34 92
BI
34 92
22
22
22
22
22
22
ENET_CLK125M_RXCLK
2
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
ENET_RXD<0>
ENET_RXD<1>
ENET_RXD<2>
ENET_RXD<3>
ENET_RX_CTRL
OUT
18 92
OUT
18 92
OUT
18 92
OUT
18 92
OUT
18 92
OUT
18 92
CLK125
CLOCK
42
RXD[0]
RXD[1]/TXDLY
RXD[2]/AN0
RXD[3]/AN1
CKXTAL1
CKXTAL2
LED
GND
47
IN
ENET_TXD<0>
ENET_TXD<1>
ENET_TXD<2>
ENET_TXD<3>
92 18
33
PLACE R3796 CLOSE TO U1400, PIN D24
TXC
5%
1/16W
402
MF-LF
20
28
RTL8211CLGR
R3752 1
R3751
If internal switcher is not used, VDDREG and REGOUT can float.
48
TQFP
22
ENET_CLK125M_TXCLK
IN
5%
1/16W
MF-LF
402
U3700
R3796
92 18
45
44
21
15
37
OMIT
CRITICAL
4.7K
AVDD12
4.7K
FB12
5%
1/16W
MF-LF
402 2
DVDD12
Alias to =PP3V3_ENET_PHY for internal switcher.

Alias to GND for external 1.05V supply.
R3725
VDDREG
10K
NO STUFF
1
AVDD33
R3720 1
DVDD33
41
R3750 1
RTL8211_PHYAD0
RTL8211_PHYAD1
RTL8211_RXDLY
35
38
NO STUFF
C3790
10PF
5%
50V
CERM
402
C3790 reserved for EMI

per RealTek request.
C3790 should be placed close to U3700.19
R3755 1
R3756 1
4.7K
4.7K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
R3757
4.7K
5%
1/16W
MF-LF
402
Ethernet PHY (RTL8211CL)

SYNC_MASTER=SUMA_K20

Configuration Settings:
SIZE
PHYAD
AN[1:0]
RXDLY
TXDLY
=
=
=
=
01
11
0
0
DRAWING NUMBER
(PHY Address 00001)

(Full auto-negotiation)
(RXCLK transitions with data)
(No TXCLK Delay)
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
37
123
3.3V ENET FET

@ 2.5V Vgs:
Rds(on) = 90mOhm max
I(max) = 1.7A (85C)
CRITICAL
Q3810
NTR4101P
SOT-23-HF
=PP3V3_ENET_FET
R3800 1
5%
1/16W
MF-LF
402
R3810
10%
16V
X5R
402
y
r
C3810
P3V3ENET_SS
5%
1/16W
MF-LF
402
10%
16V
CERM
402
SSM6N15FEAPE
SOT563
IN
a
n
i
=P3V3ENET_EN
MOBILE:
Recommend aliasing PM_SLP_RMGT_L and
=P3V3ENET_EN. Nets separated on
ARB for alternate power options.
WLAN Enable Generation

"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0"))
NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal.
PM_WLAN_EN_L
30
OUT
1.05V ENET FET
Pull-up is with power FET.
Q3805
SSM6N15FEAPE
SOT563
30 21
IN
1.8V Vgs
C3840
SSM6N15FEAPE
m
il
8
Q3801
SSM6N15FEAPE
SOT563
SOT563
R3842 1
42 41 36 21
84 82 67 41 36 21 7
IN
IN
69.8K
1%
1/16W
MF-LF
402
SMC_ADAPTER_EN
PM_SLP_S3_L
Q3841
e
r
20%
10V
CERM
402
R3840
100K
CRITICAL
Q3840
P1V05ENET_SS
SI2312BDS
SOT23
5%
1/16W
MF-LF
402
P1V05ENET_EN_L
0.1UF
AC_OR_S0_L
Q3805
=PP1V05_ENET_P1V05ENETFET
AP_PWR_EN
0.01UF
100K
P3V3ENET_EN_L
Q3801
C3811
0.033UF
10K
Q3841
=PP1V05_ENET_FET
SSM6N15FEAPE
SOT563
R3841
2
2
1%
1/16W
MF-LF
402
C3841
0.01UF
10K
10%
16V
CERM
402
P1V05ENET_EN_L_RC
SSM6N15FEAPE
SOT563
IN
=P1V05ENET_EN
Non-ARB:
Recommend aliasing PM_SLP_RMGT_L and

=P1V05ENET_EN. Nets separated on
ARB for alternate power options.
RTL8211 25MHz Clock
Ethernet & AirPort Support
NOTE: MCP79 can provide 25MHz clock, but clock runs whenever RMGT rails are powered.
Designs must ensure PHY is powered whenever RMGT rails are, or use separate crystal.
R3895
92 18
IN
MCP_CLK25M_BUF0_R
22
1
OUT

32 92
5%
1/16W
MF-LF
402

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
38
123
Page Notes
(NONE)
(NONE)
(NONE)
y
r
Place one of 0.1uf cap close to each centertap pin of transformer
ENETCONN_CTAP
1
C3900
0.1UF
C3902
0.1UF
10%
2 16V
X5R
402
10%
2 16V
X5R
402
C3904
0.1UF
10%
2 16V
X5R
402
C3906
0.1UF
10%
2 16V
X5R
402
a
n
i
CRITICAL
92 32
92 32
BI
BI
T3900
SM
ENET_MDI_P<0>
12
ENETCONN_P<0>
ENET_MDI_N<0>
96 11
ENETCONN_N<0>
10
ENET_CTAP0
ENET_CTAP1
96
ENETCONN_N<1>
96
ENETCONN_P<1>
96
CRITICAL
J3900
RJ45-M97-2
TX
F-RT-TH
9
OMIT
10
TLA-6T213HF
92 32
BI
ENET_MDI_N<1>
92 32
BI
ENET_MDI_P<1>
6
RX
CRITICAL
92 32
BI
ENET_MDI_N<2>
92 32
BI
ENET_MDI_P<2>
T3901
SM
m
il
96
12
ENETCONN_N<2>
96
11
ENETCONN_P<2>
10
ENET_CTAP2
TX
TLA-6T213HF
4
9
8
96
ENETCONN_N<3>
96
ENETCONN_P<3>
92 32
BI
ENET_MDI_N<3>
92 32
BI
ENET_MDI_P<3>
e
r
RX
Transformers should be
mirrored on opposite
sides of the board
B
1
1
C3910
10PF
C3920
10PF
5%
50V
402-1
2 CERM
C3911
10PF
C3921
10PF
5%
50V
2 CERM
402-1
5%
50V
2 CERM
402-1
5%
50V
402-1
2 CERM
5%
50V
2 CERM
402-1
C3940
10PF
10PF
5%
50V
402-1
2 CERM
C3930
P
1
C3931
10PF
5%
50V
2 CERM
402-1
PLACEMENT_NOTE=Place on MDI lines so there are no stubs all 8 caps.
C3941
10PF
ENET_CTAP3
R39001 R39011
75
5%
1/16W
MF-LF
402 2
75
5%
1/16W
MF-LF
402 2
R3902
75
5%
1/16W
MF-LF
2 402
1
2
3
4
5
6
7
8
11
12
R3903
75
5%
1/16W
MF-LF
2 402
ENET_BOB_SMITH_CAP
CRITICAL
C3908
1000PF
1
10%
2KV
CERM
1206
5%
50V
402-1
2 CERM
PART NUMBER
514-0636
QTY
1
DESCRIPTION
CONN,RJ45,HB,10/100TX
REFERENCE DES
J3900
CRITICAL
BOM OPTION
CRITICAL
Ethernet Connector

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
39
123
=PP3V3_FW_FWPHY
7 mA I/O
C4120
C4121
C4122
C4123
C4124
1UF
1UF
1UF
1UF
1UF
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
8 35 37
138 mA
L4130
120-OHM-0.3A-EMI
114 mA FireWire PHY
C4130
PP3V3_FW_FWPHY_VDDA
C4131
1UF
1UF
1UF
10%
6.3V
CERM
402
10%
6.3V
CERM
402
C4132
10%
6.3V
CERM
402
VOLTAGE=3.3V
y
r
L4110
L4135
120-OHM-0.3A-EMI
120-OHM-0.3A-EMI
25 mA PCIe SerDes
PP1V0_FW_FWPHY_AVDD
VOLTAGE=1.0V
C4110
1UF
10%
6.3V
CERM
402
C4111
C4135
1UF
1UF
10%
6.3V
CERM
402
10%
6.3V
CERM
402
C4102
C4103
C4104
C4105
C4106
1UF
1UF
1UF
1UF
1UF
1UF
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
C4141
20%
10V
CERM
402
24.576MHZ
SM-3.2X2.5MM
TP_FW643_NAND_TREE
FW643_REXT
FW_CLK24P576M_XO_R
FW_CLK24P576M_XI
R4161 1
2.94K
1%
1/16W
MF-LF
402
P
1
R4170
191
5%
50V
CERM
402
1%
1/16W
MF-LF
402
R4162 1
470K
5%
1/16W
MF-LF
402
e
r
B10
L8
F13
G13
TP_FW643_SE
TP_FW643_SM
TP_FW643_MODE_A
TP_FW643_CE
TP_FW643_FW620_L
TP_FW643_JASI_EN
TP_FW643_AVREG
TP_FW643_VBUF
FW643_PU_RST_L
M13
N13
J2
L13
D12
D1
A10
H13
K13
TP_FW643_OCR10_CTL
C4162
0.33UF
K1
10%
6.3V
CERM-X5R
402
J12
NC
J13
R0
TPCPS
NAND_TREE
REXT
XO
XI NT-9
L6
L10
L5
D8
D6
D5
A12
M2
L11
L3
J1
10%
6.3V
CERM
402
N8
90
N7
90
N5
90
N6
90
NT-4 (IPU) TCK

NT-3 (IPU) TDI
(IPU) TDO
NT-1 (IPU) TMS
M3
NT-2 (IPU) TRST*
N1
FW643_TRST_L
WAKE*
REGCLT
VAUX_DETECT
VAUX_DISABLE
(OD) CLKREQN
N2
M1
C2
D13
E1
D2
L2
IN
17 90
IN
17 90
PCIE_FW_R2D_C_N
IN
17 90
PCIE_FW_R2D_C_P
IN
17 90
PCIE_FW_D2R_N
OUT
17 90
PCIE_FW_D2R_P
OUT
17 90
X5R 402
C41711
10%
2
16V
0.1UF
X5R 402
C41751
10%
2
16V
0.1UF
X5R 402
C41761
10%
2
16V
0.1UF
PCIE_CLK100M_FW_N
PCIE_CLK100M_FW_P
TP_FW643_TCK
TP_FW643_TDI
TP_FW643_TDO
TP_FW643_TMS
10%
2
16V
0.1UF
PCIE_FW_R2D_N
PCIE_FW_R2D_P
PCIE_FW_D2R_C_N
PCIE_FW_D2R_C_P
M4
N10
X5R 402
PLACEMENT_NOTE=Place C4175 close to U4000
=PP3V3_FW_FWPHY
8 35 37
FW643_LDO
R4165 1
FW_PME_L
FW643_REGCTL
FW643_VAUX_DETECT
TP_FW643_VAUX_ENABLE
FW_CLKREQ_L

C41701
OUT
19
OUT
17
R4166
10K
10K
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
2 402
R4164
10K
5%
1/16W
MF-LF
2 402
NT-16 (IPD) SCIFCLK

NT-14 (IPD) SCIFDAIN
NT-17 SCIFDOUT
NT-15 (IPD)
SCIFMC
NOTE: NT-xx notes show

NAND tree order.
SE (IPD)
SM (IPD)
MODE_A (IPD) NT-18
CE (IPD)
FW620* (IPU)
JASI_EN (IPD) NT-11
AVREG
VBUF
FW_RESET* (IPU) NT-8
1UF
NT-10 (IPD)
SCIF
NT-OUT
SERIAL EEPROM
CONTROLLER
NT-7 SCL
NT-6 SDA
G2
G1
H1
F2
TP_FW643_SCIFCLK
TP_FW643_SCIFDAIN
TP_FW643_SCIFDOUT
TP_FW643_SCIFMC
M11
FW643_SCL
TP_FW643_SDA
N4
FW_RESET_L
N12
MISCELLANEOUS
CHIP RESET
NT-5 PERST*
IN
1
25
R4163
10K
OCR_CTL_V10
OCR_CTL_V12 (Reserved)
VSS
VREG_VSS
K5
Y4150
B11
TPBIAS0
TPBIAS1
TPBIAS2
K4
NC
NC
A2
FW643_R0
FW643_TPCPS
2
1%
1/16W
MF-LF
402
C3
N9
POWER MANAGEMENT
NT-12 (IPD)
NT-13
J10
412
1
22PF
1
BI
B7
C4140
REFCLKN
REFCLKP
FIXME!!! - TYPO IN SYMBOL REGCTL
J9
FW_CLK24P576M_XO
CRITICAL
C4151
37
FW_P0_TPBIAS
FW_P1_TPBIAS
FW_P2_TPBIAS
PCIE_RXD0N
PCIE_RXD0P
PCIE_TXD0N
PCIE_TXD0P
m
il
J5
2
5%
50V
CERM
402
BI
R4150
22PF
1
BI
37
A4
J4
C4150
37
B4
H10
1%
1/16W
MF-LF
402
BI
H8
200K
BI
37
H7
R4160 1
37
H6
=PPVP_FW_PHY_CPS
A6
H4
37
BI
B6
1394 PHY
G10
93 37
BI
A9
G8
93 37
B9
G7
BI
G6
BI
G4
BI
93 37
A3
F10
37
93 37
B3
VREG_PWR
TEST CONTROLLER
F8
BI
A5
F7
37
B5
TPA0N
TPA0P
TPA1N
TPA1P
TPA2N
TPA2P
TPB0N
TPB0P
TPB1N
TPB1P
TPB2N
TPB2P
F6
BI
A8
F4
BI
93 37
B8
VP25
PCI EXPRESS PHY
E9
93 37
FW_P0_TPA_N
FW_P0_TPA_P
FW_P1_TPA_N
FW_P1_TPA_P
FW_P2_TPA_N
FW_P2_TPA_P
FW_P0_TPB_N
FW_P0_TPB_P
FW_P1_TPB_N
FW_P1_TPB_P
FW_P2_TPB_N
FW_P2_TPB_P
BGA
E5
BI
E13
E4
BI
93 37
E12
VP
FW643
DS0 (IPD) NT-19

DS1 (IPD) NT-20
DS2 (IPD) NT-21
D10
93 37
F12
VDDH
VDD33
OMIT
CRITICAL
U4100
D7
IN
A11
ATBUSB
ATBUSH
ATBUSN
D4
IN
37
A13
B2
37
=FW_PHY_DS0
=FW_PHY_DS1
=FW_PHY_DS2
B13
D9
NC
NC
NC
G12
F1
C12
C1
N11
N3
M12
L1
K2
H12
H2
E10
E2
C13
B12
B1
A1
VDD10
IN
0.1UF
37
5%
1/16W
MF-LF
402
L12
C4101
10%
6.3V
CERM
402
1UF
10%
6.3V
CERM
402
0402-LF
K12
1UF
K6
C4100
VOLTAGE=3.3V
0 mA VReg PWR
K10
C4136
PP3V3_FW_FWPHY_VP25
a
n
i
110 mA Digital Core
L9
0402-LF
17 mA PCIe SerDes
L7
K9
K8
=PP1V0_FW_FWPHY
135 mA
K7
2
0402-LF
FireWire LLC/PHY (FW643)

SYNC_MASTER=M98_MLB

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
41
123
Page Notes
- =PPBUS_S5_FWPWRSW (system supply for bus power)
- =PP3V3_FW_LATEVG_ACTIVE
- =PPVP_FW_SUMNODE (power passthru summation node)
FireWire Port Power Switch

CRITICAL

(NONE)
Q4260
NDS9407
SOI-HF

- FW_PORT_FAULT_PU
36 8
36 8
=PPVIN_S5_FWPWRSW
=PPVOUT_FW_FWPWRSW
=PPVIN_S5_FWPWRSW
6
1
NO STUFF
C4263
R4263
PPVIN_S5_FWPWRSW_FET
P-CHN
5%
1/16W
MF-LF
2 402
10
C4260
y
r
0.01uF
5%
1/16W
MF-LF
2 402
R4262
10K
R4260
470K
FW_LVG_NEW
Q4262
2.2UF
20%
10V
X5R-CERM
402
FW_LVG_NEW
FW_LVG_NEW
20%
16V
CERM
402
FWPWR_EN_L_DIV
NTUD3127CXXG
5%
1/16W
MF-LF
402
SOT-963
R4261
330K
PPVIN_S5_FWPWRSW_R
5%
1/16W
MF-LF
402
FWPWR_EN_L
FW_LVG_NEW
Enables port power when machine
is running or on AC.
R4265
10K
FW_LVG_NEW
42 41 33 21
IN
SMC_ADAPTER_EN
84 82 67 41 33 21 7
IN
PM_SLP_S3_L
SOT-963
a
n
i
FW_PORTPWR_EN_FET
G
S
SOT563
FW_PORTPWR_EN_R
6
Q4261
SSM6N15FEAPE
SOT563
NTUD3127CXXG
N-CHN
SSM6N15FEAPE
5%
1/16W
MF-LF
2 402
Q4262
Q4261
FW_LVG_NEW
Q4263
R4264
SOT563
36
FW_PORTPWR_EN
m
il
FW_PORTPWR_EN_L
Late-VG Event Detection

8
37
e
r
=PP3V3_FW_LATEVG_ACTIVE
PP2V4_FW_LATEVG
R4211 1
R4212
10K
10K
5%
1/16W
MF-LF
402 2
1%
1/16W
MF-LF
2 402
0.1UF
P2V4_FWLATEVG_RC
V+
FWLATEGV_3V_REF
1
1
5%
50V
CERM
402
R4213
80.6K
100pF
2
2
1%
1/16W
MF-LF
402
SM-HF
1
V-
P
R4210
200K
1%
1/16W
MF-LF
402
20%
10V
CERM
402
U4210
LMC7211
C4211
C4210
D4219
LATEVG_EVENT_L
SOD-123
2
1
MBR0540XXH
SSM6N15FEAPE
5%
1/16W
MF-LF
402
CRITICAL
CRITICAL
D4260
PWRDI5
F4260
1.5A-24V
=PPBOOST_FW_FWPWRSW_F
1812L15024HF
=PPBOOST_S5_FW_FET
PP10V_FW_D
VOLTAGE=10V
PDS540XF
FW_LVG_NEW
R4219
2.0M
5%
1/16W
MF-LF
2 402
FW_PORTPWR_EN
C4219
0.33UF
R4266
10K
5%
1/16W
MF-LF
2 402
36
Q4263
SSM6N15FEAPE
SOT563
10%
10V
CERM-X5R
603
5
FWLATEVG_3V_REF Hysteresis:
2.95V when port power is on
2.81V on late Vg event and port power is off
FireWire Port Power

SYNC_MASTER=YWU_K20

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
42
123
8
Page Notes

37 35 8
=PP3V3_FW_FWPHY
- =PPVP_FW_PORT1
- =PP3V3_FW_LATEVG
R4382 1
- =GND_CHASSIS_FW_PORT1
- =GND_CHASSIS_FW_EMI_R
R4380 1
10K
10K
1%
1/16W
MF-LF
402 2
1%
1/16W
MF-LF
402 2
FWPHY_DS0
FireWire PHY Config Straps

(NONE)
NOTE: This page is expected to contain
the necessary aliases to map the
FireWire TPA/TPB pairs to their
appropriate connectors and/or to
properly terminate unused signals.
FWPHY_DS2
Configures PHY for:
FWPHY_DS1
- 1-port Portable Power Class (0)
35
35
93 35
35
35
93 35
93 35
Termination
35
35
C4360
0.33UF
NC_FW0_TPBIAS
NC_FW2_TPBIAS
NC_FW0_TPAN
NC_FW0_TPAP
NC_FW2_TPAN
NC_FW2_TPAP
PPVP_FW_CPS
MAKE_BASE=TRUE
NC_FW0_TPBN
NC_FW0_TPBP
NC_FW2_TPBN
NC_FW2_TPBP
=PPVP_FW_PHY_CPS
m
il
PP2V4_FW_LATEVG
5%
1/16W
MF-LF
402
10%
50V
X7R
402
DP4310
CPS_EN_L
BAV99DW-X-G
C4310
10%
50V
X7R
402
37
MAKE_BASE=TRUE
93 35
FW_P1_TPA_N
FW_PORT1_TPA_N
93 35
FW_P1_TPB_P
FW_PORT1_TPB_P
37
MAKE_BASE=TRUE
93 35
FW_P1_TPB_N
FW_PORT1_TPB_N
e
r
56.2
1%
1/16W
MF-LF
2 402
1%
1/16W
MF-LF
402 2
FW_PORT1_TPB_C
C4364
220pF
5%
25V
CERM
402
SOT-363
(SYM-VER1)
R4363 1
56.2
BSS8402DW
37
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY
R4362
=PP3V3_FW_FWPHY
37 35 8
MAKE_BASE=TRUE
R4364 1
4.99K
1%
1/16W
MF-LF
402 2
MAKE_BASE=TRUE
MAKE_BASE=TRUE
FERR-250-OHM
=PPVP_FW_PORT1
SM
Note: Trace PPVP_FW_PORT1 must handle up to 5A

PPVP_FW_PORT1_F
VOLTAGE=33V
0.01UF
DP4310
BAV99DW-X-G
SOT-363
C4314
10%
50V
X7R
402
PORT 1
BILINGUAL
CRITICAL
J4310
1394B-M97
37
37
F-RT-TH
FW_PORT1_TPA_N
37
FW_PORT1_TPA_P
NC
=PP3V3_FW_LATEVG
R4390
332
1%
1/16W
MF-LF
402
CRITICAL
D4390
VG
TPA<R>
TPA+
TPA(R)
INPUT
TPA+
11
10%
50V
X7R
603-1
BAV99DW-X-G
SOT-363
1
CHASSIS
GND
12
0.1uF
DP4311
13
2
5
1
C4313
0.01uF
10%
50V
X7R
402
R4319
1M
4
2
5%
1/16W
MF-LF
402
AREF needs to be isolated from all

local grounds per 1394b spec
514S0605
When a bilingual device is connected to a

beta-only device, there is no DC path
between them (to avoid ground offset issue)
PLACEMENT_NOTE=Place C4319 close to connector pin 5.
BREF should be hard-connected to logic

ground for speed signaling and connection
FireWire Ports
36 37
ESD and late-VG rail

for snap-back diodes
(Common to all ports)

SOT23
SIZE
DRAWING NUMBER
REV.
051-7656
SCALE
SHT
NONE
TPA-
10
C4319
APPLE INC.
NC
VG
MMBZ5227BLT1H
PP2V4_FWLATEVG needs to be biased

to at least 2.1V for FW signal integrity
and should be biased to 2.4V for margin
R4390 should be 390 Ohms max for a 3.3V rail
SC/NC
TPA-
SYNC_MASTER=M98_MLB
PP2V4_FW_LATEVG
FW_PORT1_AREF
OUTPUT
TPB+
VP
VOLTAGE=2.4V
VP
(GND_FW_PORT1_VG)
SOT-363
10%
50V
X7R
402
TPB+
DP4311
0.01uF
TPBTPB<R>
BAV99DW-X-G
C4312
TPB(R)
(FW_PORT1_BREF)
FW_PORT1_TPB_P
37
TPB-
FW_PORT1_TPB_N
Late-VG Protection Power

A
Q4300
37
MAKE_BASE=TRUE
SOT-363
0.01uF
FW_PORT1_TPA_P
MAKE_BASE=TRUE
0.01uF
330K
FW_P1_TPA_P
"Snapback" & "Late VG" Protection
R4312 1
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY
1%
1/16W
MF-LF
402
CRITICAL
35
C4311
1%
1/16W
MF-LF
402
MAKE_BASE=TRUE
L4310
37 36
CPS_EN_L_DIV
56.2
MAKE_BASE=TRUE
MAKE_BASE=TRUE
5%
1/16W
MF-LF
402 2
R4361
MAKE_BASE=TRUE
470K
56.2
MAKE_BASE=TRUE
a
n
i
FW_P0_TPB_N
FW_P0_TPB_P
FW_P2_TPB_N
FW_P2_TPB_P
VOLTAGE=10V
R4311 1
R4360
MAKE_BASE=TRUE
MAKE_BASE=TRUE
Cable Power
=PPVP_FW_PHY_CPS_FET
10%
6.3V
CERM-X5R
402
BSS8402DW
SOT-363
(SYM-VER2)
TI PHYs require 1uF even though

FW spec calls out 0.33uF
FW_P0_TPBIAS
FW_P2_TPBIAS
FW_P0_TPA_N
FW_P0_TPA_P
FW_P2_TPA_N
FW_P2_TPA_P
Q4300
Place close to FireWire PHY
93 35
y
r
10K
1%
1/16W
MF-LF
402 2
1394b implementation based on Apple

FireWire Design Guide (FWDG 0.6, 5/14/03)
35
R4381 1
- Port "1" Bilingual (1394B)
93 35
35
=FW_PHY_DS1
MAKE_BASE=TRUE
NOTE: FireWire TPA/TPB pairs are NOT

constrained on this page. It is
assumed that FireWire PHY page will
provide the appropriate constraints
to apply to entire TPA/TPB XNets.
FW_P1_TPBIAS
35
=FW_PHY_DS2
MAKE_BASE=TRUE

(NONE)
35
=FW_PHY_DS0
MAKE_BASE=TRUE
31
OF
43
123
ODD Power Control

CRITICAL
Q4590
6
FDC606P_G
SOT-6
PP5V_SW_ODD
MIN_LINE_WIDTH=0.6mm
VOLTAGE=5V
=PP5V_S0_ODD
4
38 8
100K
10%
10V
CERM
402
C4596
0.01UF
100K
R4597
ODD_PWR_EN_LS5V_L
Q4596
ODD_PWR_SS
2
5%
1/16W
MF-LF
402
100K
5%
1/16W
MF-LF
402
y
r
0.068UF
2
R4595
5%
1/16W
MF-LF
402
=PP3V3_S0_ODD
C4595
R4596 1
NOTE: 3.3V must be S0 if 5V is S3 or S5 to

ensure the drive is unpowered in S3/S5.
10%
16V
CERM
402
SSM6N15FEAPE
2
SOT563
ODD_PWR_EN
2
Q4596
a
n
i
SSM6N15FEAPE
SOT563
5
21
ODD_PWR_EN_L
IN
SATA ODD Port

FL4520
PLACEMENT_NOTE=PLACE C4520 CLOSE TO MCP79
90-OHM-100MA
DLP11S
PLACEMENT_NOTE=PLACE C4521 NEXT TO C4520
SYM_VER-1
CRITICAL
96
SATA_ODD_R2D_UF_P
38 8
M-ST-SM-LF
=PP3V3_S0_ODD
R4590
33K
5%
1/16W
MF-LF
402 2
10%
OUT
90 7
90 7
10
90 7
12
11
90 7
14
13
16
15
SATA_ODD_D2R_C_N
SATA_ODD_D2R_C_P
C4501
0.1UF
C4526
CRITICAL
L4500
FERR-70-OHM-4A
7 PP5V_S0_HDD_FLT
0603
PLACEMENT_NOTE=PLACE L4500 CLOSE TO J4501
CRITICAL
NC
NC
NC
10
90 7 SATA_HDD_R2D_N
11
12
90 7 SATA_HDD_R2D_P
13
14
15
16
90 7 SATA_HDD_D2R_C_P
90 7 SATA_HDD_D2R_C_N
CERM
SATA_ODD_R2D_C_N
IN
20 90
402
96
10%
16V
16V
SYM_VER-1
SATA_ODD_D2R_UF_N
CERM
96
10%
FL4525
90-OHM-100MA
DLP11S
CRITICAL
SATA_ODD_D2R_N
OUT
20 90
SATA_ODD_D2R_P
OUT
20 90
402
SATA_ODD_D2R_UF_P
CERM
402
PLACEMENT_NOTE=Place FL4525 close to J4500
SYM_VER-1
10%
16V
CERM
10%
16V
CERM
CRITICAL
SATA_HDD_D2R_P
OUT
20 90
SATA_HDD_D2R_N
OUT
20 90
402
96 SATA_HDD_D2R_UF_N
402
PLACEMENT_NOTE=PLACE FL4502 CLOSE TO J4501
FL4501
516S0350
16V
20 90
FL4502
PLACEMENT_NOTE=Place C4515 next to C4516
CRITICAL
10%
IN
90-OHM-100MA
DLP11S
90-OHM-100MA
DLP11S
NC
C4520
SATA_ODD_R2D_C_P
402
SATA HDD Port
96 SATA_HDD_D2R_UF_P
0.01UF
PLACEMENT_NOTE=PLACE C4502 CLOSE TO J4501
=PP5V_S0_HDD
C4515
M-ST-SM
0.01UF
PLACEMENT_NOTE=Place C4516 close to J4501

1
0.01UF
CERM
20%
10V
CERM
402
0.01UF
QT500166-L020
1
C4516
J4501
C4525
C4502
0.1UF
20%
10V
CERM
402
P
2

PLACEMENT_NOTE=PLACE C4525 NEXT TO C4526
e
r
Indicates disc presence
SATA_ODD_R2D_UF_N
SATA_ODD_R2D_P
SATA_ODD_R2D_N
0.01UF
SMC_ODD_DETECT
96
16V
516S0617
41 7
m
il
J4500
55560-0168
C4521
0.01UF
CRITICAL
SATA Connectors
PLACEMENT_NOTE=Place C4511 next to C4510
SYM_VER-1
C4511
96 SATA_HDD_R2D_UF_N
10%
0.01UF
1
C4510
96 SATA_HDD_R2D_UF_P
0.01UF
SATA_HDD_R2D_C_N
16V
CERM
IN
SYNC_MASTER=M98_MLB
20 90
402

1
2
10%
SATA_HDD_R2D_C_P
16V
CERM
IN
20 90

402
PLACEMENT_NOTE=Place C4510 close to MCP79

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
45
123
a
n
i
CRITICAL
CRITICAL
L4605
Q4690
FERR-220-OHM-2.5A
TPS2064DGN
IN
OUT1
VOLTAGE=5V
MSOP
PM_SLP_S4_L
67 42 41 21
20
R4690
20
USB_EXTA_OC_L
OUT
USB_EXTB_OC_L
OUT
5.1K
5%
1/16W
MF-LF
2 402
USB_PWR_EN
OC2*
EN2
20%
6.3V
X5R
603
0.47UF
20%
6.3V
X5R
603
SIGNAL_MODEL=USB_MUX
43 42 41 7
IN
43 42 41 7
OUT
SMC_RX_L
SMC_TX_L
20%
10V
CERM
402
BI
91 20
BI
VCC
2
USB_EXTA_P
USB_EXTA_N
M+
M-
U4650
Y+
Y-
D+
D-
OE*
TQFN
CRITICAL
SEL
3
SMC_DEBUG_NO
R4651
0
1
2
5%
1/16W
MF-LF
402
10
5%
1/16W
MF-LF
402
USB_DEBUGPRT_EN_L
IN
C4696
96
USB2_EXTA_MUXED_N
J4600
USB
F-RT-TH-M97-3
5
L4600
90-OHM-100MA
DLP11S
m
il
C4617
10UF
100UF
2
CRITICAL
20%
2 6.3V
POLY-TANT
CASE-B2-SM
C4616
100UF
20%
6.3V
X5R
603
96
USB2_EXTA_MUXED_P
20%
6.3V
POLY-TANT
CASE-B2-SM
96 7
USB2_LT1_N
96 7
USB2_LT1_P
6 VBUS
OMIT
1
2
3
4
7
8
1 GND
D4600
RCLAMP0502N
SLP1210N6
CRITICAL
We can add protection to 5V if we want, but leaving NC for now
CRITICAL
L4615
FERR-220-OHM-2.5A
1
2
0603
C4615
Place L4600 and L4605 at connector pin
PP5V_S3_RTUSB_B_F
VOLTAGE=5V
0.01uF
2
20%
16V
CERM
402
CRITICAL
J4610
USB
F-RT-TH-M97-3
5
CRITICAL
L4610
90-OHM-100MA
DLP11S
BI
USB_EXTB_N
OMIT
SYM_VER-1
91 20
96 7
96 7
USB_LT2_N
USB_LT2_P
2
3
4
91 20
BI
USB_EXTB_P
2
6 VBUS
1 GND
41
D4610
RCLAMP0502N
SLP1210N6
External USB Connectors
CRITICAL
SYNC_MASTER=M98_MLB
Left USB Port B

R4652
0
SMC_DEBUG_NO
CRITICAL
CRITICAL
SEL=0 Choose SMC

SEL=1 Choose USB
GND
R4650
10K
PI3USB102ZLE
91 20
P
1
SMC_DEBUG_YES
0.1UF
20%
16V
CERM
402
e
r
SMC_DEBUG_YES
VOLTAGE=5V
SYM_VER-1
10UF
20%
10V
CERM
402
PP5V_S3_RTUSB_A_F
0.01uF
CRITICAL
C4695
0.1UF
USB/SMC Debug Mux
C4650
PP5V_S3_RTUSB_B_ILIM
=PP3V42_G3H_SMCUSBMUX
C4605
VOLTAGE=5V
C4691
OUT2
10UF
10%
10V
X5R
402
EN1
0603
GND TPAD
C4690
C4692
OC1*
PP5V_S3_RTUSB_A_ILIM
NC
IO
NC
IO
98 8
NC
IO
NC
IO
=PP5V_S3_RTUSB
y
r
Left USB Port A
Port Power Switch

5%
1/16W
MF-LF
402
PART NUMBER
QTY
514-0638
DESCRIPTION
CONN,RCPT,USB,HB,4P
REFERENCE DES
J4600, J4610
CRITICAL
BOM OPTION
SIZE
DRAWING NUMBER
CRITICAL
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
46
123
D
R4801
SHORT2
40 8 =PP5V_S3_IR
y
r
PP5V_S3_IR_USB
NONE
NONE
NONE
402
1
C4801
0.1UF
10%
16V
X7R-CERM
402
14
VCC
U4800
a
n
i
CY7C63803-LQXC
QFN
91 20
91 20
BI
BI
12
13
15
16
17
18
19
USB_IR_P
DIFFERENTIAL_PAIR=USB2_IR
USB_IR_N
DIFFERENTIAL_PAIR=USB2_IR
IR_VREF_FILTER
NC
NC
NC
NC
C4803
1UF
10%
10V
X5R
402-1
8
9
10
20
21 NC
22
23
24
NC
NC
NC
NC
NC
NC
NC
NC
P0.0
P0.1
INT0/P0.2
INT1/P0.3
INT2/P0.4
TIO0/P0.5
TIO1/P0.6
J4800
F-RT-SM
CRITICAL
2
3
4
5
6
518S0692
PP5V_S3_IR_R
P
7
7
SMC_LID_R
SYS_LED_ANODE_R
C4805
C4806
THRML
PAD
10
IN
7 40
C4804
10%
50V
CERM
402
11
PLACE
PLACE
PLACE
PLACE
R4805
R4806
R4807
R4808
NEAR
NEAR
NEAR
NEAR
R4806
10
1/16W
402
5%
MF-LF
100
1/16W
C4807
0.1UF
0.001UF
10%
16V
X7R-CERM
402
10%
50V
CERM
402
C4808
0.001UF
10%
50V
CERM
402
402
5%
MF-LF
10%
16V
X7R-CERM
402
m
il
J4800
J4800
J4800
J4800
=PP3V42_G3H_LIDSWITCH
=PP5V_S3_IR
8 40
R4807
IR_RX_OUT
VSS
402
0.001UF
5%
MF-LF
100
5%
1/16W
MF-LF
402
0.1UF
IR_RX_OUT_RC
NC
1
1/16W
PP3V42_G3H_LIDSWITCH_R
R4800
CRITICAL
OMIT
R4805
FF18-6A-R11AD-B-3H
7
NC
NC
NC
NC
NC
e
r
7
6
5
4
3
2
1
P/N 338S0633
25
P1.0/D+
P1.1/DP1.2/VREG
P1.3/SSEL
P1.4/SCLK
P1.5/SMOSI
P1.6/SMISO
R4808
1
4.7
1/16W
SMC_LID 41 42
SYS_LED_ANODE 7 42
49
402
5%
MF-LF
IR_RX_OUT
7 40
PLACE C4805 NEAR J4800

Front Flex Support

SYNC_MASTER=CHANG_K20

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
48
123
NOTE: Unused pins have "SMC_Pxx" names. Unused

pins designed as outputs can be left floating,
those designated as inputs require pull-ups.
42 7
51 42 8
PP3V3_S5_AVREF_SMC
=PP3V3_S5_SMC
D
C4902
22UF
20%
6.3V
CERM
805
U4900
ESTARLDO_EN
D13
42
C12
D10
NC
NC
NC
42
SMC_P24
SMC_P26
BI
BI
91 84 43 19 7
BI
91 84 43 19 7
BI
91 84 43 19 7
IN
25
IN
91 25
43 19 7
IN
BI
LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>
LPC_FRAME_L
SMC_LRESET_L
LPC_CLK33M_SMC
LPC_SERIRQ
44
BI
OUT
C8
B7
A8
D8
D7
D6
OUT
50
OUT
43 42 41 39 7
OUT
(OC)
43 42 41 39 7
44
IN
BI
B4
A1
SMC_GFX_THROTTLE_L
SMC_SYS_KBDLED
SMC_TX_L
SMC_RX_L
SMB_0_S0_CLK
D4
A5
NC
NC
75
E10
D9
42
51
E12
A9
NC
SMC_P41
SMB_MGMT_DATA
SMS_ONOFF_L
F11
F13
NC
91 84 43 19 7
D12
E13
NC
42
E11
C2
B2
C1
C3
G2
F3
(OC)
E4
P20
P21
P22
P23
P24
P25
P26
P27
P70
P71
P72
P73
P74
P75
P76
P77
N10
L12
SMC_CPU_ISENSE
SMC_CPU_VSENSE
SMC_GPU_ISENSE
SMC_GPU_VSENSE
SMC_DCIN_ISENSE
SMC_PBUS_VSENSE
SMC_BATT_ISENSE
SMC_NB_MISC_ISENSE
P30
P31
P32
P33
P34
P35
P36
P37
P80
P81
P82
P83
P84
P85
P86
A7
SMC_WAKE_SCI_L
P90
P91
P92
P93
P94
P95
P96
P97
J4
SMC_ADAPTER_EN
K13
J10
SMC_PROCHOT_3_3_L
SMC_BIL_BUTTON_L
H12
M11
L10
N11
N12
M13
N13
B6
(OC)
PM_CLKRUN_L
LPC_PWRDWN_L
SMC_TX_L
SMC_RX_L
SMB_MGMT_CLK
(OC)
SMC_ONOFF_L
SMC_BC_ACOK
SMC_BS_ALRT_L
PM_SLP_S3_L
PM_SLP_S4_L
PM_SLP_S5_L
PM_CLK32K_SUSCLK
SMB_0_S0_DATA
D5
A6
B5
P40
P41
P42
P43
P44
P45
P46
P47
25 7
39
28 27 21
B
59 42
21
SMC_PA0
SMC_PA1
PM_SYSRST_L
OUT
USB_DEBUGPRT_EN_L
OUT
MEM_EVENT_L
BI
SMC_PA5
42
SYS_ONEWIRE
BI
PM_BATLOW_L
OUT
N3
42
N1
(OC)
(OC)
(OC)
(OC)
(OC)
(OC)
M3
M2
N2
L1
K3
L2
B8
NC
21
OUT
38 7
IN
42 31
IN
42
IN
75
IN
SMC_RUNTIME_SCI_L
SMC_ODD_DETECT
SMC_PB3
42
(See below)
SMC_EXCARD_CP
C9
B9
A10
C10
B10
NC
48
OUT
48
OUT
42
OUT
42
OUT
48
IN
48
IN
42
IN
42
IN
51
IN
51
IN
51
IN
42
IN
42
IN
42
IN
42
IN
42
IN
SMC_EXCARD_OC_L
SMC_GFX_OVERTEMP_L
C11
A11
SMC_FAN_0_CTL
SMC_FAN_1_CTL
SMC_FAN_2_CTL
SMC_FAN_3_CTL
SMC_FAN_0_TACH
SMC_FAN_1_TACH
SMC_FAN_2_TACH
SMC_FAN_3_TACH
G11
SMS_X_AXIS
SMS_Y_AXIS
SMS_Z_AXIS
SMC_ANALOG_ID
SMC_NB_CORE_ISENSE
SMC_NB_DDR_ISENSE
ALS_LEFT
ALS_RIGHT
M10
G13
F12
H13
G10
G12
H11
J13
N9
K10
L8
M9
N8
K9
L7
42
IN
45
IN
45
IN
46
IN
45
IN
45
IN
45
IN
45
IN
42
OUT
21
G3
H2
G1
H4
G4
F4
F1
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
HS82117
LGA-HF
(2 OF 3)
OMIT
PE0
PE1
PE2
PE3
PE4
PF0
K1
PF1
PF2
PF3
PF4
PF5
PF6
PF7
N5
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
M8
PH0
PH1
PH2
PH3
PH4
PH5
E2
SMC_CASE_OPEN
SMC_TCK
SMC_TDI
SMC_TDO
SMC_TMS
7 19 43
7 19 43
OUT
7 39 41 42 43
IN
7 39 41 42 43
0.1UF
20%
10V
CERM
402
AVCC
a
n
i
2
PLACEMENT_NOTE=Place R4999 close to U4900 pins N14,N15

PLACEMENT_NOTE=Place C4920 close to U4900 pins N14,N15
43 42 7
IN
42
IN
C4907
C4920
44
SMC_RESET_L
D3
RES*
SMC_XTAL
SMC_EXTAL
A3
XTAL
EXTAL
A2
K2
J1
K4
K5
NC
SMC_SYS_LED
SMC_LID
M6
L5
M5
NC
NC
L4
M4
NC
NC
NC
N7
K8
K7
K6
N6
M7
L6
(OC)
(OC)
(OC)
(OC)
(OC)
(OC)
F2
J2
A4
B3
C4
42 59
IN
7 42 59
IN
7 21 33 36 67 82 84
IN
21 39 42 67
IN
42
IN
25 91
42
IN
7 42 43
IN
7 42 43
OUT
7 42 43
IN
7 42 43
IN
VCC
0.47UF
10%
6.3V
CERM-X5R
402
VCL AVREF
U4900
NC
HS82117
E5
R4909 1
NC
LGA-HF
(3 OF 3)
OMIT
MD1
MD2
D1
NMI
E3
ETRST
H3
AVSS
L9
R4901
10K
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
2 402
SMC_MD1
IN
7 43
SMC_NMI
IN
7 43
SMC_TRST_L
IN
7 43
SMC_KBC_MDE
H1
VSS
XW4900
SM
2
10K
R4902
NO STUFF
1
R4998
10K
10K
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
R4903
0
5%
1/16W
MF-LF
2 402
GND_SMC_AVSS
42 45 46
42
40 42 49
OUT
IN
42
BI
44
BI
44
BI
44
BI
44
BI
44
BI
NOTE: P94 and P95 are shorted, P95 could be spare.
44
IN
OUT
=SMC_SMS_INT
SMB_BSA_DATA
SMB_BSA_CLK
SMB_A_S3_DATA
SMB_A_S3_CLK
SMB_B_S0_DATA
SMB_B_S0_CLK
SMC_PROCHOT
SMC_THRMTRIP
SMC_PH2
ALS_GAIN
IN
BI
SMC_MCP_SAFE_MODE
N4
7 42 49
m
il
e
r
J3
y
r
PP3V3_S5_SMC_AVCC
VOLTAGE=3.3V
42
OUT
BI
P50
P51
P52
42
42
IN
IN
U4900
(DEBUG_SW_1)
(DEBUG_SW_2)
IN
4.7
5%
1/16W
MF-LF
402
21 33 36 42
NC
C7
C6
OUT
NC
J11
SMC_VCL
R4999
1
L11
OUT
OUT
21
J12
67
E1
OUT
61
91 84 43 19 7
D11
C13
OUT
K11
OUT
NC
NC
NC
H10
NC
PM_RSMRST_L
IMVP_VR_ON
PM_PWRBTN_L
21
(1 OF 3)
OMIT
K12
20%
10V
CERM
402
M1
B13
L13
LGA-HF
PLACEMENT_NOTE=Place C4907 close to U4900 pin F1
SMC_PM_G2_EN
P60
P61
P62
P63
P64
P65
P66
P67
HS82117
0.1UF
20%
10V
CERM
402
B1
A12
P10
P11
P12
P13
P14
P15
P16
P17
0.1UF
2
C5
IN
A13
20%
10V
CERM
402
C4906
B11
IN
67
B12
0.1UF
20%
10V
CERM
402
F10
84 67 25
SMC_EXCARD_PWR_EN
SMC_RSTGATE_L
ALL_SYS_PWRGD
RSMRST_PWRGD
C4905
M12
OUT
0.1UF
C4904
L3
OUT
42
D2
31
C4903
NOTE: SMS Interrupt can be active high or low, rename net accordingly.
If SMS interrupt is not used, pull up to SMC rail.
44
OUT
42
OUT
42
OUT
42
42
NC
NC
SMC
SYNC_MASTER=T18_MLB

SMC_PB3:
SMC_IG_THROTTLE_L for MG systems.

Otherwise, TP/NC okay (was ISENSE_CAL_EN)

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
49
123
41
SMC_FAN_2_CTL
41
SMC_FAN_2_TACH
41
SMC_FAN_3_CTL
41
SMC_FAN_3_TACH
5
NC_SMC_FAN_2_CTL
MAKE_BASE=TRUE
SMC Reset "Button" / Brownout Detect
SMC FSB to 3.3V Level Shifting
NC_SMC_FAN_2_TACH
MAKE_BASE=TRUE
NC_SMC_FAN_3_CTL
51 42 41 8 =PP3V3_S5_SMC
=PP3V3_S0_SMC
42 8
MAKE_BASE=TRUE
NC_SMC_FAN_3_TACH
MAKE_BASE=TRUE
C5000
0.1uF
20%
10V
CERM
402
NCP303LSN
SOT23-5-HF
5
SMC_MANUAL_RST_L
OMIT
1
GND
C5001
0
SILK_PART=SMC_RST
NC
R5001
CD
NC
=PP1V05_S0_SMC_LS
OUT
IN
1/16W
MF-LF
1
41
ESTARLDO_EN
NC_ESTARLDO_EN
SMC_RESET_L
2
2
59 42 41
SMC_BC_ACOK
=CHGR_ACOK
Q5032
41
SMC_MCP_VSENSE
ALS_LEFT
TO CPU
45
3.3K
SOT563
41
88 61 14 10
SMC_CPU_HI_ISENSE
ALS_RIGHT
BI
CPU_PROCHOT_L
45
5%
1/16W
41
5
51 42 41 8 =PP3V3_S5_SMC
SMC_NB_CORE_ISENSE
U5001
41
SMC_NB_DDR_ISENSE
41
SMC_NB_MISC_ISENSE
41
SMC_ANALOG_ID
SMC_MCP_DDR_ISENSE
SMC_CPU_FSB_ISENSE
SMC_TPAD_RST
MAKE_BASE=TRUE
02
41
SMC_P24
41
SMC_P26
TP_SMC_P24
88 14 10
SMC_BMON_MUX_SEL
41
SMC_P41
TP_SMC_P41
ALS_GAIN
41
41
0
1
SMC_EXCARD_OC_L
EXCARD_OC_L
IN
5%
1/16W
MF-LF
402
SMC AVREF Supply

51
CRITICAL
SMS_INT_L
PP3V3_S5_AVREF_SMC
m
il
7 41
SOT23-3
VOLTAGE=3.3V
SMC Crystal Circuit
GND
C5026
C5010
0.01UF
C5025
0.47UF
10uF
10%
6.3V
CERM-X5R
402
20%
6.3V
X5R
603
41
R5010
1
BOM OPTION
REF DES
COMMENTS:
353S1912
ALL
Y5010
20.00MHZ
5X3.2-SM
Intersil ISL60002-33
41
System (Sleep) LED Circuit

8
=PP5V_S3_SYSLED
R5031
523
1%
1/16W
MF-LF
402
R5030
20
1%
1/16W
MF-LF
402
SYS_LED_ILIM
2
CRITICAL
SOD
R5032
2SA2154MFV-YAE
SYS_LED_L_VDIV
Q5030
1.47K
SYS_LED_ANODE
1%
1/16W
MF-LF
402 2
SYS_LED_L
A
Q5032
SSM6N15FEAPE
SMC_ONOFF_L
CRITICAL
VOLTAGE=0V
OUT
SMC_EXTAL
42 41
IN
41
41
SMC_PA0
41
SMC_PA1
R5091
R5092
IN
100K
100K
SMC_LID
R5070
R5071
10K
49 41 40
100K
41
SMC_PH2
R5072
10K
43 41 39 7
7 41 42 49
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
5%
1/16W
MF-LF
SMC_RX_L
10K
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
402
100K
2.0K
100K
10K
ONEWIRE_PU
59 41 7
SMC_BS_ALRT_L
43 41 7
SMC_TMS
R5077
SYS_ONEWIRE
43 41 7
SMC_TDI
R5078
R5079
43 41 7
SMC_TCK
R5080
10K
SMC_BIL_BUTTON_L
R5081
R5087
10K
42 41
59 42 41
R5015
R5073
R5074
SMC_TX_L
R5075
R5076
59 41
43 41 7
OUT
SMC_ONOFF_L
SMC_TDO
SMC_BC_ACOK
10K
10K
470K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
SILK_PART=PWR_BTN
C5011
15pF
5%
1/10W
MF-LF
603
PLACE R5015,R5001 ON BOTTOM SIDE
5%
50V
CERM
402
8 7
PP3V42_G3H
C5050
R5051
1/16W
402
MF-LF
5%
10%
2 16V
X5R
402
U5050
41
41 31
10K
0.1UF
41
67 41 39 21
R5085
R5086
SMC_ADAPTER_EN
SMC_CASE_OPEN
SMC_BIL_BUTTON_DB_L
SOT-553
4
10K
SMC_EXCARD_CP
R5088
10K
PM_SLP_S5_L
R5090
100K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
PM_SLP_S4_L
7 59
=PP3V3_S0_SMC
42 8
NC
41
10K
74LVC1G17DRL
SMC_BIL_BUTTON_L
41 36 33 21
R5089
SMC_PA5
10K
5%
NC
1
1/16W
MF-LF
402
C5051
0.01UF
7 40
10%
25V
2 X7R
402
SMC Support
SYNC_MASTER=M98_MLB

SOT563
41
C
=PP3V3_S5_SMC
51 42 41 8
43 41 39 7
OMIT
49 42 41 7
Debug Power "Button"
5%
50V
CERM
402
SMC_XTAL_R
e
r
41 45 46
TABLE_ALT_ITEM
353S1381
5%
1/16W
MF-LF
402
TABLE_ALT_HEAD
ALTERNATE FOR
PART NUMBER
GND_SMC_AVSS
PART NUMBER
SMC_XTAL
41
C5020
15pF
10%
16V
CERM
402
41
20 31
1
3
=SMC_SMS_INT
MAKE_BASE=TRUE
VR5020
IN
SMC_THRMTRIP
TP_SMC_RSTGATE_L
R5095
OUT
SSM6N15FEAPE
21
MAKE_BASE=TRUE
41
Q5059
SOT563
SMC_IG_THROTTLE_L
SMC_RSTGATE_L
MAKE_BASE=TRUE
PM_THRMTRIP_L
NC_ALS_GAIN
SMC_PB3
OUT
MAKE_BASE=TRUE
45
MAKE_BASE=TRUE
OUT
SMC_PROCHOT
41
IN
46
MAKE_BASE=TRUE
a
n
i
SMC_GPU_1V8_ISENSE
MAKE_BASE=TRUE
REF3333
SOT563
46
MAKE_BASE=TRUE
=PPVIN_S5_SMCVREF
Q5059
SSM6N15FEAPE
46
MAKE_BASE=TRUE
SOT553-5
BC847BV-X-F
SOT563-HF
402
46
MAKE_BASE=TRUE
SN74LVC1G02
4
MF-LF
SMC_MCP_CORE_ISENSE
BC847BV-X-F
SOT563-HF
Q5060
CPU_PROCHOT_L_R
MAKE_BASE=TRUE
SMC_ONOFF_L
R5062
MAKE_BASE=TRUE
SSM6N15FEAPE
49 42 41 7
Q5060
y
r
60
MAKE_BASE=TRUE
41
402
CPU_PROCHOT_BUF
OUT
1/16W
MF-LF
49 SMC_TPAD_RST_L
SMC_PROCHOT_3_3_L
5%
7 41 43
OUT
R5061
TO SMC
402
3.3K
MAKE_BASE=TRUE
CRITICAL
10%
16V
CERM
402
5%
5%
1/16W
MF-LF
402
0.01UF
5%
1/10W
MF-LF
603
R5060
470
1K
U5000
R5000
SMC_SYS_LED

2

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
50
123
LPC+SPI Connector
CRITICAL
LPCPLUS
J5100
55909-0374
91 84 41 19 7
BI
91 84 41 19 7
BI
43 7
IN
43 7
OUT
91 84 41 19 7
52 43 8
OUT
42 41 7
OUT
41 7
IN
41 7
OUT
IN
SPI_CLK_R
91 43 21
IN
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
33
34
D
LPC_CLK33M_LPCPLUS
LPC_AD<2>
LPC_AD<3>
SPIROM_USE_MLB
SPI_ALT_CLK
SPI_ALT_CS_L
LPC_SERIRQ
LPC_PWRDWN_L
SMC_TDI
SMC_TCK
SMC_RESET_L
SMC_NMI
SMC_RX_L
LPCPLUS_GPIO
SPI_MOSI_R
U5110
M+ 5
M- 4
SPI_ALT_CLK
SPI_ALT_MOSI
OUT
7 43
OUT
7 43
TQFN
R5191
10K
CRITICAL
SPI_CLK_MUX
SPI_MOSI_MUX
OUT
43 52
SPIROM_USE_MLB
10 SEL
OUT
43 52
m
il
LPCPLUS
=PP3V3_S5_LPCPLUS
From Frank Card
C5124
0.1UF
20%
2 10V
CERM
402
SPI_ALT_MISO
IN
VCC
OUT
IN
SPI_MISO
SPI_CS0_R_L
1 Y+
2 Y-
U5120
M+ 5
M- 4
1/16W
D+ 7
D- 6 SPI_MLB_CS_L_MUX
OE* 8
3
20K
5%
1/16W
MF-LF
402 2
R5146
0
5%
PLACEMENT_NOTE=PLACE NEXT TO U1400
1/16W
MF-LF
402
SPI MUX BYPASS

LPCPLUS_NOT
R5156
52 43
OUT
SPI_CLK_MUX
2
5%
1/16W
MF-LF
402
52 43
OUT
LPCPLUS_NOT
R5157
0
SPI_MOSI_MUX
LPCPLUS_NOT
R5158
52 43
IN
SPI_MISO_MUX
0
5%
1/16W
MF-LF
402
IN
MCP_CS1_YES
7 43
BI
7 19 41
IN
7 19 41
OUT
7 41 42
OUT
7 41 42
OUT
7 41 42
OUT
7 41
OUT
7 39 41 42
OUT
7 18
=PP3V3_S0_LPCPLUS
=PP3V3_S5_LPCPLUS
SPI_CLK_R
IN
21 43 91
SPI_MOSI_R
IN
21 43 91
OUT
21 43 91
OUT
NOT SUPPORTED IN REV A01 OR B01 MCP79 SILICON
R5140 1
100K
5%
1/16W
MF-LF
402 2
LPC_FRAME_PU
Q5140
MCP_CS1_YES
R5141 1
470
5%
1/16W
MF-LF
402 2
SSM3J16FV
SOD-VESM-HF
MCP_CS1_NO
LPC_FRAME_R_L
R5142
1
MCP_CS1_YES
19
OUT
5% PLACEMENT_NOTE=Place near J5100

1/16W
MF-LF
402
SPI_CS1_R_L_USE_MLB
BI
MAKE_BASE=TRUE
9 21
R5147
0
5%
1/16W
MF-LF
402
43 52
MCP_CS1_NO
0 2 R5126 SPI_MLB_CS_L
1
402
5%
MCP_CS1_NO
MF-LF
R51441
MCP_CS1_YES&LPCPLUS_NOT
7 43
SPI_MISO_MUX
1/16W
GND
5%
MF-LF
OUT
402
e
r
CRITICAL
10 SEL
7 43
MCP_CS1_NO
Pull-up on debug card
0 2 R5127 SPI_ALT_CS_L
1
SPI_ALT_CS_L_MUX
PI3USB102ZLE
TQFN
7 43
IN
SPIROM_USE_MLB
43 7
91 21
IN
MCP SPI Override Options
SEL HIGH OUTPUTS TO D (ON BOARD ROM)

SEL LOW OUTPUTS TO M (FRANKCARD ROM)
91 43 21
OUT
MCP79 REV A01 REQUIRES EXTERNAL MUX, REV B01 STILL DOES NOT SUPPORT INTERNAL MUX
OE* 8
LPCPLUS
7 19 41 84 91
7 43
GND
8
43
7 19 41 84 91
43 7
BI
5%
1/16W
MF-LF
402 2
D+ 7
D- 6
BI
43 8
PI3USB102ZLE
1
IN
a
n
i
VCC
1 Y+
2 Y-
y
r
7 25 91
MCP79 Internal SPI MUX Support
516S0573
20%
10V
402
2 CERM
LPCPLUS
5%
1/16W
MF-LF
402 2
C5114
0.1UF
10K
91 43 21
IN
LPCPLUS
=PP3V3_S5_ROM
R51901
IN
41 19 7
42 41 39 7
=PP3V3_S5_LPCPLUS
SPI_ALT_MOSI
SPI_ALT_MISO
LPC_FRAME_L
PM_CLKRUN_L
SMC_TMS
DEBUG_RESET_L
SMC_TDO
SMC_TRST_L
SMC_MD1
SMC_TX_L
OUT
MUX SEL CONTROLLED BY FRANKCARD SWITCH ONCE CS1 IS SUPPORTED IN MCP
43 8
LPC_AD<0>
LPC_AD<1>
IN
Alternate SPI ROM Support
M-ST-SM
31
32
=PP3V3_S5_LPCPLUS
=PP5V_S0_LPCPLUS
43 8
To Frank Card
PLACEMENT_NOTE=PLACE NEXT TO U5120
52
=PP3V3_S5_ROM
8 43 52
5%
1/16W
MF-LF
402
SPI_MISO
LPC+SPI Debug Connector

SYNC_MASTER=CHANG_K20

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
51
123
7
MCP79 SMBus "0" Connections
SMC "0" SMBus Connections
SMC "A" SMBus Connections

NOTE: SMC RMT bus remains powered and may be active in S3 state
8 =PP3V3_S0_SMBUS_MCP_0
R5200
MCP79
U1400
(MASTER)
8 =PP3V3_GPU_SMBUS_SMC_0_S0
R5201
4.7K
4.7K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
91 21 13 7 SMBUS_MCP_0_CLK
SO-DIMM "A"
SMC
J3100
U4900
(Write: 0xA0 Read: 0xA1)
(MASTER)
8 =PP3V3_S3_SMBUS_SMC_A_S3
R5250
=I2C_SODIMMA_SCL
27
41 SMB_0_S0_CLK
94 SMBUS_SMC_0_S0_SCL
=I2C_SODIMMA_SDA
27
41 SMB_0_S0_DATA
94 SMBUS_SMC_0_S0_SDA
MAKE_BASE=TRUE
R5251
4.7K
4.7K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
GPU Temp (Ext)
SMC
EMC1043-1: U5550
U4900
(Write: 0x98 Read: 0x99)
(MASTER)
=SMBUS_GPUTHMSNS_SCL
47
41 SMB_A_S3_CLK
=SMBUS_GPUTHMSNS_SDA
47
41 SMB_A_S3_DATA
R52701
MAKE_BASE=TRUE
SO-DIMM "B"
SMBUS_SMC_A_S3_SDA
y
r
G96: U8000
(Write: 0x9E Read: 0x9F)
=I2C_SODIMMB_SCL
28
=GPU_I2CS_SCL
76
=I2C_SODIMMB_SDA
28
=GPU_I2CS_SDA
76
a
n
i
SMC "Battery A" SMBus Connections
J3500
8 =PP3V42_G3H_SMBUS_SMC_BSA
=SMBUS_EXCARD_SDA
31
R52801
SMC
R5281
1K
(MASTER)
Battery
1K
5%
1/16W
MF-LF
402 2
U4900
5%
1/16W
MF-LF
2 402
J6955
(See Table)
SMBUS_SMC_BSA_SCL
41 SMB_BSA_CLK
=SMBUS_BATT_SCL
59
=SMBUS_BATT_SDA
59
MAKE_BASE=TRUE
41 SMB_BSA_DATA
J5800
SMBUS_SMC_A_S3_SCL
GPU Temp (Int)
J3200
31
5%
1/16W
MF-LF
2 402
=I2C_TPAD_SCL
50
=I2C_TPAD_SDA
50
MAKE_BASE=TRUE
(Write: 0xA2 Read: 0xA3)
=SMBUS_EXCARD_SCL
TRACKPAD
1K
MAKE_BASE=TRUE
MAKE_BASE=TRUE
ExpressCard Slot
R5271
5%
1/16W
MF-LF
402 2
MAKE_BASE=TRUE
91 21 13 7 SMBUS_MCP_0_DATA
1K
SMBUS_SMC_BSA_SDA
MAKE_BASE=TRUE
Battery Charger
ALS
J3401
I2C_ALS_SCL
30
I2C_ALS_SDA
30
SMC "B" SMBus Connections
8 =PP3V3_S0_SMBUS_SMC_B_S0
ISL6258 - U7000
Battery
R5260
SMC
Battery Manager - (Write: 0x16 Read: 0x17)
=SMBUS_CHGR_SCL
m
il
Battery LED Driver - (Write: 0x36 Read: 0x37)
MCP79 SMBus "1" Connections
MCP79
U1400
(MASTER?)
R5230
R5231
1.5K
1.5K
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
2 402
91 21 SMBUS_MCP_1_CLK
SMC "Management" SMBus Connections
HDCP ROM
8 =PP3V3_S3_SMBUS_SMC_MGMT
Read: 0xA1-0xAF)
=I2C_HDCPROM_SCL
24
=I2C_HDCPROM_SDA
24
SMC
U4900
MAKE_BASE=TRUE
41 SMB_MGMT_CLK
Mikey
41 SMB_MGMT_DATA
U6800
(WRITE: 0X72 READ: 0X73)
=I2C_MIKEY_SCL
58
=I2C_MIKEY_SDA
58
R5290
e
r
(MASTER)
60
41 SMB_B_S0_CLK
41 SMB_B_S0_DATA
R5261
3.3K
3.3K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
CPU Temp
EMC1043-1: U5570
94 SMBUS_SMC_B_S0_SCL
=I2C_CPUTHMSNS_SCL
47
=I2C_CPUTHMSNS_SDA
47
MAKE_BASE=TRUE
94 SMBUS_SMC_B_S0_SDA
MAKE_BASE=TRUE
The bus formerly known as "Battery B"
U2690 or U2695
(Write: 0xA0-0xAE,
MAKE_BASE=TRUE
91 21 SMBUS_MCP_1_DATA
(MASTER)
=SMBUS_CHGR_SDA
Battery Temp - (Write: 0x90 Read: 0x91)
8 =PP3V3_S0_SMBUS_MCP_1
U4900
60
R5291
4.7K
4.7K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
MCP Temp
EMC1043-2: U5500
(WRITE: 0X9A READ: 0X9B)
Vref DACs
94 SMBUS_SMC_MGMT_SCL
=SMBUS_MCPTHMSNS_SCL
47
=SMBUS_MCPTHMSNS_SDA
47
U2900
=I2C_VREFDACS_SCL
26
=I2C_VREFDACS_SDA
26
MAKE_BASE=TRUE
94 SMBUS_SMC_MGMT_SDA
Battery Charger Temp
MAKE_BASE=TRUE
TMP102: U5540
Margin Control
=SMBUS_TMPSNSR_SCL
47
=SMBUS_TMPSNSR_SDA
47
U2901
=I2C_PCA9557D_SCL
26
=I2C_PCA9557D_SDA
26
SMS
U5930
=I2C_SMS_SCL
51
=I2C_SMS_SDA
51
K20 SMBUS CONNECTIONS

SYNC_MASTER=BEN_K20

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
52
123
7
CPU Voltage Sense / Filter
XW5309
12 11 8
=PPVCORE_S0_CPU
Q5315
4.53K
CPUVSENSE_IN
PBUS Voltage Sense & Filter
R5309
SM
1
SMC_CPU_VSENSE
OUT
FDG6332CG
41
SC70-6
1%
Place short near U1000 center
P-CHN
1/16W
1
MF-LF
C5309
402
8 7
PPBUS_G3H
0.22UF
20%
6.3V
2
PPBUS_G3H_VSENSE
VOLTAGE=18.5V
X5R
402
R5315
GND_SMC_AVSS
100K
41 42 45 46
Place RC close to SMC
12.7K
1%
1/16W
402
MF-LF
402
Rthevenin = 4504 ohms
PBUSVSENS_EN_DIV
XW5359
=PPVCORE_GPU_REG
77 8
SMC_PBUS_VSENSE
41
OUT
y
r
R5359
SM
4.53K
1
1/16W
MF-LF
GPU Voltage Sense / Filter
R5385
5%
GPUVSENSE_IN
SMC_GPU_VSENSE
OUT
R5316
41
1/16W
1
MF-LF
402
C5359
20%
6.3V
R5386
C5385
6.98K
5%
1%
1/16W
1/16W
MF-LF
MF-LF
402
402
0.22UF
2
100K
1%
Place short near U8000 center
0.22UF
20%
6.3V
2
X5R
402
PBUSVSENS_EN_L
GND_SMC_AVSS
41 42 45 46
X5R
402
GND_SMC_AVSS
41 42 45 46
6
23 22 8
MCPVSENSE_IN
PLACEMENT_NOTE=Place near U1400 center
4.53K
1%
1/16W
MF-LF
402
Q5315
a
n
i
FDG6332CG
SC70-6
R5399
SM
1
Enables PBUS VSense divider when high.
XW5399
=PPVCORE_S0_MCP
=PBUSVSENS_EN
67
N-CHN
MCP Voltage Sense / Filter
SMC_MCP_VSENSE
OUT
42
C5399
0.22UF
20%
6.3V
X5R
402
GND_SMC_AVSS
41 42 45 46
C
BMON Current Sense - Entire circuit must be near SMC (U4900)
m
il
=PP3V42_G3H_BMON_ISNS
BMON_ENG
BMON_ENG
C5318
BMON_INA_OUT
0.1uF
3
20%
2 10V
CERM
REGULATOR SIDE:
BMON_ENG
V+
402
2 GND
OUT
96 60
IN
5 IN-
CHGR_CSO_R_P
SC70
4 IN+
CHGR_CSO_R_N
OUT 6
60
IN
VER 1
402
42
BMON_ENG
e
r
R5330
GND
5%
1/16W
MF-LF
402
Monitors battery discharge

current from battery to PBUS
INA214 has gain of 100V/V

U5303 only senses current up to 6.6A
4.53K
1%
1/16W
MF-LF
402
R5371
IN
BMON_AMUX_OUT
BMON_PROD
LOAD SIDE:
SMC_BMON_MUX_SEL
B0
REF 1
R5391
CHGR_BMON
20%
10V
2 CERM
VCC 5
0
INA214
C5369
0.1uF
NC7SB3157P6XG
SC70
B1
SEL
U5303
96 60
U5313
BMON_ENG
SMC_BATT_ISENSE
41
R5380
C5390
4.53K
60
0.22UF
100K
5%
1/16W
MF-LF
402
OUT
DCIN Current Sense Filter
IN
CHGR_AMON
20%
6.3V
X5R
402
SMC_DCIN_ISENSE
OUT
41
1%
1/16W
MF-LF
402
GND_SMC_AVSS
C5380
0.22UF
20%
6.3V
41 42 45 46
2
X5R
402
GND_SMC_AVSS
41 42 45 46
CPU VCore High Side Current Sensor

=PP3V42_G3H_CPUCOREISNS
OUT
=PPVIN_S5_CPU_IMVP_ISNS
V+
C5388
20%
10V
R5388
96
ISNS_CPU_N
1%
1W
MF
1206
96
2 4
ISNS_CPU_P
IN-
SC70
IN+
OUT
REF
IN
61
IMVP6_IMON
SMC_CPU_ISENSE
OUT
41
1%
MF-LF
SMC_CPU_HI_ISENSE
OUT
402
42
402
R5332
1%
1/16W
MF-LF
402
C5335
0.22UF
C5330
0.22UF
Current & Voltage Sensing
20%
6.3V
2
X5R
SYNC_MASTER=YWU_K20
402
20%
6.3V
2
17.4K
1%
1/16W
MF-LF
IN
1/16W
4.53K
CPUVCORE_HISIDE_IOUT
=PPVIN_S5_CPU_IMVP_ISNS_R
6.19K
R5335
GND
R5331
402
INA210
0.001
CERM
U5388
1 3
CPU VCore Load Side Current Sense / Filter
0.1UF
GND_SMC_AVSS
41 42 45 46
X5R
402
GND_SMC_AVSS

41 42 45 46

Consider INA211 (GAIN 500 version) since I=4.93 Amps across R5388
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
53
123
7
MCP VCore Current Sense
GPU VCore Current Sense
=PP3V3_S0_MCPCOREISNS
1
C5420
0.1UF
20%
10V
CERM
402
NC
MCP VCore Current Sense Filter
V+

77
U5420
96 64
IN
IN-
IN
MCPCORE_IOUT
OUT
402
MCPCOREISNS_P
IN+
REF
SMC_GPU_ISENSE
41
OUT
1%
1/16W
1/16W
IN
GPUVCORE_IOUT
V-
4.53K
MF-LF
42
1%
96 64
R5475
DFN
V+
1/16W
SMC_MCP_CORE_ISENSE
OPA2333
GPUISENS_P
96
1%
4.53K
OUT
SC70
R5470
INA213
MCPCOREISNS_N
2.87K
GFXIMVP6_IMON
GPU VCore Current Sense Filter
U5410
R5493
MF-LF
R5491
C5470
402
20%
6.3V
2
96
y
r
GPUISENS_N
1/16W
402
MF-LF
402
GND_SMC_AVSS
41 42 45 46
402
C5475
0.22UF
20%
6.3V
NC
NC
1%
X5R
MF-LF
10K
0.22UF
GND
THRM
X5R
402
GND_SMC_AVSS
41 42 45 46
R5498
Gain: 1.4x
4.02K
1
1%
1/16W
MF-LF
402
C5498
MCP MEM VDD Current Sense
470PF
a
n
i
1
=PP3V3_S0_MCPDDRISNS
1
C5440
0.1UF
20%
10V
CERM
402
IN
MCP MEM VDD Current Sense Filter
=PPMCPDDR_ISNS_R
R5445
1 3 96
C
OUT
DDRISNS_R_P
dual package opamp U5410
R5440
DFN
V+
4.53K
1%
MCPDDR_IOUT
SMC_MCP_DDR_ISENSE
OUT
1/16W
V-
MF-LF
1/16W
THRM
3.65K
DDRISNS_N
=PPMCPDDR_ISNS
42
1%
402
R5443
2 4
96
96
GPU VCore Current Sense and GPU 1.8V Current Sense share
OPA2333
3.65K
DDRISNS_P
0.002
1%
1/4W
MF
1206
U5440
R5444
CRITICAL
96
DDRISNS_R_N
MF-LF
402
C5490
0.22UF
20%
6.3V
1%
1/16W
X5R
402
MF-LF
402
GND_SMC_AVSS
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY
1
C5442
R5441
1M
470PF
10%
50V
CERM
402
R5442
2
2
41 42 45 46
Gain: 274x
2
1%
1/16W
MF-LF
402
C5441
m
il
470PF
1
10%
50V
CERM
402
SIGNAL_MODEL=EMPTY
IN
=PP3V3_S0_GPU1V8ISNS
=PP1V8_S0GPU_ISNS_R
R5413
96
P1V8GPU_P
3.65K
0.002
1%
1/4W
MF
1206
e
r
MCP MEM VDD Current Sense and CPU FSB 1.05V Current Sense share
dual package opamp U5440
CPU FSB 1.05V Current Sense
R5431
96 65
3.65K
1V05CPU_P
IN
96
1V05CPUISNS_R_P
1%
1/16W
NC
1V05CPU_N
3.65K
1
1%
96
CPU1V05_S0_IOUT
VTHRM
C5472
10%
50V
CERM
402
2
2
V+
4.53K
P1V8_S0GPU_IOUT
V-
MF-LF
SMC_GPU_1V8_ISENSE
MF-LF
R5414
4
96
P1V8GPU_N
THRM
3.65K
1
96
P1V8GPUISNS_R_N
MF-LF
402
C5465
0.22UF
20%
6.3V
1%
1/16W
X5R
402
MF-LF
402
GND_SMC_AVSS
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY
C5412
R5411
1M
470PF
10%
50V
CERM
402
R5412
2
2
1%
1/16W
MF-LF
402
41 42 45 46
SIGNAL_MODEL=EMPTY
1M
2
1%
1/16W
MF-LF
402
C5411
470PF
1
10%
50V
CERM
402
SIGNAL_MODEL=EMPTY
Gain: 274x
OUT
42
C5435
0.22UF
Current Sensing
X5R
402
GND_SMC_AVSS
SIGNAL_MODEL=EMPTY
41 42 45 46
1M
1
2
1%
1/16W
MF-LF

SIGNAL_MODEL=EMPTY
C5432
470PF
1
10%
50V
CERM
402
SIZE
DRAWING NUMBER
Gain: 274x
APPLE INC.
REV.
051-7656
SCALE
SHT
NONE
42
1/16W
20%
6.3V
NC
R5432
402
OUT
1%
402
SYNC_MASTER=YWU_K20
R5437
1%
1/16W
MF-LF
402
1%
1/16W
=PP1V8_S0GPU_ISNS
SMC_CPU_FSB_ISENSE
NC
1M
470PF
R5465
DFN
4.53K
1
402
1V05CPUISNS_R_N
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY
OPA2333
1%
MF-LF
GPU 1.8V Current Sense Filter
U5410
8
1/16W
1/16W
402
CERM
402
R5495
DFN
V+
R5436
IN
P1V8GPUISNS_R_P
20%
10V
1.05V CPU Current Sense Filter
402
96 65
0.1UF
OPA2333
OUT
96
C5410
U5440
MF-LF
R5415
CRITICAL1
OPA2333s for proto are placeholders for OPA2330
GPU 1.8V Current Sense
SIGNAL_MODEL=EMPTY
1M
1%
1/16W
MF-LF
402
10%
50V
CERM
402
31
OF
54
123
CPU Proximity/CPU Die/Right Fin Stack
Battery Charger Proximity
R5570
8
47
=PP3V3_S0_CPUTHMSNS
BI
VOLTAGE=3.3V
10%
50V
CERM
402
DFN
2 DP1
3 DN1
ALERT* 8
CRITICAL
4 DP2/DN3
SMDATA 9
CPU_THERMD_N
Q5501
R5572
10K
5%
1/16W
MF-LF
402
10K
V+
5%
1/16W
MF-LF
402
U5540
CPUTHMSNS_THM_L
44 =SMBUS_TMPSNSR_SDA
CPUTHMSNS_ALERT_L
SMCLK 10
BI
44
=I2C_CPUTHMSNS_SCL
BI
44
10%
50V
CERM
402
2
96
Placement note:
a
n
i
Placement note:
Place Q5501 on bottom side
close to right fin stack
MCP Proximity/MCP Die/Right Heat Pipe

R5500
8
47
=PP3V3_S0_REMTHMSNS
PP3V3_S0_REMTHMSNS_R
VOLTAGE=3.3V
5%
1/16W
MF-LF
402
96 21
1
VDD
SIGNAL_MODEL=EMPTY
C5511
Detect MCP Die Temperature
U5500
m
il
0.0022uF
EMC1403-2
10%
50V
CERM
402
J5502
96 21
78171-0002
M-RT-SM
96 7
ALERT* 8
CRITICAL
4 DP2/DN3
SMDATA 9
5 DN2/DP3
GND
6
SIGNAL_MODEL=EMPTY
C5521
518S0519
0.0022uF
10%
50V
CERM
402
4
96 7
THERM* 7
3 DN1
MCPTHMSNS_D_P
Detect Right Heat Pipe Temperature
DFN
2 DP1
MCP_THMDIODE_N
BI
SCL
ALERT
20%
10V
CERM
402
R5501 1
10K
R5502
10K
5%
1/16W
MF-LF
402 2
C5540
0.1uF
20%
10V
CERM
402
Note: EMC1403 can perform Beta

Compensation for External Diode 1 only
5%
1/16W
MF-LF
402
REMTHMSNS_THM_L
REMTHMSNS_ALERT_L
SMCLK 10
=SMBUS_MCPTHMSNS_SDA
BI
44
=SMBUS_MCPTHMSNS_SCL
BI
44
THRM_PAD
11
Placement note:
MCPTHMSNS_D_N
e
r
C5500
0.1uF
MCP_THMDIODE_P
BI
Place U5540 near battery

charger circuit
CPUTHMSNS_D2_N
ADD0
0.0022uF
SOT732-3
SDA
GND
Place U5570 under CPU

and close to left fin stack
y
r
44 =SMBUS_TMPSNSR_SCL
=I2C_CPUTHMSNS_SDA
THRM_PAD
11
SIGNAL_MODEL=EMPTY
BC846BMXXH
HPA00330AI
Placement note:
C5590
Detect Right Fin Stack Temperature
THERM* 7
CPUTHMSNS_D2_P
SOT563
5 DN2/DP3
GND
6
96
EMC1403-1
C5580
BI
TEMP SENSOR HAS ADDRESS WRITE:0X92, READ: 0X93
R5571 1
20%
10V
CERM
402
U5570
CPU_THERMD_P
0.0022UF
96 10
C5570
0.1uF
1
VDD
SIGNAL_MODEL=EMPTY
Detect CPU Die Temperature
=PP3V3_S0_BATTCHARGERTMPSNSR
PP3V3_S0_CPUTHMSNS_R
2
5%
1/16W
MF-LF
402
96 10
Place U5500 near MCP
Placement note:
Keep 2 caps as close

to IC pins as possible
NOTE: U5500 Changed to EMC1403-2.
Write Address: 0x9A
GPU Proximity/GPU Die/Left Heat Pipe
R5550
47
=PP3V3_S0_GPUTHMSNS
96 75
BI
PP3V3_S0_GPUTHMSNS_R
2
5%
1/16W
MF-LF
402
VOLTAGE=3.3V
GPU_TDIODE_P
Detect Left Heat Pipe Temperature
96
SIGNAL_MODEL=EMPTY
C5551
10%
50V
CERM
402
GPUTHMSNS_D_P
Q5503
SIGNAL_MODEL=EMPTY
10%
50V
CERM
402
SOT732-3
Placement note:
0.0022uF
BC846BMXXH
2
96
5%
1/16W
MF-LF
402
R5552
10K
5%
1/16W
MF-LF
402
U5550
2 DP1
DFN
THERM* 7
ALERT* 8
CRITICAL
4 DP2/DN3
SMDATA 9
C5552
10K
EMC1403-1
2
3 DN1
R5551 1
0.0022uF
20%
10V
CERM
402
1
VDD
GPU_TDIODE_N
BI
C5550
0.1uF
Detect GPU Die Temperature
96 75
5 DN2/DP3
GND
6
SMCLK 10
GPUTHMSNS_THM_L
GPUTHMSNS_ALERT_L
=SMBUS_GPUTHMSNS_SDA
BI
44
=SMBUS_GPUTHMSNS_SCL
BI
44
Thermal Sensors
THRM_PAD
SYNC_MASTER=YWU_K20
11

2

Placement note:
GPUTHMSNS_D_N
Place on top side under left heat pipe near CPU
Place U5550 near GPU

Placement note:
Keep 2 caps as close

to IC pins as possible
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
55
123
a
n
i
Left Fan
8 7
8
Right Fan
=PP5V_S0_FAN_LT
=PP3V3_S0_FAN_LT
CRITICAL
J5650
R5650
78171-0004
R5655
41
OUT
SMC_FAN_0_TACH
47K
m
il
1
FAN_LT_TACH
5%
1/16W
MF-LF
402
R5651 1
100K
5%
1/16W
MF-LF
402
41
IN
SMC_FAN_0_CTL
41
Q5660
2N7002DW-X-G
G
2
SOT-363
4
518S0521
FAN_LT_PWM
41
=PP5V_S0_FAN_RT
=PP3V3_S0_FAN_RT
CRITICAL
J5660
R5660
M-RT-SM
5
47K
5%
1/16W
MF-LF
402
y
r
R5665
OUT
SMC_FAN_1_TACH
47K
FAN_RT_TACH
5%
1/16W
MF-LF
402
R5661 1
78171-0004
M-RT-SM
5
47K
5%
1/16W
MF-LF
402
1
2
3
4
100K
5%
1/16W
MF-LF
402
IN
SMC_FAN_1_CTL
Q5660
2N7002DW-X-G
SOT-363
1
518S0521
FAN_RT_PWM
e
r
Fan Connectors
SYNC_MASTER=M98_MLB

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
56
123
KEYBOARD CONNECTOR
PSOC USB CONTROLLER
IC
PIN NAME
CURRENT
R_SNS
V_SNS
POWER
10UA
2.55 KOHM
0.0255 V
0.255E-6 W
0.204 V
16.32E-6 W
V+
3V3 LDO
VDD
60MA MAX
10 OHM
VOUT
60MA MAX
0.2 OHM
0.012 V
1.5 OHM
0.012 V
96E-6 W
0.021 V
294E-6 W
80UA
USB INTERFACES TO MLB

SPI HOST TO Z2
TRACKPAD PICK BUTTONS

KEYBOARD SCANNER
PSOC
VDD
18V BOOSTER
VIN
8MA (TYP)
0.6 V
14MA (MAX)
49
50
49
49
APN 518S0637
36E-3 W
NC
49 8
4MA (MAX)
4.7 OHM
0.0188 V
75.2E-6 W
49 7
49 7
49 7
49 7
50 7
50 7
50 7
50 7
50 7
50 7
50 7
50 7
50
50
43
44
45
46
47
48
49
50
51
52
53
54
55
U5701
CY8C24794
MLF
(SYM-VER2)
APN 337S2983
OMIT
15
CRITICAL
P1_7
P1_5
P1_3
18 P1_1
19 VSS
20 D+
21 D22 VDD
23
P7_7
24
P7_0
25
P1_0
26
P1_2
27
P1_4
28
P1_6
50 7
P2_3
2
P2_1
3
P4_7
4
P4_5
5
P4_3
6
P4_1
7
P3_7
8
P3_5
9 P3_3
10
P3_1
11
P5_7
12
P5_5
13
P5_3
14
P5_1
TPAD_DEBUG
CRITICAL
TEST POINTS ARE FOR ON BOARD PROGRAMMING
P2_2
P2_0
P4_6
P4_4
P4_2
P4_0
P3_6
P3_4
P3_2
P3_0
P5_6
P5_4
P5_2
P5_0
THRML
PAD
42
WS_KBD17 7 49
WS_KBD16N 49
WS_KBD15_C 49
WS_KBD14 7 49
WS_KBD13 7 49
WS_KBD12 7 49
WS_KBD11 7 49
WS_KBD10 7 49
WS_KBD9 7 49
WS_KBD8 7 49
WS_KBD7 7 49
WS_KBD1 7 49
WS_KBD2 7 49
WS_KBD3 7 49
41
40
39
38
37
36
35
34
33
32
31
30
29
49 7
49 7
APN 518S0430
J5702
R5714
FH19C-4S-0.5SH25
470
49
F-RT-SM1
NC
49 8
2
49 7
ISSP_SCLK_P1_1
49 7
ISSP_SDATA_P1_0
ISSP CLOCK
49
42 41 7
57
OUT
WS_KBD4
WS_KBD5
WS_KBD6
ISSP_SDATA_P1_0
7 49
49 8
C5725
=PP3V42_G3H_TPAD
0.1UF
7 49
m
il
7 49
Z2_CLKIN
=PP3V3_S3_TPAD
7 50
49 7
WS_LEFT_SHIFT_KBD
TC7SZ08AFEAPE
SOT665
WS_LEFT_SHIFT_KEY 49
U5725 Y
20%
10V
CERM
402
CRITICAL
TP_P7_7
C5726
ISSP SCLK/I2C SCL
27
26
25
24
23
22
21
20
19
18
17
16
15
14
7 WS_KBD16_NUM
13
WS_KBD17
7 WS_KBD18
7 WS_KBD19
7 WS_KBD20
7 WS_KBD21
7 WS_KBD22
7 WS_KBD23
7 WS_KBD_ONOFF_L
49 7
49
49
49
49
49
49
1K
20%
10V
CERM
402
49 8
=PP3V42_G3H_TPAD
49 7
WS_LEFT_SHIFT_KBD
49 7
WS_LEFT_OPTION_KBD
49 7
WS_CONTROL_KBD
12
11
10
9
8
7
6
5
4
3
2
1
NC
PLACEMENT_NOTE=NEAR J5713
7 49
49 8
ISSP_SCLK_P1_1
C5710
28
7 WS_KBD15_CAP
R5710
SMC_ONOFF_L
TP_PSOC_P1_3
49 7
0.1UF
ISSP SDATA/I2C SDA
49 7
49 7
5%
1/16W
MF-LF
402
WS_KBD16N
1%
1/16W
MF-LF
402
ISOLATION CIRCUIT
TP_PSOC_SDA
10K
TP_PSOC_SCL
R5715
ISSP DATA
NC
49 7
1%
1/16W
MF-LF
402
=PP3V3_S3_TPAD
WS_KBD15_C
49 7
a
n
i
17
50 7
WS_CONTROL_KEY
Z2_KEY_ACT_L
Z2_BOOT_CFG1
TP_P4_5
Z2_DEBUG3
Z2_RESET
PSOC_MISO
PSOC_F_CS_L
PSOC_MOSI
PSOC_SCLK
Z2_MISO
Z2_CS_L
Z2_MOSI
Z2_SCLK
16
49
P2_5
P2_7
P0_1
P0_3
P0_5
P0_7
VSS
VDD
P0_6
P0_4
P0_2
P0_0
P2_6
P2_4
56
49 7
PSOC PROGRAMMING CONNECTOR
30
WS_KBD1
WS_KBD2
WS_KBD3
WS_KBD4
WS_KBD5
WS_KBD6
WS_KBD7
WS_KBD8
WS_KBD9
WS_KBD10
WS_KBD11
WS_KBD12
WS_KBD13
WS_KBD14
y
r
49 7
49 7
PICKB_L
BUTTON_DISABLE
Z2_HOST_INTN
WS_LEFT_SHIFT_KEY
WS_LEFT_OPTION_KEY
=PP3V3_S3_TPAD
29
49 7
49
32
0.72E-3 W
49
49
49
49
J5713
WS_KBD23
WS_KBD22
WS_KBD21
WS_KBD20
WS_KBD19
WS_KBD18
50 7
49
49
PP3V3_S3_PSOC
CRITICAL
TMP102
31
F-RT-SM
FF14-30A-R11B-B-3H
SMC_MANUAL_RESET LOGIC
49 8
=PP3V42_G3H_TPAD
1
C5758
0.1UF
10%
16V
2 X7R-CERM
402
0.1UF
49 8
=PP3V42_G3H_TPAD
USB_TPAD_P
91 20
24
49 8
USB_TPAD_R_P
PP3V3_S3_PSOC
5%
1/16W
MF-LF
402
e
r
R5701
DIFFERENTIAL_PAIR=USB2_TPAD
49
49 7
NET_SPACING_TYPE=USB
NET_PHYSICAL_TYPE=USB_90D
TO MLB CONNECTOR
R5702
USB_TPAD_N
91 20
24
5%
1/16W
MF-LF
402
USB_TPAD_R_N
NET_SPACING_TYPE=USB
NET_PHYSICAL_TYPE=USB_90D
CLOSE TO U5701
CLOSE TO U5701
VDD PIN 49
P
R5704
49
PP3V3_S3_PSOC
C5701
C5702
C5703
C5704
C5705
4.7UF
100PF
0.1UF
100PF
0.1UF
20%
6.3V
X5R
603
5%
50V
CERM
402
10%
16V
X7R-CERM
402
5%
50V
CERM
402
10%
16V
X7R-CERM
402
TC7SZ08AFEAPE
SOT665
WS_LEFT_OPTION_KEY
U5726 Y
C5706
1.5
5%
1/16W
MF-LF
402
49 8
49 7
APN 311S0406
CRITICAL
5
49 7
49
49 7
49 7
WS_LEFT_SHIFT_KBD
WS_LEFT_OPTION_KBD
WS_CONTROL_KBD
1 A
3 B
6
=PP3V3_S3_TPAD
WS_CONTROL_KBD
0.1UF
CRITICAL
TC7SZ08AFEAPE
SOT665
U5727 Y
5%
1/16W
MF-LF
2 402
20%
10V
CERM
402
WS_CONTROL_KEY
R5769
33K
SN74LVC1G10
SC70
42
U5703 Y
SMC_TPAD_RST_L
C5727
=PP3V42_G3H_TPAD
PLACE C5704, C5705 & C5706
VDD PIN 22
WS_LEFT_OPTION_KBD
49 8
U5701 CHIP DECOUPLING

PLACE C5701, C5702 & C5703
=PP3V3_S3_TPAD
20%
10V
CERM
402
CRITICAL
R5770
33K
1/16W
MF-LF
2 402
R5771
33K
5%
5%
1/16W
MF-LF
402
49
TPAD BUTTONS DISABLE
=PP3V3_S3_TPAD
49
BUTTON_DISABLE
8 49
PLACE THESE COMPONENTS CLOSE TO J5800

THIS ASSUMES THERES A PP3V42_G3H PULL UP ON MLB
4.7UF
Q5701
20%
6.3V
2 X5R
SSM3K15FV
603
SOD-VESM-HF
WELLSPRING 1
D 3
SYNC_MASTER=YMA_K20
1
SMC_LID
42 41 40
IN
S 2
THE TPAD BUTTONS WILL BE DISABLE

WHEN THE LID IS CLOSED
LID OPEN => SMC_LID_LC ~ 3.42V
LID CLOSE => SMC_LID_LC < 0.50V

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
57
123
BOOSTER +18.5VDC FOR SENSORS
BOOSTER DESIGN CONSIDERATION:

- POWER CONSUMPTION
- DROOP LINE REGULATION
- RIPPLE TO MEET ERS
- 100-300 KHZ CLEAN SPECTRUM
- STARTUP TIME LESS THAN 2MS
- R5812,R5813,C5818 MODIFIED
D
APN 152S0504
PP5V_S3_TPAD_F
50
L5801
D5802
5%
1/16W
MF-LF
402
BOOST_SW
B0520WSXG
SWITCH_NODE=TRUE
1
1
C5818
39PF
APN 353S1401
NO STUFF
CRITICAL
PP5V_S3_TPAD_F
TPAD_GND_F
DO
50
THRML
PAD
7 50
R5801
J5800
0.50MM
0.20MM
TPAD_GND_F
a
n
i
50 7
7 50
C5816
C5817
0.1UF
2.2UF
10%
16V
X7R-CERM
402
10%
16V
X5R
603
SW
Z2_CS_L
49 7 Z2_DEBUG3
49 Z2_MOSI
49 7 Z2_MISO
49 Z2_SCLK
50 7 Z2_BOOST_EN
49 Z2_HOST_INTN
Z2_BOOT_CFG1
49 7
Z2_CLKIN
49 7
R5811
100K
1%
1/16W
MF-LF
402
TPAD_GND_F
PLACEMENT_NOTE=under L5800 on top side
3V3 LDO FOR IPD
m
il
R5873
10
PP5V_S3_VR
1%
1/16W
MF-LF
402
50 7
CRITICAL
2 X5R
603
To detect Keyboard backlight, SMC will

tristate SMC_SYS_KBDLED:
LOW = keyboard backlight present
1%
0.2
C5838
10%
PP3V3_S3_LDO_R
VOUT
GND
0.1UF
16V
X7R-CERM
402
IN
BOM OPTION: KBDLED_YES
R5853 ALWAYS PRESENT
0.50MM
0.20MM
10
12
11
14
13
16
15
18
17
20
19
22
21
0.50MM
Z2_KEY_ACT_L
Z2_RESET
PSOC_F_CS_L
PICKB_L
PSOC_MISO
PSOC_MOSI
PSOC_SCLK
=I2C_TPAD_SDA
=I2C_TPAD_SCL
PP18V5_S3
7 49
7 49
44
44
7 50
0.20MM
4.7UF
20%
6.3V
X5R
603
50 7 TPAD_GND_F
Keyboard LED Driver
R5853
L5850
J5815 pin 1 is grounded

CRITICAL
on keyboard backlight flex
KBDLED_SW
J5815
SWITCH_NODE=TRUE
1098AS-SM
C5850
1UF
10%
2 16V
X5R
603
HF APN 152s0898
10UH-0.58A-0.35OHM
470K
5%
1/16W
MF-LF
402
CRITICAL
=PPVIN_S0_KBDLED
SMC_SYS_KBDLED
FF18-4A-R11AD-B-3H
F-RT-SM
VIN
50 7
1
2
SW
LED
CTRL
CRITICAL
R5854 1
R5852 1
4.7K
10K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
U5850
NO STUFF
7 KBDLED_ANODE
WELLSPRING 2
APN 518S0691
R5855
SYNC_MASTER=K20_MLB
10
LT3491
1%
DFN
1/16W
MF-LF
CAP

KBDLED_CAP

1
PAD
KBD BACKLIGHT CONNECTOR
402
C5855
1UF
2
10%
35V
X5R
603
SIZE
DRAWING NUMBER
50 7
APPLE INC.
REV.
051-7656
SCALE
SHT
NONE
7 49
VOLTAGE=3.3V
THRML
7 49
7 49
GND
7 49
7 49
C5854
41
HIGH= keyboard backlight not present
=PP3V3_S0_TPAD
CE
50 7
PP3V3_S3_LDO
R5836
10%
16V
MM3243DRRE
MLF
2.2UF
VDD
VR5802
e
r
C5853
402
M-ST-SM
APN 353S1364
PP3V3_S3_LDO
VOLTAGE=3.3V
1/6W
MF
402-HF
R5813
71.5K
MF-LF
50 7
PP5V_S3_TPAD_F
10%
25V
X5R
603-1
1/16W
50
C5819
1%
5%
1/10W
MF-LF
603
CRITICAL
55560-0228
1UF
BOOST_FB
Z2_BOOST_EN
CRITICAL
VOLTAGE=0V
CTRL
7 PGND
QFN
FB
0.1UF
2
5%
50V
CERM
402
TPS61045
VOLTAGE=5V
6 GND
U5805
L5800
C5800
20%
10V
CERM
402
APN 516S0689
R5812
1M
SYM_VER-1
VOLTAGE=18.5V
49 7
0.01H-0.3A-80V
SM-HF
y
r
PP18V5_S3
7 50
1%
1/16W
MF-LF
2 402
VIN
=PP5V_S3_TPAD
402
PP5V_S3_BOOSTER
0
1
5%
1/16W
MF-LF
APN 371S0313
5%
1/10W
MF-LF
603
PP18V5_S3_SW
VOLTAGE=18.5V
VLF3010AT-SM-HF
0.50MM
0.20MM
R5806
SOD-323
INPUT_SW
R5805
R5800
IPD FLEX CONNECTOR
CRITICAL
3.3UH-870MA
PLACEMENT_NOTE=under L5800 on top side
31
OF
58
123
Digital SMS
y
r
Pull-up required if SMS_INT_L not used.
=PP3V3_S3_SMS
51 8
ENG_DIGSMS
ENG_DIGSMS
=PP3V3_S5_SMC
9
42 41 8
VDD
1
R5932
44
10K
5%
1/16W
MF-LF
2 402
42
OUT
=I2C_SMS_SCL
6 SCK
VDDIO
11 NC
7 SDO
PROD_DIGSMS
44
=I2C_SMS_SDA
8 SDI
SMS_INT_L
NC
LGA
CRITICAL
RESERVED
5 CSB
R5931
5%
1/16W
MF-LF
2 402
a
n
i
10 NC
GND
ENG_DIGSMS
ENG_DIGSMS
Stuff R5931 AND NoStuff R5932 to use U5930

NoStuff R5931 AND Stuff R5932 if U5930 is not used
12 NC
10K
10%
16V
CERM-X5R
402
10%
16V
X5R
402
1 NC
4 INT
C5932
0.1UF
0.022UF
U5930
273141043
C5931
m
il
Desired orientation when

placed on board top-side:
+Y
+X
Front of system
+Z (up)
Circle indicates pin 1 location when placed

in correct orientation
Analog SMS
e
r
R5921 PULLS UP SMS_PWRDN TO TURN OFF SMS WHEN PIN IS NOT BEING DRIVEN BY SMC
14
=PP3V3_S3_SMS
R59211
VDD
10K
U5920
5%
1/16W
MF-LF
402 2
41
IN
SMS_ONOFF_L
AP344ALH
SMS_PWRDN
MAKE_BASE=TRUE
SMS_SELFTEST
VOUTZ 8
R5922
10K
NC
NC
NC
3 NC
6 NC
9 NC
C5922
0.1UF
C5926
10UF
10%
16V
2 X5R
402
OUT
41
SMS_Y_AXIS
OUT
41
OUT
41
SMS_Z_AXIS
NC 11 NC
NC 13 NC
NC 16 NC
GND
C5923
0.01UF
10%
16V
2 CERM
402
C5924
0.01UF
10%
16V
2 CERM
402
Desired orientation when

placed on board top-side:
20%
4V
X5R
603
SMS_X_AXIS
15 RES
4 RES
NC
5%
1/16W
MF-LF
402
2
LGA
1 FS
VOUTX 12
5 PD CRITICAL
VOUTY 10
2 ST
51 8
C5925
+Y
Front of system
+X
+Z (up)
Circle indicates pin 1 location when placed

in correct orientation
0.01UF
10%
16V
2 CERM
402
Sudden Motion Sensor (SMS)

SYNC_MASTER=YWU_K20

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
59
123
43 8
a
n
i
=PP3V3_S5_ROM
10K
R6150
43
IN
SPI_CLK_MUX
PLACEMENT_NOTE=PLACE CLOSE TO U6100

43
IN
SPI_MLB_CS_L
5%
1/16W
MF-LF
402 2
R6100
R6101
3.3K
5%
1/16W
MF-LF
402 2
3.3K
5%
1/16W
MF-LF
2 402
C6100
NO STUFF
R6190
20%
10V
CERM
402
CRITICAL
VCC
0.1UF
U6100
32MBIT
R6152
SOP
91
SPI_CLK
5%
1/16W
MF-LF
402
SCLK
SI/SIO0
MX25L3205DM2I-12G
1
SPI_WP_L
SPI_HOLD_L
3
7
CE*
WP*/ACC
HOLD*
SPI_MOSI
91
SPI_MISO_R
SO/SIO1
NO STUFF
m
il
R6191
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
SPI_MOSI_MUX
43
SPI_MISO_MUX
IN
OUT
43
10K
5%
1/16W
MF-LF
2 402
e
r
MCP79 SPI Frequency Select

Frequency
31 MHz
42 MHz
25 MHz
1 MHz
SPI_MOSI
SPI_CLK
25MHz is selected with R5190 and R5191

Any of the 4 frequencies can be selected
with R6190, R6191, R5190 and R5191
91
R6105
OMIT
GND
y
r
SPI ROM
SYNC_MASTER=M98_MLB

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
61
123
AUDIO CODEC
L6202
APPLE P/N 353S1527
FERR-220-OHM
1
2
0402
PP4V6_AUDIO_ANALOG
53 54 58
L6201
VOLTAGE=3.3V
FERR-220-OHM
1
2
0402
0.001UF
10%
50V
CERM
402
10%
50V
CERM
402
HDA_BITCLK
HDA_SYNC
HDA_SDOUT
R6204
91 21
10
22
OUT HDA_SDIN0
CODEC_SDATA_IN
5%
1/16W
MF-LF
402
IN
SDATA_OUT
SDATA_IN
U6200
LQFP
33
REV B3
AUD_GPIO_1
AUD_GPIO_0_R
5%
1/16W
MF-LF
402
GPIO0/DMIC-CLK
GPIO1/DMIC-L
SENSE_A
SENSE_B
PORT-A-L
39
PORT-A-R
41
PORT-F-L
16
PORT-F-R
PORT-F-VREFO
17
PORT-C-L
24
PORT-C-R
55
OUT AUD_BI_PORT_D_L
35
PORT-D-L
PORT-A-VREFO/DCVOL
33
55
OUT AUD_BI_PORT_D_R
36
PORT-D-R
PORT-E-L
PORT-E-R
14
PORT-E-VREFO
PORT-B-VREFO
31
PORT-B-L
21
PORT-B-R
22
19
NO_TEST
20
CD-R
C
BEEP
HDA_RST_L
100K
NO_TEST
32
NO_TEST
PORT-G-L
PORT-G-R
43
NO_TEST
44
NO_TEST
NC_AUD_BI_PORT_G_L
NC_AUD_BI_PORT_G_R
PORT-H-L
45
NO_TEST
NC_AUD_BI_PORT_H_L
PORT-H-R
46
VREF
JDREF
27
NC
37
40
5%
1/16W
MF-LF
2 402
VOLTAGE=0V
e
r
AUDIO 4.6 V REGULATOR
APPLE P/N 353S1897
C6211
0.015UF
2
4V6_REG_BP
10%
25V
X7R
402
CRITICAL
L6200
55 9
PP5V_S3_AUDIO
VOLTAGE=5V
AUD_4V6_REG_IN
2
0402
R6220
58 57 53 8
=PP3V3_S0_AUDIO
1K
AUD_REG_SHDN_L
5%
1/16W
MF-LF
402
CRITICAL
C6210
0.1UF
10%
16V
X5R
402
XW6200
SM
1
R6221
10K
FERR-220-OHM
5%
1/16W
MF-LF
402
C6208
4.7UF
10%
10V
X5R 2
805
C6209
0.001UF
R6206
10%
50V
CERM
402
IN
OUT
OUTS
BP
GND
2
THRML
PAD
9
20.0K
1%
1/16W
MF-LF
2 402
AUD_VREF_PORT_B
AUD_BI_PORT_B_L
AUD_BI_PORT_B_R
AUD_BI_PORT_H_R
1
IN
54
IN
54
IN
58
IN
58
OUT
58
OUT
54
OUT
58
OUT
58
OUT
56
OUT
56
OUT
56
OUT
56
R6207
100K
5%
1/16W
MF-LF
2 402
C6222
C6221
10%
50V
CERM
402
MIKEY 3.3 V REGULATOR
APPLE P/N 353S1860
CRITICAL
U6202
TPS71733
PP4V6_AUDIO_ANALOG
6 IN
58 54 53
R6252
58 57 53 8
=PP3V3_S0_AUDIO
1K
C6250
C6251
0.1UF
0.1UF
10%
16V
X5R
402
10%
16V
X5R
402
PP4V6_AUDIO_ANALOG
53 54 58
VOLTAGE=4.6V
58 56 55 54 53
R6253
10K
SON
4 EN
MIKEY_REG_SHDN_L
4V6_REG_SENSE
58
10%
16V 2
TANT
SMA-HF1
58
IN
0.001UF
CRITICAL
5%
1/16W
MF-LF
402
57
IN
3.3UF
TDFN
SELA
SELB
AUD_BI_PORT_F_L
AUD_BI_PORT_F_R
AUD_VREF_PORT_F
AUD_VREF_PORT_A
AUD_BI_PORT_E_L
AUD_BI_PORT_E_R
AUD_CODEC_JDREF
NC_VRP
U6201
EN
IN
AUD_BI_PORT_A_L
AUD_BI_PORT_A_R
AUD_CODEC_VREF
MAX8902A
57
AUD_SPDIF_IN
AUD_SENSE_A
AUD_SENSE_B
NO_TEST
R6201
OUT
NC_AUD_VREF_PORT_C
NC_AUD_VREF_PORT_B2
29
GND_AUDIO_CODEC
y
r
53 54 55 56 58
AUD_SPDIF_OUT
NC_AUD_VREF_PORT_E
NO_TEST
28
NOSTUFF
58 56 55 54 53
33
a
n
i
15
m
il
10%
16V
X5R
402
20%
50V
CERM
402
5%
1/16W
MF-LF
402
PORT-C-VREFO
C6220
0.1UF
5%
1/16W
MF-LF
2 402
PORT-B-VREFO2
AVSS1
AVSS2
AUD_SPDIF_O
30
42
R6205
RESET*
26
11
DVSS
IN
BEEP
91 21
12
0.001UF
34
23
NO_TEST
C6207
13
OUT AUD_BI_PORT_C_R
CD-L
CD-GND
20%
6.3V 2
TANT
CASE-AL1
47
OUT AUD_BI_PORT_C_L
18
100UF
10%
50V
CERM
402
R6203
56
NO_TEST
C6205
0.001UF
48
56
NC_BAL_IN_L
NC_BAL_IN_COM
NC_BAL_IN_R
C6206
CRITICAL
R6250
1
GND_AUDIO_CODEC
SPDIFO
SPDIFI/EAPD/MIDI-I/DMIC-R
ALC885-VB3-GR
OUT AUD_GPIO_0
55
BCLK
SYNC
CRITICAL
1
20%
6.3V 2
TANT
CASE-AL1
C6204
100UF
38
0.001UF
CRITICAL
VOLTAGE=4.6V
C6203
25
IN
20%
4V
X5R
402
AVDD2
IN
91 21
C6201
AVDD1
91 21
4.7UF
20K
5%
1/16W
MF-LF
402
R6251
IN
AVDD_ADC_DAC
C6200
D
9
CODEC_DVDD
NOSTUFF
DVDD
=PP3V3_S0_AUDIO
DVDD_IO
58 57 53 8
OUT
NR/FB 3
GND
PP3V3_MIKEY_ANALOG
3V3_REG_FB
NC 5
CRITICAL
C6252
2 X5R
0.01UF
5%
1/16W
MF-LF
2 402
58
VOLTAGE=3.3V
10%
16V
CERM
402
C6253
1UF
10%
10V
402
GND_AUDIO_CODEC
XW6203
SM
CRITICAL
1
10%
16V
X5R-CERM 2
0805
C6213
10UF
C6212
0.1UF
10%
25V
X5R
402
AUDIO:CODEC
SYNC_MASTER=AUDIO_K20
GND_AUDIO_CODEC
53 54 55 56 58

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
62
123
y
r
Pseudo-Diff Line-In Filter

GAIN = -5.4 DB AV = 0.52
FC = 1.89 HZ
L6300
58 53
PP4V6_AUDIO_ANALOG
FERR-220-OHM
PP4V6_AUDIO_LINE_IN
a
n
i
0402
CRITICAL
C6310
R6310
3.3UF
57
IN
AUD_LI_INL
AUD_LI_INL_C
25.5K
1
R6312
13.3K
AUD_LI_INL_R
1%
1/16W
MF-LF
402
10%
16V
TANT
SMA-HF1
1%
1/16W
MF-LF
402
C6312
2.2UF
AUD_PORTA_L
R6302
CRITICAL
27.4K
C6301
1%
1/16W
MF-LF
402 2
CRITICAL
1
C6300
4.7UF
0.001UF
20%
6.3V
X5R-CERM
402
10%
50V
CERM
402
V+
10%
16V
X5R
603
10 CRITICAL
MAX4253EUB
UMAX-HF
9
CRITICAL
U6300
AUD_BI_PORT_A_L
OUT
53
V4
AUD_LIFILT_SHUTDOWN_L
CRITICAL
57
IN
C6311
VOLTAGE=0V
R6301
1
10
3.3UF
2
10%
16V
TANT
SMA-HF1
GND_AUDIO_CODEC
e
r
R6303 1
27.4K
1%
1/16W
MF-LF
402 2
CRITICAL
C6321
3.3UF
57
IN
AUD_LI_INR
10%
16V
TANT
SMA-HF1
AUD_LIFILT_LT_R
25.5K
1%
1/16W
MF-LF
402
CRITICAL
R6320
AUD_LIFILT_RT_R
25.5K
AUD_LIFILT_RT
1%
1/16W
MF-LF
402
R6321
AUD_LI_INR_C
25.5K
58
IN
53
R6313
AUD_LIFILT_LT
m
il
10%
16V
TANT
SMA-HF1
C6320
5%
1/16W
MF-LF
402
58 56 55 54 53
R6311
3.3UF
AUD_LI_GND
IN
AUD_LI_INR_R
1%
1/16W
MF-LF
402
13.3K
1%
1/16W
MF-LF
402
R6300
AUD_CODEC_INREF
13.3K
165
CRITICAL
1%
1/16W
MF-LF
402
C6303
CRITICAL
20%
2 6.3V
TANT
CASE-AL1
0.001UF
10%
50V
CERM
402
C6302
100UF
4
3
GND_AUDIO_CODEC
V-
V+
UMAX-HF
MAX4253EUB
10
C6322
CRITICAL
2.2UF
AUD_PORTA_R
13.3K
AUD_BI_PORT_A_R
OUT
53
10%
16V
X5R
603
R6323
1
53 54 55 56 58
U6300
2
AUD_VREF_PORT_A
1%
1/16W
MF-LF
402
R6322
CRITICAL
1%
1/16W
MF-LF
402
AUDIO: LINE IN

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
63
123
Headphone Amplifier (MAX9724A)

APN:353S1637
L6500
FERR-120-OHM-1.5A
53 9
PP5V_S3_AUDIO
y
r
PP5V_AUDIO_HPAMP_PVDD_F
VOLTAGE=5V
0402
CRITICAL
1
10%
16V
X5R-CERM 2
0805
C6500
10UF
C6501
0.001UF
12
10%
50V
CERM
402
55
IN
55
IN
AUD_HPAMP_INL_M
AUD_HPAMP_INR_M
6
8
VDD
CRITICAL
INL
INR
OUTL
OUTR
U6500
MAX9724A
AUD_HPAMP_OUTL
11
10
a
n
i
TQFN
L6501
C1P
C1N
SHDN*
SVSS
PVSS
13
AUD_HPAMP_MUTE_L
PGND
2
0402
SGND
AUD_GPIO_0
IN
THRM
PAD
53
FERR-1000-OHM
MAX9724_C1P
1
3
AUD_HPAMP_OUTR
C6504
10%
10V
X5R
402
10K
C6503
1UF
XW6500
1
VOLTAGE=0V
SM
10%
10V
X5R
402
1%
1/16W
MF-LF
402
CRITICAL
C6502
10UF
10%
16V
X5R-CERM 2
0805
R6524
2.21K
1%
1/16W
MF-LF
402
XW6501
55 57
OUT
55 57
SM
GND_AUDIO_HPAMP_PGND
2.21K
MAX9724_PVSS
CRITICAL
R6514 1
5%
1/16W
MF-LF
402 2
1UF
MAX9724_C1N
R6500
CRITICAL
OUT
AUD_LO_GND
VOLTAGE=0V
IN
57
58 56 54 53
GND_AUDIO_CODEC
m
il
1st Order DAC Filter
HP:3.52 HZ
LP:34 KHZ
VOLTAGE GAIN:1.53
e
r
CRITICAL
C6510
3.3UF
53
AUD_BI_PORT_D_L
IN
P
55
IN
10%
16V
TANT
SMA-HF1
R6510
AUD_CODEC_OUTL_C
13.7K
R6511
21K
1%
1/16W
MF-LF
402
AUD_HPAMP_OUTR
55 57
C6511
2
1
5%
25V
CERM
402
CRITICAL
C6521
220PF
2
1
5%
25V
CERM
402
CRITICAL
R6520
3.3UF
2
55 57
220PF
C6520
1
AUD_HPAMP_OUTL
CRITICAL
AUD_HPAMP_INR_M
AUD_BI_PORT_D_R
1%
1/16W
MF-LF
402
AUD_HPAMP_INL_M
55
53
AUD_CODEC_OUTR_C
13.7K
R6521
1%
1/16W
MF-LF
402
10%
16V
TANT
SMA-HF1
21K
AUDIO: HEADPHONE AMP
1%
1/16W
MF-LF
402

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
65
123
56 9
53
L6610
CRITICAL
FERR-1000-OHM
0.01UF
AUD_BI_PORT_C_L
IN
AUD_SPKRAMP_INL1_L
C6612 1
1UF
MAX9705L1_PIN
0.01UF
L6601
1
AUD_VREF_PORT_B
20%
6.3V 2
TANT
CASE-AL1
5%
1/16W
MF-LF
402
56
56 9
NOSTUFF
33
SPKRAMP_SYNC1
C6623
CRITICAL
0.082UF
2
AUD_SPKRAMP_INL2_L 1
10%
10V
X5R 2
402
MAX9705L2_PIN
MAX9705L2_NIN
0.082UF
1
1
VDD
1UF
C6624
GND_AUDIO_CODEC
R6603
C6625 1
CRITICAL
10 CRITICAL
PVDD
U6620
C6622 1
CRITICAL
1
20%
6.3V 2
TANT
CASE-AL1
C6621
OUT-
8
9
SYNC
OUT+
10%
50V
CERM
402
5 SHDN*
SPKRAMP_L2_OUT_P
SPKRAMP_L2_OUT_N
SPKRAMP_SYNC1
NOSTUFF
56
R6604
THRML
33
GND PGND PAD

7
4
11
AUD_SPKRAMP_SHUTDOWN_L
7 56 57 96
SPKRAMP_SYNC2
56 9
53
PP5V_S3_AUDIO_AMP
AUD_BI_PORT_C_R
IN
L6630
CRITICAL
FERR-1000-OHM
0.01UF
AUD_SPKRAMP_INR1_L
10%
10V 2
X5R
402
C6634
2
10%
16V
CERM
402
AUD_BI_PORT_B_R
e
r
CRITICAL
C6643
0.082UF
AUD_SPKRAMP_INR2_L
10%
16V
CERM-X7R
402
CRITICAL
C6644
0.082UF
1
GND_AUDIO_CODEC
10%
16V
CERM-X7R
402
56
56 9
PP5V_S3_AUDIO_AMP
CRITICAL
L6650
C6653
FERR-1000-OHM
53
IN
AUD_BI_PORT_H_R
0.082UF
AUD_SPKRAMP_INC_R
0402
10%
16V
CERM-X7R
402
CRITICAL
C6654
0.082UF
58 56 55 54 53
GND_AUDIO_CODEC
C6645
1
VDD
1UF
10%
10V 2
X5R
402
CRITICAL
0.001UF
100UF
5%
1/16W
MF-LF
2 402
20%
6.3V 2
TANT
CASE-AL1
C6631
10%
50V
CERM
402
SPKRAMP_SYNC2
56
CRITICAL
R6607
U6640
C6642 1
100UF
5%
1/16W
MF-LF
2 402
20%
6.3V 2
TANT
CASE-AL1
2 IN+
3 IN-
5 SHDN*
OUT+
OUT-
SYNC
56
33
5%
1/16W
MF-LF
2 402
7 56 57 96
7 56 57 96
SPKRAMP_LFE_OUT_P
7 56 57 96
R6650
0
PLACE CLOSE TO U6640 PIN 9

5%
1/16W
MF-LF
402 2
SPKRAMP_LFE_OUT_N
56
100UF
5%
1/16W
MF-LF
2 402
20%
6.3V 2
TANT
CASE-AL1
CRITICAL
1
C6651
AUDIO:SPEAKER AMP
0.001UF
10%
50V
2 CERM
402
MAX9705
SPKRAMP_LFE_OUT_P
SPKRAMP_LFE_OUT_N
8
9
6
SPKRAMP_SYNC4

7 56 57 96
7 56 57 96

56

THRML
SIZE
APPLE INC.
DRAWING NUMBER
REV.
051-7656
SCALE
SHT
NONE
OUT
GND PGND PAD

7
4
11
7 56 57 96
SIGNAL_MODEL=EMPTY
OUT
TDFN1
7 56 57 96
PLACE C6651/C6652 CLOSE TO PVDD PIN
PVDD
SYNC
OUT
NOSTUFF
SPKRAMP_SYNC4
U6650
5 SHDN*
7 56 57 96
5%
1/16W
MF-LF
402 2
SPKRAMP_R2_OUT_N
R6608
10 CRITICAL
OUT+
OUT-
OUT
SIGNAL_MODEL=EMPTY
NOSTUFF
R6609 C6652 1
2 IN+
3 IN-
7 56 57 96
0
5%
1/16W
MF-LF
402 2
R66401
NOSTUFF
CRITICAL
MAX9705C_PIN
MAX9705C_NIN
OUT
R6630
0.001UF
56
1
VDD
7 56 57 96
SPKRAMP_SYNC3
SPKRAMP_R2_OUT_P
SPKRAMP_R2_OUT_N
PLACE C6655 CLOSE TO VDD PIN
10%
10V
X5R 2
402
OUT
NOSTUFF
C6641
THRML
1UF
SIGNAL_MODEL=EMPTY
10%
50V
2 CERM
402
GND PGND PAD

7
4
11
C6655 1
CRITICAL
SPKRAMP_SYNC3
7 56 57 96
5%
1/16W
MF-LF
402 2
10 CRITICAL
PVDD
MAX9705
SPKRAMP_R2_OUT_P
5%
1/16W
MF-LF
2 402
OUT
R6620
7 56 57 96
R6606
33
7 56 57 96
7 56 57 96
NOSTUFF
56
OUT
NOSTUFF
SPKRAMP_R1_OUT_N
SPKRAMP_R1_OUT_P
SPKRAMP_R1_OUT_N
8
9
SPKRAMP_R1_OUT_P
TDFN1
MAX9705R2_PIN
MAX9705R2_NIN
10%
16V
CERM-X7R
402
56
C6632 1
0402
58 56 55 54 53
OUTSYNC
THRML
PP5V_S3_AUDIO_AMP
L6640
IN
OUT+
GND PGND PAD

4
7
11
FERR-1000-OHM
53
U6630
MAX9705
2 IN+
3 IN5 SHDN*
B
56 9
10 CRITICAL
PVDD
TDFN1
MAX9705R1_PIN
MAX9705R1_NIN
0.01UF
1
1
VDD
1UF
CRITICAL
GND_AUDIO_CODEC
R6605
C6635 1
10%
16V
CERM
402
56
m
il
CRITICAL
0402
58 56 55 54 53
C6633
SIGNAL_MODEL=EMPTY
7 56 57 96
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
402 2
SPKRAMP_L2_OUT_N
0.001UF
100UF
5%
1/16W
MF-LF
2 402
MAX9705
TDFN1
2 IN+
3 IN-
10%
16V
CERM-X7R
402
56
CRITICAL
10%
16V
CERM-X7R
402
58 56 55 54 53
a
n
i
SPKRAMP_L2_OUT_P
56
0402
PP5V_S3_AUDIO_AMP
AUD_BI_PORT_B_L
IN
5%
1/16W
MF-LF
402
11
2
L6620
53
7 56 57 96
7 56 57 96
R6602
FERR-1000-OHM
y
r
SPKRAMP_L1_OUT_N
SPKRAMP_L1_OUT_P
SPKRAMP_L1_OUT_N
100K
7 56 57 96
OUT
R6610
10%
50V
CERM
402
THRML
GND PGND PAD
R6600 1
7 56 57 96
8
9
OUTSYNC
OUT
NOSTUFF
0.001UF
OUT+
5 SHDN*
2
0402
10 CRITICAL
PVDD
C6611
MAX9705
TDFN1
2 IN+
3 IN-
MAX9705L1_NIN
10%
16V
CERM
402
FERR-1000-OHM
IN
SIGNAL_MODEL=EMPTY
SPKRAMP_L1_OUT_P
CRITICAL
100UF
U6610
10%
10V 2
X5R
402
C6614
1
1
VDD
C6615 1
CRITICAL
53
CRITICAL
10%
16V
CERM
402
GND_AUDIO_CODEC
SPEAKER CHECKPOINTS
C6613
0402
58 56 55 54 53
AMPLIFIERS (MAX9705)
353S1595
= 12 DB
L1/R1) = ~796 HZ
L2/R2/LFE) = ~97 HZ
PP5V_S3_AUDIO_AMP
4X MONO SPEAKER
APN:
GAIN
FC (SPEAKERS
FC (SPEAKERS
31
OF
66
123
MIC CONNECTOR
AUDIO JACK 1 LO/HP JACK, SPDIF TX
APN: 518S0520
AUD_SPDIF_OUT
IN
53
OUT
58
CRITICAL
J6780
78171-0003
L6703
R6713
0
AUD_CONNJ1_SLEEVE2
M-RT-SM
FERR-1000-OHM
1
AUD_CONNJ1_SLEEVE2_F
5%
1/16W
MF-LF
402
HS_MIC_HI
0402
58 7
OUT BI_MIC_LO
L6702
58 7
OUT BI_MIC_SHIELD
58 7
OUT BI_MIC_HI
FERR-1000-OHM
1
HS_MIC_LO
OUT
0402
58 57 53 8
=PP3V3_S0_AUDIO
L6701
CRITICAL
FERR-220-OHM-2.5A
R6711
APN: 514-0632
AUD_CONNJ1_SLEEVE
CRITICAL
J6700
F-RT-TH
AUD_CONNJ1_RING
AUD_CONNJ1_RING_F
AUD_CONNJ1_TIPDET
A - VIN
B - VCC
C - GND
8
9
AUD_CONNJ1_TIPDET_F
12
13
C6700
CRITICAL
C6701
0.1UF
2.2UF
10%
16V
X5R
402
20%
6.3V
CERM
402-LF
5%
1/16W
MF-LF
402
DZ6703
6.8V-100PF
6.8V-100PF
402
402
NOSTUFF
1
CRITICAL
CRITICAL
DZ6700
DZ6702
DZ6704
6.8V-100PF
6.8V-100PF
402
402
402
NOSTUFF
C6710
100PF
C6712
C6711
5%
1/16W
MF-LF
402
C6714
5%
2 50V
CERM
402
NOSTUFF
C6715
100PF
5%
50V
CERM 2
402
100PF
C6713
100PF
5%
2 50V
CERM
402
NOSTUFF
NOSTUFF
100PF
5%
2 50V
CERM
402
6.8V-100PF
10K
AUD_CONNJ1_SLEEVEDET_F
CRITICAL
DZ6701
CRITICAL
R6700
100PF
5%
50V
CERM 2
402
5%
50V
CERM 2
402
AUD_HPAMP_OUTL
m
il
AUDIO JACK 2 LINE IN JACK, SPDIF RX

=PP3V3_S0_AUDIO
R6749
AUD_J2_OPT_OUT
APN: 514-0633
10
5%
1/16W
MF-LF
402
CRITICAL
AUD_CONNJ2_SLEEVE
J6750
F-RT-TH
5
2
5%
1/16W
MF-LF
402
AUD_CONNJ2_RING
R6764
AUDIO
6
7
8
AUD_CONNJ2_TIP
OPERATING VOLTAGE 3.3
POF
9
SHIELD
PINS
R6762
SHELL
AUD_CONNJ2_TIPDET
1
3
A - VDD
B - GND
C - VOUT
5%
1/16W
MF-LF
402
SPDIF-RX-K20
10
11
AUD_CONNJ2_SLEEVEDET
12
1
C6750
0.1UF
2
10%
16V
X5R
402
1
CRITICAL
CRITICAL
DZ6752
DZ6754
6.8V-100PF
6.8V-100PF
402
402
CRITICAL
CRITICAL
DZ6753
DZ6755
6.8V-100PF
6.8V-100PF
402
402
5%
1/16W
MF-LF
402
R6766
R6768
AUD_CONNJ2_SLEEVE_F
AUD_CONNJ2_TIPDET_F
100PF
5%
50V
2 CERM
402
IN
96 56 7
IN
SPKRAMP_L2_OUT_P
SPKRAMP_L2_OUT_N
SPKRAMP_L1_OUT_P
SPKRAMP_L1_OUT_N
NOSTUFF
C6781
2
3
4
NOSTUFF
C6783
100PF
C6782
C6784
100PF
5%
50V
CERM 2
402
NOSTUFF
NOSTUFF
100PF
5%
50V
2 CERM
402
100PF
5%
50V
CERM 2
402
5%
50V
2 CERM
402
APN: 518S0672
96 56 7
IN
96 56 7
IN
96 56 7
IN
96 56 7
IN
96 56 7
IN
96 56 7
IN
CRITICAL
J6782
78171-6006
M-RT-SM
7
SPKRAMP_R2_OUT_P
SPKRAMP_R2_OUT_N
SPKRAMP_R1_OUT_P
SPKRAMP_R1_OUT_N
SPKRAMP_LFE_OUT_P
SPKRAMP_LFE_OUT_N
1
2
3
4
5
6
NOSTUFF
AUD_SPDIF_IN
OUT
53
C6787
NOSTUFF
1
100PF
M-RT-SM
5
NOSTUFF
C6785
NOSTUFF
1
100PF
5%
50V
CERM
402
AUD_J2_TIPDET_R
OUT
58
5%
50V
CERM
402
C6788
5%
50V
CERM
402
NOSTUFF
C6789
C6786
NOSTUFF
1
100PF
100PF
2
100PF
5%
50V
CERM 2
402
5%
50V
CERM
402
C6790
100PF
5%
50V
2 CERM
402
L6754
FERR-1000-OHM
AUD_CONNJ2_RING_F
AUD_LI_INR
BI
54
AUD_LI_INL
BI
54
0402
L6756
FERR-1000-OHM
AUD_CONNJ2_TIP_F
2
0402
L6758
XW6701
FERR-220-OHM
AUD_CONNJ2_SLEEVEDET_F
SM
AUD_J2_COM
AUD_LI_GND
54
0402
NOSTUFF
C6763
IN
96 56 7
78171-0004
0402
NOSTUFF
C6761
IN
96 56 7
CRITICAL
J6781
57
FERR-1000-OHM
5%
1/16W
MF-LF
402
96 56 7
58
L6752
NOSTUFF
OUT
0402
5%
1/16W
MF-LF
402
55
FERR-220-OHM
58
L6751
e
r
R6761
BI
AUD_J1_SLEEVEDET_R
GND_CHASSIS_AUDIO_JACK
58 57 53 8
OUT
a
n
i
0402
R6710
10
11
SHIELD
PINS
AUD_J1_TIPDET_R
L6706 CRITICAL
FERR-220-OHM
1
AUD_CONNJ1_TIP_F
5%
1/16W
MF-LF
402
AUD_CONNJ1_SLEEVEDET
SHELL
2
0402
OPERATING VOLTAGE 3.3
POF
y
r
55
L6705
BI
FERR-1000-OHM
R6716
AUD_CONNJ1_TIP
APN: 518S0521
AUD_HPAMP_OUTR
0402
5%
1/16W
MF-LF
402
55
SPEAKER CONNECTORS
3
4
AUDIO
OUT
CRITICAL
FERR-220-OHM
R6715
2
1
AUD_LO_GND
0603
L6704
5%
1/16W
MF-LF
402
5%
1/10W
MF-LF
603
R6714
SPDIF-TX-K20
AUD_CONNJ1_SLEEVE_F
58
100PF
C6765
100PF
5%
50V
2 CERM
402
5%
50V
CERM
402
NOSTUFF
C6762
C6764
100PF
1
100PF
5%
50V
CERM 2
402
5%
50V
CERM 2
402
AUDIO: JACKS
57

RETURN FOR HF NOISE

R6701
57
SIZE
DRAWING NUMBER
5%
1/16W
MF-LF
402
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
67
123
L6882
FERR-1000-OHM
53
CODEC OUTPUT SIGNAL PATHS

PIN COMPLEX
0X14 (20,D)
0X1A (26,C)
0X18 (24,B)
0X17 (23,H)
0x1E (SPDIF OUT)
MUTE CONTROL
GPIO_0
VREF_B (100%)
VREF_B (100%)
VREF_B (100%)
N/A
DET ASSIGNMENT
0X14 (20,D)
N/A
N/A
N/A
0X16 (22,G)
NOSTUFF
L6880
58 57 53 8
CONVERTER
0X08 (8)
0X0A (10)
0X07 (7)
0X07 (7)
PIN COMPLEX
0X15 (21,A)
0x1F (SPDIF IN)
0X19 (25,F)
0X1B (27,E)
VREF
VREF_A (50%)
N/A
VREF_F (100%)
MIKEY
IN
=I2C_MIKEY_SCL
CRITICAL
C6880 1
DET ASSIGNMENT
0X15 (21,A)
N/A
N/A
MIKEY
44
BI
19 9
58 53
OUT AUD_SENSE_A
58
PP3V3_S0_AUDIO_F
R6801
AUD_OUTJACK_INSERT_L
220K
5%
1/16W
MF-LF
2 402
AUD_I2C_INT_L
Q6800
SSM6N15FEAPE
Q6801
SOT563
58 57
IN
AUD_J1_TIPDET_R
47K
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
58 56 55 54 53
Q6801
SSM6N15FEAPE
SSM6N15FEAPE
SOT563
SOT563
220K
5%
1/16W
MF-LF
2 402
58 57
R6880
OUT AUD_BI_PORT_E_L
Q6800
C6802
6
58 57
OUT AUD_BI_PORT_E_R
m
il
AUD_J1_SLEEVEDET_R
58 56 55 54 53
10%
16V
CERM
402
PP4V6_AUDIO_ANALOG
e
r
PORT A DETECT (Line-in)

58 53
R6813
58
PP3V3_S0_AUDIO_F
5%
1/16W
MF-LF
2 402
39.2K
1%
1/16W
MF-LF
402 2
R6811
AUD_INJACK_INSERT_L
270K
5%
1/16W
MF-LF
402
SSM3K15FV
Q6803
AUD_J2_TIPDET_R
47K
AUD_J2_DET_RC
5%
1/16W
MF-LF
402
C6811
0.1UF
2
58 56 55 54 53
20%
CERM
10V
402
GND_AUDIO_CODEC
PLACE L6800/C6800 CLOSE TO Q6800/01/02
L6800
FERR-1000-OHM
58 57 53 8
=PP3V3_S0_AUDIO
P
S
PP3V3_S0_AUDIO_F
0402
1
C6800
58 56 55 54 53
SOT563
THM
CRITICAL
C6881
0.01UF
58 57
IN
AUD_J1_TIPDET_R
IN
AUD_VREF_PORT_F
GND_AUDIO_CODEC
Q6803
53 8
58 57
58 56 55 54 53
2.2K 2
C6885
2.2K
CRITICAL
HS_MIC_LO
IN
57
C6853
10UF
20%
16V
TANT-POLY
2012-LLP
L6850
FERR-1000-OHM
0.1UF
1
OUT AUD_BI_PORT_F_L
BI_MIC_HI_F
MAKE_BASE=TRUE
53
57
5%
1/16W
MF-LF
402
C6850
54
IN
R6850
1
CRITICAL
53
HS_MIC_HI
5%
1/16W
MF-LF
402
OUT AUD_BI_PORT_F_R
SM
GND_AUDIO_CODEC
R6852
100K
XW6850
58 56 55 54 53
BI_MIC_HI
IN
7 57
BI_MIC_LO
IN
7 57
BI_MIC_SHIELD
IN
7 57
0402
10%
25V
X5R
402
5%
1/16W
MF-LF
402
C6852
C6851
15PF
50V
402
5%
CERM
0.001UF
10%
CERM
50V
402
L6851
FERR-1000-OHM
1
BI_MIC_LO_F
0402
XW6851
SM
1
R6865
1
R6861
100K
TPDT_DEBOUNCE
1
C6861
TPDT_DEBOUNCE
AUD_IP_PERPH_DET_R
AUDIO: JACK TRANSLATORS
CRITICAL
0.1UF
10%
16V
2 X5R
402
5%
1/16W
MF-LF
2 402
4
VDD
5
TPS3801E18DCK
U6860
RST*
MR*
C6860
TPDT_DEBOUNCE
R6862
3
AUD_IP_PERPH_DET_DB 1
SC-70-1
GND
1
2
NOSTUFF
1
5%
1/16W
MF-LF
402
NOSTUFF
R6860
5%
1/16W
MF-LF
402
TPDT_BYPASS
TIPDET DEBOUNCE CIRCUIT
=PP3V3_S0_AUDIO
TPDT_DEBOUNCE
R6851
5%
1/16W
MF-LF
402
AUD_IP_PERIPHERAL_DET_R
R6863
R6864
AUD_IP_PERIPHERAL_DET
OUT

17
5%
1/16W
MF-LF
402

100K
5%
1/16W
MF-LF
2 402
SIZE
DRAWING NUMBER
D
APPLE INC.
REV.
051-7656
SCALE
SHT
NONE
5%
1/16W
MF-LF
2 402
GND_AUDIO_CODEC
GND_CHASSIS_AUDIO_MIC
0.1UF
2.2K
5%
1/16W
MF-LF
2 402
10%
2 16V
X5R
402
R6882
1K
10%
25V
2 X7R
402
BI_MIC_BIAS
SOT563
5%
1/16W
MF-LF
402
R6881
PORT F (BUILT-IN MIC)
SSM6N15FEAPE
0.0082UF
5%
50V
2 CERM
402
2.2K
5%
1/16W
MF-LF
2 402
OUT
100PF
53
100K
AUD_LIFILT_SHUTDOWN_L
C6884
15PF
5%
1/16W
MF-LF
2 402
R6855
R6815
C6887
5%
1/16W
MF-LF
402
10%
16V
X5R
402
5%
50V
2 CERM
402
20%
2 6.3V
TANT
603-HF
R6885
R6883
XW6800
SM
GND_AUDIO_CODEC
C6882
4.7UF
10%
25V
2 X7R
402
AUD_LIN_SHUTDOWN
58
0.1UF
2
SSM6N15FEAPE
SOD-VESM-HF
IN
NC
Q6802
R6812
57
R6814
100K
OUT AUD_SENSE_A
KEEP DET TRACE AS SHORT AS POSS
HS_MIC_HI_R
10%
16V
X7R-CERM
402
LINE_IN AMP SHUTDOWN CONTROL

54 53
10 HS_RX_BP
100K
SOT563
GND_AUDIO_CODEC
ENABLE
GND
BYPASS
0.1UF
AUD_J1_SLEEVEDET_INV
0.01UF
58 56 55 54 53
2 HS_SW_DET
MAKE_BASE=TRUE
SSM6N15FEAPE
HS_RST_L
1 HS_MIC_BIAS
DETECT
C6883
53
AUD_J1_SLEEVEDET_R
IN
5%
1/16W
MF-LF
2 402
10V
402
5%
1/16W
MF-LF
402
R6804
INT*
MICBIAS
a
n
i
NC
53
100K
GND_AUDIO_CODEC
R6893
HS_INT_L
R6884
0.1UF
PP3V3_S0_AUDIO_F
SDA
NOSTUFF
R6803
58
GND_AUDIO_CODEC
C6801
20%
CERM
HS_SDA
CRITICAL
SCL
AUD_PORTG_DET_L
NC
y
r
5%
1/16W
MF-LF
2 402
AUD_J1_DET_RC
5%
1/16W
MF-LF
402
58 56 55 54 53
10K
DRC
HS_SCL
100K
R6805
5.11K
U6800
CD3275
5%
1/16W
MF-LF
402
R6802
R6806
CRITICAL
AVDD
AUD_IPHS_SWITCH_EN
10%
2 50V
CERM
402
5%
1/16W
MF-LF
402
PORT G DETECT
(SPDIF DELEGATE)
AUD_PORTD_DET_L
IN
=I2C_MIKEY_SDA
C6886
0.001UF
20%
6.3V 2
X5R
603
R6891
R6892
OUT
10UF
5%
1/16W
MF-LF
402
OUT AUD_SENSE_B
PP3V3_S0_HS_RX
0402
21
53
R6890
5%
1/16W
MF-LF
402
PORT D DETECT (Line-out)
=PP3V3_S0_AUDIO
CODEC INPUT SIGNAL PATHS

MIXER(INPUT)
0X23 (35)
N/A
0X24 (36)
0X24 (36)
VOLTAGE=3.3V
FERR-1000-OHM
MIXER(OUTPUT)
0X0C (12)
0X0F (15)
0X0D (13)
0X0E (14)
N/A
11
CONVERTER
0X02 (2)
0X05 (5)
0X03 (3)
0X04 (4)
0X06 (6)
44
FUNCTION
LINE IN
SPDIF IN
MIC
HEADSET MIC
2
0402
VOLUME
0X0C (12)
0X0F (15)
0X0D (13)
0X0E (14)
N/A
PP3V3_MIKEY_ANALOG
FUNCTION
HP/LINE OUT
SPEAKERS L1/R1
SPEAKERS L2/R2
SPEAKER LFE
SPDIF OUT
31
OF
68
123
MagSafe DC Power Jack

CRITICAL
CRITICAL
6AMP-24V
GND
GND
SIG
C6905
y
r
Q6910
0.01UF
BSS84V
1-Wire OverVoltage Protection
20%
PLACEMENT_NOTE=Place near L6900
50V
CERM
603
SOT-563
Vgs(max) = 20V
PP18V5_DCIN_ONEWIRE
MIN_LINE_WIDTH=0.25mm
VOLTAGE=18.5V
3
C6915
R6917
<Ra>
R6913 1
If ADAPTER_SENSE > Vth

then turn off FET
R6915 1
100K
LM397
V+
<Vth>
<Rb>
R6914 1
ONEWIRE_ESD
Q6915
270K
5%
1/16W
MF-LF
402
SOT563
R6916 1
R6918 1
CRITICAL
SSM6N15FEAPE
SOT23-5-HF
4
ONEWIRE_OVERVOLT
V-
100K
0.001UF
5%
1/16W
MF-LF
402 2
Vth = Vdcin * (Rb / (Ra + Rb))

Vth = Vdcin / 2
10%
50V
CERM
402
Voltage divider from DCIN ensures Q6901

Vgs is met when SYS_ONEWIRE is high or low.
Q6920 used as bilateral switch to ensure
SYS_ONEWIRE doesnt drive unpowered U6990
CRITICAL
R6920
24.3K
R6911 1
m
il
SSM6N15FEAPE
SOT563
470K
5%
1/16W
MF-LF
402
Vgs = 11.750V @ 20V DCIN

Vgs = 7.63V @ 13V DCIN
R6912 1
330K
5%
1/16W
MF-LF
402
ONEWIRE_PWR_EN_L
Q6915
SSM6N15FEAPE
SOT563
R6910
SMC_BC_ACOK_RC
C6910
0.001UF
10%
50V
CERM
402
CRITICAL
1K
Q6920
1%
1/16W
MF-LF
2 402
C6917
270K
The chassis ground will otherwise float and can

send transients onto ADAPTER_SENSE when AC is
connected.
ONEWIRE_PWR_EN_L_DIV
a
n
i
U6915
ONEWIRE_DCIN_DIV
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402 2
CRITICAL
2
5
ADAPTER_SENSE
ONEWIRE_EN
270K
5%
1/16W
MF-LF
402
CRITICAL
5%
1/16W
MF-LF
402
D6900
RCLAMP2402B
10%
25V
X5R
402
SMC_BC_ACOK
IN
41 42
5%
1/16W
MF-LF
402
Q6920
SYS_ONEWIRE_BILAT
SC-75
270K
0.1UF
8 59
CRITICAL
1206-1
SSM6N15FEAPE
SOT563
PWR
=PP18V5_DCIN_CONN
SYS_ONEWIRE
PWR
PP18V5_DCIN_FUSE
MIN_LINE_WIDTH=1mm
VOLTAGE=18.5V
M-RT-SM
78048-0573
Q6910 restricts system load to 10K-70K window until

adapter detects system and enables 16.5V output.
F6905
J6900
BI
41 42
3.425V "G3Hot" Supply
CRITICAL
Supply needs to guarantee 3.31V delivered to SMC VRef generator
D6905
BAT30CWFILM
VOLTAGE=18.5V
1%
1/3W
MF
805
XW6953
SHORT-1206
Battery Connector
CRITICAL
J6950
GS731301047E7H
14
XW6950
SHORT-1206
1
2
PPVBAT_G3H_CONN_F
VOLTAGE=8.6V
3
4
5
C6950
0.001UF
=SMBUS_BATT_SCL
=SMBUS_BATT_SDA
SMC_BS_ALRT_L
7
8
44 59
2
44 59
7 41 42
11
2
CRITICAL
1
10%
50V
CERM
402
402
CERM
50V
10%
PPVBAT_G3H_CONN
D6950
PPVIN_G3H_P3V42G3H
VOLTAGE=18.5V
C6990
C6994
VIN
10UF
10%
25V
X5R
805
P3V42G3H_BOOST
BOOST
20%
6.3V
X5R
402
U6990
LTC3470A
DFN
8 SHDN*
SW 4
CRITICAL BIAS 2
NC
0.22UF
7 NC
CRITICAL
L6995
33UH
=PP3V42_G3H_REG
P3V42G3H_SW
CDPH4D19FHF-SM
200mA max output
FB 1
GND
Vout = 3.425
SWITCH_NODE=TRUE
<Ra>
THRM
PAD
C6995
5%
50V
CERM
402
(Switcher limit)
R6995
348K
22pF
2
2
1%
1/16W
MF-LF
402
C6999
22UF
P3V42G3H_FB
<Rb>
1
20%
6.3V
X5R-CERM
603
R6996
200K
BIL Connector
2
1%
1/16W
MF-LF
402
CRITICAL
60
Vout = 1.25V * (1 + Ra / Rb)
J6995
FF18-5A-R11A-3H
F-RT-SM-HF
1
=PP3V42_G3H_BATT
=SMBUS_BATT_SDA
=SMBUS_BATT_SCL
SMC_BIL_BUTTON_DB_L
0.001UF
C6951
GND_BATT_CHGND
9
10
12
13
XW6951
SHORT-1206
1
M-RT-SM
BI
44 59
BI
44 59
OUT
9 59 60
C6954
518S0599
C6953
C6952
0.001UF
47PF
47PF
10%
50V
CERM
402
5%
50V
CERM
402
5%
50V
CERM
402
DC-In & Battery Connectors
7 42
SYNC_MASTER=RXU_K20
0.001UF
C6955
10%
50V
CERM
402

RCLAMP2402B
SC-75
15

3
=PPVBAT_G3H_P3V42G3H
e
r
XW6952
SHORT-1206
SOT-323
1
PPDCIN_S5_P3V42G3H
47
59 8
R6905
=PP18V5_DCIN_CONN
GND_BATT_CHGND
9 59 60
SIZE
518S0694
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
69
123
FROM ADAPTER
8
Inrush Limiter
=PPDCIN_S5_CHGR
Reverse-Current Protection
PPDCIN_S5_CHGR_R
C7060
100K
CHGR_SGATE_DIV
5%
1/16W
MF-LF
402 2
U7070
1M
5%
1/16W
MF-LF
2 402
GND
y
r
3
SGATE_P0V1_VREF
Q7074
SSM6N15FEAPE
SOT563
R7071
Q7074
SSM6N15FEAPE
1.82K
1%
1/16W
MF-LF
402 2
(CHGR_AGATE)
a
n
i
VREF = 3.2V, < 300uA

CHGR_ACIN
9.31K
1%
1/16W
MF-LF
402 2
R7015
94
56.2K
94
1%
1/16W
MF-LF
2 402
NC
4
3
CHGR_ICOMP
CHGR_VCOMP
CHGR_VNEG
CHGR_CSO_P
CHGR_CSO_N
5
7
8
18
17
ICOMP
VCOMP
VNEG
CSOP
CSON
SIGNAL_MODEL=EMPTY
C7050
0.1uF
C7015
10%
16V
X5R
402
29
CHGR_VCOMP_R
1
OMIT
CHGR_VNEG_R
1
C7016
470PF
10%
50V
CERM
402
C7042
C7000
0.033UF
2
1UF
10%
16V
X5R
402
10%
10V
X5R
402
PART NUMBER
QTY
DESCRIPTION
94
23
21
(OD) TRKL*
20V/V AMON
32V/V BMON
(OD) ACOK
13
VOLTAGE=18.5V
10%
25V
X5R
402
CRITICAL
GND_CHGR_AGND
Q7030
m
il
4
RJK0305DPB
CHGR_LGATE
TP_CHGR_TRKL
CHGR_AMON
CHGR_BMON
=CHGR_ACOK
15
14
152S0542
RJK0305DPB
LFPAK-HF
152S0542
CRITICAL
L7030
1UF
10%
25V
X5R
603-1
10%
25V
X5R
603-1
OUT
OUT
45
60
45
42
Q7035
NO STUFF
1
LFPAK-HF
CRITICAL
Q7036
LFPAK-HF
(CHGR_CSO_P)
(CHGR_CSO_N)
C7005
0.01UF
0.1UF
96 45
10
96
45
CRITICAL
HAT1127H
HAT1127H
LFPAK-SM
LFPAK-SM
Q7058
Q7057
2
1
VOLTAGE=12.6V
C7099
10%
50V
X7R
402
CRITICAL
R7050
CRITICAL
0.005
CRITICAL
HAT1127H
HAT1127H
1%
1W
MF
0612
LFPAK-SM
LFPAK-SM
PPVBAT_G3H_CHGR_R
VOLTAGE=12.6V
C7055
C7057
10%
16V
CERM
402
1UF
10%
25V
X5R
603-1
Q7056
Q7055
CHGR_CSO_R_P
5%
1/16W
MF-LF
402
10%
50V
X7R
402
CRITICAL
CHGR_CSO_R_N
0.001UF
VOLTAGE=12.6V
VOLTAGE=12.6V
R7052
C7041
PPVBAT_G3H_CHGR_REG
PPVBAT_G3H_FET
VOLTAGE=12.6V
PPVBAT_G3H_CONN
2
60
C7056
10%
16V
X5R
402
5%
MF-LF
402
1/16W
BATT_POS_GATE
20K
C7026
10%
50V
CERM
402
59 9
GND_BATT_CHGND
PBus Supply & Battery Charger

SYNC_MASTER=RXU_K20
M99
1.
2.
3.
4.
5.
REFERENCE DES
CRITICAL
IC,ISL6258,BAT CHARGER,28P,4X4,QFN,L
U7000
CRITICAL
ISL6258
2S Battery Default
353S1832
IC,ISL6258A,BAT CHARGER,4X4MM,QFN28
U7000
CRITICAL
ISL6258A
3S Battery Default
differences from last sync on 12/02/07 to T18 MLB:

L7030 changed from T18 MLB inductor to 152S0542.
Added Q7056, C7058,R7055,R7056..
U7000 Thermal Pad is now connected to GND, not through XW.
Q7060 and Q7065 changed to 376S0667.
Q7055 and Q7056 changed to 376S0666.

BOM OPTION
SIZE
DRAWING NUMBER
D
APPLE INC.
REV.
051-7656
SCALE
SHT
NONE
R7057
1M
10%
2 10V
X5R
402-1
VOLTAGE=0V
5%
MF-LF
402
1/16W
1UF
GND_CHGR_AGND
353S1938
R7056
C7058
0.001UF
10%
25V
X5R
402
59
VOLTAGE=12.6V
0.1UF
(PPVBAT_G3H_CHGR_R)
33UF
0.01uF
5%
1/16W
MF-LF
402
2.2UH-20A-5.5M-OHM
SM
R7051
10
20%
16V 2
POLY-TANT
CASED2E-SM
C7040
20%
16V 2
POLY-TANT
CASED2E-SM
L7031
0.001UF
Max Current = 8.5A

(L7030 limit)
f = 400 kHz
33UF
1206
CRITICAL
C7043
CHGR_PHASE_RC
152S0542
CRITICAL
10%
50V
X7R
402
152S0542
RJK0305DPB
8AMP-24V
1206
C7034
10
5%
1/10W
MF-LF
603
F7041
8AMP-24V
R7099
RJK0305DPB
CRITICAL
F7040
20%
2 25V
POLY-TANT
CASE-D2-SM
0.001UF
CRITICAL
22UF
20%
2 25V
POLY-TANT
CASE-D2-SM
PPVBAT_G3H_CHGR_REG_L
CRITICAL
C7037
CRITICAL
SM
OUT
2.2UH-20A-5.5M-OHM
SWITCH_NODE=TRUE
C7033
1UF
CRITICAL
C7036
22UF
20%
2 25V
POLY-TANT
CASE-D2-SM
C7032
CRITICAL
C7031
22UF
20%
2 25V
POLY-TANT
CASE-D2-SM
CRITICAL
10%
10V
CERM
402
CRITICAL
C7030
22UF
Q7031
e
r
PPDCIN_S5_FET_CHGR
CRITICAL
CHGR_AGATE
CHGR_CSI_P
CHGR_CSI_N
CHGR_BGATE
CHGR_BOOT
CHGR_UGATE
CHGR_PHASE
24
C7011
10%
16V
CERM
402
CHGR_DCIN
LGATE
3.01K
1%
1/16W
MF-LF
402
27
25
SM
1
94
BOOT
UGATE
PHASE
28
16
XW7000
R7016
C7021
0.1UF
C703560
0.22UF
LFPAK-HF
BGATE
DCIN
0.001UF
10%
50V
CERM
402
20
VREF
ACIN
THRM_PAD
R7011 1
10%
25V
X5R
402
10
PGND
11
AGND
BI
=SMBUS_CHGR_SCL
=SMBUS_CHGR_SDA
ISL6258A
12
IN
44
C7001
VDD
VDDP
CRITICAL
VHST
AGATE
U7000 CSIP
SCL
QFN
CSIN
SDA
26
1%
1/16W
MF-LF
402 2
0.1UF
10%
10V
X5R
402
19
30.1K
VOLTAGE=5.1V
1
44
C7022
1UF
10%
10V
X5R
402
Input impedance of ~40K meets

sparkitecture requirements
R7010
5%
1/16W
MF-LF
402
30mA max load
PP5V1_CHGR_VDDP
4.7
VOLTAGE=5.1V
1UF
Divider sets ACIN

threshold at 13.07V
C7002
ACIN pin threshold

is 3.2V, +/- 50mV
PP5V1_CHGR_VDD
0.5%
1W
MF
0612
=PPBUS_G3H
TO SYSTEM
60
60
R7001
=PP3V42_G3H_CHGR
10
5%
1/16W
MF-LF
402
22
60 8
CHGR_CSI_R_N
R7020
0.02
R7022
1
96
3 1
PP5V1_CHGR_VDD
10%
10V
CERM
402
CHGR_CSI_R_P
0.047UF
96
C7020
CRITICAL
SIGNAL_MODEL=EMPTY
5%
1/16W
MF-LF
402
10
R7021
SOT-323
1
AMON_CLAMP
BAT30CWFILM
SOT563
(CHGR_DCIN)
D7005
CRITICAL
45 60
R7075 clamps CHGR_AMON when charger is

not powered to counter TL331 bias current.
PPDCIN_S5_INRUSH
VOLTAGE=18.5V
R7074
CHGR_AMON
VCC
1%
1/16W
MF-LF
402 2
10%
16V
X5R
402
TL331
SOT23-5
4
CHGR_SGATE
57.6K
0.1uF
62K
R7070
C7070
D2
D1
D3
D4
HAT1128R01
SOI
D4
1%
1/16W
MF-LF
2 402
D3
D2
D1
332K
R7066 1
2 3
Q7060
R7061
8 60
SOI
CRITICAL
=PP3V42_G3H_CHGR
2
1 2
5%
1/16W
MF-LF
402
GATE
HAT1128R01
S1
S1
S3
S2
Q7065
S3
S2
CHGR_AGATE_DIV
CRITICAL
1
10%
25V
X5R
402
GATE
R7065 1
0.1UF
1%
1/16W
MF-LF
402
470K
R7060
VOLTAGE=18.5V
31
OF
70
123
8
8
10
C7108
PPVIN_S5_IMVP6_VIN
C7196
10%
50V
X7R
402
0.1UF
10%
16V
X5R
402
=PP5V_S0_CPU_IMVP
C7126
R7119
Operation
Mode
2-Phase
CCM
1-Phase
CCM
1-Phase
DCM
1-Phase
DCM
C7130
R7199
0.1uF
10%
16V
X5R
402
5%
1/16W
MF-LF
402
R7197
10K
2
2
5%
1/16W
MF-LF
402
22
VIN
0
2
LAYOUT NOTE:
IN
88 9
IN
88 9
(IMVP6_NTC)
Place R7126 in hot
88 9
spot of reg circuit.

1
88 9
IN
88 9
IN
88 9
IN
88 9
IN
CRITICAL
R7126
C7110
470K
88 14 10 9
IN
10
IN
88
0.01uF
10%
16V
CERM
402
402
2
IMVP6_VID<6>
IMVP6_VID<5>
IMVP6_VID<4>
IMVP6_VID<3>
IMVP6_VID<2>
IMVP6_VID<1>
IMVP6_VID<0>
IN
2
45
OUT
43
VID6
42
VID5
41
CPU_DPRSTP_L
IMVP_DPRSLPVR
CPU_PSI_L
IMVP6_IMON
9
61
VID3
39
VID2
38
VID1
37
VID0
C7105
R7108
25
IN
OUT
147K
0.015UF
10%
16V
X7R
402
1%
1/16W
MF-LF
402
2
2
1%
1/16W
MF-LF
402
36
BOOT2
26
U7100
R7113
0.001UF
2
61
(GND_IMVP6_SGND)
IMVP6_SOFT
61
IMVP6_RBIAS
61
(GND_IMVP6_SGND)
IMVP6_VDIFF
61
1K
10%
50V
CERM
402
1%
1/16W
MF-LF
402
61
61
61
61
61
DPRSTP*
45
DPRSLPVR
UGATE1
35
PHASE1
34
LGATE1
32
PGND1
33
ISEN1
24
61
IMVP6_ISEN1
UGATE2
27
61
IMVP6_UGATE2
PHASE2
28
61
IMVP6_PHASE2
LGATE2
30
61
IMVP6_LGATE2
PGND2
29
ISEN2
23
VSUM
19
61
IMVP6_UGATE1
61
IMVP6_PHASE1
61
IMVP6_LGATE1
C7127
IMON
(PGD_IN)
3V3
47
CLK_EN*
44
VR_ON
PGOOD
VR_TT*
NTC
SOFT
13
IMVP6_FB2
IMVP6_FB
IMVP6_COMP
IMVP6_VW
255
11
FB
COMP
61
a
n
i
61
VO
18
DROOP
16
DFB
17
m
il
IMVP6_VSUM
IMVP6_OCSET
IMVP6_VO
IMVP6_DROOP
61
IMVP6_DFB
VSEN
14
RTN
15
470PF
2
10%
50V
CERM
402
10%
50V
CERM
402
(IMVP6_VW)
R7114 1
C7107
97.6K
1%
1/16W
MF-LF
402
IMVP_VR_ON_R
61
5%
1/16W
MF-LF
402
61
61
61
61
61
61
61
61
61
61
61
IMVP6_OCSET
IMVP6_VO
IMVP6_DROOP
IMVP6_DFB
IMVP6_SOFT
IMVP6_RBIAS
IMVP6_VDIFF
IMVP6_FB2
IMVP6_FB
IMVP6_COMP
IMVP6_VW
R7110
6.81K
10%
50V
CERM
402
R7160
1
0.001UF
(IMVP6_COMP)
IMVP_VR_ON
1%
1/16W
MF-LF
402
61
61
61
61
61
61
61
88 61
TPAD
IMVP6_PHASE1
IMVP6_BOOT1
IMVP6_UGATE1
IMVP6_LGATE1
IMVP6_ISEN1
IMVP6_VSUM1
IMVP6_VO1
IMVP6_VSEN_P
XW7104
R7104
1
C7103
R7100
5%
1/16W
MF-LF
402
0.22UF
10K
1%
1/16W
MF-LF
402
10%
50V
X7R
402
IMVP6_VO1
61
0.001UF
IMVP6_VSUM1
C7156
SM
10%
10V
CERM
402
R7101
3.65K
1%
1/10W
MF-LF
2 603
61
OUT
61
49
0.22UF
SM
1
20%
6.3V
X5R
402
LFPAK-HF
C7116
10%
50V
CERM
402
R7118
C7129
L7101
0.36UH-30A-1.05MOHM
1
(IMVP6_PHASE2)
2
PCMC104T-SM
XW7101
XW7102
SM
1
C7134
Q7103
4
61
IMVP6_VSUM2
10%
10V
CERM
402
RJK0328DPB
1
1%
1/16W
MF-LF
402
R7105
1%
1/16W
MF-LF
402
CRITICAL
C7104
5%
1/16W
MF-LF
402
0.22UF
1
10%
10V
CERM
402
R7106
3.65K
R7131
10%
6.3V
CERM-X5R
402
10K
1%
1/10W
MF-LF
2 603
10KOHM-5%
0.22UF
R7107
IMVP6_VO_R
C7128
1
1
2.61K
1%
1/16W
MF-LF
402
10%
50V
X7R
402
IMVP6_VO2
61
0.001UF
LFPAK-HF
R7130
11K
0.068UF
R7115
C7157
SM
2
CRITICAL
1%
1/16W
MF-LF
2 402
5%
50V
CERM
402
13.3K
180pF
1%
1/16W
MF-LF
402
R7116
CRITICAL
(IMVP6_VO)
0603-LF
(IMVP6_ISEN2)
(IMVP6_VSUM)
Place R7131 Between L7100,L7101 and CPU
(IMVP6_VO)
R7122
88 61
88 61
C7143
0.001UF
2
RJK0305DPB
NO STUFF
SIGNAL_MODEL=EMPTY
C7121
XW7100
3.92K
Q7102
0.001uF
1K
e
r
390PF
IMVP6_COMP_RC
41
10%
50V
CERM
402
NC
VOLTAGE=0V
OUT
1%
1/16W
MF-LF
402
GND_IMVP6_SGND
C7113
CRITICAL
C7131
21
C7114
20%
25V
X5R
603
IMVP6_ISEN2
VW
GND
(IMVP6_FB)
10%
25V
X5R
603-1
(IMVP6_ISEN1)
R7117
R7109
1%
1/16W
MF-LF
402
61
0.22UF
20%
25V
X5R
603
(GND)
VDIFF
FB2
10
1K
1UF
2
RBIAS
12
C7115
0.22UF
PSI*
48
25
1%
1/16W
MF-LF
402
XW7103
RJK0328DPB
(GND)
0.001UF
C7158
44A MAX CURRENT
0.36UH-30A-1.05MOHM
LFPAK-HF
5%
1/10W
MF-LF
603
IMVP6_BOOT1
IMVP6_BOOT2
IMVP6_VDIFF_RC
R7111 1
y
r
IMVP6_BOOT1_R
5%
1/10W
MF-LF IMVP6_BOOT2_R
603
QFN
OCSET
C7106
Q7101
PVCC
CRITICAL BOOT1
46
VR_PWRGD_CLKEN_L
IMVP_VR_ON_R
VR_PWRGOOD_DELAY
IMVP6_VR_TT_L
IMVP6_NTC
OUT
10%
25V
X5R
603-1
D
(IMVP6_PHASE1)
(ISL9504A)
4.02K
31
VDD
VID4
40
IMVP6_NTC_R
R7127 1
=PPVCORE_S0_CPU_REG
SM
R7198
5%
1/16W
MF-LF
402
C7154
1UF
16V
TANTD
SM
L7100
R7188
20
20%
RJK0305DPB
CRITICAL
ISL9504BCRZ
CPU_PROCHOT_L
68UF
CRITICAL
20%
6.3V
X5R-CERM
402
OUT
10%
50V
X7R
402
16V
2
POLY-TANT
CASED2E-SM
R7189
2
1%
1/16W
MF-LF
402
C7133
Q7100
4
C7135
499
PM_DPRSLPVR
16V
2
POLY-TANT
CASED2E-SM
4.7UF
68
88 42 14 10
C7152
0.001UF
20%
20%
10%
25V
X5R
603-1
CRITICAL
1
33UF
PCMC104T-SM
IN
PSI*
=PP1V05_S0_CPU
88 21
1UF
C7153
VOLTAGE=3.3V
1%
1/16W
MF-LF
402
13 12 11 10 8 6
DPRSTP*
PP3V3_S0_IMVP6_3V3
33UF
10%
10V
X5R
402
10
1
DPRSLPVR
1UF
R7121
=PP3V3_S0_IMVP
16V
TANTD
SM
10%
25V
X5R
603-1
CRITICAL
1
C7155
C7118
LFPAK-HF
VOLTAGE=5V
1%
1/16W
MF-LF
402
1UF
20%
2
C7109
CRITICAL
PP5V_S0_IMVP6_VDD
68UF
R7112
10
CRITICAL
1
C7117
0.001UF
VOLTAGE=12.6V
1%
1/16W
MF-LF
402
These caps are for Q7102
CRITICAL
R7120
These caps are for Q7100
=PPVIN_S5_CPU_IMVP
10%
50V
CERM
402
IMVP6_VSEN_P
2
5%
1/16W
MF-LF
402
IMVP6_VSEN_N
CPU_VCCSENSE_P
IN
11 88
CPU_VCCSENSE_N
IN
11 88
R7123
0
1
2
5%
1/16W
MF-LF
402
C7132
0.001UF
10%
50V
CERM
402
IMVP6 CPU VCore Regulator
SYNC_MASTER=RXU_K20

61
61
61
61
61
61
61
I849
88 61
IMVP6_PHASE2
IMVP6_BOOT2
IMVP6_UGATE2
IMVP6_LGATE2
IMVP6_ISEN2
IMVP6_VSUM2
IMVP6_VO2
IMVP6_VSEN_N

SIZE
APPLE INC.
REV.
051-7656
SCALE
SHT
NONE
I848
DRAWING NUMBER
31
OF
71
123
y
r
=PPVIN_S5_P5VP3V3
CRITICAL
P5VP3V3_VREG5
CRITICAL
1UF
10%
25V
X5R
603-1
5%
1/10W
MF-LF
603
XW7222
SM
PLACEMENT_NOTE=PLACE XW7222 NEXT TO L7220.
Q7225
SI7110DN
P5VS3_LL_RC
PWRPK-1212-8-HF
1
C7299
10%
50V
CERM
402
20.0K
1%
MF-LF
1/16W
402
MF-LF
2
P5VS3_COMP1_R
402
5%
1/16W
P5VS3_CSP1-R
C7237
470PF
100PF
10%
50V
CERM
402
5%
50V
CERM
402
P5VP3V3_VREF2
62
R7221
F=400KHZ
=PP3V3_S5_REG
CRITICAL
L7260
2.2UH-14A
SW
13
P3V3S5_VFB2
1/16W
1%
1/16W
402
MF-LF
402
XW7260
C7239
100PF
10%
50V
CERM
402
5%
50V
CERM
402
67
1%
1/16W
MF-LF
402
OUT
P5V3V3_PGOOD
67
IN
C7290
C7292
10UF
SM
20%
6.3V
SM
2
1
X5R
C7272
0.001UF
330UF
20%
6.3V
POLY-TANT
CASE-D3L-SM1
603
10%
50V
X7R
402
PLACEMENT_NOTE=PLACE XW7260 AND XW7261 NEXT TO L7260 .
P3V3S5_LL_RC
NO STUFF
1
7
C7298
0.001UF
10%
50V
X7R
402
XW7262
SM
PLACEMENT_NOTE=PLACE XW7262 NEXT TO L7260.
R7216
P3V3S5_VFB2_R
1%
1/16W
470PF
2
XW7261
3.83K
P3V3S5_COMP2_R
C7238
5%
1/10W
MF-LF
603 2
20.0K
MF-LF
402
CRITICAL
2
10
Q2
2
IHLP2525CZ-SM1
NO STUFF
1
R7239
1/16W
MF-LF
1%
1%
PLACEMENT_NOTE=Place XW7200 between pins U7200.28 and 33.
R7238
10K
R7206
249K
402
P3V3S5_COMP2
(L7260 limit)
R7298
6A MAX OUTPUT
Q1
10
Vout = 3.3V
PATH=I621
MF-LF
402
R7260
23.2K
P3V3S5_CSP2_R
1%
1/16W
MF-LF
402
P5VP3V3_VREF2
62
One master PGOOD for both 5V and 3V3
10K
402
e
r
C7236
2 402
1%
1/16W
MF-LF
402
P3V3S5_RF
SM
P3V3S5_CSN2
THRM_PAD
XW7200
10%
25V
X5R
603-1
MLP
P3V3S5_CSP2
EN2 21
PGOOD2 20
R7249
MF-LF
MF-LF
R7220
X5R
MF-LF
1/16W
5%
2 402
R7248
R7237
1/16W
1/16W
40.2K
402
R7256
1%
10K
2.74K
PATH=I623
RF 3
VFB2 16
COMP2 15
GND
R7236
1%
2 1
P3V3S5_DRVL
m
il
DRVL2 27
11 FUNC
9 VFB1
10 COMP1
10%
50V
X7R
402
Q7260
P3V3S5_LL
SWITCH_NODE=TRUE
4 EN1
5 PGOOD1
0.0033UF
P5VS3_VFB1-R
P5VS3_COMP1
P3V3S5_DRVH
GATE_NODE=TRUE
SW2 25
CSP2 18
CSN2 17
28
P5VS3_FUNC
P5VS3_VFB1
NO STUFF
R7247
10%
50V
X7R
402
X5R
0.001UF
2
62 P5VP3V3_VREG3
CRITICAL
R7299 1
C7271
805
0.1UF
MF-LF
P5VS3_CSN1
1UF
DRVH2 24
7 CSP1
8 CSN1
C7281
P3V3S5_VBST
GATE_NODE=TRUE
P5VS3_CSP1
SM
PLACEMENT_NOTE=PLACE XW7220 AND XW7221 NEXT TO L7220.

2
VBST2 26
GATE_NODE=TRUE
10%
16V
2 402
X5R
XW7221
SM
20%
10V
XW7220
1 C7218
10UF
30 DRVL1
P5VS3_DRVL
1/16W
1%
C7250
C7273
0.001UF
16V
2
POLY-TANT
CASED2E-SM
FDMS9600S
402
10%
25V
SWITCH_NODE=TRUE
1.54K
330UF
32 SW1
P5VS3_LL
20%
GATE_NODE=TRUE
SM-IHLP
CRITICAL
1 DRVH1
P5VS3_DRVH
X7R
0.1UF
CRITICAL
10%
50V
33UF
402
0.1UF
C7288
603-1
C7264
C7280
L7220
1
31 VBST1
P5VS3_VBST
X7R
1.0UH-22A-10M-OHM
(Q7220 limit)
20%
6.3V
POLY-TANT
CASE-D3L-SM1
EN 12
20%
6.3V
X5R
603
TPS51220
CRITICAL
7A MAX OUTPUT
C7252
10%
50V
CERM
10UF
603-1
10%
10V
LLP
0.1UF
MF-LF
C7224
Vout = 5.0V
0.22UF
CRITICAL
U7201
C7201
C7205
1%
LFPAK-HF
62 8 =PP5V_S3_REG
1/16W
6 SKIPSEL1
19 SKIPSEL2
14 TRIP
RJK0305DPB
1UF
10%
6.3V
CERM
402
1.18K
Q7220
F=400KHZ
VREF2
CRITICAL
22
1UF
10%
25V
X5R
603-1
C7203
V5SW
C7200
5
VREG3
62 P5VP3V3_VREF2
33
20%
16V
2
POLY-TANT
CASED2E-SM
R7246
33UF
C7241
29
10%
50V
X7R
402
VREG5
0.001UF
2
C7240
23
C7270
62 P5VP3V3_VREG3
VIN
a
n
i
62 8 =PP5V_S3_REG
R7261
10K
1%
1/16W
MF-LF
402
GND_P5VP3V3_SGND
VOLTAGE=0V
=P5VS3_EN
67
IN
P3V3S5_EN
5V / 3.3V Power Supply

SYNC_MASTER=RXU_K20

.
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
72
123
y
r
=PPVIN_S0_DDRREG_LDO
C7355
=PPVIN_S3_DDRREG
10UF
2
20%
6.3V
X5R
603
CRITICAL
C7330
CRITICAL
C7331
20%
16V
TANTD
SM
68UF
20%
16V
TANTD
SM
R7305
=PP5V_S3_DDRREG
4.7
PP5V_S3_DDRREG_V5FILT
a
n
i
68UF
VOLTAGE=5V
5%
1/16W
MF-LF
402
C7332
C7333
1UF
0.001UF
10%
25V
X5R
603-1
10%
50V
X7R
402
10%
10V
X5R
402
CRITICAL
DDRREG_VDDQSNS
23
1UF
20%
6.3V
CERM
603
14
C7305
4.7UF
15
C7300
Q7330
(DDRREG_DRVH)
V5IN
V5FILT
VLDOIN
R7310 1
COMP
VDDQSNS
MODE
CRITICAL
IN
67
IN
67
OUT
=DDRVTT_EN
=DDRREG_EN
DDRREG_PGOOD
26 8
=PPVTT_S3_DDR_BUF
=PPVTT_S0_DDR_LDO
10
11
13
S3
S5
PGOOD
VTT Enable
10mA max load

5
VDDQ/VTTREF Enable
VBST
24
XW7360
22UF
20%
6.3V
X5R-CERM
603
PLACEMENT_NOTE=Place next to C7361
NC
NC
C7361
22UF
7
12
20%
6.3V
X5R-CERM
603
20
DDRREG_DRVH
DDRREG_LL
CS
NC0
NC1
VDDQSET
VTTGND
THRM_PAD GND
(DDRREG_LL)
19
DDRREG_DRVL
16
(DDRREG_DRVL)
DDRREG_FB
PGND CS_GND
(DDRREG_CSGND)
1.0UH-20A
CRITICAL
Q7335
RJK0328DPB
LFPAK-HF
=PPDDR_S3_REG
IHLP4040DZ11-SM
10%
50V
X7R
603-1
PLACEMENT_NOTE=Place next to Q7335
DDRREG_CSGND
DDRREG_CS
330UF
20%
2 2.5V
POLY-TANT
CASE-C2-SM
CRITICAL
1
20%
2.5V 2
POLY-TANT
CASE-C2-SM
C7341
10%
16V
X5R
402
XW7300
SM
GND_DDRREG_SGND
VOLTAGE=0V
C7346
10%
50V
X7R
402
XW7345
SM
PLACEMENT_NOTE=Place next to L7330

1
XW7335
SM
NO STUFF
C7320
1
1
5%
50V
CERM
402
R7320
15.0K
100PF
2
1%
1/16W
MF-LF
2 402
<Ra>
(DDRREG_FB)
PLACEMENT_NOTE=Place next to U7300.3
0.001UF
20%
6.3V
X5R
603
e
r
2
C7345
10UF
330UF
(DDRREG_VDDQSNS)
C7350
Vout = 1.50V or 1.80V

18A MAX OUTPUT
(Q7335 limit)
f = 400 kHz
CRITICAL
C7340
0.033UF
L7330
m
il
VTTSNS
18
LL
DRVL
21
SWITCH_NODE=TRUE
Vout = VTTREF
DDRREG_VTTSNS
(DDRREG_VBST)
GATE_NODE=TRUE
VTT
C7360
CRITICAL
DRVH
QFN
VTTREF
25
CRITICAL
DDRREG_VBST
GATE_NODE=TRUE
CRITICAL
C7325
SM
1
22
U7300
VDDQ PGOOD
SYM (2 OF 2)
Vout = VDDQSNS/2
LFPAK-HF
0.1UF
TPS51116
MIN_LINE_WIDTH=2 mm
1%
1/16W
MF-LF
402 2
17
68 9
RJK0305DPB
8.06K
6
Vout = 0.75V * (1 + Ra / Rb)
R7321
15.0K
1%
1/16W
MF-LF
402
<Rb>
1.5V DDR3 Supply

SYNC_MASTER=RXU_K20

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
73
123
=PPVIN_S0_P5VRTS0_MCPCORE
CRITICAL
1
C7512
C7510
0.001UF
2
20%
50V
CERM
402
C7511
1UF
33UF
20%
16V 2
POLY-TANT
CASED2E-SM
10%
25V
CRITICAL
X5R
603-1
y
r
Q7510
SI7110DN
PWRPK-1212-8-HF
S
3
(P5VRTS0_UGATE)
CRITICAL
GATE_NODE=TRUE
R7500 1
NO STUFF
R7599 1
1.00
CRITICAL
PVIN_P5VRTS0_MCPCORE
(P5VRTS0_LGATE)
CRITICAL
8
2.2UH-14A
1
C7514
10%
16V
X7R
603
P5VRTS0_BOOT
P5VRTS0_UGATE
P5VRTS0_PHASE
P5VRTS0_LGATE
(P5VRTS0_PHASE)
SWITCH_NODE=TRUE
IHLP2525CZ-SM1
0.22UF
L7510
Vout = 5.03V
3.5A MAX OUTPUT
(=PP5V_RTS0_REG)
(Q7510 limit?)
(=P5V_RTS0_EN)
1
f = 200 kHz
C7516
2
10UF
20%
10V
2
P5V_RTS0_FB
P5V_RTS0_ILIM
XW7516
SM
X5R
805
CRITICAL
C7515
1PLACEMENT_NOTE=Place next to C7516
P5VRTS0_VSNS
330UF
2
NO STUFF
R7520
NO STUFF
C7520
61.9K
5%
50V
CERM
402
R7521
67
OUT
67
IN
21
IN
21
IN
21
IN
e
r
=P5V_RTS0_EN
MCPCORES0_PGOOD
P5V_RTS0_PGOOD
=MCPCORES0_EN
MCP_VID<0>
MCP_VID<1>
MCP_VID<2>
PART NUMBER
QTY
114S0382
114S0400
114S0482
114S0453
114S0422
114S0373
114S0404
114S0458
114S0447
114S0411
1
1
1
DESCRIPTION
REFERENCE DES
CRITICAL
20%
6.3V
X5R-CERM
402
(MCPCORES0_LGATE)
100K
0.1UF
R7570
LFPAK-HF
MCPCORES0_PHASE_L
SWITCH_NODE=TRUE
0.1%
1/16W
MF
402 2
R7505
CRITICAL
0.001
L7560
1% CRITICAL
1W
MF
0612
1.0UH-20A
2
4
IHLP4040DZ11-SM
96 46
NO STUFF1
CRITICAL
R7598
96 46
1.00
Q7565
RJK0328DPB
LFPAK-HF
1%
1/6W
MF
402
R7571
54.9K
0.1%
1/16W
MF
402 2
C7590
0.01UF
<Rb>
10%
16V
CERM
402
PPMCPCORE_LL_RC
0.001UF
2
10%
50V
X7R
402
<Rd>
Q7580
R7582
0.1%
1/16W
MF
2 402
<Rc>
C7567
C7569
0.001UF
10UF
110K
20%
2 2.5V
POLY-TANT
CASE-C2-SM
CRITICAL
MCP_PROD
1
330UF
2
1
0.1%
1/16W
MF
2 402
C7568
SM
237K
XW7510
1
0.1%
1/16W
MF
2 402
CRITICAL
C7565
20%
2 2.5V
POLY-TANT
CASE-C2-SM
C7598
475K
MCP_VID0_L
F = 300 KHZ
330UF
NO STUFF
1
R7581
(Q7560 Limit)
2
MCP_PROD
R7580
20%
4V
X5R
603
CRITICAL
<Ra>
MCP_PROD
MAX CURRENT: 11A
10UF
PMCPCORE_VSNS
MCP_PROD
C7566
MCPCOREISNS_N
IN
Vout = See below
MCPCOREISNS_P
IN
=PPMCPCORE_S0_REG
1
3
20%
4V
X5R
603
C7562
330UF
10%
50V
X7R
402
20%
2 2.5V
POLY-TANT
CASE-C2-SM
<Re>
MCP_VID1_L
Q7580
MCP_VID2_L
Q7582
SSM6N15FEAPE
SSM6N15FEAPE
SSM6N15FEAPE
SOT563
SOT563
SOT563
BOM OPTION
MCP_A01
R7571
MCP_A01
RES,MTL FILM,1/16W,523K,1,0402,SMD,LF
R7580
MCP_A01
VID<2:0>
Rev A01
Production
Voltage
Voltage
MCP Target
R7581
MCP_A01
000
+1.224V
+1.060V
+1.05V
R7582
MCP_A01
001
+1.159V
+0.994V
+1.00V
RES,MTL FILM,1/16W,40.2K,1,0402,SMD,LF
R7570
MCP_A01Q
010
+1.101V
+0.937V
+0.95V
R7571
MCP_A01Q
011
+1.049V
+0.885V
+0.90V
RJK0305DPB
Req = Rb || Rc || Rd || Re
Q7560
10%
25V
X5R
603-1
CRITICAL
48.7K
Vout = 2.0V * Req / (Ra + Req)
R7570
C7561
1UF
MCP_PROD
1%
1/16W
MF-LF
402 2
20%
10V
CERM
402
GATE_NODE=TRUE
VOLTAGE=0V
R7564
C7530
GATE_NODE=TRUE
SWITCH_NODE=TRUE
Max load 50uA
4.7UF
(MCPCORES0_PHASE)
VOLTAGE=2V
(MCPCORES0_UGATE)
5%
10V
CERM-X7R
603
(=PPMCPCORE_S0_REG)
PP2V_S0_MCPREG_REF
C7502
0.22UF
(SGND)
MCPCORES0_BOOT
MCPCORES0_UGATE
MCPCORES0_PHASE
MCPCORES0_LGATE
VREF2 1
PGOOD1 13
PGOOD2 28
68UF
10%
50V
X7R
402
C7564
VOLTAGE=5V
MCPCORES0_REFIN
MCPCORES0_ILIM
GND_MCPREG_SGND
MCP79 Rev A01 requires higher core & analog voltage
Max load 100mA

PP5V_S0_MCPREG_LDO
<Rb>
IN
10%
10V
X5R
402-1
10%
10V
X5R
402-1
20%
16V 2
TANTD
SM
C7560
0.001UF
a
n
i
1
1UF
REFIN2 32
TRIP2 31
SM
1%
1/16W
MF-LF
2 402
Vout = 0.7V * (1 + Ra / Rb)

OUT
7
8
24
26
25
23
30
27
XW7500
R7514
100K
5%
1/16W
MF-LF
2 402
67
LDO
LDOREFIN
VBST2
DRVH2
LL2
DRVL2
VOUT2
EN2
m
il
67
10%
10V
X5R
402-1
U7500
<Ra>
1
1UF
VIN
VBST1
CRITICAL
DRVH1
LL1
QFN
DRVL1
VOUT1
EN1
VSW
VFB1
TRIP1
SKIPSEL
EN_LDO
V5DRV1
TONSEL
C7503
THRM_PAD GND PGND
100PF
1%
1/16W
MF-LF
2 402
6
17
15
16
18
10
14
9
11
12
29
4
20
2
33
20%
6.3V
POLY-TANT
CASE-D3L-SM1
10%
25V
X5R
805
(P5VRTS0_BOOT)
=PP5V_S0_REG
10UF
VREF3
C7504
22
VOLTAGE=3.3V
V5FILT
10%
50V
X7R
402
C7500
SN0802043
GATE_NODE=TRUE
0.001UF
2
PWRPK-1212-8-HF
C7599
21
SI7108DN
NO STUFF
1
PP3V3_S0_MCP_VREF
19
PP5VRTS0_LL_RC
VOLTAGE=5V
Q7511
V5DRV
1%
1/6W
MF
402
C7501
1UF
(Internal 10-ohm path

from PVCC to VCC)
PP5V_S0_MCPREG_VCC
5%
1/16W
MF-LF
402 2
C7563
4.7
R7580
MCP_A01Q
R7581
MCP_A01Q
R7582
MCP_A01Q
100
101
+0.995V
+0.952V
+0.830V
+0.789V
5V_S0 / MCP CORE REGULATOR

SYNC_MASTER=RXU_K20
+0.85V
+0.80V
110
+0.913V
+0.752V
+0.75V
111
+0.876V
+0.719V
+0.70V

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
75
123
=PPVIN_S0_CPUVTTS0
8
=PP5V_S0_CPUVTTS0
R7699
1
D
C7651
1UF
y
r
10%
25V
X5R 2
603-1
1
20%
16V
POLY-TANT
2
CASED2E-SM
VOLTAGE=5V
5%
1/16W
MF-LF
402
CRITICAL
C7650
33UF
PP5V_S0_CPUVTTS0_R
10
V5V
PPCPUVTT_ISNS_R
CRITICAL
CRITICAL
VLDO
BST
DH
R7651
NC
FBL
130K
29
1%
1/16W
MF-LF
402 2
EN/PSV
26
PGOOD
LX0
LX1
LX2
LX3
LX4
LX5
ILIM
27
DL
1
5%
1/10W
MF-LF
603
96 46
96 46
R7654
32
C7698
10%
50V
X7R
402
CPUVTTS0_LL_XW
m
il
C7657
1UF
NO STUFF
R7631
10%
10V
2 X5R
402
10K
1%
1/16W
MF-LF
402
XW7660
SM
e
r
C7654
150UF
20%
2 6.3V
POLY-TANT
CASE-B2-SM
C7655
0.01UF
10%
2 16V
CERM
402
C7658
0.001UF
20%
50V
CERM
402
PPCPUVTT_S0_REG_XW
MAX CURRENT = 6A
NO STUFF
PWM FREQ = 400KHZ
C7630
0.01UF
10%
16V
2 CERM
402
CRITICAL
1
R7655
12.1K
1%
1/16W
MF-LF
2 402
CPUVTTS0_FB_C
=PPCPUVTT_S0_REG
CRITICAL
1V05CPU_N
IN
0.001UF
2
1/16W
MF-LF
402
14 NC
2
4
1V05CPU_P
IN
CPUVTTS0_LL_RC
7.15K
1%
1
1
3
PGND
15
16
17
18
19
20
21
22
4
30
34
AGND
R7698
CPUVTTS0_LL
CPUVTTS0_ILIM
IHLP2525CZ-SM1
12 NC
13
23
24
25
28
33
ENL
0.22UF
8 CPUVTTS0_VBST
1%
1/4W
MF
1206
a
n
i
C7653
10%
10V
CERM
402
2
1
0.002
VOUT
R7650
TON
CRITICAL
XW7662
SM
NC
MLPQ
6
9
10
11
35
CPUVTTS0_TONE
VIN0
VIN1
VIN2
VIN3
VIN4
SC417
31
U7600
FB
XW7661
SM
L7650
2.2UH-14A
NO STUFF
1
C7656
180PF
5%
50V
2 CERM
402
NO STUFF
1
C7631
330PF
10%
50V
2 CERM
402
CPUVTTS0_FB
GND_CPUVTTS0_SGND
67
IN
=CPUVTTS0_EN
67
IN
CPUVTTS0_PGOOD
CRITICAL
VOLTAGE=0V
R7656
11K
1%
1/16W
MF-LF
402
2
R7630
56.2K
1%
1/16W
MF-LF
402
CPU VTT Power Supply

SYNC_MASTER=RXU_K20

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
76
123
1.8V S0 Switcher / 1.0VFW SWITCHER
FW BOOST POWER
R7790
0.02
CRITICAL
2.2UH-1.2A
(Switcher limit)
SW1
SW2
RUN1
RUN2
CRITICAL
2.2UH-1.2A
1
=PP1V8_S0_REG
C7701
5%
50V
CERM
402
<Ra>
1
1
R7700
1%
1/16W
MF-LF
402
F = 2.25 MHZ
NO STUFF
U7740
DFN
3 IN
6 SHDN*
1%
1/16W
MF-LF
402
GND
C7741
10%
6.3V
CERM
402
=PP3V3_FW_P1V0FW
Vout = 0.6V * (1 + Ra/Rb)
ADJ
5
1
THRML
PAD
<Ra>
R7740
1%
1/16W
MF-LF
2 402
C7742
<Rb>
R7741
10uF
20%
6.3V
X5R
603
84 83 67
m
il
CRITICAL
L7760
10UH-0.55A-330MOHM
TPS62202
2
PCAA031B-SM
SOT23-5
FB
EN
=P1V8FB_EN
CRITICAL
SW 5
MAX CURRENT = 300MA
P1V8GPU_SW
=PP1V8_GPUIFPX_REG
GND
C7762
10uF
20%
6.3V
X5R
603
66 8
=PPVIN_S0_P1V05S5
e
r
MCP 1.05V AUXC Supply
P5V_P1V05S5_V5FILT
R7751
1
66 8
=PPVIN_S0_P1V05S5
1
4.7
5%
1/16W
MF-LF
402
C7752
P5V_P1V05S5
4.7UF
10%
25V
X5R
603-1
20%
6.3V
CERM
603
P1V05_S5_FSET
R7752
67
38.3K
C7753
0.01UF
10%
16V
CERM
402
1%
1/16W
MF-LF
2 402
IN
P
U7750
ISL6269
=P1V05S5_EN
OUT
P1V05_S5_PGOOD
P1V05_S5_COMP
P1V05S5_VFB
1
R7753
C7755
5%
50V
CERM
402
1%
1/16W
MF-LF
402
2
VIN
FSET
FB
16
5 OVT
C7711
CRITICAL
UG
BOOT
PHASE
ISEN
14
13
15
LG
11
PGND
10
C7750
2.2UF
R7779
1%
1/16W
MF-LF
402
0.1UF
10%
16V
2 X5R
GATE_NODE=TRUE
P1V05S5_VBST
P1V05S5_LL
SWITCH_NODE=TRUE
CRITICAL
2 50V
CERM
5%
402
2
1
1%
1/16W
MF-LF
402
CRITICAL MAX
<Rb> 2
R7711
100K
1%
1/16W
MF-LF
402
1
C7713
22UF
=PP1V05_S5_MCP
20%
6.3V
CERM
805
XW7710
SM
Vout = 1.052V
5A max output
2
XW7775
2
1
C7776
(L7770 limit)
f = 400 kHz
4.7UF
SM
20%
4V
X5R
402
CRITICAL
C7771
330UF
20%
2.0V
POLY-TANT
B2-SM
P1V05S5_VSNS
1
VO
<Ra>
R7780
3.74K
1%
1/16W
MF-LF
2 402
Misc Power Supplies

SYNC_MASTER=RXU_K20
(GND)
<Rb>
1
R7781

4.42K
XW7750
SM
1
1%
1/16W
MF-LF
402

GND_P1V05S5_SGND
VOLTAGE=0V
SIZE
Vout = 0.6V * (1 + Ra / Rb)
(P1V05S5_VFB)
DRAWING NUMBER
D
APPLE INC.
(=PP1V05_S5_REG)
REV.
051-7656
SCALE
SHT
NONE
Current = 1.2A
FREQ = 1Mhz
PLACEMENT_NOTE=Place XW7775 next to C7775

2
CRITICAL
P1V05S5_DRVL
GATE_NODE=TRUE
4 P1V5EXPS0_FB
Vout = 1.5V
PCMB065T-SM
PWRPK-1212-8-HF
=PP1V5_EXP_S0
<Ra>
1 C7712
R7710
22PF
150K
1
L7770
1
0.22UF
VOUT = 0.6V * (1 + Ra / Rb)
2.2UH-8.0A
SI7108DN
G
1%
1/16W
MF-LF
402
PCAA031B-SM
1 P1V5EXPS0_SW1
P1V5EXPS0_SGND
CRITICAL
TP_P1V5_EXP_S0_PGOOD
86.6K
2
L7710
10%
10V
CERM
402
BQA
C7770
PG
402
Q7771
P1V05S5_DRVH
33UF
2.2UH-1.2A
AGND PGND THRM_PAD
PWRPK-1212-8-HF
2.0K
10%
16V
X5R
603
U7710FB
TPS62510
7 MODE
SI7110DN
20%
6.3V
CERM
805
AVINPVIN
Q7770
R7796
C7710
22UF
CRITICAL SW
6 EN
=P1V5_EXP_S0_EN
5%
1/16W
MF-LF
402
CRITICAL
17
470PF
10%
50V
CERM
402
10%
25V
X5R
603-1
C7798
20%
2 16V
POLY-TANT
CASED2E-SM
VOUT = 0.8V * (1 + RA / RB)
P1V5EXPS0_AVIN
C7775
1UF
THRML
PAD
P1V05S5_COMP_R
C7754
QFN
EN
FCCM
PGOOD
COMP
22PF
100K
4
3
67
VCC
PVCC
12
C7751
1UF
2
P1V05S5_ISEN
VOLTAGE=5V
20%
2 16V
POLY-TANT
CASED2E-SM
CRITICAL
R7712
VI
U7760
8 23
C7799
33UF
<Rb>
=PP3V3_S3_P1V5EXPS0
1.8V S0 Switcher
C7760
10%
16V
X5R
402
EXPRESSCARD 1.5V_S0 SUPPLY
1%
1/16W
MF-LF
2 402
INPUT RAIL IS 3.3V S0
1UF
PFWBOOST_FB
40.2K
=PP3V3_GPU_P1V8S0
C7794
1UF
10%
6.3V
CERM
402
P1V05_S0_MCP_PLL_UF_ADJ
1%
1/4W
MF-LF
1206
Vout = 1.052V
66.5K
5%
50V
CERM
402
SUPERSOT-6
Q7790
F=550KHZ?
R7795
1.00M
33PF
FDC796NG
C7795
CRITICAL
NGATE 6
MAX CURRENT = 300MA
OUT
1UF
8
5%
1/16W
MF-LF
2 402
<Ra>
1
STPS1L30MF
PFWBOOST_NGATE
a
n
i
1 BIAS CRITICAL
8
10%
50V
CERM
402
R7742
LTC3025
20%
4V
X5R
402
y
r
3 VFB
1%
1/16W
MF-LF
402
0.0012UF
10%
6.3V
CERM
402
C7705
280K
C7797
=PP1V05_S0_FET
68 8
?MA MAX OUTPUT
GND
4.7UF
R7701
SOT23-6
VOUT = 10V
D7790
DO222-SM
PFWBOOST_SENSE
PFWBOOST_ITH_R
1UF
(Switcher limit)
<Rb>
=P1V8S0_EN
2 PP3V3_S0_MCP_PLL_VLDO_BIAS
C7740
562K
100
0.3A max output
P1V8S0_VFB
IN
VOUT = 1.804V
PCAA031B-SM
GND
5%
1/16W
MF-LF
402
10PF
67
L7700
R7743
8
SENSE- 4
LTC1872
R7797
38.3K
1%
1/16W
MF-LF
2 402
P1V8S0_LX
SWITCH_NODE=TRUE
1 ITH/RUN
LTC3547
DFN-HF
280K
CRITICAL
THRML
PAD
20%
4V
X5R
402
CRITICAL
VIN
U7700
8
PFWBOOST_ITH
4.7UF
<Rb>
1
R7783
=PFWBOOST_REG 8
VIN
U7790
f = 2.25 MHz
1
C7785
P1V0FW_VFB
VFB1
VFB2
1%
1/16W
MF-LF
402
CRITICAL
10%
16V
X5R
1206
10UF
187K
10PF
C7790
MCP79 PLL VLDO
300mA max output
10
PCMC063T-SM
11
C7782
5%
50V
CERM
402
PFWBOOST_SW
SWITCH_NODE=TRUE
PFWBOOST_BOOST
Vout = 1.001V
<Ra>
R7782
2
PCAA031B-SM
SWITCH_NODE=TRUE
20%
6.3V
CERM
402-LF
P1V0FW_SW
2.2UF
2
4
C7700
=PP1V0_FW_REG
=PP3V3_S3_P1V8S0
L7795
4.7UH-10A
1
3
=PPVIN_PFWBOOST
L7780
8
CRITICAL
0.5%
1W
MF
0612
S5 power required for output discharge feature
31
OF
77
123
State
SMC_PM_G2_ENABLE
PM_SLP_S4_L
Run (S0)
Sleep (S3)
Soft-Off (S5)
Battery Off (G3Hot)
5
PM_SLP_S3_L
3.3V 1,05V S5 ENABLE
3.3V,5V S3 ENABLE
R7802
P3V3S5_EN
5%
1/16W
MF-LF
402
OUT
62
42 41 39 21
IN
R7810
0.068UF
10%
10V
CERM
R7811
100K
5.1K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
1
2
R7812
5%
1/16W
MF-LF
402
PLACEMENT_NOTE=near U7201
S5 rail PWRGD
SMC_PM_G2_EN
P5VS3_EN
8
R7858
=PP3V42_G3H_PWRCTL
67 8
C7840
R7801
MF-LF
402
20%
PM_G2_P1V05S5_EN
=P1V05S5_EN
MAKE_BASE=TRUE
OUT
CERM
66
C7801
1/16W
MF-LF
VDD
C7810
0.47UF
5%
402
5%
1/16W
MF-LF
402
402
5 SENSE
10%
6.3V
CERM-X5R
CERM-X5R
402
10%
6.3V
RESET* 1
RSMRST_PWRGD
MR* 3
SOT23-6
P1V05_S5_PGOOD
66
0.001UF
a
n
i
20%
50V
402
Other S0 RAILS
S0 ENABLE
67 8 =PP3V3_S0_PWRCTL
PM_SLP_S3_L_R
MAKE_BASE=TRUE
22K
2
5%
1/16W
MF-LF
402
33K
5%
1/16W
MF-LF
402
R7885
R7886
10K
5%
1/16W
MF-LF
402
5.1K
5%
1/16W
MF-LF
402
OUT
64
=P3V3S0_EN
OUT
68
10K
45
5%
1/16W
MF-LF
402
=PBUSVSENS_EN
OUT
5%
1/16W
MF-LF
402
PLACEMENT_NOTE=nearU9900
PLACEMENT_NOTE=nearQ7971
P2V5S0_EN
=P2V5S0_EN
OUT
MAKE_BASE=TRUE
100K
5%
1/16W
MF-LF
402
P1V2_S0_EN
=P1V2S0_EN
OUT
MAKE_BASE=TRUE
P1V05S0_EN
P1V8S0_EN
=P1V8S0_EN
MAKE_BASE=TRUE
MCPDDR_EN
=MCPDDR_EN
OUT
66
MAKE_BASE=TRUE
MCPCORES0_EN
MAKE_BASE=TRUE
NO STUFF
Unused PGOOD signal

DDRREG_PGOOD
63
0.47UF
10%
6.3V
CERM-X5R
402
MAKE_BASE=TRUE
C7881
0.47UF
2
TP_DDRREG_PGOOD
C7880
C7882
0.47UF
10%
6.3V
CERM-X5R
CERM-X5R
5%
MF-LF
EG_PWRSEQ_HW
R7852
402
1/16W
P1V1_GPU_EN_RC
10K
EG_PWRSEQ_HW
R7850
402
1/16W
EG_PWRSEQ_HW
D
Q7850
5% MF-LF 402
NO STUFF
C7850
IN EXTGPU_PWR_EN
EG_PWRSEQ_HW
Q7850
0.022UF
20%
16V
CERM
402
SSM6N15FEAPE
SOT563
R7853
GPU_S0_EN_L
100K
5%
1/16W
MF-LF
402
GPUVCORE_EN_RC_L
MAKE_BASE=TRUE
GPUVCORE ENABLE
EG_PWRSEQ_HW
EG_PWRSEQ_HW
67 8
R7863
=PP3V3_GPU_PWRCTL
1
1/16W
MF-LF 402
GPUVCORE_EN
MF-LF 402
0
EG_PWRSEQ_HW
Q7861
OUT
EG_PWRSEQ_HW
C7861
83 84
P
67
=GPUVCORE_EN
MAKE_BASE=TRUE
1/16W 5%
100K
R7864
GPUVCORE_EN_RC
2
5%
=P1V1GPU_EN
MAKE_BASE=TRUE
OUT
77
GPUVCORE_PGOOD
EG_PWRSEQ_HW
Q7861
SSM6N15FEAPE
16V
64
IN
P5V_RTS0_PGOOD
62
IN
P5V3V3_PGOOD
5%
1/16W
MF-LF
402
0.1UF
2
S0_PWR_PGOOD
5 TC7SZ08AFEAPE
2
SOT665
R7891
U7880
PM_ALL_GPU_PGOOD
67 9
ALL_GFX_PGOOD_R
ALL_SYS_PWRGD
OUT
25 41 84
5%
1/16W
MF-LF
402
3.3V 1.05V AND 1.5V S0 RAILS MONITOR CIRCUIT

place XW0402 if needed to save trace space for pin 7,8
EG_PWRSEQ_HW
R7869
P1V8_S0GPU_EN
1/16W
5%
=P1V8FB_EN
OUT
67 8 =PP3V3_S0_VMON
66 83 84
CLOSE TO U7870 & U7871
MAKE_BASE=TRUE
C7870
MF-LF 402
0.1uF
G96 GPU requires rails to come
20%
10V
CERM
402
up in the following order:
NO STUFF
C7869
VCC
1) 1.1V
2) GPU_3.3V
0.022UF
U7870
20%
16V
CERM
3) GPUVcore
LTC2909
1
4) GDDR3 1.8V
402
SEL
BOMOPTION: EG
4
67 8
=PP1V5_S0_VMON
NC
67 8
=PP1V05_S0_VMON
8
7
ADJ1
ADJ2
REF
DFN
NO STUFF
GND
TMR
RST*
TIE TMR TO GND

TRST = 200MS
S0PGOOD_PWROK
67
THRM_PAD
=PP3V3_S0_VMON
67 8
EXT GPU PWRGD Pullup
77 84
LTC2909 THRESHOLD IS 3.136V

1.5V 1.05V COMPARED TO 0.5V
U7871
Power Control
ISL88042IRTEZ
TDFN
=PP3V3_S0_PWRCTL
67 8
67 8
=PP3V3_S0_PWRCTL
EG_PWRSEQ_HW 1
R7889
5%
1/16W
MF-LF
402
402
R7890
67 8
=PP3V3_S0_VMON
67 8
=PP1V5_S0_VMON
67 8
=PP1V05_S0_VMON
3 V2MON
5 V3MON
6 V4MON
GND
100K
5%
1/16W
MF-LF
402
20%
10V
CERM
402
NO STUFF
Graphic MEM ENABLE
P1V8S0_PGOOD
C7889
VDD
10%
CERM
64
402
SOT563
0.01UF
SOT563
GPUVCORE_EN_RC_L
65
OUT
CERM-X5R
IN
MR*
SYNC_MASTER=YMA_K20
V2MON THRESHOLD IS 2.866V


RST*
S0PGOOD_PWROK
67

THRM_PAD

EG_PWRSEQ_HW
NC
100K
SSM6N15FEAPE
67
OUT
10%
6.3V
R7894
MAKE_BASE=TRUE
=MCPCORES0_EN
C7886
CPUVTTS0_PGOOD
2
MF-LF 402
5%
CERM-X5R
402
100K
P1V1_GPU_EN
84
1/16W
8 67
68
=CPUVTTS0_EN
0.47UF
10%
6.3V
=PP3V3_S5_PWRCTL
P1V8_S0GPU_EN_RC
SOT563
CERM-X5R
402
=PP3V3_GPU_PWRCTL
SSM6N15FEAPE
100K
R7868
67 8
5%
1/16W
MF-LF
402
0.47UF
10%
6.3V
EG_PWRSEQ_HW
67 8 =PP3V3_S5_PWRCTL
CERM-X5R
C7885
IN
e
r
1.1V GPU ENABLE
C7884
0.47UF
10%
6.3V
EG_PWRSEQ_HW
R7851
=PP3V3_S0_PWRCTL
C7883
402
402
0.47UF
10%
6.3V
67 8
IN
65
NO STUFF
OUT
64
MCPCORES0_PGOOD
87
68
m
il
MAKE_BASE=TRUE
CPUVTTS0_EN
87
OUT
PM_ALL_GPU_PGOOD
S0PGOOD_PWROK
67
5%
1/16W
MF-LF
402
=P5V_RTS0_EN
R7892
R7884
10K
5%
1/16W
MF-LF
402
R7879
5%
1/16W
MF-LF
402
R7883
high
EG
R7882
IN
R7881
IG
100
PM_SLP_S3_L
84 82 41 36 33 21 7
R7880
R7878
PM_ALL_GFX_PGOOD
(PM_SLP_S3_L)
63
41
TPS3808 MR* HAS INTERNAL PULLUP
GND
C7841 1
CERM
OUT
MAKE_BASE=TRUE
CERM-X5R
402
U7840
4 CT
CT
62
C7812
TPS3808G33DBVRG4
402
OUT
=DDRREG_EN
0.47UF
10%
6.3V
0.47UF
DDRREG_EN
NO STUFF
R7840
100K
10V
0.1uF
5.1K
2
y
r
5%
1/16W
=P5VS3_EN
MAKE_BASE=TRUE
=PP3V3_S5_PWRCTL
100K
68
OUT
IN
402
41
=P3V3S3_EN
MAKE_BASE=TRUE
NO STUFF
C7802
(PM_S4_STATE_L)
PM_SLP_S4_L
100
2
R7888
83
P1V1GPU_PGOOD
P3V3GPU_EN
1
1/16W
OUT
68 84
83
P1V8FB_PGOOD
PM_ALL_GPU_PGOOD
MAKE_BASE=TRUE
OUT
9 67
SIZE
U7871 IS TO REPLACE U7870
5% MF-LF 402
DRAWING NUMBER
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
78
123
3.3V S0 FET
3.3V S3 FET
CRITICAL
CRITICAL
Q7910
Q7930
FDC638P_G
FDC606P_G
=PP3V3_S0_FET
SOT-6
SM
=PP3V3_S3_P3V3S3FET
=PP3V3_S0_P3V3S0FET
=PP3V3_S3_FET
6
FDC638P
CHANNEL
P-TYPE
Q7912
5%
1/16W
SSM6N15FEAPE
402
P3V3S3_EN_L
48 mOhm @4.5V
P3V3S3_SS
LOADING
0.087 A (EDP)
67
5%
IN
=P3V3S0_EN
MF-LF
16V
402
CERM
5%
CERM
402
402
=PP1V05_S5_P1V05S0FET
a
n
i
=PP3V3_GPU_P3V3GPUFET
CRITICAL
Q7953
220K
=PP5V_S3_P1V05S0FET
R7972
1.05V S0 FET
APN 376S0651
MOSFET
SI7108DN
=PP3V3_S5_P1V05FET
Q7951
5%
1/16W
MF-LF
402
100K
84 67
1
1
8 66
5%
1/16W
MF-LF
402
C7953
0.068UF
10%
10V
CERM
402
P1V05_EN_L_RC
SSM6N15FEAPE
SOT563
67
1.5V S0 FET
=PP1V8R1V5_S0_MCP_FET
C7902
APN 376S0651
0.1UF
20%
10V
CERM
402
R7901
=PP5V_S3_MCPDDRFET
10K
1
R7903
MCPDDR_SS
Q7901
5%
1/16W
MF-LF
402
Q7971
100K
SSM6N15FEAPE
SOT563
2
2
R7971
1
SI7108DN
2
5%
1/16W
MF-LF
402
SSM6N15FEAPE
MOSFET
67
IN
LOADING
1.1 A (EDP)
10%
CERM
402
402
=PPVTT_S0_VTTCLAMP
R7975
SI7108DN
90mA max load @ 0.9V

81mW max power
10
5%
1/16W
MF-LF
402
CHANNEL
N-TYPE
RDS(ON)
5 mOhm @4.5V
LOADING
5.4 A (EDP)
VTTCLAMP_L
8
=PP5V_S3_VTTCLAMP
Q7975
R7976
SSM6N15FEAPE
SOT563
100K
5%
1/16W
MF-LF
402
Power FETs
2
SYNC_MASTER=YMA_K20
VTTCLAMP_EN
C7903
10%
10V
CERM
402
Q7975
20%
50V
CERM
402
MCPDDR_EN_L_RC
0.001UF
SOT563
IN

NO STUFF
C7976
SSM6N15FEAPE
16V
MF-LF
63 9
0.01UF
P3V3GPU_SS
MCP79 DDR FETs
SOT563

SIZE
=DDRVTT_EN
DRAWING NUMBER
=MCPDDR_EN
APPLE INC.
REV.
051-7656
SCALE
SHT
NONE
26 mOhm @4.5V
1.5V S0 FET
=PP1V8R1V5_S0_FET
P-TYPE
MCP79 DDR pad leakage is high enough that nVidia recommends unpowering during sleep.
In order to support unpowering rail, hardware must guarantee MEM_CKE signals are low
before rail is turned off, and remains low until after rail turns back on or DIMMs
will exit self-refresh prematurely. MEM_VTT_EN output from MCP79 used to enable clamp
on VTT rail, which pulls all CKE signals low through VTT termination resistors.
FDC606P
CHANNEL
RDS(ON)
C7970
1/16W
PWRPK-1212-8-HF
MOSFET
0.068UF
47K
MCPDDR_EN_L
Q7971
P3V3GPU_EN
5%
1/16W
MF-LF
402
CRITICAL
IN
e
r
P1V05S0_EN
IN
3.3V GPU FET
5%
SSM3K15FV
m
il
=PP1V05_S0_FET
402
Q7972
5.1 A (EDP)
R7951
Q7951
=PP3V3_S0GPU_FET
1K
SOT563
P1V05_EN_L
FDC606P_G
SOD-VESM-HF
SSM6N15FEAPE
10K
Q7970
SOT-6
R7970
5 mOhm @4.5V
LOADING
CRITICAL
P3V3GPU_EN_L
R7953
X5R
MF-LF
N-TYPE
RDS(ON)
8
10%
10V
402
CHANNEL
1UF
1/16W
C7971
5%
PWRPK-1212-8-HF
5%
1/16W
MF-LF
402
51K
SI7108DN
P1V05S0_SS
2.9 A (EDP)
16V
MF-LF
1.05V S0 FET
R7952
26 mOhm @4.5V
10%
1/16W
3.3V GPU FET
RDS(ON)
LOADING
402
2
1
y
r
1
P3V3S0_SS
10%
1/16W
C7930
0.01UF
47K
P3V3S0_EN_L
=P3V3S3_EN
IN
67
R7930
RDS(ON)
0.01UF
47K
P-TYPE
R7910
1
FDC606P
CHANNEL
402
C7910
MOSFET
402
X5R
MF-LF
SOT563
3.3V S0 FET
10%
16V
402
MOSFET
C7931
0.033UF
X5R
100K
10%
16V
5%
MF-LF
10K
1/16W
SOT563
0.033UF
Q7912
SSM6N15FEAPE
R7932
R7912
6
3.3V S3 FET
C7911
5
4
1
31
OF
79
123
OMIT
Page Notes
U8000
NB9P-GS
BGA
- =PP1V2_GPU_PEX_PLLXVDD
- =PP1V2_GPU_PEX_IOVDDQ
90 9
IN
C8020
PEG_R2D_C_P<0>
0.1uF
90
10% 16V X5R 402 90
- =PP1V2_GPU_PEX_IOVDD
90 9
IN
C8021
PEG_R2D_C_N<0>
0.1uF
AP17
PEG_R2D_P<0>
PEG_R2D_N<0>
AN17
SYMBOL 1 OF 9
PEX_RX0
PEX_TX0
PEX_RX0*
PEX_TX0*
AL17
AM17
90
90
PEG_D2R_C_P<0>
PEG_D2R_C_N<0>
(NONE)
90 9
IN
C8022
PEG_R2D_C_P<1>
0.1uF
90 9
IN
C8023
PEG_R2D_C_N<1>
0.1uF
90
AN19
PEG_R2D_P<1>
PEG_R2D_N<1>
AP19
PEX_RX1
PEX_RX1*
PEX_TX1
PEX_TX1*
AM18
90
AM19
90
PEG_D2R_C_P<1>
PEG_D2R_C_N<1>
8
8
=PP1V1_GPU_PEX_PLLXVDD
=PP1V1_GPU_PEX_IOVDDQ
=PP1V1_GPU_PEX_IOVDD
90 9
IN
PEG_R2D_C_P<2>
90 9
IN
PEG_R2D_C_N<2>
C8024
0.1uF
0.1uF
90
AR19
PEG_R2D_P<2>
PEG_R2D_N<2>
AR20
PEX_RX2
PEX_RX2*
PEX_TX2
PEX_TX2*
AL19
AK19
90
90
PEG_D2R_C_P<2>
PEG_D2R_C_N<2>
IN
C8026
PEG_R2D_C_P<3>
0.1uF
90
10% 16V X5R 402 90

90 9
IN
C8027
PEG_R2D_C_N<3>
0.1uF
AP20
PEG_R2D_P<3>
PEG_R2D_N<3>
AN20
PEX_RX3
PEX_RX3*
PEX_TX3
PEX_TX3*
AL20
AM20
90
90
PEG_D2R_C_P<3>
PEG_D2R_C_N<3>
2
10% 16V X5R 402
90 9
IN
C8028
PEG_R2D_C_P<4>
0.1uF
90
10% 16V X5R 402 90

90 9
IN
C8029
PEG_R2D_C_N<4>
0.1uF
AN22
PEG_R2D_P<4>
PEG_R2D_N<4>
AP22
90 9
IN
C8030
PEG_R2D_C_P<5>
0.1uF
90
10% 16V X5R 402 90

250mA
90 9
IN
C8031
PEG_R2D_C_N<5>
0.1uF
C8002
1UF
2
NC_GPU_DFM
C8001
4.7UF
10%
6.3V
CERM
402
90 9
C8000
IN
AR23
22UF
20%
6.3V
CERM
603
20%
6.3V
CERM-X5R
805
90 9
90 9
U8000
M7
P6
P7
NC
R7
NC
U7
NC
V6
NC
AB7
NC
AD6
NC
AF6
NC
AG6
NC
AJ5
NC
D35
NC
AK15
NC
AL7
NC E7
NC
E35
NC
F7
NC
A2
NC
C8003
1UF
BGA
H32
90
IN
C8033
PEG_R2D_C_N<6>
0.1uF
2
AK16
C8004
0.1UF
10%
6.3V
CERM
402
IN
C8034
PEG_R2D_C_P<7>
0.1uF
90 9
C8005
IN
C8035
PEG_R2D_C_N<7>
0.1uF
AN23
90
AN25
PEG_R2D_P<7>
PEG_R2D_N<7>
AP25
2
10% 16V X5R 402
0.1UF
20%
10V
CERM
402
AP23
PEG_R2D_P<6>
PEG_R2D_N<6>
10% 16V X5R 402 90
NB9P-GS
NC
NC
10% 16V X5R 402
OMIT
SYMBOL 2 OF 9
PEX_IOVDD1
PEX_IOVDD2
PEX_IOVDD3
PEX_IOVDD4
PEX_IOVDD5
0.1uF
10% 16V X5R 402 90
NO_TEST=TRUE
C8032
PEG_R2D_C_P<6>
20%
10V
CERM
402
IN
PEG_R2D_C_P<8>
C8036
0.1uF
90 9
IN
PEG_R2D_C_N<8>
C8037
0.1uF
90 9
90
10% 16V X5R 402 90
AK17
AK21
AR25
PEG_R2D_P<8>
PEG_R2D_N<8>
AR26
10% 16V X5R 402
AK24
90 9
AK27
IN
C8038
PEG_R2D_C_P<9>
0.1uF
90
10% 16V X5R 402 90
1500mA
90 9
IN
AP26
PEG_R2D_P<9>
PEG_R2D_N<9>
AN26
m
il
PEG_R2D_C_N<9>
C8039
0.1uF
10% 16V X5R 402
PEX_IOVDDQ1
PEX_IOVDDQ2
PEX_IOVDDQ3
PEX_IOVDDQ4
PEX_IOVDDQ5
PEX_IOVDDQ6
PEX_IOVDDQ7
PEX_IOVDDQ8
PEX_IOVDDQ9
PEX_IOVDDQ10
PEX_IOVDDQ11
PEX_IOVDDQ12
PEX_IOVDDQ13
PEX_IOVDDQ14
PEX_IOVDDQ15
PEX_IOVDDQ16
PEX_IOVDDQ17
PEX_IOVDDQ18
PEX_IOVDDQ19
PEX_IOVDDQ20
PEX_IOVDDQ21
PEX_IOVDDQ22
PEX_IOVDDQ23
PEX_IOVDDQ24
PEX_IOVDDQ25
NC
PEX_PLLVDD
AG11
AG12
AG13
C8008
C8007
C8006
1UF
4.7UF
22UF
10%
6.3V
CERM
402
20%
6.3V
CERM
603
20%
6.3V
CERM-X5R
805
90 9
IN
PEG_R2D_C_P<10>
90 9
IN
PEG_R2D_C_N<10>
90 9
AG17
1
AG18
C8009
1UF
AG22
2
AG23
C8010
0.1UF
10%
6.3V
CERM
402
PEG_R2D_C_P<11>
C8011
0.1UF
20%
10V
CERM
402
IN
90 9
20%
10V
CERM
402
IN
PEG_R2D_C_N<11>
C8041
0.1uF
90 9
IN
PEG_R2D_C_P<12>
e
r
AG26
90 9
L8015
AJ14
180mA
10NH-600MA
1
PP1V1_GPU_PEX_PLLVDD_F
VOLTAGE=1.2V
AJ24
AJ25
AJ27
90 9
2
0603
C8017
C8016
0.1UF
4.7UF
20%
10V
CERM
402
20%
6.3V
CERM
603
C8015
4.7UF
20%
6.3V
CERM
603
AK18
90 9
90 9
90 9
AK20
AK23
90 9
AK26
AL16
AG14
VDD_SENSE
AD20
GPU_VDD_SENSE
77
GND_SENSE
AD19
GPU_GND_SENSE
77
C8042
0.1uF
C8043
0.1uF
AM21
AM22
90
90
PEG_D2R_C_P<4>
PEG_D2R_C_N<4>
90
PEG_R2D_P<10>
PEG_R2D_N<10>
90
PEG_R2D_P<11>
PEG_R2D_N<11>
AN28
AP28
AR28
AR29
PEX_RX5
PEX_RX5*
PEX_RX6
PEX_RX6*
PEX_RX7
PEX_RX7*
PEX_RX8
PEX_RX8*
PEX_RX9
PEX_RX9*
PEX_RX10
PEX_RX10*
PEX_RX11
PEX_RX11*
PEX_TX5
PEX_TX5*
PEX_TX6
PEX_TX6*
PEX_TX7
PEX_TX7*
PEX_TX8
PEX_TX8*
PEX_TX9
PEX_TX9*
PEX_TX10
PEX_TX10*
PEX_TX11
PEX_TX11*
AL22
90
AK22
90
AL23
90
AM23
90
AM24
AM25
90
90
AL25
90
AK25
90
AL26
90
AM26
90
AM27
AM28
AL28
AK28
90
90
90
90
PEG_D2R_C_P<5>
PEG_D2R_C_N<5>
PEG_D2R_C_P<6>
PEG_D2R_C_N<6>
PEG_D2R_C_P<7>
PEG_D2R_C_N<7>
PEG_D2R_C_P<8>
PEG_D2R_C_N<8>
PEG_D2R_C_P<9>
PEG_D2R_C_N<9>
PEG_D2R_C_P<10>
PEG_D2R_C_N<10>
PEG_D2R_C_P<11>
PEG_D2R_C_N<11>
10% 16V X5R 402
AG25
AJ22
10% 16V X5R 402 90
AG24
AJ21
10% 16V X5R 402
AG16
AJ19
0.1uF
10% 16V X5R 402 90
AG15
AJ15
C8040
PEX_TX4
PEX_TX4*
a
n
i
AR22
PEG_R2D_P<5>
PEG_R2D_N<5>
10% 16V X5R 402
PEX_RX4
PEX_RX4*
2
10% 16V X5R 402
PEX 1.1V Current = 2A
90 9
90 17
90 17
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
PEG_R2D_C_N<12>
PEG_R2D_C_P<13>
PEG_R2D_C_N<13>
PEG_R2D_C_P<14>
PEG_R2D_C_N<14>
PEG_R2D_C_P<15>
PEG_R2D_C_N<15>
C8044
0.1uF
90
10% 16V X5R 402 90
C8045
0.1uF
PEG_R2D_P<12>
PEG_R2D_N<12>
0.1uF
90
10% 16V X5R 402 90
C8047
0.1uF
AN29
PEX_RX12
PEX_RX12*
PEX_TX12
PEX_TX12*
AK29
90
AL29
90
PEG_D2R_C_P<12>
PEG_D2R_C_N<12>
0.1uF
C8049
0.1uF
90
10% 16V X5R 402 90
PEG_R2D_P<13>
PEG_R2D_N<13>
AN31
AP31
PEX_RX13
PEX_RX13*
PEX_TX13
PEX_TX13*
AM29
90
AM30
90
PEG_D2R_C_P<13>
PEG_D2R_C_N<13>
90
10% 16V X5R 402 90
C8051
0.1uF
C8059
0.1uF
PEG_R2D_P<14>
PEG_R2D_N<14>
AR31
AR32
PEG_R2D_P<15>
PEG_R2D_N<15>
AR34
AP34
C8060
0.1uF
PEG_D2R_P<1>
OUT
9 90
PEG_D2R_N<1>
OUT
9 90
PEG_D2R_P<2>
OUT
9 90
PEG_D2R_N<2>
OUT
9 90
0.1uF
C8062
0.1uF
C8063
0.1uF
C8064
0.1uF
C8065
0.1uF
C8066
0.1uF
C8067
0.1uF
C8068
0.1uF
C8069
0.1uF
C8070
0.1uF
C8071
0.1uF
PEG_D2R_P<3>
OUT
9 90
PEG_D2R_N<3>
OUT
9 90
PEG_D2R_P<4>
OUT
9 90
PEG_D2R_N<4>
OUT
9 90
PEG_D2R_P<5>
OUT
9 90
PEG_D2R_N<5>
OUT
9 90
PEG_D2R_P<6>
OUT
9 90
PEG_D2R_N<6>
OUT
9 90
PEG_D2R_P<7>
OUT
9 90
PEG_D2R_N<7>
OUT
9 90
PEG_D2R_P<8>
OUT
9 90
PEG_D2R_N<8>
OUT
9 90
PEG_D2R_P<9>
OUT
9 90
PEG_D2R_N<9>
OUT
9 90
PEG_D2R_P<10>
OUT
9 90
PEG_D2R_N<10>
OUT
9 90
PEG_D2R_P<11>
OUT
9 90
PEG_D2R_N<11>
OUT
9 90
PEG_D2R_P<12>
OUT
9 90
PEG_D2R_N<12>
OUT
9 90
PEG_D2R_P<13>
OUT
9 90
PEG_D2R_N<13>
OUT
9 90
PEG_D2R_P<14>
OUT
9 90
PEG_D2R_N<14>
OUT
9 90
PEG_D2R_P<15>
OUT
9 90
PEG_D2R_N<15>
OUT
9 90
10% 16V X5R 402

2
10% 16V X5R 402
10% 16V X5R 402
10% 16V X5R 402
10% 16V X5R 402
10% 16V X5R 402
10% 16V X5R 402
10% 16V X5R 402
10% 16V X5R 402

2
10% 16V X5R 402
2
10% 16V X5R 402

2
10% 16V X5R 402
C8072
0.1uF
C8073
0.1uF
C8074
0.1uF
2
10% 16V X5R 402
10% 16V X5R 402
10% 16V X5R 402
C8075
0.1uF
C8076
0.1uF
10% 16V X5R 402
10% 16V X5R 402
C8077
0.1uF
C8078
0.1uF
C8079
0.1uF
C8080
0.1uF
C8081
0.1uF
C8082
0.1uF
10% 16V X5R 402
10% 16V X5R 402
10% 16V X5R 402
10% 16V X5R 402
PEX_RX14
PEX_RX14*
PEX_TX14
PEX_TX14*
AM31
90
AM32
90
PEG_D2R_C_P<14>
PEG_D2R_C_N<14>
C8083
0.1uF
C8084
0.1uF
10% 16V X5R 402
PEX_RX15
PEX_RX15*
PEX_TX15
PEX_TX15*
AN32
AP32
90
90
PEG_D2R_C_P<15>
PEG_D2R_C_N<15>
C8085
0.1uF
C8086
0.1uF
10% 16V X5R 402
10% 16V X5R 402
R8060
PEX_REFCLK
PEX_REFCLK*
PEX_TSTCLK_OUT
PEX_TSTCLK_OUT*
AJ17
AJ18
PEX_TSTCLK_P
PEX_TSTCLK_N
GPU_RESET_R_L
7
TP_PEX_CLKREQ_L
AM16
PEX_RST*
AR13
PEX_CLKREQ*
PEX_TERMP
AG21
PEX_RFU1
AG19
PEX_RFU2
AG20
NC
NC
PEX_TERMP_PD
2.49K
200
1%
1/16W
MF-LF
402
R8050
0
9 90
10% 16V X5R 402
C8061
AR17
5%
1/16W
MF-LF
402
OUT
10% 16V X5R 402
AR16
PEG_D2R_N<0>
10% 16V X5R 402
10% 16V X5R 402
R8020
9 90
10% 16V X5R 402
10% 16V X5R 402
C8048
0.1uF
0.1uF
OUT
10% 16V X5R 402
10% 16V X5R 402
C8050
C8058
PEG_CLK100M_P
PEG_CLK100M_N
GPU_RESET_L
AP29
10% 16V X5R 402
C8046
C8057
0.1uF
PEG_D2R_P<0>
10% 16V X5R 402
y
r
2
10% 16V X5R 402
90 9
10% 16V X5R 402
10% 16V X5R 402 90
C8025
2
10% 16V X5R 402
0.1uF
10% 16V X5R 402
10% 16V X5R 402 90
(NONE)
0.1uF
C8056
2
10% 16V X5R 402
C8055
1%
1/16W
MF-LF
402
NV G96 PCI-E
SYNC_MASTER=M98_MLB

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
80
123
Page Notes
OMIT
U8000
U8000
- =PPVCORE_GPU
NB9P-GS
BGA
NB9P-GS
- =PP1V8_GPU_FBVDDQ
B3
BGA

8
=PPVCORE_GPU
(NONE)
???A @ ???/???MHz Core/Mem Clk for VDD
(NONE)
1
L12
V21
B9
V22
L13
V23
B12
V24
L14
V25
B15
V31
SYMBOL 9 OF 9
C8102
L15
W11
B21
Y11
4.7UF
4.7UF
L16
W12
B24
Y13
20%
6.3V
20%
6.3V
L17
W13
B27
Y15
L18
W14
B30
Y17
L19
W15
B33
Y19
L20
W16
C2
Y21
L21
W17
C34
Y23
L22
W18
E6
Y25
L23
W19
E9
AA2
L24
AD24
E12
AA5
L25
W21
E15
AA11
X5R-CERM
C8103
C8101
X5R-CERM
402
402
C8104
C8105
C8106
C8107
0.47UF
0.47UF
0.47UF
0.47UF
10%
6.3V
10%
6.3V
10%
6.3V
10%
6.3V
10%
6.3V
M12
W22
E18
AA12
CERM-X5R
M14
W23
E24
AA13
M16
W24
E27
AA14
M18
W25
E30
AA15
M20
Y12
F2
AA16
CERM-X5R
CERM-X5R
402
CERM-X5R
402
CERM-X5R
402
C8112
M22
Y14
0.47UF
0.47UF
0.47UF
0.47UF
M24
Y16
10%
6.3V
10%
6.3V
10%
6.3V
10%
6.3V
10%
6.3V
P11
Y18
P13
Y20
P15
Y22
P17
Y24
CERM-X5R
C8109
CERM-X5R
402
C8110
CERM-X5R
402
C8111
CERM-X5R
402
402
C8116
C8117
0.1UF
0.1UF
0.1UF
0.1UF
20%
10V
20%
10V
20%
10V
20%
10V
20%
10V
CERM
C8118
CERM
402
CERM
402
C8119
C8120
CERM
402
C8121
P25
AB17
R11
AB19
R12
AB21
R13
AB23
C8122
R14
AB25
CERM
402
0.1UF
0.1UF
0.1UF
0.1UF
R15
AC11
20%
10V
20%
10V
20%
10V
20%
10V
20%
10V
R16
AC12
R17
AC13
R18
AC14
R19
AC15
R20
AC16
R21
AC17
CERM
CERM
402
CERM
402
CERM
402
402
m
il
e
r
C8150
4.7UF
20%
6.3V
603
C8158
C8159
C8160
CERM
C8161
0.1UF
0.1UF
0.1UF
0.47UF
0.47UF
20%
10V
20%
10V
20%
10V
20%
10V
10%
6.3V
10%
6.3V
402
C8162
402
CERM
CERM
C8169
C8164
CERM
C8170
CERM
C8171
0.47UF
0.47UF
0.47UF
10%
6.3V
10%
6.3V
10%
6.3V
10%
6.3V
402
CERM-X5R
402
CERM-X5R
402
CERM-X5R
C8166
CERM-X5R
402
C8167
CERM-X5R
AC19
R24
AC20
R25
AC21
T12
AC22
T14
AC23
T16
AC24
T18
AC25
T20
AD12
T22
AD14
T24
AA17
AA18
F34
AA19
J2
AA20
J5
AA21
J31
AA22
J34
AA23
L9
AA24
M2
AA25
M5
AA34
M13
AB12
AB14
M15
AB16
M17
AB18
M19
AB20
M21
AB22
M23
AB24
M25
AC9
M31
AD2
M34
AD5
N11
AD11
N12
AD13
N13
AD15
N14
AD17
N15
AD21
N17
GND
GND
AD25
AD31
N19
AD34
N20
AE11
N21
AE12
AD16
N22
AE13
V11
AD18
N23
AE14
V13
AD22
N24
AE15
V15
W20
N25
AE16
P12
AE17
P14
AE18
P16
AE19
P18
AE20
P20
AE21
P22
AE22
P24
AE23
R2
AE24
R5
AE25
U8000
NB9P-GS
AD23
N16
N18
OMIT
R31
AG2
R34
AG5
T11
AG31
T13
AG34
T15
AK2
T17
AK5
T19
AP33
T21
AK31
T23
AK34
T25
AL6
U11
AL9
U12
AL12
U13
AL15
U14
AL18
U15
AL21
U16
AL24
BGA
B18
SYMBOL 7 OF 9
J20
J17
J21
U27
J22
AB27
10%
6.3V
AC18
R23
V17
0.47UF
10%
6.3V
CERM-X5R
402
0.47UF
402
0.47UF
CERM-X5R
20%
10V
402
C8165
CERM-X5R
402
0.1UF
20%
10V
402
0.1UF
402
C8163
20%
10V
CERM
402
0.1UF
20%
10V
C8168
402
0.1UF
CERM
CERM
603
0.1UF
CERM
4.7UF
20%
6.3V
CERM
C8151
R22
F5
F31
M11
CERM
???A @ ???MHz 1.8V GDDR3
C8157
VDD
AB15
Nvidia PRD for GB-128 uses 4x4.7uF, 8x0.47uF, 16x0.1uF
C8156
AB13
VDD
P23
=PP1V8_GPU_FBVDDQ
AB11
P21
0.1UF
402
C8115
0.1UF
402
C8114
a
n
i
CERM-X5R
P19
C8113
y
r
402
0.47UF
C8108
X5R-CERM
0.47UF
402
V20
20%
6.3V
402
V18
B6
4.7UF
C8100
402
SYMBOL 8 OF 9
V19
L11
J23
AB29
J24
AC27
J29
AD27
N27
402
AE27
P27
AJ28
R27
E21
T27
FBVDDQ
G8
FBVDDQ
U29
G9
V27
G17
V29
G18
V34
U17
402
G22
AL27
U18
AL30
U19
AN2
U20
AN34
U21
AP3
U22
AP6
U23
AP9
U24
AP12
U25
AP15
V2
AP18
V5
AP21
V9
AP24
V12
AP27
V14
AP30
W27
H29
Y27
J14
AA27
J15
AA29
J16
AA31
NV G96 CORE/FB POWER

SYNC_MASTER=M98_MLB

SIZE
DRAWING NUMBER
V16
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
81
123
Page Notes
- =PP1V2_GPU_FBPLLAVDD
- =PP1V8_GPU_FBIO
OMIT
OMIT
(NONE)
U8000
NB9P-GS
(NONE)
95 79 72 7
BI
FB_A_DQ<0>
R30
FB_A_DQ<1>
R32
BI
FB_A_DQ<2>
95 79 72 7
N30
BI
FB_A_DQ<3>
95 79 72 7
FB_A_DQ<4>
L31
BI
95 79 72 7
FB_A_DQ<5>
M32
BI
M30
BI
FB_A_DQ<6>
95 79 72 7
L30
BI
FB_A_DQ<7>
95 79 72 7
BI
FB_A_DQ<8>
P33
95 79 72 7
BI
FB_A_DQ<9>
P34
95 79 72 7
N35
BI
FB_A_DQ<10>
95 79 72 7
FB_A_DQ<11>
P35
BI
95 79 72 7
FB_A_DQ<12>
N34
FB_A_DQ<13>
L33
BI
95 79 72 7
L32
BI
FB_A_DQ<14>
95 79 72 7
FB_A_DQ<15>
N33
BI
95 79 72 7
FB_A_DQ<16>
K31
BI
95 79 72 7
K30
BI
FB_A_DQ<17>
95 79 72 7
FB_A_DQ<18>
G30
BI
95 79 72 7
BI
FB_A_DQ<19>
K32
BI
FB_A_DQ<20>
G32
BI
FB_A_DQ<21>
95 79 72 7
BI
95 79 72 7
95 79 72 7
95 79 72 7
H30
95 79 72 7
FB_A_DQ<22>
F30
BI
95 79 72 7
FB_A_DQ<23>
G31
BI
95 79 72 7
FB_A_DQ<24>
H33
BI
95 79 72 7
K35
BI
FB_A_DQ<25>
95 79 72 7
FB_A_DQ<26>
K33
BI
95 79 72 7
FB_A_DQ<27>
G34
BI
95 79 72 7
K34
BI
FB_A_DQ<28>
95 79 72 7
FB_A_DQ<29>
E33
BI
E34
95 79 72 7
BI
FB_A_DQ<30>
95 79 72 7
FB_A_DQ<31>
G33
BI
95 79 72 7
AG30
BI
FB_A_DQ<32>
95 79 72 7
FB_A_DQ<33>
AH31
BI
95 79 72 7
FB_A_DQ<34>
AG32
BI
95 79 72 7
FB_A_DQ<35>
AF31
BI
95 79 72 7
FB_A_DQ<36>
AF30
BI
95 79 72 7
BI
FB_A_DQ<37>
AD30
95 79 72 7
FB_A_DQ<38>
AC32
BI
BI
FB_A_DQ<39>
95 79 72 7
AE30
95 79 72 7
FB_A_DQ<40>
AE32
BI
95 79 72 7
BI
FB_A_DQ<41>
AF33
BI
FB_A_DQ<42>
FB_A_DQ<43>
AE35
BI
95 79 72 7
95 79 72 7
AF34
95 79 72 7
BI
FB_A_DQ<44>
AE33
95 79 72 7
FB_A_DQ<45>
AE34
BI
95 79 72 7
FB_A_DQ<46>
AC35
BI
95 79 72 7
FB_A_DQ<47>
AB32
BI
95 79 72 7
FB_A_DQ<48>
AN33
BI
95 79 72 7
FB_A_DQ<49>
AK32
BI
FB_A_DQ<50>
AL33
BI
95 79 72 7
BI
P31
95 79 72 7
NB9P-GS
BGA
95 79 72 7
U8000
95 79 72 7
BI
FB_A_DQ<51>
AM33
95 79 72 7
BI
FB_A_DQ<52>
AL31
BI
FB_A_DQ<53>
95 79 72 7
FB_A_DQ<54>
AJ30
BI
95 79 72 7
FB_A_DQ<55>
AH30
BI
95 79 72 7
AM35
BI
FB_A_DQ<56>
95 79 72 7
FB_A_DQ<57>
AH33
BI
95 79 72 7
FB_A_DQ<58>
AH35
BI
95 79 72 7
BI
FB_A_DQ<59>
95 79 72 7
AH34
BI
FB_A_DQ<60>
95 79 72 7
FB_A_DQ<61>
AM34
BI
95 79 72 7
AK30
AH32
95 79 72 7
BI
FB_A_DQ<62>
AL35
95 79 72 7
BI
FB_A_DQ<63>
AJ33
P29
NC
R29
NC
L29
NC
M29
NC
AD29
NC
AE29
NC
AG29
NC
AH29
NC
SYMBOL 3 OF 9
FBA_D0
FBA_CMD0
FBA_CMD1
FBA_D1
FBA_CMD2
FBA_D2
FBA_D3
FBA_CMD3
FBA_D4
FBA_CMD4
FBA_D5
FBA_CMD5
FBA_D6
FBA_CMD6
FBA_CMD7
FBA_D7
FBA_D8
FBA_CMD8
FBA_D9
FBA_CMD9
FBA_CMD10
FBA_D10
FBA_CMD11
FBA_D11
FBA_CMD12
FBA_D12
FBA_CMD13
FBA_D13
FBA_D14
FBA_CMD14
FBA_D15
FBA_CMD15
FBA_D16
FBA_CMD16
FBA_D17
FBA_CMD17
FBA_D18
FBA_CMD18
FBA_D19
FBA_CMD19
FBA_D20
FBA_CMD20
FBA_D21
FBA_CMD21
FBA_D22
FBA_CMD22
FBA_D23
FBA_CMD23
FBA_D24
FBA_CMD24
FBA_CMD25
FBA_D25
FBA_CMD26
FBA_D26
FBA_CMD27
FBA_D27
FBA_CMD28
FBA_D28
FBA_CMD29
FBA_D29
FBA_CMD30
FBA_D30
FBA_D31
FBA_CLK0
FBA_D32
FBA_CLK0*
FBA_D33
FBA_CLK1
FBA_D34
FBA_CLK1*
FBA_D35
FBA_D36
FBA_DQM0
FBA_D37
FBA_DQM1
FBA_D38
FBA_DQM2
FBA_D39
FBA_DQM3
FBA_D40
FBA_DQM4
FBA_D41
FBA_DQM5
FBA_D42
FBA_DQM6
FBA_D43
FBA_DQM7
FBA_D44
FBA_D45
FBA_DQS_RN0
FBA_D46
FBA_DQS_RN1
FBA_D47
FBA_DQS_RN2
FBA_D48
FBA_DQS_RN3
FBA_D49
FBA_DQS_RN4
FBA_D50
FBA_DQS_RN5
FBA_D51
FBA_DQS_RN6
FBA_D52
FBA_DQS_RN7
FBA_D53
FBA_D54
FBA_DQS_WP0
FBA_D55
FBA_DQS_WP1
FBA_D56
FBA_DQS_WP2
FBA_D57
FBA_DQS_WP3
FBA_D58
FBA_DQS_WP4
FBA_D59
FBA_DQS_WP5
FBA_D60
FBA_DQS_WP6
FBA_D61
FBA_DQS_WP7
FBA_D62
FBA_D63
FB_DLLAVDD0
FB_PLLAVDD0
FBA_RFU0
FBA_RFU1*
FBA_DEBUG
FBA_RFU2
FB_CAL_PD_VDDQ
FBA_RFU3*
FB_CAL_PU_GND
FBA_RFU4
FB_CAL_TERM_GND
FBA_RFU5*
FBA_RFU6
FBA_RFU7*
BGA
V32
W31
FB_A_LMA<4>
OUT
FB_A_RAS_L
OUT
95 80 73 7
72 79 95
95 80 73 7
BI
BI
FB_B_DQ<0>
D11
FB_B_DQ<1>
E11
U31
FB_A_LMA<5>
OUT
72 79 95
95 80 73 7
BI
FB_B_DQ<2>
F10
Y32
FB_A_BA<1>
95 80 73 7
BI
FB_B_DQ<3>
D8
OUT
72 79 95
AB35
FB_A_UMA<2>
72 79 95
95 80 73 7
BI
FB_B_DQ<4>
F8
OUT
AB34
FB_A_UMA<4>
72 79 95
95 80 73 7
BI
FB_B_DQ<5>
F9
OUT
E8
W35
FB_A_UMA<3>
OUT
72 79 95
95 80 73 7
BI
FB_B_DQ<6>
W33
FB_A_CS1_L
95 80 73 7
BI
FB_B_DQ<7>
F12
OUT
79 95
W30
FB_A_CS0_L
OUT
72 95
95 80 73 7
BI
FB_B_DQ<8>
B11
T34
FB_A_MA<11>
OUT
72 79 95
95 80 73 7
BI
FB_B_DQ<9>
C13
T35
FB_A_CAS_L
95 80 73 7
BI
FB_B_DQ<10>
A11
OUT
72 79 95
AB31
FB_A_WE_L
72 79 95
95 80 73 7
BI
FB_B_DQ<11>
B8
OUT
A8
Y30
FB_A_BA<0>
OUT
72 79 95
95 80 73 7
BI
FB_B_DQ<12>
Y34
FB_A_UMA<5>
72 79 95
95 80 73 7
BI
FB_B_DQ<13>
C8
OUT
W32
FB_A_MA<12>
95 80 73 7
BI
FB_B_DQ<14>
C11
OUT
72 79 95
AA30
FB_A_DRAM_RST
95 80 73 7
FB_B_DQ<15>
C10
BI
AA32
FB_A_MA<7>
72 79 95
95 80 73 7
BI
FB_B_DQ<16>
D12
OUT
E13
Y33
FB_A_MA<10>
U32
FB_A_CKE
Y31
FB_A_MA<0>
U34
Y35
W34
OUT
OUT
72 79 95
OUT
72 79 95
OUT
72 79 95
72 79 95
95 80 73 7
BI
10K
95 80 73 7
FB_B_DQ<18>
F17
BI
95 80 73 7
BI
FB_B_DQ<19>
F15
BI
FB_B_DQ<20>
F16
BI
FB_B_DQ<21>
1/16W
MF-LF
FB_A_MA<9>
FB_A_MA<6>
OUT
72 79 95
OUT
72 79 95
R8201
95 80 73 7
402
10K
95 80 73 7
5%
FB_A_LMA<2>
OUT
72 79 95
V30
FB_A_MA<8>
OUT
72 79 95
U35
FB_A_LMA<3>
OUT
72 79 95
1/16W
402
E16
95 80 73 7
FB_B_DQ<22>
F14
BI
95 80 73 7
FB_B_DQ<23>
F13
BI
95 80 73 7
FB_B_DQ<24>
D13
BI
95 80 73 7
A13
MF-LF
2
U30
FB_A_MA<1>
OUT
72 79 95
BI
FB_B_DQ<25>
U33
FB_A_MA<13>
75
95 80 73 7
BI
FB_B_DQ<26>
B13
OUT
AB30
FB_A_BA<2>
72 79 95
95 80 73 7
BI
FB_B_DQ<27>
A14
OUT
C16
AB33
TP_FBA_CMD28
75
95 80 73 7
BI
FB_B_DQ<28>
T33
TP_FBA_CMD29
75
95 80 73 7
FB_B_DQ<29>
A17
BI
W29
TP_FBA_CMD30
T32
FB_A_CLK_P<0>
T31
75
FB_A_CLK_N<0>
AC31
FB_A_CLK_P<1>
AC30
FB_A_CLK_N<1>
P30
OUT
72 79 95
OUT
72 79 95
OUT
OUT
72 79 95
P32
FB_A_DQM_L<1>
BI
72 79 95
J30
FB_A_DQM_L<2>
BI
72 79 95
H34
FB_A_DQM_L<3>
BI
72 79 95
FB_A_DQM_L<4>
AF35
FB_A_DQM_L<5>
BI
72 79 95
AL32
FB_A_DQM_L<6>
BI
72 79 95
AL34
FB_A_DQM_L<7>
BI
72 79 95
IN
L35
FB_A_RDQS<1>
IN
72 79 95
H31
FB_A_RDQS<2>
IN
72 79 95
G35
FB_A_RDQS<3>
IN
72 79 95
AD32
FB_A_RDQS<4>
IN
72 79 95
AC34
FB_A_RDQS<5>
IN
72 79 95
e
r
71 8 =PP1V1_GPU_FBPLLAVDD
IN
72 79 95
IN
72 79 95
PP1V1_GPU_FBPLLAVDD_F
L34
FB_A_WDQS<0>
FB_A_WDQS<1>
J32
FB_A_WDQS<2>
H35
FB_A_WDQS<3>
OUT
VOLTAGE=1.1V
72 79 95
OUT
72 79 95
OUT
72 79 95
OUT
72 79 95
FB_A_WDQS<4>
AC33
FB_A_WDQS<5>
AJ32
FB_A_WDQS<6>
AJ34
FB_A_WDQS<7>
P
AG27
AF27
T30
FBA_DEBUG
K27
FBCAL_PD_VDDQ
L27
FBCAL_PU_GND
M27
FBCAL_TERM_GND
OUT
20%
10V
72 79 95
OUT
72 79 95
OUT
72 79 95
OUT
72 79 95
R8292
C8202
CERM
402
95 80 73 7
BI
FB_B_DQ<35>
95 80 73 7
FB_B_DQ<36>
F27
BI
95 80 73 7
BI
FB_B_DQ<37>
95 80 73 7
FB_B_DQ<38>
F28
BI
BI
FB_B_DQ<39>
FB_B_DQ<40>
A25
BI
95 80 73 7
BI
FB_B_DQ<41>
B25
BI
FB_B_DQ<42>
FB_B_DQ<43>
C26
BI
R8291
95 80 73 7
BI
FB_B_DQ<44>
95 80 73 7
FB_B_DQ<45>
B28
BI
95 80 73 7
FB_B_DQ<46>
A28
BI
95 80 73 7
FB_B_DQ<47>
A29
BI
95 80 73 7
FB_B_DQ<48>
E29
BI
95 80 73 7
FB_B_DQ<49>
F29
BI
FB_B_DQ<50>
D30
BI
95 80 73 7
BI
FB_B_DQ<51>
E31
95 80 73 7
BI
FB_B_DQ<52>
C33
95 80 73 7
BI
FB_B_DQ<53>
95 80 73 7
FB_B_DQ<54>
F32
BI
95 80 73 7
FB_B_DQ<55>
E32
BI
95 80 73 7
B29
BI
FB_B_DQ<56>
95 80 73 7
FB_B_DQ<57>
C29
BI
95 80 73 7
FB_B_DQ<58>
B31
BI
95 80 73 7
FB_B_DQ<59>
C31
BI
95 80 73 7
B32
BI
FB_B_DQ<60>
95 80 73 7
FB_B_DQ<61>
C32
BI
0402
C8201
0.1UF
C8200
1UF
20%
10V
10%
6.3V
CERM
402
CERM
402
71 8
=PP1V8_GPU_FBIO
R8293
R8290
60.4
1%
1/16W
MF-LF
402
48.7
2
1%
1/16W
MF-LF
402
1/16W
1/16W
MF-LF
MF-LF
402
D33
95 80 73 7
BI
FB_B_DQ<62>
B34
95 80 73 7
BI
FB_B_DQ<63>
B35
G11
NC
G12
NC
G14
NC
G15
NC
G24
NC
G25
NC
G27
NC
NC G28
PLACEMENT_NOTE=Place close to U8000.
1%
1%
D25
C28
95 80 73 7
L8200
D29
95 80 73 7
CRITICAL
FERR-220-OHM
F25
E28
33.2
40.2
402
0.1UF
AE31
FB_B_DQ<34>
E25
BI
95 80 73 7
72 79 95
N31
95 80 73 7
95 80 73 7
FB_A_RDQS<0>
FB_A_RDQS<7>
FB_B_DQ<33>
D26
BI
m
il
72 79 95
N32
FB_A_RDQS<6>
95 80 73 7
95 80 73 7
AF32
AJ35
D24
BI
FB_B_DQ<32>
BI
72 79 95
BI
AJ31
FB_B_DQ<31>
D16
BI
95 80 73 7
95 80 73 7
72 79 95
FB_A_DQM_L<0>
BI
FB_B_DQ<30>
B16
95 80 73 7
C17
FB_B_LMA<4>
OUT
73 80 95
B19
FB_B_RAS_L
OUT
73 80 95
FB_B_LMA<5>
D18
A23
D21
B23
E20
G21
F20
F19
F23
A22
C22
B17
FBC_D36
FBC_D37
FBC_D38
FBC_D39
FBC_D40
FBC_D41
FBC_D42
FBC_D43
FBC_D44
FBC_D45
FBC_D46
FBC_D47
FBC_D48
FBC_D49
FBC_D50
FBC_D51
FBC_D52
FBC_D53
FBC_D54
FBC_D55
FBC_D56
FBC_D57
FBC_D58
FBC_D59
FBC_D60
FBC_D61
FBC_D62
FBC_D63
FBC_DQM0
FBC_DQM1
FBC_DQM2
FBC_DQM3
FBC_DQM4
FBC_DQM5
FBC_DQM6
FBC_DQM7
FBC_DQS_RN0
FBC_DQS_RN1
FBC_DQS_RN2
FBC_DQS_RN3
FBC_DQS_RN4
FBC_DQS_RN5
FBC_DQS_RN6
FBC_DQS_RN7
F24
C25
E22
C20
B22
A19
D22
D20
E19
D19
F18
C19
F22
C23
OUT
73 80 95
FB_B_BA<1>
OUT
7 73 80 95
FB_B_UMA<2>
OUT
73 80 95
FB_B_UMA<4>
OUT
73 80 95
FB_B_UMA<3>
OUT
73 80 95
FB_B_CS1_L
OUT
80 95
FB_B_CS0_L
OUT
7 73 95
FB_B_MA<11>
OUT
FB_B_CAS_L
OUT
7 73 80 95
FB_B_WE_L
OUT
73 80 95
FB_B_BA<0>
OUT
FB_B_UMA<5>
OUT
73 80 95
OUT
73 80 95
OUT
73 80 95
y
r
F21
FB_B_MA<12>
a
n
i
R8200
FB_B_DQ<17>
5%
72 79 95
SYMBOL 4 OF 9
FBC_CMD0
FBC_D0
FBC_D1
FBC_CMD1
FBC_D2
FBC_CMD2
FBC_D3
FBC_CMD3
FBC_D4
FBC_CMD4
FBC_D5
FBC_CMD5
FBC_D6
FBC_CMD6
FBC_D7
FBC_CMD7
FBC_D8
FBC_CMD8
FBC_D9
FBC_CMD9
FBC_CMD10
FBC_D10
FBC_CMD11
FBC_D11
FBC_D12
FBC_CMD12
FBC_CMD13
FBC_D13
FBC_CMD14
FBC_D14
FBC_D15
FBC_CMD15
FBC_CMD16
FBC_D16
FBC_CMD17
FBC_D17
FBC_D18
FBC_CMD18
FBC_CMD19
FBC_D19
FBC_CMD20
FBC_D20
FBC_D21
FBC_CMD21
FBC_CMD22
FBC_D22
FBC_CMD23
FBC_D23
FBC_D24
FBC_CMD24
FBC_D25
FBC_CMD25
FBC_D26
FBC_CMD26
FBC_D27
FBC_CMD27
FBC_D28
FBC_CMD28
FBC_D29
FBC_CMD29
FBC_D30
FBC_CMD30
FBC_D31
FBC_CLK0
FBC_D32
FBC_CLK0*
FBC_D33
FBC_CLK1
FBC_D34
FBC_CLK1*
FBC_D35
7 73 80 95
73 80 95
FB_B_DRAM_RST
FB_B_MA<7>
FB_B_MA<10>
OUT
73 80 95
OUT
73 80 95
OUT
1
FB_B_CKE
FB_B_MA<0>
FB_B_MA<9>
FB_B_MA<6>
OUT
73 80 95
OUT
73 80 95
FB_B_LMA<2>
OUT
73 80 95
FB_B_MA<8>
OUT
73 80 95
FB_B_LMA<3>
OUT
73 80 95
OUT
73 80 95
OUT
75
OUT
73 80 95
FB_B_MA<1>
FB_B_MA<13>
FB_B_BA<2>
TP_FBC_CMD28
75
B20
TP_FBC_CMD29
75
A20
TP_FBC_CMD30
75
E17
FB_B_CLK_P<0>
D17
OUT
73 80 95
FB_B_CLK_N<0>
OUT
73 80 95
D23
FB_B_CLK_P<1>
OUT
73 80 95
E23
FB_B_CLK_N<1>
OUT
73 80 95
FB_B_DQM_L<0>
BI
73 80 95
D10
FB_B_DQM_L<1>
BI
73 80 95
D15
FB_B_DQM_L<2>
BI
73 80 95
A16
FB_B_DQM_L<3>
BI
73 80 95
D27
FB_B_DQM_L<4>
BI
73 80 95
D28
FB_B_DQM_L<5>
BI
73 80 95
D34
FB_B_DQM_L<6>
BI
73 80 95
A34
FB_B_DQM_L<7>
BI
F11
D9
FB_B_RDQS<0>
B10
R8250
10K
73 80 95
OUT
73 80 95
5%
1/16W
MF-LF
1
R8251
402
10K
5%
1/16W
MF-LF
2
402
73 80 95
IN
73 80 95
FB_B_RDQS<1>
IN
73 80 95
E14
FB_B_RDQS<2>
IN
73 80 95
B14
FB_B_RDQS<3>
IN
73 80 95
F26
FB_B_RDQS<4>
IN
73 80 95
A26
FB_B_RDQS<5>
IN
73 80 95
D31
FB_B_RDQS<6>
IN
73 80 95
A31
FB_B_RDQS<7>
IN
73 80 95
71 8 =PP1V1_GPU_FBPLLAVDD
C8290
0.1UF
20%
10V
2
CERM
402
FBC_RFU0
FBC_RFU1*
FBC_RFU2
FBC_RFU3*
FBC_RFU4
FBC_RFU5*
FBC_RFU6
FBC_RFU7*
FBC_DQS_WP0
FBC_DQS_WP1
FBC_DQS_WP2
FBC_DQS_WP3
FBC_DQS_WP4
FBC_DQS_WP5
FBC_DQS_WP6
FBC_DQS_WP7
E10
FB_DLLAVDD1
FB_PLLAVDD1
J19
FBC_DEBUG
G19
FB_VREF
J27
FB_B_WDQS<0>
OUT
73 80 95
FB_B_WDQS<1>
OUT
73 80 95
D14
FB_B_WDQS<2>
C14
A10
OUT
73 80 95
FB_B_WDQS<3>
OUT
73 80 95
E26
FB_B_WDQS<4>
OUT
73 80 95
B26
FB_B_WDQS<5>
OUT
73 80 95
D32
FB_B_WDQS<6>
OUT
73 80 95
A32
FB_B_WDQS<7>
OUT
73 80 95
71 8
C8291
0.1UF
20%
10V
CERM
402
=PP1V8_GPU_FBIO
R8294
R8295
60.4
1%
1/16W
MF-LF
402
1.07K
1%
1/16W
MF-LF
402
J18
FBC_DEBUG
GPU_FB_VREF
NO STUFF
C8296
NO STUFF1
0.1uF
X5R
R8297
R8296
1.02K
2.49K
1%
10%
16V
1/16W
2
1/16W
MF-LF
402
402
1%
MF-LF
402

GPU_FB_VREF_UNTERM_L
NO STUFF
Q8295
SSM6N15FEAPE
NV G96 FRAME BUFFER I/F
SOT563
SYNC_MASTER=K20_MLB
2
75 73 72
IN
FB_VREF_UNTERM

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
82
123
5
OMIT
CRITICAL
603
0.1uF
10%
16V
X5R
402
0.1uF
10%
16V
X5R
402
F12
10%
16V
X5R
402
M1
M12
V2
V11
K1
K12
A1
1
C8410
C8415
0.1uF
0.1uF
10%
16V
X5R
402
10%
16V
X5R
402
U8400.J1
A12
C1
C4
C9
U8400.J12
Connect to designated pin, then GND
C12
E1
80 79 73 72 9 8 =PP1V8_GPU_FB_VDDQ
E4
E9
E12
C8420
10UF
20%
6.3V
X5R
603
C8421
C8422
C8423
C8424
C8425
C8426
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
J4
J9
N1
N4
N9
N12
72 9 =PP1V8_GPU_FB_VREF_A
R1
R8430
R8433
549
549
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
R4
R9
R12
V1
V12
79 FB_A0_VREF
H1
79 FB_A2_VREF
H12
C
R8431
R8432
1.33K
1%
1/16W
MF-LF
402
931
1%
1/16W
MF-LF
402
C8431
R8434
0.01UF
1.33K
10%
16V
CERM
402
1%
1/16W
MF-LF
402
R8435
931
1%
1/16W
MF-LF
402
VDDA0
VDDA1
VSS3
G12
VSS4
VSS5
L1
VSS6
VSS7
V3
VSSA0
VSSA1
J1
VSSQ0
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ15
VSSQ16
VSSQ17
VSSQ18
VSSQ19
B1
(2 OF 2)
VDDQ0
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21
G1
C8450
10UF
0.1uF
2
X5R
603
K1
B4
B12
D1
VRAM4
VRAM4
1
R8443
R8445
2
1
121
121
243
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
73 72 71
75
D4
C12
E4
G2
E9
G11
E12
C8470
L2
10UF
L11
20%
6.3V
X5R
P1
603
C8471
C8472
0.1uF
0.1uF
0.1uF
0.1uF
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
A1
A2
A3
IN
IN
FB_A_LMA<2>
K10
95 79 71
IN
FB_A_LMA<3>
M9
95 79 71
IN
FB_A_LMA<4>
K4
95 79 71
IN
FB_A_LMA<5>
H2
A4
A5
95 79 72 71
IN
FB_A_MA<6>
K3
A6
95 79 72 71
IN
FB_A_MA<7>
L4
P12
T1
95 79 72 71
IN
FB_A_MA<8>
K2
95 79 72 71
IN
FB_A_MA<9>
95 79 72 71
IN
FB_A_MA<10>
95 79 72 71
IN
FB_A_MA<11>
95 79 72 71
IN
FB_A_CKE
IN
FB_A_MA<12>
95 79 72 71
95 79 71
IN
FB_A_CLK_P<0>
IN
FB_A_CLK_N<0>
95 72 71
IN
FB_A_CS0_L
95 79 72 71
IN
FB_A_WE_L
95 79 71
95 79 72 71
95 79 72 71
IN
FB_A_CAS_L
IN
FB_A_RAS_L
M4
K11
L9
H9
J3
R8480
T9
R8483
549
1%
1/16W
MF-LF
402
T12
F4
H4
F9
H10
FB_A0_ZQ
FB_A0_MF
FB_A0_SEN
95 79 72 71
IN
FB_A_DRAM_RST
95 79 71
OUT FB_A_RDQS<3>
R8482
931
1%
1/16W
MF-LF
402
95 79 71
OUT FB_A_RDQS<2>
95 79 71
95 79 71
OUT FB_A_RDQS<1>
95 79 71
IN
FB_A_WDQS<3>
95 79 71
IN
FB_A_WDQS<2>
95 79 71
IN
FB_A_WDQS<0>
95 79 71
IN
FB_A_WDQS<1>
95 79 72 71
IN
R8484
0.01uF
1.33K
10%
16V
CERM
402
5
1
VRAM4
R8490
1%
1/16W
MF-LF
402
R8485
1%
1/16W
MF-LF
402
R8492
VRAM4
R8494
1K
121
121
5%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
VRAM4
R8493
BGA
DM1
IN
71 79 95
(1 OF 2)
DM2
DM3
N10
FB_A_DQM_L<0>
IN
71 79 95
N3
FB_A_DQM_L<1>
IN
71 79 95
DQ0
B2
FB_A_DQ<24>
BI
7 71 79 95
IN
71 79 95
e
r
B3
FB_A_DQ<30>
BI
7 71 79 95
C2
FB_A_DQ<29>
BI
7 71 79 95
DQ3
C3
FB_A_DQ<31>
FB_A_DQ<28>
BI
7 71 79 95
1%
1/16W
MF-LF
402
C8496
VRAM4
10%
16V
CERM
402
R8495
121
243
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
B1
B4
B9
B12
D1
D4
D9
D12
G2
G11
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12
10%
16V
CERM
402
DM0
E3
FB_A_DQM_L<7>
IN
71 79 95
DM1
E10
FB_A_DQM_L<5>
IN
71 79 95
IN
N10
FB_A_DQM_L<6>
IN
71 79 95
95 79 71
IN
FB_A_UMA<3>
M9
DM2
DM3
N3
FB_A_DQM_L<4>
IN
71 79 95
95 79 71
DQ0
B2
FB_A_DQ<59>
BI
7 71 79 95
DQ1
DQ2
B3
FB_A_DQ<58>
BI
7 71 79 95
C2
FB_A_DQ<63>
BI
7 71 79 95
DQ3
C3
FB_A_DQ<60>
BI
7 71 79 95
FB_A_DQ<57>
IN
FB_A_UMA<4>
K4
95 79 71
IN
FB_A_UMA<5>
H2
A4
A5
95 79 72 71
IN
FB_A_MA<6>
K3
A6
95 79 72 71
IN
FB_A_MA<7>
L4
95 79 72 71
IN
FB_A_MA<8>
K2
A7
A8/AP
DQ10
DQ11
C11
FB_A_DQ<21>
BI
7 71 79 95
C10
FB_A_DQ<23>
BI
7 71 79 95
95 79 71
DQ12
DQ13
E11
FB_A_DQ<19>
BI
7 71 79 95
95 72 71
F10
FB_A_DQ<18>
BI
7 71 79 95
95 79 72 71
DQ14
F11
FB_A_DQ<16>
BI
7 71 79 95
95 79 72 71
G10
FB_A_DQ<17>
BI
7 71 79 95
95 79 72 71
M11
FB_A_DQ<5>
BI
7 71 79 95
FB_A1_ZQ
A4
BI
7 71 79 95
FB_A1_MF
A9
FB_A1_SEN
V4
SEN
V9
RESET
7 71 79 95
BI
7 71 79 95
DQ20
R11
FB_A_DQ<2>
BI
7 71 79 95
DQ21
DQ22
R10
FB_A_DQ<3>
BI
7 71 79 95
T11
FB_A_DQ<1>
BI
7 71 79 95
DQ23
DQ24
T10
FB_A_DQ<0>
BI
7 71 79 95
M2
FB_A_DQ<13>
BI
7 71 79 95
DQ25
L3
FB_A_DQ<15>
BI
N2
FB_A_DQ<14>
M3
FB_A_DQ<12>
BGA
7 71 79 95
BI
U8450
BI
FB_A_DQ<7>
5
1
(1 OF 2)
BI
M10
A2
A3
FB_A_DQ<22>
DQ18
DQ19
A1
B10
FB_A_DQ<6>
A0
DQ9
FB_A_DQ<4>
FB_VREF_UNTERM
IN
K9
95 79 72 71
IN
FB_A_MA<9>
95 79 72 71
IN
FB_A_MA<10>
95 79 72 71
IN
FB_A_MA<11>
95 79 72 71
IN
FB_A_CKE
IN
FB_A_MA<12>
95 79 72 71
95 79 71
95 79 72 71
M4
K11
L9
H9
J3
IN
FB_A_CLK_P<1>
J11
IN
FB_A_CLK_N<1>
J10
IN
FB_A_CS0_L
F4
IN
FB_A_WE_L
H4
IN
FB_A_CAS_L
F9
IN
FB_A_RAS_L
H10
IN
FB_A_DRAM_RST
95 79 71
OUT FB_A_RDQS<7>
D3
95 79 71
OUT FB_A_RDQS<5>
D10
OUT FB_A_RDQS<6>
P10
95 79 71
DQ4
DQ5
E2
BI
7 71 79 95
F3
FB_A_DQ<56>
BI
7 71 79 95
A10
A11
DQ6
F2
FB_A_DQ<61>
BI
7 71 79 95
FB_A_DQ<62>
BI
7 71 79 95
CKE
DQ7
DQ8
G3
B11
FB_A_DQ<40>
BI
7 71 79 95
DQ9
B10
FB_A_DQ<47>
BI
7 71 79 95
DQ10
DQ11
C11
FB_A_DQ<46>
BI
7 71 79 95
C10
FB_A_DQ<45>
BI
7 71 79 95
DQ12
DQ13
E11
FB_A_DQ<42>
BI
7 71 79 95
F10
FB_A_DQ<44>
BI
7 71 79 95
DQ14
F11
FB_A_DQ<43>
BI
7 71 79 95
G10
FB_A_DQ<41>
BI
7 71 79 95
ZQ
DQ15
DQ16
M11
FB_A_DQ<54>
BI
7 71 79 95
MF
DQ17
L10
FB_A_DQ<55>
BI
7 71 79 95
DQ18
DQ19
N11
FB_A_DQ<53>
BI
7 71 79 95
M10
FB_A_DQ<52>
BI
7 71 79 95
DQ20
R11
FB_A_DQ<49>
BI
7 71 79 95
DQ21
DQ22
R10
FB_A_DQ<51>
BI
7 71 79 95
T11
FB_A_DQ<50>
BI
7 71 79 95
DQ23
DQ24
T10
FB_A_DQ<48>
BI
7 71 79 95
M2
FB_A_DQ<36>
BI
7 71 79 95
DQ25
L3
FB_A_DQ<37>
BI
7 71 79 95
N2
FB_A_DQ<32>
BI
7 71 79 95
M3
FB_A_DQ<38>
BI
7 71 79 95
A9
A12/CS1*
CK
CK*
CS0*
WE*
CAS*
RAS*
RDQS0
RDQS1
RDQS2
95 79 71
OUT FB_A_RDQS<4>
P3
7 71 79 95
95 79 71
IN
FB_A_WDQS<7>
D2
BI
7 71 79 95
95 79 71
IN
FB_A_WDQS<5>
D11
WDQS0
WDQS1
BI
7 71 79 95
95 79 71
IN
FB_A_WDQS<6>
P11
WDQS2
DQ26
DQ27
BI
7 71 79 95
95 79 71
IN
FB_A_WDQS<4>
P2
WDQS3
DQ28
R2
FB_A_DQ<39>
BI
7 71 79 95
DQ29
DQ30
R3
FB_A_DQ<34>
BI
7 71 79 95
T2
FB_A_DQ<33>
BI
7 71 79 95
DQ31
T3
FB_A_DQ<35>
BI
7 71 79 95
D11
WDQS0
WDQS1
P11
WDQS2
DQ26
DQ27
P2
WDQS3
DQ28
R2
FB_A_DQ<10>
DQ29
DQ30
R3
FB_A_DQ<9>
BI
7 71 79 95
T2
FB_A_DQ<8>
BI
7 71 79 95
DQ31
T3
FB_A_DQ<11>
BI
7 71 79 95
95 79 72 71
IN
SOT563
K10
7 71 79 95
N11
Q8450
SSM6N15FEAPE
H11
7 71 79 95
L10
FB_A_UMA<2>
BI
DQ17
IN
FB_A_MA<0>
FB_A_DQ<20>
RFU
J12
95 79 71
95 79 72 71
IN
FB_A_DQ<26>
J2
J1
FB_A_MA<1>
95 79 72 71
B11
BA1
BA2
VSSA0
VSSA1
OMIT
CRITICAL
DQ7
DQ8
H3
VRAM4
V10
R8497
CKE
G4
V3
73 72 71
75
G3
FB_A_BA<2>
VSS6
VSS7
(NONE)
0.01uF
7 71 79 95
BA0
L12
0.01UF
243
1%
1/16W
MF-LF
402
7 71 79 95
RDQS3
L1
SOT563
7 71 79 95
RDQS1
RDQS2
VSS4
VSS5
SSM6N15FEAPE
BI
RDQS0
VSS3
C8482
BI
RESET
- =PP1V8_S0_FB_VREFA
G12
G1
y
r
Q8450
BI
SEN
- =PP1V8_S0_FB_VDD
A10
VSSQ0
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ15
VSSQ16
VSSQ17
VSSQ18
VSSQ19
VOLTAGE=0.9V
R8496
FB_A_DQ<25>
V9
A3
VSS1
VSS2
FB_A_CLK1_TERM
FB_A_DQ<27>
CK*
CS0*
WE*
CAS*
RAS*
931
F2
FB_A_BA<1>
G9
FB_A_BA<0>
RDQS3
BA0
95 79 72 71
IN
FB_A_BA<1>
G4
95 79 72 71
IN
FB_A_BA<2>
H3
BA1
BA2
J2
RFU
NC
GDDR3 Frame Buffer A (Bottom)

SYNC_MASTER=M98_MLB

R8449
100
121
FB_A_DQM_L<2>
CK
VREF0
VREF1
H12
F3
IN
V1
DQ6
IN
R9
R12
DQ4
DQ5
95 79 72 71
NC
R4
A10
A11
95 79 72 71
243
MF
G9
E2
V4
D2
1%
1/16W
MF-LF
402
A9
P3
R8448
SOT563
FB_A_DQM_L<3>
A12/CS1*
N1
H1
C8481
m
il
Q8400
SSM6N15FEAPE
ZQ
P10
FB_A_BA<0>
A4
D10
OUT FB_A_RDQS<0>
E3
A9
(2 OF 2)
VSS0
FB_A1_VREF_UNTERM_L
DQ15
DQ16
D3
549
1%
1/16W
MF-LF
402
BGA
FB_A3_VREF_UNTERM_L
FB_VREF_UNTERM
P
J11
J10
R1
T4
U8450
a
n
i
2
N12
72 9 =PP1V8_GPU_FB_VREF_A
E10
A7
A8/AP
J9
N9
1%
1/16W
MF-LF
402
DQ1
DQ2
J4
N4
95 79 71
C8476
10%
16V
X5R
402
1.33K
U8400
C8475
0.1uF
P9
DM0
A0
C8474
10%
16V
X5R
402
P4
OMIT
CRITICAL
K9
C8473
0.1uF
H11
C9
E1
R8481
FB_A_MA<0>
U8400.J12
C4
80 79 73 72 9 8 =PP1V8_GPU_FB_VDDQ
D12
IN
C1
D9
10%
16V
CERM
402
IN
A12
10%
16V
X5R
402
R8447
FB_A_MA<1>
95 79 72 71
10%
16V
CERM
402
K4J10324QD-HC11
0.01UF
32MX32-900MHZ-MFH
243
1%
1/16W
MF-LF
402
C8465
VDDQ0
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21
0.1uF
10%
16V
X5R
402
U8400.J1
SOT563
MFHIGH
121
1%
1/16W
MF-LF
402
C8460
0.1uF
B9
MFHIGH
121
1%
1/16W
MF-LF
402
VDDA0
VDDA1
A1
0.01UF
M12
79 FB_A3_VREF
SSM6N15FEAPE
C8446
M1
K12
C8432
MFHIGH
1K
R8446
5%
1/16W
MF-LF
402
2
95 79 72 71
10%
16V
X5R
402
79 FB_A1_VREF
Q8400
R8444
10%
16V
X5R
402
F12
J12
VREF0
VREF1
VRAM4
1
0.1uF
V12
VOLTAGE=0.9V
R8442
0.1uF
10%
16V
X5R
402
F1
C8454
V2
FB_A_CLK0_TERM
VRAM4
VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
V11
FB_A0_VREF_UNTERM_L
C8453
V10
FB_A2_VREF_UNTERM_L
R8440
C8452
0.1uF
10%
16V
X5R
402
20%
6.3V
L12
C8451
K4J10324QD-HC11
10%
16V
X5R
402
20%
6.3V
X5R
0.1uF
F1
C8404
A2
A11
MFHIGH
0.1uF
C8403
A10
32MX32-900MHZ-MFH
10UF
C8402
A3
VSS1
VSS2
BGA
MFHIGH
C8401
VSS0
U8400
Page Notes
CRITICAL
80 79 73 72 8 =PP1V8_GPU_FB_VDD
MFHIGH
C8400
VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
K4J10324QD-HC11
A2
A11
32MX32-900MHZ-MFH
80 79 73 72 8 =PP1V8_GPU_FB_VDD
OMIT
K4J10324QD-HC11
32MX32-900MHZ-MFH
R8498
5%
1/16W
MF-LF
402
243
1%
1/16W
MF-LF
402
SIZE
R8499
DRAWING NUMBER
100
5%
1/16W
MF-LF
402
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
84
123
5
OMIT
CRITICAL
603
0.1uF
10%
16V
X5R
402
0.1uF
10%
16V
X5R
402
F12
10%
16V
X5R
402
M1
M12
V2
V11
K1
K12
A1
1
C8510
C8515
0.1uF
0.1uF
10%
16V
X5R
402
10%
16V
X5R
402
U8500.J1
A12
C1
C4
C9
U8500.J12
C12
E1
80 79 73 72 9 8 =PP1V8_GPU_FB_VDDQ
E4
E9
E12
C8520
10UF
20%
6.3V
X5R
603
C8521
C8522
C8523
C8524
C8525
C8526
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
J4
J9
N1
N4
N9
N12
73 9 =PP1V8_GPU_FB_VREF_B
R1
R8530
R4
549
1%
1/16W
MF-LF
402
R8533
R9
R12
549
1%
1/16W
MF-LF
402
V1
V12
2
80 FB_B0_VREF
H1
H12
80 FB_B2_VREF
C
R8531
R8532
1.33K
1%
1/16W
MF-LF
402
931
1%
1/16W
MF-LF
402
C8531
R8534
0.01uF
1.33K
10%
16V
CERM
402
1%
1/16W
MF-LF
402
R8535
931
1%
1/16W
MF-LF
402
VDDA0
VDDA1
VSS3
G12
VSS4
VSS5
L1
VSS6
VSS7
V3
VSSA0
VSSA1
J1
VSSQ0
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ15
VSSQ16
VSSQ17
VSSQ18
VSSQ19
B1
(2 OF 2)
VDDQ0
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21
G1
0.1uF
2
X5R
603
B4
B12
D1
D4
VRAM4
VRAM4
1
R8543
R8545
C12
G2
E9
G11
E12
C8570
L2
10UF
L11
20%
6.3V
X5R
P1
603
C8571
C8572
121
243
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
0.1uF
0.1uF
0.1uF
0.1uF
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
A1
A2
A3
IN
IN
FB_B_LMA<2>
K10
95 80 71
IN
FB_B_LMA<3>
M9
95 80 71
IN
FB_B_LMA<4>
K4
95 80 71
IN
FB_B_LMA<5>
H2
A4
A5
95 80 73 71
IN
FB_B_MA<6>
K3
A6
P12
T1
95 80 73 71
IN
FB_B_MA<7>
L4
R8580
T9
95 80 73 71
IN
FB_B_MA<8>
K2
95 80 73 71
IN
FB_B_MA<9>
95 80 73 71
IN
FB_B_MA<10>
95 80 73 71 7
IN
FB_B_MA<11>
95 80 73 71
IN
FB_B_CKE
IN
FB_B_MA<12>
95 80 73 71
95 80 71
IN
FB_B_CLK_P<0>
IN
FB_B_CLK_N<0>
95 73 71 7
IN
FB_B_CS0_L
95 80 73 71
IN
FB_B_WE_L
95 80 71
95 80 73 71 7
95 80 73 71
IN
FB_B_CAS_L
IN
FB_B_RAS_L
M4
K11
L9
H9
J3
R8583
R8582
931
1%
1/16W
MF-LF
402
F4
H4
F9
H10
FB_B0_ZQ
FB_B0_MF
FB_B0_SEN
95 80 73 71
IN
FB_B_DRAM_RST
95 80 71
OUT FB_B_RDQS<1>
95 80 71
OUT FB_B_RDQS<0>
95 80 71
95 80 71
OUT FB_B_RDQS<3>
95 80 71
IN
FB_B_WDQS<1>
95 80 71
IN
FB_B_WDQS<0>
95 80 71
IN
FB_B_WDQS<2>
95 80 71
IN
FB_B_WDQS<3>
95 80 73 71
IN
R8584
0.01uF
1.33K
10%
16V
CERM
402
1%
1/16W
MF-LF
402
R8585
1%
1/16W
MF-LF
402
VRAM4
R8594
1K
121
121
5%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
R8592
VRAM4
R8593
DM1
IN
71 80 95
DM2
DM3
N10
FB_B_DQM_L<2>
IN
71 80 95
N3
FB_B_DQM_L<3>
IN
71 80 95
DQ0
B2
FB_B_DQ<12>
IN
71 80 95
e
r
B3
FB_B_DQ<8>
BI
7 71 80 95
C2
FB_B_DQ<11>
BI
7 71 80 95
DQ3
C3
FB_B_DQ<10>
FB_B_DQ<13>
BI
10%
16V
CERM
402
R8595
121
243
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
J12
y
r
B1
B4
B9
B12
D1
D4
D9
D12
G2
G11
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12
DM0
E3
FB_B_DQM_L<6>
IN
71 80 95
BGA
DM1
E10
FB_B_DQM_L<5>
IN
71 80 95
IN
N10
FB_B_DQM_L<4>
IN
71 80 95
95 80 71
IN
FB_B_UMA<3>
M9
DM2
DM3
N3
FB_B_DQM_L<7>
IN
71 80 95
95 80 71
DQ0
B2
FB_B_DQ<49>
BI
7 71 80 95
DQ1
DQ2
B3
FB_B_DQ<50>
BI
7 71 80 95
C2
FB_B_DQ<48>
BI
7 71 80 95
DQ3
C3
FB_B_DQ<51>
BI
7 71 80 95
FB_B_DQ<53>
IN
FB_B_UMA<4>
K4
95 80 71
IN
FB_B_UMA<5>
H2
A4
A5
95 80 73 71
IN
FB_B_MA<6>
K3
A6
95 80 73 71
IN
FB_B_MA<7>
L4
95 80 73 71
IN
FB_B_MA<8>
K2
A7
A8/AP
DQ10
DQ11
C11
FB_B_DQ<3>
C10
FB_B_DQ<4>
BI
7 71 80 95
95 80 71
DQ12
DQ13
E11
FB_B_DQ<0>
BI
7 71 80 95
95 73 71 7
F10
FB_B_DQ<2>
BI
7 71 80 95 95 80 73 71
DQ14
F11
FB_B_DQ<1>
BI
7 71 80
95
G10
FB_B_DQ<7>
BI
7 71 80 95 95 80 73 71
M11
FB_B_DQ<21>
BI
7 71 80 95
FB_B1_ZQ
A4
BI
7 71 80 95
FB_B1_MF
A9
FB_B1_SEN
V4
SEN
V9
RESET
M4
BI
BI
7 71 80 95
95 80 71
IN
FB_B_CLK_P<1>
J11
IN
FB_B_CLK_N<1>
J10
IN
FB_B_CS0_L
F4
IN
FB_B_WE_L
H4
IN
FB_B_CAS_L
F9
IN
FB_B_RAS_L
H10
95 80 73 71 7
DQ17
L10
FB_B_DQ<16>
DQ18
DQ19
N11
FB_B_DQ<19>
BI
7 71 80 95
M10
FB_B_DQ<17>
BI
7 71 80 95 95 80 73 71
DQ20
R11
FB_B_DQ<20>
BI
7 71 80 95
DQ21
DQ22
R10
FB_B_DQ<22>
BI
7 71 80 95
T11
FB_B_DQ<18>
BI
7 71 80 95
T10
FB_B_DQ<23>
BI
7 71 80 95
BI
7 71 80 95
BI
M3
FB_B_DQ<28>
U8550
BI
FB_B_DQ<31>
(1 OF 2)
FB_B_DQ<5>
N2
5
1
A2
A3
B10
DQ25
A1
FB_B_MA<10>
FB_B_DQ<27>
A0
FB_B_MA<9>
FB_B_DQ<26>
K9
IN
L3
FB_VREF_UNTERM
IN
K10
7 71 80 95
IN
FB_B_MA<11>
IN
FB_B_CKE
IN
FB_B_MA<12>
IN
K11
L9
H9
J3
FB_B_DRAM_RST
95 80 71
OUT FB_B_RDQS<6>
D3
95 80 71
OUT FB_B_RDQS<5>
D10
OUT FB_B_RDQS<4>
P10
95 80 71
DQ4
DQ5
E2
BI
7 71 80 95
F3
FB_B_DQ<55>
BI
7 71 80 95
A10
A11
DQ6
F2
FB_B_DQ<54>
BI
7 71 80 95
FB_B_DQ<52>
BI
7 71 80 95
CKE
DQ7
DQ8
G3
B11
FB_B_DQ<41>
BI
7 71 80 95
DQ9
B10
FB_B_DQ<42>
BI
7 71 80 95
DQ10
DQ11
C11
FB_B_DQ<40>
BI
7 71 80 95
C10
FB_B_DQ<47>
BI
7 71 80 95
DQ12
DQ13
E11
FB_B_DQ<44>
BI
7 71 80 95
F10
FB_B_DQ<45>
BI
7 71 80 95
DQ14
F11
FB_B_DQ<43>
BI
7 71 80 95
G10
FB_B_DQ<46>
BI
7 71 80 95
ZQ
DQ15
DQ16
M11
FB_B_DQ<34>
BI
7 71 80 95
MF
DQ17
L10
FB_B_DQ<35>
BI
7 71 80 95
DQ18
DQ19
N11
FB_B_DQ<33>
BI
7 71 80 95
M10
FB_B_DQ<32>
BI
7 71 80 95
DQ20
R11
FB_B_DQ<37>
BI
7 71 80 95
DQ21
DQ22
R10
FB_B_DQ<38>
BI
7 71 80 95
T11
FB_B_DQ<39>
BI
7 71 80 95
DQ23
DQ24
T10
FB_B_DQ<36>
BI
7 71 80 95
M2
FB_B_DQ<56>
BI
7 71 80 95
DQ25
L3
FB_B_DQ<57>
BI
7 71 80 95
N2
FB_B_DQ<63>
BI
7 71 80 95
M3
FB_B_DQ<59>
BI
7 71 80 95
A9
A12/CS1*
CK
CK*
CS0*
WE*
CAS*
RAS*
RDQS0
RDQS1
RDQS2
95 80 71
OUT FB_B_RDQS<7>
P3
7 71 80 95
95 80 71
IN
FB_B_WDQS<6>
D2
BI
7 71 80 95
95 80 71
IN
FB_B_WDQS<5>
D11
WDQS0
WDQS1
BI
7 71 80 95
95 80 71
IN
FB_B_WDQS<4>
P11
WDQS2
DQ26
DQ27
BI
7 71 80 95
95 80 71
IN
FB_B_WDQS<7>
P2
WDQS3
DQ28
R2
FB_B_DQ<58>
BI
7 71 80 95
DQ29
DQ30
R3
FB_B_DQ<62>
BI
7 71 80 95
T2
FB_B_DQ<61>
BI
7 71 80 95
DQ31
T3
FB_B_DQ<60>
BI
7 71 80 95
D11
WDQS0
WDQS1
P11
WDQS2
DQ26
DQ27
P2
WDQS3
DQ28
R2
FB_B_DQ<24>
DQ29
DQ30
R3
FB_B_DQ<25>
BI
T2
FB_B_DQ<29>
BI
DQ31
T3
FB_B_DQ<30>
BI
7 71 80 95
95 80 73 71
7 71 80 95
95 80 73 71 7
7 71 80 95
95 80 73 71
IN
G9
FB_B_BA<0>
FB_B_BA<1>
G4
FB_B_BA<2>
H3
BA1
BA2
J2
RFU
243
100
1%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
BA0
IN
NC
R8549
RDQS3
IN
R8598
SOT563
H11
IN
M2
Q8550
SSM6N15FEAPE
FB_B_UMA<2>
FB_B_MA<0>
95 80 73 71
DQ23
DQ24
IN
IN
95 80 73 71
7 71 80 95
95 80 73 71 7
7 71 80 95
95 80 73 71
7 71 80 95
95 80 73 71
7 71 80 95
BI
OMIT
CRITICAL
DQ9
RFU
J1
R8597
FB_B_DQ<6>
J2
VSSA0
VSSA1
73 72 71
75
FB_B_DQ<9>
BA1
BA2
VRAM4
V10
10%
16V
CERM
402
B11
H3
V3
95 80 71
95 80 73 71
7 71 80 95
VRAM4
DQ7
DQ8
G4
VSS6
VSS7
(NONE)
0.01UF
243
1%
1/16W
MF-LF
402
CKE
FB_B_BA<2>
L12
SOT563
G3
BA0
L1
SSM6N15FEAPE
7 71 80 95
RDQS3
VSS4
VSS5
0.01uF
7 71 80 95
RDQS1
RDQS2
VSS3
VSSQ0
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ15
VSSQ16
VSSQ17
VSSQ18
VSSQ19
Q8550
C8596
BI
RDQS0
- =PP1V8_S0_FB_VREF_B
G12
G1
FB_B_MA<1>
95 80 73 71
BI
1%
1/16W
MF-LF
402
BI
RESET
- =PP1V8_S0_FB_VDD
A10
C8582
VOLTAGE=0.9V
R8596
BI
SEN
A3
VSS1
VSS2
FB_B_CLK1_TERM
FB_B_DQ<14>
V9
931
FB_B_DQ<15>
CK*
CS0*
WE*
CAS*
RAS*
VREF0
VREF1
H1
H12
F2
FB_B_BA<1>
F3
IN
V1
DQ6
IN
V12
DQ4
DQ5
95 80 73 71
NC
R9
R12
A10
A11
95 80 73 71 7
5
1
VRAM4
R8590
MF
G9
1%
1/16W
MF-LF
402
E2
V4
D2
243
A9
P3
1%
1/16W
MF-LF
402
ZQ
P10
R8548
SOT563
BGA
CK
N1
549
C8581
m
il
Q8500
SSM6N15FEAPE
A4
D10
FB_B_BA<0>
DQ15
DQ16
D3
OUT FB_B_RDQS<2>
(1 OF 2)
A12/CS1*
(2 OF 2)
VSS0
FB_B1_VREF_UNTERM_L
FB_B_DQM_L<0>
A9
BGA
FB_B3_VREF_UNTERM_L
FB_B_DQM_L<1>
P
J11
J10
R4
549
1%
1/16W
MF-LF
402
T12
E3
A7
A8/AP
R1
T4
U8550
a
n
i
2
N12
73 9 =PP1V8_GPU_FB_VREF_B
121
DQ1
DQ2
J9
N9
E10
U8500
J4
N4
DM0
A0
C8576
0.1uF
K9
H11
95 80 71
95 80 73 71
FB_B_MA<1>
C8575
10%
16V
X5R
402
P9
OMIT
CRITICAL
FB_B_MA<0>
C8574
0.1uF
IN
C8573
P4
R8547
1%
1/16W
MF-LF
402
C9
E4
1%
1/16W
MF-LF
402
U8500.J12
C4
E1
FB_VREF_UNTERM
IN
C1
80 79 73 72 9 8 =PP1V8_GPU_FB_VDDQ
D12
1.33K
121
73 72 71
75
VDDQ0
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21
A12
10%
16V
X5R
402
D9
0.01UF
2
C8565
SOT563
10%
16V
CERM
402
VDDA0
VDDA1
0.1uF
10%
16V
X5R
402
U8500.J1
R8581
K4J10324QD-HC11
243
1%
1/16W
MF-LF
402
C8560
0.1uF
B9
80 FB_B3_VREF
SSM6N15FEAPE
32MX32-900MHZ-MFH
121
1%
1/16W
MF-LF
402
M12
A1
0.01uF
M1
80 FB_B1_VREF
Q8500
C8546
MFHIGH
121
1%
1/16W
MF-LF
402
MFHIGH
1K
R8546
5%
1/16W
MF-LF
402
2
95 80 73 71
10%
16V
X5R
402
K1
MFHIGH
R8544
10%
16V
X5R
402
F12
K12
C8532
VOLTAGE=0.9V
1
0.1uF
J12
VREF0
VREF1
VRAM4
R8542
0.1uF
10%
16V
X5R
402
F1
C8554
V2
FB_B_CLK0_TERM
VRAM4
VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
V11
FB_B0_VREF_UNTERM_L
C8553
V10
FB_B2_VREF_UNTERM_L
R8540
C8552
0.1uF
10%
16V
X5R
402
20%
6.3V
L12
C8551
10UF
10%
16V
CERM
402
C8550
K4J10324QD-HC11
10%
16V
X5R
402
20%
6.3V
X5R
0.1uF
F1
C8504
A2
A11
MFHIGH
0.1uF
C8503
A10
32MX32-900MHZ-MFH
10UF
C8502
A3
VSS1
VSS2
BGA
MFHIGH
C8501
VSS0
U8500
Page Notes
CRITICAL
80 79 73 72 8 =PP1V8_GPU_FB_VDD
MFHIGH
C8500
VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
K4J10324QD-HC11
A2
A11
32MX32-900MHZ-MFH
80 79 73 72 8 =PP1V8_GPU_FB_VDD
OMIT
K4J10324QD-HC11
32MX32-900MHZ-MFH
GDDR3 Frame Buffer B (Bottom)

SYNC_MASTER=M98_MLB

R8599
100
SIZE
5%
1/16W
MF-LF
402
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
85
123
7
Page Notes
110mA
75 74 8 6
OMIT
=PP3V3_GPU_VDD33
U8000
- =PP3V3_GPU_VDD33
NB9P-GS
- =PP3V3_GPI_MIO
BGA
- =PP1V2_GPU_PLLVDD
J9
- =PP1V2_GPU_H_PLLVDD
J10
- =PP1V2_GPU_VID_PLLVDD
J11
1

(NONE)
2
C8690
C8692
C8694
C8696
C8698
0.022UF
0.022UF
0.1UF
0.47UF
1UF
10%
16V
CERM-X5R
402
10%
16V
CERM-X5R
402
20%
10V
CERM
402
10%
6.3V
CERM-X5R
402
10%
6.3V
J12
J13
VDD33_1
VDD33_2
VDD33_3
VDD33_4
VDD33_5
SYMBOL 6 OF 9
CERM
402
(NONE)
NC
1
75 74 8 6 =PP3V3_GPU_VDD33
Typically <??mA
C8691
C8693
C8695
C8697
0.022UF
0.022UF
0.1UF
0.47UF
10%
16V
CERM-X5R
402
10%
16V
CERM-X5R
402
20%
10V
CERM
402
10%
6.3V
CERM-X5R
402
NC
J25
RFU0
J26
RFU1
AK14
K9
C8600
C8601
0.47UF
0.47UF
10%
6.3V
10%
6.3V
10%
6.3V
402
CERM-X5R
CERM-X5R
C3
75 GPU_ROM_CS_L
402
402
RFU1_GND
C8602
0.47UF
CERM-X5R
RFU0_GND
D4
75 GPU_ROM_SCLK
D3
75 GPU_ROM_SI
C4
75 GPU_ROM_SO
R8696
40.2K
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
GPU_STRAP_REF_3V3_PD
N9
GPU_STRAP_REF_MIOB_PD
M9
STRAP_REF_3V3
STRAP_REF_MIOB
(IPD)
75 74 8
=PP3V3_GPU_MIO
P9
75 74 8 =PP3V3_GPU_MIO
R9
C8610
C8611
1UF
R8620
49.9
1/16W
1/16W
MF-LF
MF-LF
2
R8616
402
GPU_MIOA_PD_VDDQ
74
GPU_MIOB_PD_VDDQ
74
49.9
5%
GPU_MIOA_PU_GND
74
GPU_MIOB_PU_GND
74
R8623
1/16W
1/16W
5%
MF-LF
MF-LF
1/16W
402
MF-LF
1
1
10K
1%
Y9
5%
MF-LF
402
C8617
1
1
10%
16V
1/16W
MF-LF
X5R
402
402
C8619
0.1uF
5%
10%
16V
R8619
10K
0.1uF
2
GPU_TESTMODE_PD
402
X5R
402
GPU_MIOA_VREF
GPU_MIOB_VREF
AF1
10K
74 GPU_MIOA_PU_GND
74 GPU_MIOB_PU_GND
AA6
AF9
AE9
65mA
PP1V1_GPU_PLLVDD_F
AD9
VOLTAGE=1.2V
0402
1
C8630
4.7UF
4.7UF
20%
6.3V
20%
6.3V
CERM
CERM
603
e
r
C8631
0.1uF
10%
16V
603
X5R
402
CRITICAL
L8635
8
FERR-220-OHM
=PP1V1_GPU_H_PLLVDD
1
C8635
4.7UF
4.7UF
20%
6.3V
20%
6.3V
CERM
CERM
603
L8640
FERR-220-OHM
=PP1V1_GPU_VID_PLLVDD
1
0402
C8643
0.1uF
2
P
402
PP1V1_GPU_VID_PLLVDD_F
VOLTAGE=1.2V
CERM
603
C8641
0.1uF
20%
6.3V
603
X5R
10%
16V
X5R
402
75
IN
GPU_XTALIN
75
OUT
GPU_XTALOUT
75
10%
16V
4.7UF
20%
6.3V
C8636
50mA
C8640
4.7UF
CERM
603
CRITICAL
8
25mA
PP1V1_GPU_H_PLLVDD_F
VOLTAGE=1.2V
0402
C8637
T5
AA7
L8630
C8633
U5
74 GPU_MIOB_PD_VDDQ
FERR-220-OHM
1
75
OUT
IN
BI
75
GPU_GPIO_1
BI
75
K3
GPU_GPIO_2
BI
75
H3
GPU_GPIO_3
BI
75
H2
GPU_GPIO_4
BI
75
H1
GPU_GPIO_5
BI
75
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
H4
GPU_GPIO_6
BI
75
H5
GPU_GPIO_7
BI
75
H6
GPU_GPIO_8
BI
75
J7
GPU_GPIO_9
BI
75
K4
GPU_GPIO_10
BI
75
K5
GPU_GPIO_11
BI
75
H7
GPU_GPIO_12
BI
75
J4
GPU_GPIO_13
BI
75
J6
GPU_GPIO_14
BI
75
L1
GPU_GPIO_15
BI
75
L2
GPU_GPIO_16
BI
75
L4
GPU_GPIO_17
BI
75
M4
GPU_GPIO_18
BI
75
L7
GPU_GPIO_19
BI
75
L5
GPU_GPIO_20
BI
75
K6
GPU_GPIO_21
BI
75
L6
GPU_GPIO_22
BI
75
M6
GPU_GPIO_23
BI
HDA_SDI
HDA_SDO
HDA_SYNC
HDA_BCLK
HDA_RST*
C7
GPU_HDA_SDI
OUT
75
B7
GPU_HDA_SDO
OUT
75
A7
GPU_HDA_SYNC
OUT
75
D7
GPU_HDA_BCLK
OUT
75
GPU_HDA_RST_L
OUT
75
SPDIF
A5
IN
75
MIOB_VDDQ_1
MIOB_VDDQ_2
MIOB_VDDQ_3
MIOB_VDDQ_4
OUT
TESTMODE
MIOA_VREF
MIOB_VREF
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST*
m
il
74 GPU_MIOA_PD_VDDQ
CRITICAL
=PP1V1_GPU_PLLVDD
AP35
N5
R8660
5%
1/16W
MF-LF
402
GPU_GPIO_0
K2
BUFRST*
AA9
10K
1/16W
MIOA_VDDQ_1
MIOA_VDDQ_2
MIOA_VDDQ_3
MIOA_VDDQ_4
W9
MF-LF
R8617
49.9
1%
402
R8618
1/16W
402
402
CERM
AB9
10K
R8622
10%
6.3V
2
402
1%
1%
402
CERM
49.9
T9
U9
1UF
10%
6.3V
R8621
K1
B1
B2
GPU_XTALOUTBUFF
D1
GPU_XTALSSIN
D2
MIOA_CAL_PD_VDDQ
MIOA_CAL_PU_GND
MIOB_CAL_PD_VDDQ
MIOB_CAL_PU_GND
SP_PLLVDD
PLLVDD
VID_PLLVDD
XTAL_IN
XTAL_OUT
XTAL_OUTBUFF
XTAL_SSIN
y
r
a
n
i
R8697
40.2K
ROM_CS*
ROM_SCLK
ROM_SI
ROM_SO
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
MIOA_CLKIN
MIOA_CLKOUT
MIOA_CLKOUT*
MIOA_CTL3
MIOA_DE
MIOA_D0
MIOA_D1
MIOA_D2
MIOA_D3
MIOA_D4
MIOA_D5
MIOA_D6
MIOA_D7
MIOA_D8
MIOA_D9
MIOA_D10
MIOA_D11
MIOA_D12
MIOA_D13
MIOA_D14
MIOA_HSYNC
MIOA_VSYNC
MIOB_CLKIN
MIOB_CLKOUT
MIOB_CLKOUT*
MIOB_CTL3
MIOB_DE
MIOB_D0
MIOB_D1
MIOB_D2
MIOB_D3
MIOB_D4
MIOB_D5
MIOB_D6
MIOB_D7
MIOB_D8
MIOB_D9
MIOB_D10
MIOB_D11
MIOB_D12
MIOB_D13
MIOB_D14
MIOB_D15
MIOB_D16
MIOB_D17
MIOB_HSYNC
MIOB_VSYNC
D6
A4
GPU_SPDIF
TP_GPU_BUFRST_L
75
AP14
GPU_JTAG_TCK
IN
AN14
GPU_JTAG_TDI
IN
AN16
GPU_JTAG_TDO
OUT
AR14
GPU_JTAG_TMS
IN
AP16
GPU_JTAG_TRST_L
IN
N4
GPU_MIOA_CLKIN
IN
75
R4
GPU_MIOA_CLKOUT_P
BI
75
T4
GPU_MIOA_CLKOUT_N
BI
75
P5
GPU_MIOA_CTL3
BI
75
N2
GPU_MIOA_DE
BI
75
N1
GPU_MIOA_D<0>
BI
75
P4
GPU_MIOA_D<1>
BI
75
P1
GPU_MIOA_D<2>
BI
75
P2
GPU_MIOA_D<3>
BI
75
P3
GPU_MIOA_D<4>
BI
75
T3
GPU_MIOA_D<5>
BI
75
T2
GPU_MIOA_D<6>
BI
75
T1
GPU_MIOA_D<7>
BI
75
U4
GPU_MIOA_D<8>
BI
75
U1
GPU_MIOA_D<9>
BI
75
U2
GPU_MIOA_D<10>
BI
75
U3
GPU_MIOA_D<11>
BI
75
R6
GPU_MIOA_D<12>
BI
75
T6
GPU_MIOA_D<13>
BI
75
N6
GPU_MIOA_D<14>
BI
75
GPU_MIOA_HSYNC
BI
75
N3
L3
GPU_MIOA_VSYNC
BI
AE1
GPU_MIOB_CLKIN
IN
V4
GPU_MIOB_CLKOUT_P
BI
75
W4
GPU_MIOB_CLKOUT_N
BI
75
W3
GPU_MIOB_CTL3
BI
75
Y5
GPU_MIOB_DE
BI
75
Y1
GPU_MIOB_D<0>
BI
75
Y2
GPU_MIOB_D<1>
BI
75
Y3
GPU_MIOB_D<2>
BI
75
AB3
GPU_MIOB_D<3>
BI
75
AB2
GPU_MIOB_D<4>
BI
75
AB1
GPU_MIOB_D<5>
BI
75
AC4
GPU_MIOB_D<6>
BI
75
AC1
GPU_MIOB_D<7>
BI
75
AC2
GPU_MIOB_D<8>
BI
75
AC3
GPU_MIOB_D<9>
BI
75
AE3
GPU_MIOB_D<10>
BI
75
AE2
GPU_MIOB_D<11>
BI
75
U6
GPU_MIOB_D<12>
BI
75
W6
GPU_MIOB_D<13>
BI
75
Y6
GPU_MIOB_D<14>
BI
75
W5
GPU_STRAP<0>
BI
75
W7
GPU_STRAP<1>
BI
75
V7
GPU_STRAP<2>
BI
75
W1
GPU_MIOB_HSYNC
BI
75
W2
GPU_MIOB_VSYNC
BI
75
75
75
THERMDP
THERMDN
B5
GPU_THERMD_P
IN
75
B4
GPU_THERMD_N
OUT
75
PGOOD_OUT*
C5
TP_GPU_PGOOD_OUT_L
OUT
NV G96 GPIO/MIO/MISC
SYNC_MASTER=K20_MLB

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
86
123
Renamed signals
Native Func
Native Func
GPIOs
GPIOs
75 74 GPU_XTALOUT
Unused signals
GPU_XTALOUT
74 75
NC_GPU_SPDIF
GPU_XTALIN
74
NC_CPU_HDA_SDI
MAKE_BASE=TRUE
74
GP
GPU_GPIO_0
NC_GPU_GPIO_0
74
MAKE_BASE=TRUE
74
GPU_GPIO_1
74
GPU_GPIO_2
HPDC
HPDE
GPU_GPIO_15
NC_GPU_GPIO_15
MAKE_BASE=TRUE
NO_TEST=TRUE
DP_EG_HPD
IN
81
74
GPU_GPIO_16
74
GPU_GPIO_17
DVI_MODE0
MAKE_BASE=TRUE
EG_DP_CA_DET
LCD0_VDD
GPU_GPIO_3
HDMI_DETECT0
NC_GPU_GPIO_17
MAKE_BASE=TRUE
EG_LCD_PWR_EN
75 84
74
DVI_MODE1
GPU_GPIO_18
GPU_GPIO_4
74
GPU_GPIO_5
LCD0_BL_EN
75 84
74
GPU_GPIO_19
74
GPU_GPIO_20
HDMI_DETECT1
GPU_GPIO_6
74
GPU_GPIO_7
VID1
HPDD
74
GPU_GPIO_21
75 83
74
GPU_GPIO_22
74
GPU_GPIO_23
HPDF
THERM
GPU_GPIO_8
SMC_GFX_OVERTEMP_R_L
MAKE_BASE=TRUE
FAN_PWM
GPU_GPIO_9
75
SMC_GFX_THROTTLE_R_L
74
GPU_GPIO_11
NC_GPU_I2CC_SCL
71 72 73 75
MAKE_BASE=TRUE
GPU_I2CC_SCL
MAKE_BASE=TRUE
NO_TEST=TRUE
GPU_VCORE_VID0
OUT
NC_GPU_I2CC_SDA
77
GPU_I2CC_SDA
MAKE_BASE=TRUE
NO_TEST=TRUE
GPU_GPIO_12
74
GPU_GPIO_13
GPU_VCORE_VID1
OUT
77
NC_GPU_I2CD_SCL
OUT
77
NC_GPU_I2CD_SDA
MAKE_BASE=TRUE
GPU_I2CD_SCL
MAKE_BASE=TRUE
GPU_VCORE_VID2
MAKE_BASE=TRUE
GPU_I2CD_SDA
TP_GPU_VCORE_VID3
a
n
i
NC_GPU_I2CE_SCL
GPU_I2CE_SCL
MAKE_BASE=TRUE
MAKE_BASE=TRUE
Config Straps
NO_TEST=TRUE
NC_GPU_I2CE_SDA
GPU_I2CE_SDA
MAKE_BASE=TRUE
Physical
Strapping Pin
NO_TEST=TRUE
NC_GPU_I2CH_SCL
Strapping Bit 3
Strapping Bit 2
Strapping Bit 1
GPU_I2CH_SCL
MAKE_BASE=TRUE
Strapping Bit 0
NO_TEST=TRUE
NC_GPU_I2CH_SDA
ROM_SO
C
OUT GPU_ROM_SI
74
IN
GPU_ROM_SO
74
IN
GPU_ROM_SCLK
R8709
4.99K
4.99K
5%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
R8710
2.0K
15.0K
1%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
R8701
74
BI
R8712
45.3K
NO STUFF
BI
ROM_SCLK
PCI_DEVID[4]
SUB_VENDOR
SLOT_CLK_CFG
PEX_PLLEN_TERM100
ROM_SI
RAMCFG[3]
RAMCFG[2]
RAMCFG[1]
RAMCFG[0]
STRAP 2
2
PCI_DEVID[3]
PCI_DEVID[2]
3GIO_PADCFG[3]
3GIO_PADCFG[2]
3GIO_PADCFG[1]
3GIO_PADCFG[0]
STRAP 0
USER[3]
USER[2]
USER[1]
USER[0]
Strap S1/S2 Bit[3:0] PU/PD Rval

0 0000 PD 5k
1 0001 PD 10k
2 0010 PD 15k
3 0011 PD 20k
4 0100 PD 25k
5 0101 PD 30k
6 0110 PD 35k
7 0111 PD 45k
Strap S1/S2 Bit[3:0] PU/PD Rval

8 1000 PU 5k
9 1001 PU 10k
A 1010 PU 15k
B 1011 PU 20k
C 1100 PU 25k
D 1101 PU 30k
E 1110 PU 35k
F 1111 PU 45k
R8703
NO STUFF
1
R8705
45.3K
10K
10K
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
PART NUMBER
QTY
DESCRIPTION
R8708
114S0361
R8708
114S0343
e
r
R8708
114S0378
R8707
R8702
R8704
R8706
2.0K
10K
45.3K
5%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
78 8 7
75 74 8 6
=PP3V3_S0_DDC_LCD
=PP3V3_GPU_VDD33
R8750
81 75
81 75
=PP3V3_GPU_VDD33
81 9
DP_CA_DET_EG_FET
Q8742
DP_CA_DET_EG_FET
1
SSM3K15FV
EG_DP_CA_DET
DP_CA_DET
1%
1/16W
MF-LF
402 2
81 9
SOD-VESM-HF
1
100K
R8742
R8743
R8707
NO STUFF
1
R8708
114S0331
114S0361
IN
IN
BI
IN
BI
DP_EG_DDC_CLK
DP_EG_DDC_DATA
DP_IG_DDC_CLK
DP_IG_DDC_DATA
CRITICAL
R8751
R8752
R8753
4.7K
4.7K
4.7K
4.7K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
DP_CA_DET_EG
IN
76
76
TP_LVDS_EG_B_CLK_N
NC_LVDS_EG_A_DATA_P<3>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_LVDS_EG_B_DATA_N<3>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_GPU_MIOA_CTL3
MAKE_BASE=TRUE
R8782
7 TP_GPU_MIOA_D<9..0>
NC_GPU_MIOA_CLKIN
MAKE_BASE=TRUE
12pF
MAKE_BASE=TRUE
75 74
Y8780
27MHZ
SM-2
NC
NC
2
5%
50V
CERM
402
74
GPU_MIOA_D<14..10>
NC_GPU_MIOA_HSYNC
74
GPU_MIOA_HSYNC
MAKE_BASE=TRUE
74
GPU_MIOA_VSYNC
74
GPU_MIOB_CLKIN
74
GPU_MIOB_CLKOUT_P
74
GPU_MIOB_CLKOUT_N
74
GPU_MIOB_CTL3
74
GPU_MIOB_DE
74
GPU_MIOB_D<14..0>
74
GPU_MIOB_VSYNC
74
GPU_MIOB_HSYNC
74
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NC_GPU_MIOB_D<14..0>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_GPU_MIOB_VSYNC
NO_TEST=TRUE
NC_GPU_MIOB_HSYNC
MAKE_BASE=TRUE
NO_TEST=TRUE
C8781
12pF
1
GPU_XTALOUT
OUT
74
GPU_MIOA_CLKIN
NO_TEST=TRUE
MAKE_BASE=TRUE
CRITICAL
74
GPU_MIOA_D<9..0>
NO_TEST=TRUE
NC_GPU_MIOA_D<14..10>
MAKE_BASE=TRUE
C8780
5%
1/16W
MF-LF
402 2
74
GPU_MIOA_DE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
10M
74
GPU_MIOA_CTL3
MAKE_BASE=TRUE
MAKE_BASE=TRUE
74
GPU_MIOA_CLKOUT_N
NO_TEST=TRUE
7 TP_GPU_MIOA_DE
NC_GPU_MIOB_CTL3
GPU_CLK27M_XTALOUT_R
GPU_MIOA_CLKOUT_P
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_GPU_MIOB_DE
Unused Clocks
2
5%
50V
CERM
402
=PP3V3_GPU_VDD33
75 74
74
GPU_XTALSSIN
GPU_XTALOUTBUFF
GPU_SS_INT
R8796
R8797
R8780
10K
10K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
75 SMC_GFX_THROTTLE_R_L
R8799
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
81 82 84
SMC_GFX_OVERTEMP_L
OUT
41
SMC_GFX_THROTTLE_L
OUT
41
EG_LCD_PWR_EN
OUT
75 84
EG_BKLT_EN
OUT
75 84
GPIO7_FBVDD_ALTVO
OUT
75 83
OUT
71 72 73 75
FB_VREF_UNTERM
R8792
84
R8793
R8794
NO STUFF
R8795
10K
10K
10K
10K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
R8798
R8781
2.2K
75 SMC_GFX_OVERTEMP_R_L
2.2K
5%
1/16W
MF-LF
402
G96 GPIOs & Straps

SYNC_MASTER=M98_MLB

DP_CA_DET_EG_PLD
SIZE
DRAWING NUMBER
Isolation FETs for DP MUX inputs
APPLE INC.
REV.
051-7656
SCALE
SHT
NONE
NO_TEST=TRUE
NC_GPU_MIOA_CLKOUT_N
GPU 27MHz Crystal
5%
1/16W
MF-LF
402
76
G96 MIOA_DE and MIOA_D<9..0> are used as Debug Port.

NC_GPU_MIOA_CLKOUT_P
NC_GPU_MIOB_CLKOUT_N
76
LVDS_EG_B_DATA_N<3>
NO_TEST=TRUE
MAKE_BASE=TRUE
76
LVDS_EG_B_DATA_P<3>
NO_TEST=TRUE
MAKE_BASE=TRUE
NO STUFF
76
LVDS_EG_A_DATA_N<3>
NO_TEST=TRUE
NC_LVDS_EG_B_DATA_P<3>
NC_GPU_MIOB_CLKOUT_P
GPU_CLK27M
LVDS_EG_A_DATA_P<3>
NO_TEST=TRUE
NC_LVDS_EG_A_DATA_N<3>
NC_GPU_MIOB_CLKIN
IN
76
76
MAKE_BASE=TRUE
MAKE_BASE=TRUE
R8783
LVDS_EG_B_CLK_P
LVDS_EG_B_CLK_N
MAKE_BASE=TRUE
VRAM_1024_QIMONDA
75 74 8 6
TP_LVDS_EG_B_CLK_P
VRAM_256_SAMSUNG
95 75
74
NO_TEST=TRUE
NC_GPU_MIOA_VSYNC
71
GPU_ROM_CS_L
76
VRAM_512_QIMONDA
VRAM_1024_SAMSUNG
71
TP_FBC_CMD30
76
VRAM_256_HYNIX
0
1
BOM OPTION
71
TP_FBA_CMD30
NO_TEST=TRUE
NC_GPU_ROM_CS_L
VRAM_512_SAMSUNG
GPU_STRAP<2>
m
il
REFERENCE DES
114S0378
GPU_STRAP<1>
75
I2CS ties into SMBus connection page
PCI_DEVID[0]
STRAP 1
GPU_STRAP<0>
75 74 8 6
PCI_DEVID[1]
=PP3V3_GPU_MIO
75 74 8
74
NO STUFF
R8708
BI
TVMODE[0]
(I2CS requires pullups even if not used)
R8711
2.0K
OMIT
74
TVMODE[1]
NO STUFF
R8707
74
TVMODE[2]
NO_TEST=TRUE
OMIT
XCLK_277
MAKE_BASE=TRUE
75 74 8
=PP3V3_GPU_MIO
GPU_I2CH_SDA
GPU_GPIO_14
71
TP_FBC_CMD29
76
NO_TEST=TRUE
74
71
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_FBC_CMD30
76
PWR_CTL0
PWR_CTL1
76
MAKE_BASE=TRUE
AC_DET
74
NC_FBA_CMD30
TP_FBC_CMD28
TP_FBA_CMD29
NO_TEST=TRUE
MAKE_BASE=TRUE
SLI_SYNC
MAKE_BASE=TRUE
76
NO_TEST=TRUE
MAKE_BASE=TRUE
FB_VREF_UNTERM
71
NO_TEST=TRUE
NC_FBC_CMD29
75
71
TP_FBA_CMD28
NO_TEST=TRUE
MAKE_BASE=TRUE
MEM_VREF
GPU_GPIO_10
NC_FBC_CMD28
NC_FBA_CMD29
Unused I2C Buses
MAKE_BASE=TRUE
74
76
MAKE_BASE=TRUE
MAKE_BASE=TRUE
74
NC_FBA_CMD28
MAKE_BASE=TRUE
GPU_I2CB_SDA
81 75 DP_EG_DDC_DATA
NO_TEST=TRUE
76
71
FB_B_MA<13>
NO_TEST=TRUE
y
r
GPU_I2CB_SCL
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_GPU_GPIO_23
MAKE_BASE=TRUE
MAKE_BASE=TRUE
81 75 DP_EG_DDC_CLK
74
FB_A_MA<13>
NO_TEST=TRUE
NC_FBB_MA<13>
76
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
GPU_I2CA_SDA
74
GPU_HDA_RST_L
NO_TEST=TRUE
NC_FBA_MA<13>
76
MAKE_BASE=TRUE
81 LVDS_EG_DDC_DATA
NC_GPU_GPIO_22
GP
GPU_I2CA_SCL
MAKE_BASE=TRUE
74
GPU_HDA_BCLK
NO_TEST=TRUE
MAKE_BASE=TRUE
81 LVDS_EG_DDC_CLK
NO_TEST=TRUE
MAKE_BASE=TRUE
SWAPRDY_A
MAKE_BASE=TRUE
74
MAKE_BASE=TRUE
NO_TEST=TRUE
74
GPU_HDA_SYNC
NO_TEST=TRUE
NC_CPU_HDA_BCLK
74
74
GPU_HDA_SDO
NO_TEST=TRUE
NC_CPU_HDA_RST_L
NC_GPU_GPIO_21
MAKE_BASE=TRUE
GPIO7_FBVDD_ALTVO
GPU_THERMD_N
MAKE_BASE=TRUE
NC_GPU_GPIO_20
MAKE_BASE=TRUE
TP_GPU_GSTATE<1>
VID2/MEM_VID
NC_CPU_HDA_SYNC
MAKE_BASE=TRUE
96 47 GPU_TDIODE_N
NO_TEST=TRUE
MAKE_BASE=TRUE
TP_GPU_GSTATE<0>
MAKE_BASE=TRUE
74
74
NC_GPU_GPIO_19
MAKE_BASE=TRUE
GPU_THERMD_P
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
EG_BKLT_EN
VID0
NC_CPU_HDA_SD0
74
NO_TEST=TRUE
MAKE_BASE=TRUE
96 47 GPU_TDIODE_P
NC_GPU_GPIO_18
MAKE_BASE=TRUE
74
74 75
MAKE_BASE=TRUE
TP_LVDS_EG_BKL_PWM
MAKE_BASE=TRUE
74
GPU_XTALSSIN
GPU_SPDIF
GPU_HDA_SDI
NO_TEST=TRUE
MAKE_BASE=TRUE
95 GPU_CLK27M_SS
75
MAKE_BASE=TRUE
LCD0_BL_PWM
MAKE_BASE=TRUE
95 75 GPU_CLK27M
NO_TEST=TRUE
31
OF
87
123
Page Notes
CRITICAL
Sum of peak currents: 240mA
L8800
?mA peak per diff pair
FERR-220-OHM
8 =PP1V8_GPU_IFPX
- =PP1V8_GPU_IFPX
- =PP3V3_GPU_IFPCD_IOVDD
?mA peak for all pairs
PP1V8_GPU_IFPAB_IOVDD_F
VOLTAGE=1.8V
0402
C8800
C8801
4.7UF
CERM
OMIT
0.1UF
20%
10V
CERM
402
603
C8803
0.1UF
20%
6.3V
(NONE)
20%
10V
CERM
402
U8000
NB9P-GS
BGA
(NONE)
Place at AG9
Place at AG10
AG9
CRITICAL
AG10
L8805
GPU_IFPEF_RSET
76
GPU_IFPCD_RSET
76
GPU_IFPAB_RSET
FERR-220-OHM
1
76
AK8
80mA peak
PP1V8_GPU_IFPAB_PLLVDD_F
0402
C8805
0.1UF
20%
6.3V
20%
10V
CERM
402
603
R8855
R8850
1K
1K
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
AE7
76 PP1V1_GPU_IFPEF_IOVDD_F
VOLTAGE=1.8V
AD7
AK9
AJ11
76 GPU_IFPAB_RSET
2
AJ9
76 PP1V8_GPU_IFPCD_PLLVDD_F
R8851
1K
C8806
4.7UF
CERM
AJ8
76 PP1V1_GPU_IFPCD_IOVDD_F
AK7
76 GPU_IFPCD_RSET
AJ6
76 PP1V8_GPU_IFPEF_PLLVDD_F
AL1
76 GPU_IFPEF_RSET
L8810
1
8 =PP1V1_GPU_IFPCD_IOVDD
?mA peak per diff pair

?mA peak for all pairs
PP1V1_GPU_IFPCD_IOVDD_F
C8810
C8811
4.7UF
C8813
0.1UF
2
603
20%
10V
CERM
402
Place at AJ8
75
75
GPU_I2CA_SCL
BI
GPU_I2CA_SDA
G4
Place at AK8
75
BI
GPU_I2CC_SCL
75
BI
GPU_I2CC_SDA
I2CS addr fixed at 0x9E,0x9F
L8815
BI
G1
I2CS must be pulled up if not used
CRITICAL
0.1UF
20%
10V
CERM
402
20%
6.3V
CERM
76
VOLTAGE=1.1V
0402
E3
E4
FERR-220-OHM
1
160mA peak
PP1V8_GPU_IFPCD_PLLVDD_F
VOLTAGE=1.8V
0402
C8815
4.7UF
0.1UF
20%
6.3V
CERM
PP1V1_GPU_IFPEF_IOVDD_F
PP1V8_GPU_IFPEF_PLLVDD_F
603
76
76
44
BI
=GPU_I2CS_SCL
44
BI
=GPU_I2CS_SDA
C8816
20%
10V
CERM
402
75
Power inputs must be pulled down if not used
R8856
R8857
10K
10K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
75
75
e
r
E1
m
il
76
75
E2
I2CS must be pulled up if not used.

I2CS addr fixed at 0x9E,0x9F
BI
BI
GPU_I2CH_SCL
GPU_I2CH_SDA
BI
GPU_I2CB_SCL
BI
GPU_I2CB_SDA
F6
G6
G3
G2
75
GPU_I2CD_SCL
F4
BI
75
GPU_I2CD_SDA
G5
BI
75
75
GPU_I2CE_SCL
D5
BI
E5
BI
GPU_I2CE_SDA
AJ12
R8853
10K
10K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
84 95
OUT
84 95
LVDS_EG_A_DATA_P<0>
AL8
OUT
84 95
LVDS_EG_A_DATA_N<0>
OUT
84 95
AM10
LVDS_EG_A_DATA_P<1>
OUT
84 95
AM9
LVDS_EG_A_DATA_N<1>
OUT
84 95
AK10
LVDS_EG_A_DATA_P<2>
OUT
84 95
AL10
LVDS_EG_A_DATA_N<2>
OUT
7 84 95
AK11
LVDS_EG_A_DATA_P<3>
OUT
75
AL11
LVDS_EG_A_DATA_N<3>
OUT
75
AP13
LVDS_EG_B_CLK_P
OUT
75
AN13
LVDS_EG_B_CLK_N
OUT
75
LVDS_EG_B_DATA_P<0>
OUT
84 95
I2CS_SCL
I2CS_SDA
I2CH_SCL
I2CH_SDA
I2CB_SCL
I2CB_SDA
I2CD_SCL
I2CD_SDA
I2CE_SCL
I2CE_SDA
AN8
AP8
LVDS_EG_B_DATA_N<0>
OUT
84 95
AP10
LVDS_EG_B_DATA_P<1>
OUT
84 95
AN10
LVDS_EG_B_DATA_N<1>
OUT
84 95
AR11
LVDS_EG_B_DATA_P<2>
OUT
84 95
AR10
LVDS_EG_B_DATA_N<2>
OUT
84 95
AN11
LVDS_EG_B_DATA_P<3>
OUT
75
AP11
LVDS_EG_B_DATA_N<3>
OUT
75
IFPC_AUX
IFPC_AUX*
AP2
DP_EG_AUX_CH_P
OUT
81 95
AN3
DP_EG_AUX_CH_N
OUT
81 95
IFPC_L0
IFPC_L0*
IFPC_L1
IFPC_L1*
IFPC_L2
IFPC_L2*
IFPC_L3
IFPC_L3*
AM7
IFPD_AUX
IFPD_AUX*
AP4
IFPD_L0
IFPD_L0*
IFPD_L1
IFPD_L1*
IFPD_L2
IFPD_L2*
IFPD_L3
IFPD_L3*
AR8
IFPE_AUX
IFPE_AUX*
AE4
IFPE_L0
IFPE_L0*
IFPE_L1
IFPE_L1*
IFPE_L2
IFPE_L2*
IFPE_L3
IFPE_L3*
AH6
IFPF_AUX
IFPF_AUX*
AF3
IFPF_L0
IFPF_L0*
IFPF_L1
IFPF_L1*
IFPF_L2
IFPF_L2*
IFPF_L3
IFPF_L3*
AL2
DP_EG_ML_P<0>
OUT
81 95
DP_EG_ML_N<0>
OUT
81 95
DP_EG_ML_P<1>
OUT
81 95
OUT
81 95
DP_EG_ML_P<2>
OUT
81 95
AM4
DP_EG_ML_N<2>
OUT
81 95
AP1
DP_EG_ML_P<3>
OUT
81 95
DP_EG_ML_N<3>
OUT
81 95
AM6
AL5
AM5
DP_EG_ML_N<1>
AM3
AR2
AN4
AR7
AP7
AN7
AN5
AP5
AR5
AR4
AD4
AH5
AH4
AG4
AF4
AF5
AE6
AE5
AF2
AL3
AJ3
AJ2
AJ1
AH1
AH2
AH3
5%
1/16W
MF-LF
402
NC
NC
NC
NC
NC
NC
NC
NC
AA4
AC5
DACB_VREF
DACB_RSET
DACB_CSYNC
AB5
DACC_VREF
DACC_RSET
1K
R8860
5%
1/16W
MF-LF
402
NC
NC
DACB_RED
DACB_GREEN
DACB_BLUE
AK6
1K
NC
NC
NC
NC
NC
NC
NC
NC
DACB_VDD
NC
AH7
NC
R8861
NC
NC
AC6
DACC_VDD
NC
NC
NC
NC
NC
NC
NC
NC
AM13
AG7
NO STUFF
NC
NC
DACA_HSYNC
DACA_VSYNC
DACA_VDD
y
r
AM8
DACA_VREF
DACA_RSET
NC AB6
NC
R8854
10K
OUT
LVDS_EG_A_CLK_N
AM15
AK12
GPU_DACA_VDD
I2CC_SCL
I2CC_SDA
GPU_DACB_VDD
R8852
LVDS_EG_A_CLK_P
AM12
DACA_RED
DACA_GREEN
DACA_BLUE
NC
AK13
NC
GPU_DACC_VDD
AM11
a
n
i
CRITICAL
FERR-220-OHM
SYMBOL 5 OF 9
IFPA_TXC
IFPA_IOVDD
IFPB_IOVDD
IFPA_TXC*
IFPC_IOVDD
IFPA_TXD0
IFPD_IOVDD
IFPA_TXD0*
IFPE_IOVDD
IFPA_TXD1
IFPF_IOVDD
IFPA_TXD1*
IFPAB_PLLVDD
IFPA_TXD2
IFPAB_RSET
IFPA_TXD2*
IFPA_TXD3
IFPCD_PLLVDD
IFPA_TXD3*
IFPCD_RSET
IFPB_TXC
IFPEF_PLLVDD
IFPB_TXC*
IFPEF_RSET
IFPB_TXD4
IFPB_TXD4*
IFPB_TXD5
IFPB_TXD5*
IFPB_TXD6
IFPB_TXD6*
I2CA_SCL
I2CA_SDA
IFPB_TXD7
IFPB_TXD7*
NC
NC
NC
AM14
AL14
NC
NC
AL13
AB4
Y4
DACC_RED
DACC_GREEN
DACC_BLUE
AK4
DACC_HSYNC
DACC_VSYNC
AM1
AL4
AJ4
AM2
NC
NC
NC
NV G96 Video Interfaces
NC
SYNC_MASTER=K20_MLB
NC
NC
NC

NC
NC

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
88
123
8
1
1
VOLTAGE=5V
C8902
C8903
4.7UF
0.01uF
20%
6.3V
X5R-CERM
402
10%
16V
CERM
402
CRITICAL
C8931
R8904
PP5V_S5_GFXIMVP6_VDD
16
10%
10V
X5R
402
VDD
150K
GFXIMVP6_RBIAS 1 RBIAS
1%
1/16W
MF-LF
402
GFXIMVP6_SOFT
GFXIMVP6_IMON
67
GPUVCORE_PGOOD
GFXIMVP6_VID0
GFXIMVP6_VID1
GFXIMVP6_VID2
GFXIMVP6_VID3
GFXIMVP6_VID4
=GPUVCORE_EN
GFXIMVP6_AF_EN
GFXIMVP6_FDE
OUT
77
77
R8910
77
10K
77
5%
1/16W
MF-LF
402
2 SOFT
46
1UF
2
2
C8933
10%
25V
X5R
603-1
1UF
C8934
0.001UF
10%
25V
X5R
603-1
10%
50V
X7R
402
77
84 67
IN
VIN 14
28 IMON
31
23
24
25
26
27
29
30
32
5
2
GFXIMVP6_VIN
CRITICAL
UGATE 18
Q8950
GFXIMVP6_UGATE
RJK0305DPB
LFPAK-HF
GFXIMVP6_BOOT
BOOT 17
C8956
10%
16V
X7R
603
PGOOD
VID0
VID1
VID2
VID3
VID4
VR_ON
AF_EN
FDE
PHASE 19
a
n
i
1
1
0.22UF
C
R8920
20
GFXIMVP6_PHASE
Q8951
GFXIMVP6_LGATE
RJK0328DPB
LFPAK-HF
1
1
20
C8921
10%
50V
CERM
402
10%
50V
CERM
402
(GFXIMVP6_AGND)
5%
1/16W
MF-LF
402
4 VW
R8909 1
180PF
GFXIMVP6_COMP_RC
R8950
374K
R8900
OCSET 3
R8951
C8951
560PF
1
GFXIMVP6_VDIFF_RC
GFXIMVP6_DFB
R8953
10%
50V
CERM
402
ICOMP 10
7 VDIFF
GFXIMVP6_VDIFF
9.76K
PGND
R8986
75
IN
GPU_VCORE_VID0
IN
GPU_VCORE_VID1
GPUVID1_1
R8987 1
5%
1/16W
MF-LF
402
R8990
75
GPUVID0_1
2.2K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
R8994
75
IN
GPU_VCORE_VID2
GPUVID1_0
GFXIMVP6_DROOP
THRM_PAD
VSS
2
5%
1/16W
MF-LF
402
R8982 1
2.2K
5%
1/16W
MF-LF
402
R8980 1
0
5%
1/16W
MF-LF
402
C8971
68PF
2.2K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
C8906
1%
1/16W
MF-LF
2 402
10UF
20%
6.3V
X5R
603
10UF
20%
6.3V
X5R
603
10UF
20%
6.3V
X5R
603
C8965
330UF
20%
2.0V
POLY-TANT
D2T-SM2
CRITICAL
10UF
C8967
C8942
20%
6.3V
X5R
603
C8943
330UF
20%
2.0V
POLY-TANT
D2T-SM2
PLACE C8965,C8966,C8967 AND C8968 ON THE BACK SIDE OF GPU
5%
50V
COG
402
5%
50V
CERM
402-1
C8972
330PF
(PPVCORE_GPU_REG)
0.1uF
10%
16V
X5R
402
GPU VCore Setpoints
XW8900
SM
VID3
VID2
VID1
VID0
Voltage
Max Batt
X
0.90125V
0.92700V
1.00425V
Balanced
Max perf
-
Other VID states may not be valid
GFXIMVP6_VID0
GFXIMVP6_VID1
GFXIMVP6_VID2
GFXIMVP6_VID3
GFXIMVP6_VID4
77
Default Vcore Setpoints
GPU (G96) CORE SUPPLY
77
SYNC_MASTER=RXU_K20
77
77
TABLE_BOMGROUP_HEAD
BOM GROUP
BOM OPTIONS
GPUVID_0P90V
GPUVID2_1,GPUVID1_1,GPUVID0_1
GPUVID_1P00V
GPUVID2_0,GPUVID1_1,GPUVID0_1
77
TABLE_BOMGROUP_ITEM
R8983 1
2.2K
C8968
VOLTAGE=0V
GPUVID2_0
R8985 1
0
1
GPUVID2_1
R8984 1
2.2K
5%
1/16W
MF-LF
402
8 45
12A max output

(L8920 limit)
CRITICAL
R8901
5.11K
GND_GFXIMVP6_AGND
77 8
10%
50V
X7R
402
R8902 2
1%
1/16W
MF-LF
402 1
1%
1/16W
MF-LF
402
C8969
0.001UF
=PPVCORE_GPU_REG
C8966
1%
1/16W
MF-LF
402
ISP 13
ISN 11
20
7.15K
e
r
6 FB
2.21K
4.99K
GFXIMVP6_OCSET
GFXIMVP6_VO
GFXIMVP6_FB
Vout = 1.05V - 0.96V
m
il
GFXIMVP6_VSUM
VO 12
5%
50V
CERM
402-1
1%
1/16W
MF-LF
402
1K
1%
1/16W
MF-LF
402 2
C8952
5 COMP
68PF
1%
1/16W
MF-LF
2 402
10%
50V
CERM
402
10%
50V
X7R
402
5%
50V
CERM
402
R8903 1
C8922
GFXIMVP6_COMP
GFXIMVP6_PHASE_VSUM
C8953
0.001UF
1%
1/16W
MF-LF
402 2
C8950
1
4.99K
PLACEMENT_NOTE=Place R8920 at U8900

PLACEMENT_NOTE=Place R8908 at U8900
680pF
GFXIMVP6_VW
VOLTAGE=0V
0.001UF
10%
50V
CERM
402
33
GPU_GND_SENSE
C8923
0.001UF
0.001UF
R8908
69
C8920
5%
1/16W
MF-LF
402
PPVCORE_GPU_REG_R
PCMC063T-SM
5
CRITICAL
15
GPU_VDD_SENSE
1%
1W
MF
0612
0.68UH-25A-5.5MOHM
8 VSEN
9 RTN
GFXIMVP6_VSEN_P
GFXIMVP6_VSEN_N
0.001
L8920
SWITCH_NODE=TRUE
LGATE 21
R8940
CRITICAL
VOLTAGE=1.25V
y
r
1K
5%
1/16W
MF-LF
402
QFN
C8904
10%
16V
X5R
402
C8932
R8930 1
U8900
0.033UF
2
10K
20%
16V
POLY-TANT
CASED2E-SM
PVCC
ISL6263C
5%
1/16W
MF-LF
402
33UF
CRITICAL
R8905
R8907
C8930
20%
16V
POLY-TANT
CASED2E-SM
=PPVIN_GPU_GPUVCORE
C8901
1uF
33UF
VOLTAGE=5V
1%
1/16W
MF-LF
402
CRITICAL
22
10
69
PP5V_S5_GFXIMVP6_PVCC
2
5%
1/16W
MF-LF
402
77 8
R8911
=PP5V_S3_GPUVCORE
6
5
GPU VCore Regulator

TABLE_BOMGROUP_ITEM
R8988
0
2
2
5%
1/16W
MF-LF
402

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
89
123
y
r
LCD (LVDS) INTERFACE

8 =PP3V3_S0_LCD
C9000
R9000
0.0022uF
100K
R9001
CRITICAL
10%
50V
CERM
402
VOLTAGE=3.3V
CRITICAL
2
5%
1/16W
MF-LF
402
FERR-250-OHM
PP3V3_SW_LCD_UF
100K
1
Q9000
LCD_PWREN_L_RC
3
FDC638P_G
SM
C9001
SM
C9002
0.1UF
0.001UF
10%
16V
X5R
402
10%
50V
X7R
402
LCD_PWREN_L
Q9001
SSM3K15FV
a
n
i
L9000
4
5%
1/16W
MF-LF
402
CRITICAL
3
6
J9000
SOD-VESM-HF
20474-040E-11
84
IN
F-RT-SM
41
LCD_PWR_EN
75 8 7 =PP3V3_S0_DDC_LCD
42
R9010
100K pull-ups are for

no-panel case (development).
Panel has 2K pull-ups
R9011
100K
100K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
7 PP3V3_SW_LCD
VOLTAGE=3.3V
85 7
LVDS_DDC_CLK
81 7
LVDS_DDC_DATA
7
8
m
il
C9010
10%
50V
X7R
402
CRITICAL
L9010
90-OHM-100MA
DLP11S
SYM_VER-1
e
r
95 81 LVDS_CONN_B_CLK_N
95 81 LVDS_CONN_B_CLK_P
95 81 7 LVDS_CONN_A_DATA_N<1>
11
95 81 7 LVDS_CONN_A_DATA_P<1>
12
13
14
15
16
95 7 LVDS_CONN_A_CLK_F_N
17
95 7 LVDS_CONN_A_CLK_F_P
18
19
95 81 7 LVDS_CONN_B_DATA_N<0>
20
95 81 7 LVDS_CONN_B_DATA_P<0>
21
22
23
24
CRITICAL
25
L9011
90-OHM-100MA
26
27
DLP11S
SYM_VER-1
28
95 7 LVDS_CONN_B_CLK_F_N
29
95 7 LVDS_CONN_B_CLK_F_P
30
Place close to the connector
10
Place close to the connector
0.001UF
95 81 LVDS_CONN_A_CLK_P
81 7
BKL_SYNC
95 81 LVDS_CONN_A_CLK_N
85 7
LED_RETURN_1
31
85 7
LED_RETURN_2
32
85 7
LED_RETURN_3
33
85 7
LED_RETURN_4
34
85 7
LED_RETURN_5
35
85 7
LED_RETURN_6
518S0651
36
NC
37
38
39
85 7
PPVOUT_S0_LCDBKLT
40
43
44
LVDS Display Connector

SYNC_MASTER=M98_MLB

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
90
123
CRITICAL
OMIT
VRAM8
C9100
10UF
C9101
0.1uF
20%
6.3V
X5R
VRAM8
603
VRAM8
1
C9102
0.1uF
10%
16V
X5R
402
C9103
F1
C9104
0.1uF
10%
16V
X5R
402
A11
VRAM8
0.1uF
10%
16V
X5R
402
F12
10%
16V
X5R
402
M1
M12
V2
V11
K1
K12
VRAM8
1
VRAM8
1
C9110
C9115
0.1uF
0.1uF
10%
16V
X5R
402
10%
16V
X5R
402
U8400.J1
A1
A12
C1
C4
C9
U8400.J12
C12
E1
80 79 73 72 9 8 =PP1V8_GPU_FB_VDDQ
E4
E9
VRAM8
VRAM8
VRAM8
VRAM8
VRAM8
VRAM8
VRAM8
E12
C9120
10UF
20%
6.3V
X5R
603
C9121
C9122
C9123
C9124
C9125
C9126
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
V1
V12
72
IN
FB_A2_VREF
H1
72
IN
FB_A0_VREF
H12
VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDDA0
VDDA1
VDDQ0
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21
VSS0
A3
VSS1
VSS2
A10
VSS3
G12
VSS4
VSS5
L1
VSS6
VSS7
V3
VSSA0
VSSA1
J1
VSSQ0
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ15
VSSQ16
VSSQ17
VSSQ18
VSSQ19
B1
BGA
(2 OF 2)
A2
G1
603
L12
C9151
0.1uF
20%
6.3V
X5R
VRAM8
VRAM8
1
C9152
0.1uF
10%
16V
X5R
402
C9153
F1
C9154
0.1uF
10%
16V
X5R
402
A11
VRAM8
0.1uF
10%
16V
X5R
402
F12
10%
16V
X5R
402
M1
M12
V2
V10
V11
K1
J12
K12
VRAM8
1
B4
VRAM8
1
C9160
C9165
0.1uF
B9
2
B12
D1
A1
A12
0.1uF
10%
16V
X5R
402
10%
16V
X5R
402
C1
U8400.J12
C9
U8400.J1
C4
D4
C12
D9
E1
80 79 73 72 9 8 =PP1V8_GPU_FB_VDDQ
E4
G2
E9
VRAM8
VRAM8
VRAM8
VRAM8
VRAM8
VRAM8
VRAM8
E12
C9170
L2
10UF
L11
20%
6.3V
X5R
P1
603
C9171
C9172
C9173
C9174
C9175
C9176
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
J4
J9
VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDDA0
VDDA1
VDDQ0
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21
U9150
BGA
(2 OF 2)
N1
N4
P4
N9
P9
P12
N12
T1
R1
T4
R4
T9
R9
T12
R12
V1
V12
VREF0
VREF1
72
IN
FB_A3_VREF
H1
72
IN
FB_A1_VREF
H12
m
il
VREF0
VREF1
A3
- =PP1V8_S0_FB_VDD
VSS1
VSS2
A10
- =PP1V8_S0_FB_VDDQ
VSS3
G12
VSS4
VSS5
L1
L12
VSS6
VSS7
V3
VRAM8
VSSA0
VSSA1
J1
G1
(NONE)
V10
J12
y
r
a
n
i
2
VSS0
VSSQ0
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ15
VSSQ16
VSSQ17
VSSQ18
VSSQ19
B1
B4
B9
B12
D1
D4
D9
D12
G2
G11
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12
DM0
E3
FB_A_DQM_L<2>
IN
71 72 95
95 79 72 71
IN
FB_A_MA<0>
K4
A0
U9150
DM0
E3
FB_A_DQM_L<5>
IN
71 72 95
BGA
DM1
E10
FB_A_DQM_L<3>
IN
71 72 95
95 79 72 71
IN
FB_A_MA<1>
H2
A1
BGA
DM1
E10
FB_A_DQM_L<7>
IN
71 72 95
IN
(1 OF 2)
FB_A_DQM_L<1>
IN
71 72 95
95 72 71
IN
FB_A_UMA<2>
K3
FB_A_DQM_L<4>
IN
71 72 95
M4
N3
FB_A_DQM_L<0>
IN
71 72 95
95 72 71
IN
FB_A_UMA<3>
M4
DM2
DM3
N10
FB_A_LMA<3>
A2
A3
(1 OF 2)
IN
DM2
DM3
N10
95 72 71
A2
A3
N3
FB_A_DQM_L<6>
IN
71 72 95
95 72 71
B2
95 72 71
DQ0
FB_A_DQ<20>
BI
7 71 72 95
DQ0
B2
FB_A_DQ<40>
BI
7 71 72 95
DQ1
DQ2
B3
FB_A_DQ<47>
BI
7 71 72 95
C2
FB_A_DQ<46>
BI
7 71 72 95
DQ3
C3
FB_A_DQ<45>
BI
7 71 72 95
FB_A_DQ<42>
A4
A5
95 79 72 71
IN
FB_A_MA<6>
K10
A6
95 79 72 71
IN
FB_A_MA<7>
L9
95 79 72 71
IN
FB_A_MA<8>
K11
95 79 72 71
IN
FB_A_MA<9>
M9
A9
95 79 72 71
IN
FB_A_MA<10>
K2
A10
A11
CKE
FB_A_MA<11>
95 79 72 71
IN
FB_A_CKE
IN
FB_A_MA<12>
95 72 71
IN
FB_A_CLK_P<0>
IN
FB_A_CLK_N<0>
95 79 71
IN
FB_A_CS1_L
95 79 72 71
IN
FB_A_WE_L
95 72 71
95 79 72 71
95 79 72 71
IN
FB_A_CAS_L
IN
FB_A_RAS_L
L4
H4
J3
95 79 72 71
IN
95 72 71
OUT FB_A_RDQS<2>
95 72 71
OUT FB_A_RDQS<3>
95 72 71
95 72 71
OUT FB_A_RDQS<0>
95 72 71
IN
FB_A_WDQS<2>
95 72 71
IN
FB_A_WDQS<3>
95 72 71
IN
FB_A_WDQS<1>
95 72 71
IN
FB_A_WDQS<0>
95 79 72 71
IN
R9140
R9148
1K
243
5%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
2
VRAM8
1
R9149
NC
FB_A_DQ<43>
BI
7 71 72 95
FB_A_DQ<41>
BI
7 71 72 95
CKE
DQ7
DQ8
G3
B11
FB_A_DQ<59>
BI
7 71 72 95
DQ9
B10
FB_A_DQ<58>
BI
7 71 72 95
DQ10
DQ11
C11
FB_A_DQ<63>
BI
7 71 72 95
C10
FB_A_DQ<60>
BI
7 71 72 95
DQ12
DQ13
E11
FB_A_DQ<57>
BI
7 71 72 95
F10
FB_A_DQ<56>
BI
7 71 72 95
DQ14
F11
FB_A_DQ<61>
BI
7 71 72 95
G10
FB_A_DQ<62>
BI
7 71 72 95
M11
FB_A_DQ<36>
BI
7 71 72 95
BI
7 71 72 95
DQ9
B10
FB_A_DQ<30>
BI
7 71 72 95
DQ10
DQ11
C11
FB_A_DQ<29>
BI
7 71 72 95
C10
FB_A_DQ<31>
BI
7 71 72 95
95 72 71
DQ12
DQ13
E11
FB_A_DQ<28>
BI
7 71 72 95
95 79 71
F10
FB_A_DQ<27>
BI
7 71 72 95
95 79 72 71
DQ14
F11
FB_A_DQ<25>
BI
7 71 72 95
95 79 72 71
G10
FB_A_DQ<26>
BI
7 71 72 95
95 79 72 71
M11
FB_A_DQ<13>
BI
7 71 72 95
BI
95 79 72 71
IN
FB_A_MA<11>
95 79 72 71
IN
FB_A_CKE
IN
FB_A_MA<12>
95 79 72 71
L4
H4
J3
A7
A8/AP
A12/CS1*
IN
FB_A_CLK_P<1>
J11
IN
FB_A_CLK_N<1>
J10
IN
FB_A_CS1_L
F9
IN
FB_A_WE_L
H9
IN
FB_A_CAS_L
F4
IN
FB_A_RAS_L
H3
CK*
CS0*
WE*
CAS*
RAS*
FB_A3_ZQ
A4
ZQ
DQ15
DQ16
7 71 72 95
FB_A3_MF
A9
MF
DQ17
L10
FB_A_DQ<37>
BI
7 71 72 95
FB_A3_SEN
V4
SEN
FB_A_DQ<32>
BI
7 71 72 95
V9
RESET
DQ18
DQ19
N11
M10
FB_A_DQ<38>
BI
7 71 72 95
DQ20
R11
FB_A_DQ<39>
BI
7 71 72 95
DQ21
DQ22
R10
FB_A_DQ<34>
BI
7 71 72 95
T11
FB_A_DQ<33>
BI
7 71 72 95
DQ23
DQ24
T10
FB_A_DQ<35>
BI
7 71 72 95
M2
FB_A_DQ<54>
BI
DQ25
L3
FB_A_DQ<55>
BI
7 71 72
95
7 71 72
95
N2
FB_A_DQ<53>
BI
M3
FB_A_DQ<52>
BI
BI
7 71 72 95
FB_A_DQ<8>
BI
7 71 72 95
DQ23
DQ24
T10
FB_A_DQ<11>
BI
7 71 72 95
M2
FB_A_DQ<5>
BI
7 71 72 95
DQ25
L3
FB_A_DQ<4>
BI
N2
FB_A_DQ<6>
M3
FB_A_DQ<7>
95 72 71
95 79 72 71
IN
FB_A_DRAM_RST
95 72 71
OUT FB_A_RDQS<5>
D3
95 72 71
OUT FB_A_RDQS<7>
D10
OUT FB_A_RDQS<4>
P10
95 72 71
CK
RDQS0
RDQS1
RDQS2
95 72 71
OUT FB_A_RDQS<6>
P3
7 71 72 95
95 72 71
IN
FB_A_WDQS<5>
D2
BI
7 71 72 95
95 72 71
IN
FB_A_WDQS<7>
D11
WDQS0
WDQS1
BI
7 71 72 95
95 72 71
IN
FB_A_WDQS<4>
P11
WDQS2
DQ26
DQ27
BI
7 71 72 95
95 72 71
IN
FB_A_WDQS<6>
P2
WDQS3
DQ28
R2
FB_A_DQ<49>
BI
DQ29
DQ30
R3
FB_A_DQ<51>
BI
T2
FB_A_DQ<50>
BI
7 71 72
95
7 71 72
95
DQ31
T3
FB_A_DQ<48>
BI
7 71 72
95
D11
WDQS0
WDQS1
P11
WDQS2
DQ26
DQ27
P2
WDQS3
DQ28
R2
FB_A_DQ<2>
DQ29
DQ30
R3
FB_A_DQ<3>
BI
7 71 72 95
T2
FB_A_DQ<1>
BI
7 71 72 95
DQ31
T3
FB_A_DQ<0>
BI
7 71 72 95
95 79 72 71
IN
G4
FB_A_BA<0>
BA0
95 79 72 71
IN
FB_A_BA<1>
G9
IN
FB_A_BA<2>
H10
BA1
BA2
J2
RFU
7 71 72
95
7 71 72
95
7 71 72
95
GDDR3 Frame Buffer A (Top)

SYNC_MASTER=M99_MLB

VRAM8
R9190
5%
1/16W
MF-LF
402
RDQS3
95 79 72 71
VRAM8
100
F2
7 71 72 95
FB_A_DQ<9>
RFU
VRAM8
DQ6
BI
T11
J2
VRAM8
BI
7 71 72 95
A10
A11
FB_A_DQ<24>
DQ21
DQ22
BA1
BA2
K2
FB_A_DQ<17>
R10
G9
FB_A_DQ<44>
FB_A_MA<10>
B11
7 71 72 95
H10
F3
IN
DQ7
DQ8
BI
FB_A_BA<2>
A9
95 79 72 71
G3
BI
FB_A_BA<1>
FB_A_MA<9>
BI
IN
M9
7 71 72 95
95 79 72 71
DQ4
DQ5
E2
7 71 72 95
FB_A_DQ<10>
IN
K11
7 71 72 95
R11
IN
FB_A_MA<8>
7 71 72 95
DQ20
95 79 72 71
IN
BI
7 71 72 95
95 79 72 71
95 79 72 71
BI
7 71 72 95
BA0
L9
BI
BI
G4
FB_A_MA<7>
FB_A_DQ<16>
FB_A_DQ<12>
D2
IN
FB_A_DQ<18>
M10
RDQS3
95 79 72 71
F2
DQ18
DQ19
P3
A6
F3
FB_A_DQ<14>
P10
K10
DQ6
FB_A_DQ<15>
RDQS1
RDQS2
FB_A_MA<6>
7 71 72 95
N11
RDQS0
IN
DQ4
DQ5
BI
L10
RESET
95 79 72 71
FB_A_DQ<19>
DQ17
SEN
A4
A5
FB_A_DQ<23>
MF
V9
IN
H11
E2
A9
V4
K9
FB_A_UMA<5>
C3
ZQ
D10
FB_A_BA<0>
7 71 72 95
A4
D3
OUT FB_A_RDQS<1>
7 71 72 95
BI
DQ15
DQ16
F4
FB_A_DRAM_RST
BI
FB_A_DQ<21>
H3
H9
FB_A2_SEN
e
r
FB_A_DQ<22>
C2
CK*
CS0*
WE*
CAS*
RAS*
F9
FB_A2_MF
CK
B3
FB_A_UMA<4>
DQ3
P
J11
J10
FB_A2_ZQ
A12/CS1*
MFLOW
IN
MFLOW
95 79 72 71
A7
A8/AP
DQ1
DQ2
IN
95 72 71
MFLOW
IN
H11
MFLOW
K9
FB_A_LMA<5>
MFLOW
FB_A_LMA<4>
MFLOW
IN
95 72 71
K4J10324QD-HC11
U9100
A1
K3
32MX32-900MHZ-MFL
A0
H2
FB_A_LMA<2>
K4J10324QD-HC11
K4
FB_A_MA<1>
32MX32-900MHZ-MFL
FB_A_MA<0>
IN
IN
95 79 72 71
CRITICAL
OMIT
95 72 71
95 79 72 71
95 79 72 71
10UF
CRITICAL
OMIT
VRAM8
C9150
G11
Page Notes
VRAM8
D12
CRITICAL
OMIT
80 79 73 72 8 =PP1V8_GPU_FB_VDD
U9100
K4J10324QD-HC11
A2
VRAM8
32MX32-900MHZ-MFL
80 79 73 72 8 =PP1V8_GPU_FB_VDD
K4J10324QD-HC11
32MX32-900MHZ-MFL
R9198
1K
243
5%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
2
VRAM8
1
R9199
NC

100
5%
1/16W
MF-LF
402
2
SIZE
DRAWING NUMBER
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
91
123
CRITICAL
OMIT
VRAM8
C9200
10UF
C9201
0.1uF
20%
6.3V
X5R
VRAM8
603
VRAM8
1
C9202
0.1uF
10%
16V
X5R
402
C9203
F1
C9204
0.1uF
10%
16V
X5R
402
A11
VRAM8
0.1uF
10%
16V
X5R
402
F12
10%
16V
X5R
402
M1
M12
V2
V11
K1
K12
VRAM8
1
VRAM8
1
C9210
C9215
0.1uF
0.1uF
10%
16V
X5R
402
10%
16V
X5R
402
U8500.J1
A1
A12
C1
C4
C9
U8500.J12
C12
E1
80 79 73 72 9 8 =PP1V8_GPU_FB_VDDQ
E4
E9
VRAM8
VRAM8
VRAM8
VRAM8
VRAM8
VRAM8
VRAM8
E12
C9220
10UF
20%
6.3V
X5R
603
C9221
C9222
C9223
C9224
C9225
C9226
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
V1
V12
73
IN
FB_B2_VREF
H1
73
IN
FB_B0_VREF
H12
VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDDA0
VDDA1
VDDQ0
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21
VSS0
A3
VSS1
VSS2
A10
VSS3
G12
VSS4
VSS5
L1
VSS6
VSS7
V3
VSSA0
VSSA1
J1
VSSQ0
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ15
VSSQ16
VSSQ17
VSSQ18
VSSQ19
B1
BGA
(2 OF 2)
A2
G1
603
L12
C9251
0.1uF
20%
6.3V
X5R
VRAM8
VRAM8
1
C9252
0.1uF
10%
16V
X5R
402
C9253
F1
C9254
0.1uF
10%
16V
X5R
402
A11
VRAM8
0.1uF
10%
16V
X5R
402
F12
10%
16V
X5R
402
M1
M12
V2
V10
V11
K1
J12
K12
VRAM8
1
B4
VRAM8
1
C9260
C9265
0.1uF
B9
2
B12
D1
A1
A12
0.1uF
10%
16V
X5R
402
10%
16V
X5R
402
C1
U8500.J12
C9
U8500.J1
C4
D4
C12
D9
E1
80 79 73 72 9 8 =PP1V8_GPU_FB_VDDQ
E4
G2
E9
VRAM8
VRAM8
VRAM8
VRAM8
VRAM8
VRAM8
VRAM8
E12
C9270
L2
10UF
L11
20%
6.3V
X5R
P1
603
C9271
C9272
C9273
C9274
C9275
C9276
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
J4
J9
VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDDA0
VDDA1
VDDQ0
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21
U9250
BGA
(2 OF 2)
N1
N4
P4
N9
P9
P12
N12
T1
R1
T4
R4
T9
R9
T12
R12
V1
V12
VREF0
VREF1
73
IN
FB_B3_VREF
H1
73
IN
FB_B1_VREF
H12
m
il
VREF0
VREF1
A3
- =PP1V8_S0_FB_VDD
VSS1
VSS2
A10
- =PP1V8_S0_FB_VDDQ
VSS3
G12
VSS4
VSS5
L1
L12
VSS6
VSS7
V3
VRAM8
VSSA0
VSSA1
J1
G1
(NONE)
V10
J12
y
r
a
n
i
2
VSS0
VSSQ0
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ15
VSSQ16
VSSQ17
VSSQ18
VSSQ19
B1
B4
B9
B12
D1
D4
D9
D12
G2
G11
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12
DM0
E3
FB_B_DQM_L<0>
IN
71 73 95
95 80 73 71
IN
FB_B_MA<0>
K4
A0
U9250
DM0
E3
FB_B_DQM_L<5>
IN
71 73 95
BGA
DM1
E10
FB_B_DQM_L<1>
IN
71 73 95
95 80 73 71
IN
FB_B_MA<1>
H2
A1
BGA
DM1
E10
FB_B_DQM_L<6>
IN
71 73 95
IN
(1 OF 2)
FB_B_DQM_L<3>
IN
71 73 95
95 73 71
IN
FB_B_UMA<2>
K3
FB_B_DQM_L<7>
IN
71 73 95
M4
N3
FB_B_DQM_L<2>
IN
71 73 95
95 73 71
IN
FB_B_UMA<3>
M4
DM2
DM3
N10
FB_B_LMA<3>
A2
A3
(1 OF 2)
IN
DM2
DM3
N10
95 73 71
A2
A3
N3
FB_B_DQM_L<4>
IN
71 73 95
95 73 71
B2
95 73 71
DQ0
FB_B_DQ<6>
BI
7 71 73 95
DQ0
B2
FB_B_DQ<41>
BI
7 71 73 95
DQ1
DQ2
B3
FB_B_DQ<42>
BI
7 71 73 95
C2
FB_B_DQ<40>
BI
7 71 73 95
DQ3
C3
FB_B_DQ<47>
BI
7 71 73 95
FB_B_DQ<44>
A4
A5
95 80 73 71
IN
FB_B_MA<6>
K10
A6
95 80 73 71
IN
FB_B_MA<7>
L9
95 80 73 71
IN
FB_B_MA<8>
K11
95 80 73 71
IN
FB_B_MA<9>
M9
A9
95 80 73 71
IN
FB_B_MA<10>
K2
A10
A11
CKE
FB_B_MA<11>
95 80 73 71
IN
FB_B_CKE
IN
FB_B_MA<12>
95 73 71
IN
FB_B_CLK_P<0>
IN
FB_B_CLK_N<0>
95 80 71
IN
FB_B_CS1_L
95 80 73 71
IN
FB_B_WE_L
95 73 71
95 80 73 71 7
95 80 73 71
IN
FB_B_CAS_L
IN
FB_B_RAS_L
L4
H4
J3
95 80 73 71
IN
95 73 71
OUT
FB_B_RDQS<0>
95 73 71
OUT
FB_B_RDQS<1>
OUT
FB_B_RDQS<3>
95 73 71
95 73 71
OUT
FB_B_RDQS<2>
IN
FB_B_WDQS<0>
95 73 71
IN
FB_B_WDQS<1>
95 73 71
IN
FB_B_WDQS<3>
95 73 71
IN
FB_B_WDQS<2>
95 73 71
95 80 73 71
IN
R9240
R9248
1K
243
5%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
NC
BI
7 71 73 95
FB_B_DQ<46>
BI
7 71 73 95
CKE
DQ7
DQ8
G3
B11
FB_B_DQ<49>
BI
7 71 73 95
DQ9
B10
FB_B_DQ<50>
BI
7 71 73 95
DQ10
DQ11
C11
FB_B_DQ<48>
BI
7 71 73 95
C10
FB_B_DQ<51>
BI
7 71 73 95
DQ12
DQ13
E11
FB_B_DQ<53>
BI
7 71 73 95
F10
FB_B_DQ<55>
BI
7 71 73 95
DQ14
F11
FB_B_DQ<54>
BI
7 71 73 95
G10
FB_B_DQ<52>
BI
7 71 73 95
M11
FB_B_DQ<56>
BI
7 71 73 95
BI
DQ9
B10
FB_B_DQ<8>
BI
7 71 73 95
DQ10
DQ11
C11
FB_B_DQ<11>
BI
7 71 73 95
C10
FB_B_DQ<10>
BI
7 71 73 95
95 73 71
DQ12
DQ13
E11
FB_B_DQ<13>
BI
7 71 73 95
95 80 71
F10
FB_B_DQ<15>
BI
7 71 73 95
95 80 73 71
DQ14
F11
FB_B_DQ<14>
BI
7 71 73 95
95 80 73 71 7
G10
FB_B_DQ<9>
BI
7 71 73 95
95 80 73 71
M11
FB_B_DQ<26>
BI
7 71 73 95
BI
95 80 73 71 7
IN
FB_B_MA<11>
95 80 73 71
IN
FB_B_CKE
IN
FB_B_MA<12>
95 80 73 71
L4
H4
J3
A7
A8/AP
A12/CS1*
IN
FB_B_CLK_P<1>
J11
IN
FB_B_CLK_N<1>
J10
IN
FB_B_CS1_L
F9
IN
FB_B_WE_L
H9
IN
FB_B_CAS_L
F4
IN
FB_B_RAS_L
H3
CK*
CS0*
WE*
CAS*
RAS*
FB_B3_ZQ
A4
ZQ
DQ15
DQ16
7 71 73 95
FB_B3_MF
A9
MF
DQ17
L10
FB_B_DQ<57>
BI
7 71 73 95
FB_B3_SEN
V4
SEN
FB_B_DQ<63>
BI
7 71 73 95
V9
RESET
DQ18
DQ19
N11
M10
FB_B_DQ<59>
BI
7 71 73 95
DQ20
R11
FB_B_DQ<58>
BI
7 71 73 95
DQ21
DQ22
R10
FB_B_DQ<62>
BI
7 71 73 95
T11
FB_B_DQ<61>
BI
7 71 73 95
DQ23
DQ24
T10
FB_B_DQ<60>
BI
7 71 73 95
M2
FB_B_DQ<34>
BI
DQ25
L3
FB_B_DQ<35>
BI
7 71 73
95
7 71 73
95
N2
FB_B_DQ<33>
BI
M3
FB_B_DQ<32>
BI
BI
7 71 73 95
FB_B_DQ<29>
BI
7 71 73 95
DQ23
DQ24
T10
FB_B_DQ<30>
BI
7 71 73 95
M2
FB_B_DQ<21>
BI
7 71 73 95
DQ25
L3
FB_B_DQ<16>
BI
N2
FB_B_DQ<19>
M3
FB_B_DQ<17>
95 73 71
95 80 73 71
IN
FB_B_DRAM_RST
95 73 71
OUT FB_B_RDQS<5>
D3
95 73 71
OUT FB_B_RDQS<6>
D10
OUT FB_B_RDQS<7>
P10
95 73 71
CK
RDQS0
RDQS1
RDQS2
95 73 71
OUT FB_B_RDQS<4>
P3
7 71 73 95
95 73 71
IN
FB_B_WDQS<5>
D2
BI
7 71 73 95
95 73 71
IN
FB_B_WDQS<6>
D11
WDQS0
WDQS1
BI
7 71 73 95
95 73 71
IN
FB_B_WDQS<7>
P11
WDQS2
DQ26
DQ27
BI
7 71 73 95
95 73 71
IN
FB_B_WDQS<4>
P2
WDQS3
DQ28
R2
FB_B_DQ<37>
BI
DQ29
DQ30
R3
FB_B_DQ<38>
BI
T2
FB_B_DQ<39>
BI
7 71 73
95
7 71 73
95
DQ31
T3
FB_B_DQ<36>
BI
7 71 73
95
D11
WDQS0
WDQS1
P11
WDQS2
DQ26
DQ27
P2
WDQS3
DQ28
R2
FB_B_DQ<20>
DQ29
DQ30
R3
FB_B_DQ<22>
BI
7 71 73 95
T2
FB_B_DQ<18>
BI
7 71 73 95
DQ31
T3
FB_B_DQ<23>
BI
7 71 73 95
95 80 73 71
IN
G4
FB_B_BA<0>
BA0
IN
FB_B_BA<1>
G9
95 80 73 71
IN
FB_B_BA<2>
H10
BA1
BA2
J2
RFU
7 71 73
95
7 71 73
95
7 71 73
95
GDDR3 Frame Buffer B (Top)

SYNC_MASTER=M88_MLB

NC
VRAM8
R9290
5%
1/16W
MF-LF
402
RDQS3
95 80 73 71 7
VRAM8
R9249
FB_B_DQ<43>
7 71 73 95
100
F2
7 71 73 95
FB_B_DQ<25>
RFU
VRAM8
DQ6
BI
T11
J2
VRAM8
BI
7 71 73 95
A10
A11
FB_B_DQ<12>
DQ21
DQ22
BA1
BA2
K2
FB_B_DQ<7>
R10
G9
FB_B_DQ<45>
FB_B_MA<10>
B11
7 71 73 95
H10
F3
IN
DQ7
DQ8
BI
FB_B_BA<2>
A9
95 80 73 71
G3
BI
FB_B_BA<1>
FB_B_MA<9>
BI
IN
M9
7 71 73 95
95 80 73 71
DQ4
DQ5
E2
7 71 73 95
FB_B_DQ<24>
IN
K11
7 71 73 95
R11
IN
FB_B_MA<8>
7 71 73 95
DQ20
95 80 73 71
IN
BI
7 71 73 95
95 80 73 71 7
95 80 73 71
BI
7 71 73 95
BA0
L9
BI
BI
G4
FB_B_MA<7>
FB_B_DQ<1>
FB_B_DQ<28>
D2
IN
FB_B_DQ<2>
M10
RDQS3
95 80 73 71
F2
DQ18
DQ19
P3
A6
F3
FB_B_DQ<31>
P10
K10
DQ6
FB_B_DQ<27>
RDQS1
RDQS2
FB_B_MA<6>
7 71 73 95
N11
RDQS0
IN
DQ4
DQ5
BI
L10
RESET
95 80 73 71
FB_B_DQ<0>
DQ17
SEN
A4
A5
FB_B_DQ<4>
MF
V9
IN
H11
E2
A9
V4
K9
FB_B_UMA<5>
C3
ZQ
D10
VRAM8
7 71 73 95
A4
D3
FB_B_BA<0>
7 71 73 95
BI
DQ15
DQ16
F4
FB_B_DRAM_RST
BI
FB_B_DQ<3>
H3
H9
FB_B2_SEN
e
r
FB_B_DQ<5>
C2
CK*
CS0*
WE*
CAS*
RAS*
F9
FB_B2_MF
CK
B3
FB_B_UMA<4>
DQ3
P
J11
J10
FB_B2_ZQ
A12/CS1*
MFLOW
IN
MFLOW
95 80 73 71 7
A7
A8/AP
DQ1
DQ2
IN
95 73 71
MFLOW
IN
H11
MFLOW
K9
FB_B_LMA<5>
MFLOW
FB_B_LMA<4>
MFLOW
IN
95 73 71
K4J10324QD-HC11
U9200
A1
K3
32MX32-900MHZ-MFL
A0
H2
FB_B_LMA<2>
K4J10324QD-HC11
K4
FB_B_MA<1>
32MX32-900MHZ-MFL
FB_B_MA<0>
IN
IN
CRITICAL
OMIT
95 73 71
95 80 73 71
95 80 73 71
95 80 73 71
10UF
CRITICAL
OMIT
VRAM8
C9250
G11
Page Notes
VRAM8
D12
CRITICAL
OMIT
80 79 73 72 8 =PP1V8_GPU_FB_VDD
U9200
K4J10324QD-HC11
A2
VRAM8
32MX32-900MHZ-MFL
80 79 73 72 8 =PP1V8_GPU_FB_VDD
K4J10324QD-HC11
32MX32-900MHZ-MFL
R9298
1K
243
5%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402

VRAM8
1
R9299
SIZE
DRAWING NUMBER
5%
1/16W
MF-LF
402
APPLE INC.
051-7656
SCALE
SHT
NONE
REV.
100
31
OF
92
123
DisplayPort Mux
81 8
=PP3V3_S0_DPMUX
A2
OUT
GMUX_2V5
1
133
R9322
IN
LVDS_A_CLK_N
1%
1/16W
MF-LF
2 402
LVDS_CONN_A_CLK_N
2
1%
1/16W
MF-LF
402
95 84 7
IN
OUT
78 95
90 18
BI
270
OMIT
LVDS_A_DATA_N<0>
R9330
LVDS_A_DATA_P<1>
270
OUT
7 78 95
9
OUT
OUT
5%
1/16W
MF-LF
402
7 78 95
OUT
R9306 1
7 78 95
1K
5%
1/16W
MF-LF
402
GMUX_2V5
1
R9331
OMIT
R9332
95 84
IN
LVDS_A_DATA_N<1>
1%
1/16W
MF-LF
402
2
2
1%
1/16W
MF-LF
402
95 84
IN
OUT
OMIT
75
270
1
2
1%
1/16W
MF-LF
402
95 84 7
IN
LVDS_B_CLK_P
270
5%
1/16W
MF-LF
402
SIGNAL_MODEL=EMPTY
OUT
IN
LVDS_B_CLK_N
270
95 84 7
OUT
78 95
84
IN
DP_MUX_EN
IN
SIGNAL_MODEL=EMPTY
e
r
OUT
78 95
OUT
7 78 95
OMIT
R9345
LVDS_B_DATA_P<0>
270
1%
1/16W
MF-LF
402
GMUX_2V5
R9346
133
OMIT
R9347
95 84 7
IN
95 84
IN
GMUX_2V5
R9351
133
OMIT
R9352
95 84
IN
LVDS_B_DATA_N<1>
270
1%
1/16W
MF-LF
402
95 84
IN
LVDS_B_DATA_P<2>
1%
1/16W
MF-LF
402
2
SIGNAL_MODEL=EMPTY
1%
1/16W
MF-LF
402
OUT
7 78 95
R9356
133
OMIT
95 84
IN
LVDS_B_DATA_N<2>
270
1%
1/16W
MF-LF
402
16V
X5R
H9
402
J9
1
96
10%
DP_IG_AUX_CH_C_N
16V
X5R
402
H8
IN
95 76
IN
95 76
IN
95 76
IN
95 76
BI
95 76
BI
75
IN
75
BI
CBTL06141EE
1%
1/16W
MF-LF
402
B9
D8
D9
E8
E9
F8
DP_EG_ML_P<3>
DP_EG_ML_N<3>
F9
C9335
DP_EG_AUX_CH_P
DP_EG_AUX_CH_N
95
DP_EG_AUX_CH_C_P
95
DP_EG_AUX_CH_C_N
10%
0.1uF
C9336
DP_EG_DDC_CLK
DP_EG_DDC_DATA
16V
X5R
H6
402
J6
10%
0.1uF
16V
X5R
402
H5
J5
DP_MUX_SEL_EG
IN
84
OUT
18
OUT
OUT
C9321
0.1UF
20%
10V
CERM
402
20%
10V
CERM
402
U9320
BGA
y
r
DIN1_2+
DIN1_2-
CRITICAL
DIN1_3+
DIN1_3DAUX1+
DAUX1-
DDC_CLK1
DDC_DAT1
HPD_1
a
n
i
B8
DP_EG_ML_P<2>
DP_EG_ML_N<2>
DP_HOTPLUG_DET
MAKE_BASE=TRUE
DP_IG_CA_DET
DPMUX_EN_HPD
DOUT_1+
DOUT_1-
D2
DOUT_2+
DOUT_2-
E2
DOUT_3+
DOUT_3-
F2
AUX+
AUX-
H2
B1
D1
E1
DP_ML_P<0>
DP_ML_N<0>
OUT
82 95
OUT
82 95
DP_ML_P<1>
DP_ML_N<1>
OUT
82 95
OUT
82 95
DP_ML_P<2>
DP_ML_N<2>
OUT
82 95
OUT
82 95
DIN2_1+
DIN2_1DIN2_2+
DIN2_2DIN2_3+
DIN2_3-
F1
DP_ML_P<3>
DP_ML_N<3>
OUT
82 95
OUT
82 95
DP_AUX_CH_C_P
DP_AUX_CH_C_N
H1
HPDIN
DDC_CLK2
DDC_DAT2
HPD_2
A1
GPU_SEL
B7
XSD*
C9301
82 95
BI
82 95
PLACEMENT_NOTE=Place at U9320
MUXGFX
DAUX2+
DAUX2-
H3
BI
J1
DP_HPD_R
R9307
1K
DP_HPD
IN
82
5%
1/16W
MF-LF
402
LO=AUX_CH
HI=DDC
DDC_AUX_SEL
C2
TST0
G2
DP_CA_DET
IN
MAKE_BASE=TRUE
GND
75 82 84
1UF
10K
1%
1/16W
MF-LF
402
B2
DIN2_0+
DIN2_0-
DPMUX_EN_HPD
R9301 1
DOUT_0+
DOUT_0-
10%
6.3V
CERM-X5R
402
LVDS DDC MUX

=PP3V3_GPU_LVDS_DDC
R9370 1
C9370
5%
1/16W
MF-LF
402
R9372 1
20%
10V
CERM
402
14
2
84
IN
LVDS_DDC_SEL_EG
13
84
IN
LVDS_DDC_SEL_IG
12
7 78 95
20K
0.1UF
VCC
U9370
QFN1
1
C1
A1 2
B1
C2
C3
A2 3
B2
20K
5%
1/16W
MF-LF
402
R9373
20K
5%
1/16W
MF-LF
402
LVDS_EG_DDC_CLK
IN
75
LVDS_IG_DDC_CLK
LVDS_DDC_CLK
IN
18
OUT
7 78
LVDS_EG_DDC_DATA
BI
11
LVDS_IG_DDC_DATA
LVDS_DDC_DATA
BI
18
BI
7 78
A4
B4 10
GND THRM
7
R9371
A3
9
B3
C4
5%
1/16W
MF-LF
402
20K
=PP3V3_S0_LVDSDDCMUX
SIGNAL_MODEL=EMPTY
1%
1/16W
MF-LF
402
DP_IG_AUX_CH_C_P
J8
7 78 95
7 78 95
GMUX_2V5
1
R9357
OUT
OUT
R9355
270
7 78 95
OMIT
OUT
2
1%
1/16W
MF-LF
402
SIGNAL_MODEL=EMPTY
270
1
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
OMIT
R9350
LVDS_B_DATA_P<1>
270
LVDS_B_DATA_N<0>
95 76
5%
1/16W
MF-LF
402
LVDS_CONN_B_CLK_N
96
10%
0.1uF
DP_EG_ML_P<1>
DP_EG_ML_N<1>
=PP3V3_S0_DPMUX
R9303
1%
1/16W
MF-LF
402
IN
10K
7 78 95
133
95 84
0.1uF
m
il
81 8
DPMUX_EN_PLD
1%
1/16W
MF-LF
402
DP_MUX_XSD_L
R9341
IN
95 76
84
GMUX_2V5
1
R9342
IN
95 76
R9302 1
LVDS_CONN_B_CLK_P
OMIT
C9330
DP_EG_ML_P<0>
DP_EG_ML_N<0>
IN
DPMUX_EN_S0&DPMUX_EN_PLD
1%
1/16W
MF-LF
402
BI
1%
1/16W
MF-LF
402
OMIT
R9340
75 9
DP_IG_DDC_CLK
DP_IG_DDC_DATA
100K
1%
1/16W
MF-LF
402
2
270
1
IN
A9
DP_EG_HPD
R9305
R9336
R9337
LVDS_A_DATA_N<2>
OUT
7 78 95
133
IN
75 9
95 76
DIN1_1+
DIN1_1-
LO=PORT1
HI=PORT2
OUT
GMUX_2V5
1
OMIT
95 84
DP_IG_AUX_CH_P
7 78 95
R9335
LVDS_A_DATA_P<2>
BI
SIGNAL_MODEL=EMPTY
270
A8
DP_IG_ML_P<3>
DP_IG_ML_N<3>
90 18
95 76
100K
SIGNAL_MODEL=DPMUX
J2
133
IN
A6
DP_IG_HPD
R9304 1
SIGNAL_MODEL=EMPTY
1%
1/16W
MF-LF
402
IN
90 9
B6
DP_IG_ML_P<2>
DP_IG_ML_N<2>
GMUX_2V5
1%
1/16W
MF-LF
402
OMIT
IN
270
90 9
A5
R9326
1%
1/16W
MF-LF
402
2
R9327
95 84
IN
B5
C9331
R9325
LVDS_A_DATA_P<0>
133
IN
IN
90 9
DP_IG_ML_P<1>
DP_IG_ML_N<1>
DP_IG_AUX_CH_N
OMIT
1%
1/16W
MF-LF
402
95 84 7
90 9
SIGNAL_MODEL=EMPTY
270
1
IN
R9321
OMIT
95 84
IN
90 9
VDD
MUXGFX
H4
1%
1/16W
MF-LF
402
90 9
78 95
A4
DIN1_0+
DIN1_0-
G8
LVDS_CONN_A_CLK_P
IN
B4
C8
270
1
90 9
DP_IG_ML_P<0>
DP_IG_ML_N<0>
SN74LV4066A
IN
LVDS_A_CLK_P
IN
(All 24 resistors)
R9320
95 84
MUXGFX
C9320
H7
90 9
B3
OMIT
0.1UF
All emulated LVDS outputs require this termination
J4
MUXGFX
LVDS Transmitter Termination
75
Muxed Graphics Support

SYNC_MASTER=M98_MLB
15

TABLE_5_HEAD
PART#
QTY
DESCRIPTION
REFERENCE DESIGNATOR(S)
CRITICAL
BOM OPTION
TABLE_5_ITEM
114S0517
16
RES,MTL FILM,270 OHM,1%,1/16W,0402,SMD,L
R9320,R9322,R9325,R9327,R9330,R9332,R9335,R9337,R9340,R9342,R9345,R9347,R9350,R9352,R9355,R9357
GMUX_2V5
114S0174
16
RES,MTL FILM,1/16W,357 OHM,1,0402,SMD,LF
R9320,R9322,R9325,R9327,R9330,R9332,R9335,R9337,R9340,R9342,R9345,R9347,R9350,R9352,R9355,R9357
GMUX_1V8
SIZE
DRAWING NUMBER
TABLE_5_ITEM
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
93
123
Port Power Switch

D
DP_ESD
CRITICAL
DP_ESD
CRITICAL
CRITICAL
L9400
84 67 41 36 33 21 7
IN
5 IN
=PP3V3_S5_DP_PORT_PWR
PM_SLP_S3_L
4 EN
PP3V3_S0_DPILIM
OC* 3
VOLTAGE=3.3V
TP_DPPWR_OC_L
2
0603
GND
2
C9400
PP3V3_S0_DPPWR
VOLTAGE=3.3V
2 IO
IO
NC
9 NC
0.01UF
2
y
r
SLP2510P8
FERR-120-OHM-3A
TPS2051B
SOT23
OUT 1
SLP2510P8
5 IO
20%
50V
CERM
603
10UF
C9481
C9485
0.1UF
20%
6.3V
X5R
603
20%
6.3V
2 X5R-CERM
603
22UF
0.1UF
20%
10V
CERM
402
20%
10V
CERM
402
C9486
R9420
a
n
i
100K
5%
1/16W
MF-LF
402
R9400
R9430
NO STUFF
R9401
5%
CRITICAL
HDMI_CEC
R9431
J9400
1
1/16W
NO STUFF
R9413
1
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
IN
DP_ML_P<3>
C9414
95 81
IN
DP_ML_N<3>
C9415
95 81
BI
DP_AUX_CH_C_P
BI
DP_AUX_CH_C_N
95 81
2 95 DP_ML_C_P<3>
10%
16V
X5R
402
2 95 DP_ML_C_N<3>
10%
16V
X5R
402
0.1uF
0.1uF
SYM_VER-2
6
1
95
DP_ML_CONN_P<3>
95
DP_ML_CONN_N<3>
8
10
12
14
82 8
20
DP_ESD
CRITICAL
=PP3V3_S0_DPCONN
R9443 1
5%
1/16W
MF-LF
402
84 81 75
OUT
D9411
R9442 1
100K
DP_CA_DET
SLP2510P8
R9421 1
100K
5%
1/16W
MF-LF
402
2 IO
GND
SOT-363
DP_CA_DET_L_Q
Q9440
2N7002DW-X-G
SOT-363
DP_CA_DET_Q
R9422
1M
5%
1/16W
MF-LF
402
Q9440 must have Drain to Gate leakage of <500nA and Gate to Source resistance of >5MOhm
=PP3V3_S0_DPCONN
R9445
R9444
10K
5%
MF-LF
402
81
OUT
10K
5%
1/16W
1/16W
MF-LF
402
DP_HPD
Q9441
2N7002DW-X-G
SOT-363
DP_HPD_L_Q
3
7
9
11
13
GND
ML_LANE2P
ML_LANE2N
RETURN
22
402
1/16W
MF-LF
402
15
17
19
21
95
DP_ML_CONN_P<0>
DP_ML_CONN_N<0>
5%
95
DP_ML_CONN_N<1>
MF-LF
402
1/16W
MF-LF
402
5%
CRITICAL
FL9400
SYM_VER-2
95
DP_ML_C_P<0>
C9410
95
95
DP_ML_CONN_N<2>
DP_ML_P<0>
10%
16V
DP_ML_C_N<0>
C9411
95
DP_ML_C_P<1>
C9412
DP_ML_N<0>
10%
16V
2
10%
DP_ML_P<1>
95
DP_ML_C_N<1>
C9413
2
10%
DP_ML_N<1>
95
DP_ML_C_P<2>
C9416
DP_ML_P<2>
95
DP_ML_C_N<2>
C9417
10%
16V
DP_ML_N<2>
10%
16V
0.1uF
12-OHM-100MA
TCM1210-4SM
CRITICAL
DP_ML_CONN_P<2>
95
0.1uF
FL9402
0.1uF
SYM_VER-2
12-OHM-100MA
TCM1210-4SM
FL9401
DP_ML_CONN_P<1>
1/16W
NO STUFF
12-OHM-100MA
TCM1210-4SM
95
SYM_VER-2
0.1uF
0.1uF
3
0.1uF
CRITICAL
16V
16V
X5R
X5R
X5R
X5R
X5R
X5R
402
402
402
402
402
402
IN
81 95
IN
81 95
IN
81 95
IN
81 95
IN
81 95
IN
81 95
NO STUFF
R9402
R9432
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
NO STUFF
10
DP_ESD
CRITICAL
D9400
DP_ESD
CRITICAL
RCLAMP0504F
D9411
SC70-6-1
RCLAMP0524P
SLP2510P8
DP to DVI/HDMI
Cable Adapter
(CA) has 100k
pull-up to DP_PWR.
MF-LF
NO STUFF
5 IO
IO
NC
6 NC
4
7
PART NUMBER
514-0637
QTY
1
DESCRIPTION
REFERENCE DES
CRITICAL
J9400
CRITICAL
CONN,RCP,MDP,HB,20P,P=0.6
BOM OPTION
Q9441
2N7002DW-X-G
SOT-363
SHIELD PINS
e
r
2N7002DW-X-G
82 8
IO
NC
9 NC
Q9440
RCLAMP0524P
100K
5%
1/16W
MF-LF
402
m
il
GND
AUX_CHP
AUX_CHN
DP_PWR
16
18
95 81
95
SM PINS
HOT_PLUG_DETECT
GND
CONFIG1
ML_LANE0P
CONFIG2
ML_LANE0N
GND
GND
ML_LANE3P
ML_LANE1P
ML_LANE3N
ML_LANE1N
12-OHM-100MA
TCM1210-4SM
4
TOP ROW
TH PINS
FL9403
1M
OMIT
BOT ROW
CRITICAL
R9425
MF-LF
5%
F-RT-THSM
5%
GND
1/16W
NO STUFF
DSPLYPRT-M97
NO STUFF
R9403
CRITICAL
C9480
IO
NC
6 NC
10
GND
RCLAMP0524P
GND
U9480
D9410
D9410
RCLAMP0524P
DisplayPort Connector
DP_HPD_Q
SYNC_MASTER=K20_MLB
R9423
DP Source must pull
down HPD input with
100K

greater than or equal
5%
1/16W
to 100K (DPv1.1a).
MF-LF
402

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
94
123
y
r
=PPVIN_S0GPU_P1V8P1V1
CRITICAL
C9540
20%
16V
POLY-TANT
CASED2E-SM
C9545
CRITICAL
1UF
33UF
C9590
10%
25V
X5R
603-1
4.7
2
20%
16V
POLY-TANT
CASED2E-SM
PVIN_S0GPU_P1V1
CRITICAL
5%
1/16W
MF-LF
402
Q9510
SI7110DN
PWRPK-1212-8-HF
GATE_NODE=TRUE
C9500
=PP5V_S0GPU_P1V1P1V8_GPU
10UF
2 1
10%
25V
X5R
805
C9501
1UF
10%
10V
X5R
402-1
(Internal 10-ohm path

from PVCC to VCC)
PP5V_S0GPU_P1V1P1V8_VCC
CRITICAL
PP5V_S0GPU_VREF
4
=PP1V1_S0GPU_REG
Vout = 1.103V
2.2UH-8.0A
1
f = 400 kHz
1
CRITICAL
XW9515
SM
20%
2 2.0V
POLY-TANT
B2-SM
6
2
P1V1GPU_VBST
17
15
P1V1GPU_LL
SWITCH_NODE=TRUE
PCMB065T-SM
18
10
14
9
P1V1GPU_VFB
P1V1GPU_TRIP
11
12
PLACEMENT_NOTE=Place XW9515 next to C7615
29
4
20
2
VIN
BOOT1
UGATE1
PHASE1
LGATE1
OUT1
EN1
BYP
FB1
ILIM1
SKIP*
EN_LDO
SECFB
TON
LDO
LDOREFIN
CRITICAL
BOOT2
U9500 UGATE2
PHASE2
ISL6236
LGATE2
QFN
OUT2
EN2
OMIT
REFIN2
ILIM2
REF
POK1
POK2
P1V1S0_VSNS
5.76K
1%
1/16W
MF-LF
2 402
<Rb>
R9521
e
r
NO STUFF
C9520
100PF
5%
50V
CERM
402
1%
1/16W
MF-LF
2 402
Vout = 0.7V * (1 + Ra / Rb)

(Rb should be between 10K and 100K)
10K
R9535
75K
1%
1/16W
MF-LF
402
10%
10V
X5R
402-1
IN
67
OUT
67
OUT
84 67 66
IN
1UF
NC
(SGND)
25
23
(=PP1V8FB_S0_REG)
27
31
GPU_P1V8_REFIN
P1V8FB_TRIP
VOLTAGE=2V
28
R9585 1
130K
1%
1/16W
MF-LF
402 2
XW9500
2
C9585
0.1UF
SM
20%
10V
CERM
402
=P1V1GPU_EN
P1V1GPU_PGOOD
P1V8FB_PGOOD
=P1V8FB_EN
P1V8FB_DRVL
SI7110DN
PWRPK-1212-8-HF
1 2
CRITICAL
=PP1V8_GPU_REG
L9560
Vout = 1.8V
8A MAX OUTPUT
2
PCMB065T-SM
C9560
CRITICAL
D
(Q9560 limit?)
CRITICAL
1
F = 500 KHZ
220UF
20%
2.5V 2
POLY-TANT
CASE-B2-SM2
Q9561
SI7108DN
C9565
10UF
PWRPK-1212-8-HF
20%
6.3V
X5R
603
C9580
2 3
10%
50V
X7R
603-1
P1V8FB_LL
SWITCH_NODE=TRUE
<Ra>
R9563 1
XW9565
SM
P1V8_GPU_VSNS
14.0K
1%
1/16W
MF-LF
402 2
Vout = 2(Req/(Ra+Req))
<Rb>
R9564 1
GPIO7
FBVDDQ
1
0
1.553V
1.8V
R9562
78.7K
127K
1%
1/16W
MF-LF
402 2
PLACEMENT_NOTE=Place next to C7665
C9561
0.01UF
10%
16V
CERM
402
1%
1/16W
MF-LF
402
GPUFB_VID_L
Q9565
3
SSM3K15FV
SOD-VESM-HF
VOLTAGE=0V
GPIO7_FBVDD_ALTVO
PART NUMBER
353S2312
QTY
1
DESCRIPTION
IC,ISL6236,DUAL PWM CNTRL,QFN32
IN
75
REFERENCE DES
U9500
CRITICAL
BOM OPTION
CRITICAL
1.1V / 1V8 FB Power Supply

SYNC_MASTER=RXU_K20

SIZE
DRAWING NUMBER
D
APPLE INC.
REV.
051-7656
SCALE
SHT
NONE
1.0UH-13A-5.6MOHM
0.1UF
Q9560
GATE_NODE=TRUE
PP2V_S0GPU_P1V8_REF
13
PGND
CRITICAL
26
32
P1V8FB_VBST
24
30
10%
25V
X5R
603-1
GND_P1V1P1V8_SGND
84 67
21
33
THRM_PAD GND
<Ra>
1
R9520
10%
10V
X5R
402-1
m
il
16
10UF
20%
6.3V
X5R
603
C9510
330UF
C9515
10%
50V
X7R
603-1
L9510
(Q9510 limit?)
0.1UF
CRITICAL
GATE_NODE=TRUE
1UF
1UF
PVCC VCC VREF3
C9530
3.5A MAX OUTPUT
2 1
C9503
22
C9504
GATE_NODE=TRUE
C9595
P1V8FB_DRVH
VOLTAGE=5V
P1V1GPU_DRVL
3
19
SI7108DN
VOLTAGE=5V
Q9515
PWRPK-1212-8-HF
a
n
i
P1V1GPU_DRVH
33UF
R9500
31
OF
95
123
LVDS Receiver Termination
GMUX CPLD
=PP3V3_S0_GMUX
84 8
1
C9610
C9621
C9622
C9623
C9624
C9625
C9626
C9627
C9628
C9629
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
90 84 18
90 84 18
90 84 18
L9621
90 84 18
PP3V3_S0_GMUX_ULC_VCCPLL
D
1
C9611
0.1UF
2
C9612
0.1UF
20%
10V
CERM
402
C9613
0.1UF
20%
10V
CERM
402
C9614
0.1UF
20%
10V
CERM
402
C9615
C9616
0.1UF
20%
10V
CERM
402
0.1UF
20%
10V
CERM
402
VOLTAGE=3.3V
C9617
90 84 18
C9631
20%
10V
CERM
402
20%
10V
CERM
402
95 84 76
95 84 76
95 84 76
FERR-220-OHM
PP3V3_S0_GMUX_LRC_VCCPLL
VOLTAGE=3.3V
95 84 76
0402
95 84 76
4.7UF
20%
4V
X5R
402
C9604
C9605
C9606
C9607
C9608
C9609
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
84 6
P11
A4
K12
F2
C3
M1
N5
M3
M12
M9
F13
C14
VCCIO3
A12
VCCIO2
B7
B5
M8
J14
J2
C11
P8
N11
J13
J3
C4
B11
a
n
i
JTAG_GMUX_TCK
JTAG_GMUX_TCK
IN
9 6
OUT
9 6
IN
JTAG_GMUX_TCK
JTAG_GMUX_TDI
JTAG_GMUX_TDO
JTAG_GMUX_TMS
GMUX_TOE
K2
TCK
TDI
TDO
TMS
TOE
GMUX_CFG0
K1
CFG0
LCD_BKLT_EN
LCD_BKLT_PWM
LVDS_DDC_SEL_EG
LVDS_DDC_SEL_IG
DP_MUX_EN
DP_MUX_SEL_EG
EG_RESET_L
EG_RAIL1_EN
EG_RAIL2_EN
EG_RAIL3_EN
EG_RAIL4_EN
EG_CLKREQ_OUT_L
DP_CA_DET_EG
LCD_PWR_EN
LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>
LPC_FRAME_L
LPC_RESET_L
LPC_CLK33M_GMUX
GMUX_INT
P2
PB2A
PB2B
PB14A
PB14B
PB15A (OD)
PB15B
PB16A
PB16B
PB17A
PB17B
PB18A
PB18B (OD)
PB19A
PB19B
PB20A
PB20B
PB30A
PB30B
PB31A
PB31B
PB32A
PB32B
K14
L13
K13
L12
VCCIO7
9 6
VCCJ
OMIT
CRITICAL
NO STUFF
R9647
10K
1%
1/16W
MF-LF
402
IN
90 84 18
IN
90 84 18
IN
90 84 18
IN
90 84 18
IN
90 84 18
IN
90 84 18
IN
90 84 18
IN
90 84 18
IN
90 84 18
IN
90 84 18
IN
90 84 18
90 84 18
90 84 18
9
IN
IN
IN
OUT
IN
84
IN
IN
84
IN
B2
C2
D3
D1
E1
D2
E3
F1
G1
(Tie/strap low if EGPU doesnt provide CLKREQ_L output, provide pullup to GPU rail if using CLKREQ_L output from EGPU)
PM_SLP_S3_L Isolation
84 8
=PP3V3_S0_GMUX
Q9670
SSM6N15FEAPE
2
1%
1/16W
MF-LF
402
G2
H2
G3
H1
H3
L1
L3
K3
L2
N1
P1
BANK1
BANK0
GND
PR2A
PR2B
PR10A
PR10B
PR11A
PR11B
PR12A
PR12B
PR13A
PR13B
PR14A
PR14B
PR15A
PR15B
PR16A
PR16B
PR18A
PR18B
PR30A
PR30B
A14
LVDS_B_DATA_P<0>
LVDS_B_DATA_N<0>
LVDS_B_DATA_P<1>
LVDS_B_DATA_N<1>
LVDS_B_DATA_P<2>
LVDS_B_DATA_N<2>
EG_PWRSEQ_EN
GMUX_DEBUG_RESET_L
LVDS_A_CLK_P
LVDS_A_CLK_N
LVDS_B_CLK_P
LVDS_B_CLK_N
LVDS_A_DATA_P<0>
LVDS_A_DATA_N<0>
LVDS_A_DATA_P<1>
LVDS_A_DATA_N<1>
LVDS_A_DATA_P<2>
LVDS_A_DATA_N<2>
TP_GMUX_PT20A
TP_GMUX_PT20B
TP_GMUX_PT32A
TP_GMUX_PT32B
A3
A1
B3
C5
A5
B6
C7
A6
A7
C8
C9
A8
B9
A9
C10
B10
A10
A11
B12
B13
A13
B14
D12
D13
D14
E14
E12
F12
F14
G14
G12
G13
H13
H12
H14
J12
L14
M13
N14
N13
IC,XP2-8,HF,CPLD,BLANK
IC,CPLD,LATTICE,132CSBGA,K20
100
100
100
100
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
100
100
100
100
100
100
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
IN
17
R9680
1K
R9690
4.7K
R9695
10K
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
81 95
OUT
81 95
OUT
81 95
84 81
84 81
84 81
81 95
IN
84
IN
84
R9681
DP_MUX_SEL_EG
10K
U9600
CRITICAL
LVDS_IG_B_DATA_N<0>
LVDS_IG_B_DATA_N<1>
LVDS_IG_B_DATA_N<2>
18 84 90
18 84 90
LVDS_EG_A_CLK_N
LVDS_EG_A_DATA_N<0>
LVDS_EG_A_DATA_N<1>
LVDS_EG_A_DATA_N<2>
76 84 95
76 84 95
76 84 95
7 76 84 95
LVDS_EG_B_DATA_N<0>
LVDS_EG_B_DATA_N<1>
LVDS_EG_B_DATA_N<2>
76 84 95
76 84 95
76 84 95
=PP3V3_S0_GMUX
=PP3V3_S0_GMUX
10K
LVDS_DDC_SEL_IG
R9682
10K
LVDS_DDC_SEL_EG
R9683
10K
84 9
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
81 95
84 9
OUT
81 95
OUT
7 81 95
OUT
81 95
OUT
7 81 95
OUT
7 81 95
OUT
81 95
OUT
81 95
OUT
81 95
OUT
81 95
85 84 7
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
84
402
5%
1/16W
MF-LF
402
NO STUFF
R9691
R9692
R9693
R9694
EG_RESET_L
GMUX_INT
LCD_BKLT_PWM
EG_CLKREQ_IN_L
100K
20K
100K
100K
EG_PWRSEQ_HW
R9630
R9631
EG_PWRSEQ_GMUX
0
1
2
R9632
EG_PWRSEQ_GMUX
0
1
2
EXTGPU_PWR_EN
5%
EG_RAIL1_EN
84
5%
IN
75 81 82
IN
81
IN
76 84 95
IN
76 84 95
IN
5%
EG_RAIL3_EN
R9633
84
EG_RAIL4_EN
R9634
EG_PWRSEQ_GMUX
0
1
2
5%
76 84 95
IN
76 84 95
IN
7 76 84 95
84 78
76 84 95
5%
LCD_PWR_EN
76 84 95
IN
76 84 95
IN
76 84 95
IN
76 84 95
IN
76 84 95
76 84 95
IN
IN
75
IN
IN
75
402
1/16W
MF-LF
402
1/16W
MF-LF
402
=P1V1GPU_EN
P3V3GPU_EN
=GPUVCORE_EN
1/16W
MF-LF
402
1/16W
MF-LF
402
=P1V8FB_EN
R9674
NO STUFF
4.7K
4.7K
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
R9672
EG_PWRSEQ_GMUX
76 84 95
IN
MF-LF
GMUX_8K_BLANK
IN
ALL_SYS_PWRGD
R9671
R9673
4.7K
4.7K
4.7K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
OUT
67 83
OUT
67 68
OUT
67 77
OUT
66 67 83
C9693
0.1UF
20%
10V
CERM
402
NO STUFF
1
20%
10V
CERM
402
NO STUFF
C9692
0.1UF
2
C9694
0.1UF
20%
10V
CERM
402
20%
10V
CERM
402
GMUX_S3_PD_GND
Q9607
D 3
NO STUFF
1
SSM6N15FEAPE
R9675
SOT563
0
5%
1/16W
MF-LF
5%
1/16W
MF-LF
402
S 4
Graphics MUX (GMUX)
2 402
SYNC_MASTER=T18_MXMGMUX
D 6
SSM6N15FEAPE
GMUX_S0_PD_DIS_RC
0
5%
1/16W
MF-LF
402
GMUX_PROG
67
NO STUFF
C9691
0.1UF
EG_PWRSEQ_GMUX
Q9607
R9684
67 41 25
OUT
EG_PWRSEQ_GMUX
R9678
1/16W
The MAKE BASE properties for these signals are on the POWER CONTROL page.
EG_PWRSEQ_GMUX
IN
IN
84
EG_PWRSEQ_GMUX
0
1
2
76 84 95
IN
IN
EG_RAIL2_EN
84
SOT563
BOM OPTION
5%

2
S 1
C9695
1UF
SIZE
10%
6.3V
CERM
402
DRAWING NUMBER
D
APPLE INC.
REV.
051-7656
SCALE
SHT
NONE
18 84 90
NO STUFF
CRITICAL
18 84 90
(Use open-drain PGOOD output to hold off the start of the GPU PWRSEQ until the first GPU rails source is valid)
R9676
R9677
84
U9600
18 84 90
18 84 90
1%
1/16W
MF-LF
402
CRITICAL
18 84 90
PLACEMENT_NOTE=Place on top side at U9600
NO STUFF
84
LVDS_IG_A_CLK_N
LVDS_IG_A_DATA_N<0>
LVDS_IG_A_DATA_N<1>
LVDS_IG_A_DATA_N<2>
84 8
5%
GMUX_S3_PD_EN
TABLE_5_ITEM
341S2354
7 81 95
OUT
OUT
TABLE_5_ITEM
336S0027
OUT
OUT
MAKE_BASE=TRUE
DESCRIPTION
7 81 95
=PP3V3_S3_GMUX
1
QTY
OUT
DP_CA_DET
DP_HOTPLUG_DET
LVDS_EG_A_DATA_P<0>
LVDS_EG_A_DATA_N<0>
LVDS_EG_A_DATA_P<1>
LVDS_EG_A_DATA_N<1>
LVDS_EG_A_DATA_P<2>
LVDS_EG_A_DATA_N<2>
LVDS_EG_B_DATA_P<0>
LVDS_EG_B_DATA_N<0>
LVDS_EG_B_DATA_P<1>
LVDS_EG_B_DATA_N<1>
LVDS_EG_B_DATA_P<2>
LVDS_EG_B_DATA_N<2>
LVDS_EG_A_CLK_P
LVDS_EG_A_CLK_N
IG_LCD_PWR_EN
EG_LCD_PWR_EN
IG_BKLT_EN
EG_BKLT_EN
TABLE_5_HEAD
PART#
SILK_PART=GMUX_RST
100K
84 8
GMUX_PM_SLP_S3_L
IN
41 36 33 21 7
82 67
PM_SLP_S3_L
EG_PWRSEQ_EN
10K
SOT563
R9670
F3
PL2A
PL2B
PL10A
PL10B
PL11A
PL11B
PL12A
PL12B
PL13A
PL13B
PL14A
PL14B
PL15A
PL15B
PL16A
PL16B
PL18A
PL18B
PL19A
PL19B
PL32A
PL32B
BANK6
25
B1
A2
m
il
e
r
LVDS_IG_B_DATA_P<2>
LVDS_IG_B_DATA_N<2>
TP_GMUX_PL10A
TP_GMUX_PL10B
LVDS_IG_A_DATA_P<0>
LVDS_IG_A_DATA_N<0>
LVDS_IG_A_DATA_P<1>
LVDS_IG_A_DATA_N<1>
LVDS_IG_A_DATA_P<2>
LVDS_IG_A_DATA_N<2>
LVDS_IG_B_DATA_P<0>
LVDS_IG_B_DATA_N<0>
LVDS_IG_B_DATA_P<1>
LVDS_IG_B_DATA_N<1>
LVDS_IG_A_CLK_P
LVDS_IG_A_CLK_N
LVDS_MUX_SEL_EG
TP_GMUX_PL18B_VSYNC
=GMUX_PCIE_RESET_L
GMUX_PM_SLP_S3_L
ALL_EG_PGOOD
EG_CLKREQ_IN_L
BANK7
NO STUFF
90 84 18
P14
BANK2
IN
OUT
N12
BANK3
84 9
P13
PT2A
PT2B
PT3A
PT3B
PT4A
PT4B
PT14A
PT14B
PT15A
PT15B
PT16A
PT16B
PT17A
PT17B
PT18A
PT18B
PT19A
PT19B
PT20A
PT20B
PT32A
PT32B
M11
IN
ULC_GNDPLL
LRC_GNDPLL
91 25 19
P12
B4
BI
M10
E2
BI
91 43 41 19 7
P10
GNDIO7
BI
91 43 41 19 7
N9
C1
91 43 41 19 7
P9
GNDIO6
BI
N8
BANK4
BI
91 43 41 19 7
25
OUT
91 43 41 19 7
N7
Required Pulldowns
M2
OUT
M7
GNDIO5
75
84 78
P7
P3
OUT
M6
N6
OUT
84 9
P6
N10
OUT
84
M5
GNDIO3
GNDIO4
OUT
84
P5
M14
84
M4
GNDIO2
OUT
E13
OUT
84
GNDIO1
OUT
84 9
C13
84 81
N3
BANK5
1%
1/16W
MF-LF
402
N4
C12
OUT
P4
GNDIO0
OUT
81
N2
10K
SOT563
CSBGA-HF
C6
R9646
10K
OUT
84 81
NO STUFF
1
10K
1%
1/16W
MF-LF
402
OUT
84 81
R9679 1
GMUX_JTAG_TCK_L
B8
R9641
85 84 7
Q9670
SSM6N15FEAPE
U9600
J1
NO STUFF
OUT
XP28
9
EG_CLKREQ_OUT_L
84 9
ULC_VCCPLL
LRC_VCCPLL
1%
1/16W
MF-LF
402
VCCIO6
84 6
10K
VCCIO5
R9645
VCCIO4
10K
1%
1/16W
MF-LF
402
VCCAUX
VCCIO1
R9640
VCCIO0
VCC
1
Required Pullups
GMUX_DEBUG_RESET_L
84
=PP3V3_S0_GMUX
1
100
(All 14 resistors)
SIGNAL_MODEL=EMPTY
GMUX_JTAG_TCK Inversion
84 8
y
r
C9630
0.1UF
C9600
100
R9664
R9665
R9666
LVDS_EG_B_DATA_P<0>
LVDS_EG_B_DATA_P<1>
LVDS_EG_B_DATA_P<2>
95 84 76
=PP1V2_S0_GMUX
R9660
R9661
R9662
R9663
LVDS_EG_A_CLK_P
LVDS_EG_A_DATA_P<0>
LVDS_EG_A_DATA_P<1>
LVDS_EG_A_DATA_P<2>
95 84 76
0.1UF
L9620
100
100
0402
0.1UF
20%
10V
CERM
402
R9654
R9655
R9656
LVDS_IG_B_DATA_P<0>
LVDS_IG_B_DATA_P<1>
LVDS_IG_B_DATA_P<2>
90 84 18
FERR-220-OHM
=PP2V5_S0_GMUX
R9650
R9651
R9652
R9653
LVDS_IG_A_CLK_P
LVDS_IG_A_DATA_P<0>
LVDS_IG_A_DATA_P<1>
LVDS_IG_A_DATA_P<2>
90 84 18
31
OF
96
123
*Q9701, D9701, C9709, C9710, L9701, R9702, AND R9715 SHOULD ALL BE PLACED NEAR EACHOTHER.
*BOOST_FET_CNTL AND PPVOUT_S0_LCDBKLT_SW SHOULD BE KEPT AS SHORT AS POSSIBLE.
CRITICAL
PLACEMENT_NOTE=D9701 PLACE NEAR Q9701
L9701
D9701
22UH-2.5A
PPBUS_S0_LCDBKLT_PWR
VOLTAGE=6V
PPVIN_S0_LCDBKLT_BUF
VOLTAGE=6V
R9730
0
5%
1/10W
MF-LF
603
CRITICAL
CRITICAL
Q9701
PLACEMENT_NOTE=C9701 PLACE NEAR L9701
XW9701
SM
1
GND_BKL_PWRGND
2 3
C9702
0.1UF
GND_BKL_PWRGND
85
PLACEMENT_NOTE=XW9701 PLACE NEAR C9701
10%
25V
X5R
402
BOOST_SINK
C9709
2.2UF
PWRPK-1212-8
BKL_VIN
SI7308DN
CRITICAL
y
r
CRITICAL
BOOST_FET_CNTL
10%
25V
X5R
805
PLACEMENT_NOTE=C9710 PLACE NEAR J9000
RB160M-60G
1%
1/16W
MF-LF
402
C9701
10UF
VOLTAGE=50V
SWITCH_NODE=TRUE
PLACEMENT_NOTE=L9701 PLACE NEAR Q9701
49.9
1
PPVOUT_S0_LCDBKLT_SW
IHLP2525CZ-SM
CRITICAL
PLACEMENT_NOTE=C9709 PLACE NEAR C9710
SOD-123
2
R9701
IN
86 85
C9710
2.2UF
10%
100V
X7R
1210
10%
100V
X7R
1210
GND_BKL_PWRGND
85
PLACEMENT_NOTE=R9715 PLACE NEAR C9709 AND Q9701
a
n
i
2
R9702
R9715
0.4
0.4
1%
1/6W
MF
402
R9704
100
1%
1/16W
MF-LF
402
1%
1/6W
MF
402
85
BKL_VREF_4V9
R9731
PPBUS_S0_LCDBKLT_PWR
187K
BKLT_PLL
1%
1/16W
MF-LF
402
78 7
BKL_SYNC
IN
BKL_VSYNC
GND_BKL_PWRGND_X
C9713
0.1UF
100K
10%
25V
X5R
402
1%
1/16W
MF-LF
402
R9706
4 VREF
5 ENA
17 VSYNC
*R9702 AND R9715 PIN 1 SHOULD BE PLACED NEAR C9709 PIN 2

1
U9700
5%
1/16W
MF-LF
402
XW9702
SM
PLACEMENT_NOTE=R9702 PLACE NEAR C9709 AND Q9701
VIN
10K
1
1%
1/16W
MF-LF
402
10%
10V
X5R
402
CRITICAL
5%
1/16W
MF-LF
402
R9705
1UF
2.67K
1
C9703
R9707
OMIT
R9734
BKLT_EN
C9712
47PF
DRV 1
QFN
APP001
86 85
ISWSEN 2
ISEN1 10
BOOST_SINK_R
PPVOUT_S0_LCDBKLT
5%
50V
CERM
402
BKL_ISET
R9717
1
10.2
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
R9703
1K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
1UF
10%
50V
CERM
402
10%
10V
X5R
402
BKL_VREF_4V9
BKLT_PLL_NOT
CRITICAL
Q9702
NTUD3127CXXG
SOT-963
CRITICAL
D
2
SOT-963
C9707
2.2UF
20%
6.3V
CERM
402-LF
1
1
7 78
LED_RETURN_4
OUT
7 78
10.2
LED_RETURN_3
0.1%
OUT
7 78
OUT
7 78
OUT
7 78
1/16W
TF
402
R9721
1
GND_BKL_PWRGND
10.2
LED_RETURN_2
0.1%
1/16W
TF
402
R9722
10.2
1
R9727
LED_RETURN_1
0.1%
1/16W
TF
402
1%
1/16W
MF-LF
402
PPVOUT_S0_LCDBKLT
PLACEMENT_NOTE=R9727 AWAY FROM Q9701
7 78 85
C9708
0.1UF
OUT
R9720
1
75K
BKLT_PLL
BKL_LRT_RC
10.2
0.1%
R9714
BKLT_PLL
1/16W
TF
402
BKLT_PLL
5%
1/16W
MF-LF
402
7 78
R9719
1
10K
LED_RETURN_5
2
0.1%
THRM_PAD
PART NUMBER
10%
25V
X5R
402
353S2413
QTY
1
DESCRIPTION
REFERENCE DES
IC,APP001A,WHT LED BKLGHT CTR,SCRN,QFN20
CRITICAL
U9700
BOM OPTION
CRITICAL
R9723
1.2M
1%
1/10W
MF-LF
603
THRESHOLD=2.5V
R9711
BKL_VSEN
8.06K
G
S
85
OUT
1/16W
TF
402
BKL_ISEN6
1%
1/16W
MF-LF
402
LCD BACKLIGHT DRIVER
50.4*R9724/(R9723+R9724)=2.4V
2
NTUD3127CXXG
1%
1/16W
MF-LF
402
10.2
BKL_ISEN5
R9724
SYNC_MASTER=KIRAN_K20
60.4K
1
N-CHN
R9710
4.02K
BKL_PWR_EN_L
BKL_VREF_IN_4V9
2
1
10K
1%
1/16W
MF-LF
402
P-CHN
R9700
BKL_VREF_4V9
VSEN 9
R9718
1
5%
1/16W
MF-LF
402
IN
18 LRT
BKL_ISEN4
R9713
0
ISEN6 16
BKL_ISEN3
85
20%
10V
CERM
402
LCD_BKLT_PWM
ISEN5 15
19 LPF
GNDA
0.1UF
84 7
20 DIM
13
e
r
C9705
Q9702
ISEN4 14
BKL_LRT
C9714
BKL_SSTCMP_RC
85
ISEN3 12
7 SSTCMP
BKL_LPF
0.0022UF
2
C9706
6 RT
BKL_SSTCMP
BKL_DIM
4.7K
NO STUFF
R9733
2.0M
1
BKLT_PWM_RC
R9709
BKL_RT
LED_RETURN_6
0.1%
1/16W
TF
402
BKL_ISEN2
21
R9708
ISEN2 11
m
il
100K
8 ISET
1%
1/16W
MF-LF
402

SIZE
DRAWING NUMBER
D
APPLE INC.
*R9707, R9708, R9709, R9713, R9714, R9727, AND R9729 SHOULD AWAY FROM BOOST CIRCUIT
REV.
051-7656
SCALE
SHT
NONE
NO STUFF
BKL_ISEN1
7 78 85
OUT
VOLTAGE=50V
31
OF
97
123
CRITICAL
Q9806
FDC638APZ_SBMS001
PPBUS S0 LCDBkLT FET
603-HF
PPBUS_S0_LCDBKLT_FUSED
VOLTAGE=6V
R9808
301K
FDC638APZ
P-TYPE
1/16W
MF-LF
402
RDS(ON)
y
r
43 mOhm @4.5V
C9802
LOADING
0.1UF
1%
MOSFET
CHANNEL
0.4 A (EDP)
=PPBUS_S0_LCDBKLT
3AMP-32V-467
8
F9800
2 5
SSOT6-HF
10%
16V
X5R
402
PPBUS_S0_LCDBKLT_EN_DIV
R9809
147K
1%
a
n
i
1/16W
MF-LF
402
PPBUS_S0_LCDBKLT_EN_L
Q9807
SSM6N15FEAPE
SOT563
PPBUS_S0_LCDBKLT_PWR 85
VOLTAGE=6V
5
9
IN
LVDS_BKL_ON
BKLT_EN_L
R9840
4.7K
5%
1/16W
MF-LF
2 402
Q9807
SSM6N15FEAPE
SOT563
2
25
IN
m
il
BKLT_PLT_RST_L
e
r
LCD Backlight Support

SYNC_MASTER=YLEE_K20

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
98
123
GMUX 1.8V/1.2V S0 Switcher

D
C9900
CRITICAL
L9980
2.2UF
20%
6.3V
CERM
402-LF
2.2UH-1.2A
2
P1V2S0_SW
SWITCH_NODE=TRUE
=PP1V2_S0_REG
2
PCAA031B-SM
1
5%
50V
CERM
402
VIN
LTC3547
DFN-HF
CRITICAL
VFB2
SW2
(Switcher limit)
f = 2.25 MHz
1
C9985
2
7
GND
<Rb>
R9983
280K
RUN2
1%
1/16W
MF-LF
2 402
CRITICAL
L9900
m
il
2.2UH-1.2A
P2V5S0_SW
SWITCH_NODE=TRUE
PCAA031B-SM
C9901
5%
50V
CERM
402
<Ra>
10PF
R9900
475K
1%
1/16W
MF-LF
402
P2V5S0_VFB
<Rb>
67
IN
67
=P2V5S0_EN
e
r
OMIT
R9901
150K
=P1V2S0_EN
4.7UF
RUN1
THRML
PAD
SW1
VFB1
300mA max output
1%
1/16W
MF-LF
2 402
P1V2S0_VFB
U9900
1
<Ra>
R9982
280K
10PF
Vout = 1.2V
C9982
y
r
a
n
i
=PP3V3_S0_P1V2P2V5
20%
4V
X5R
402
=PP2V5_S0_REG
Vout = 2.5V
0.3A max output
(Switcher limit)
f = 2.25 MHz
C9905
4.7UF
20%
4V
X5R
402
TABLE_5_HEAD
PART#
1%
1/16W
MF-LF
402
QTY
DESCRIPTION
CRITICAL
BOM OPTION
TABLE_5_ITEM
114S0428
R9901
GMUX_2V5
114S0447
R9901
GMUX_1V8
TABLE_5_ITEM
Vout = 0.6V * (1 + Ra/Rb)
Misc Power Supplies

SYNC_MASTER=RXU_K20

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
99
123
FSB (Front-Side Bus) Constraints
CPU / FSB Net Properties

TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
FSB_50S
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
NET_TYPE
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
TABLE_PHYSICAL_RULE_ITEM
FSB_DATA_GROUP0
FSB_50S
FSB_DATA
FSB_DATA_GROUP0
FSB_50S
FSB_DATA
FSB_DSTB0
FSB_DSTB_50S
FSB_DSTB
FSB_DSTB0
FSB_DSTB_50S
FSB_DSTB
FSB_DATA_GROUP1
FSB_50S
FSB_DATA
FSB_DATA_GROUP1
FSB_50S
FSB_DATA
FSB_DSTB1
FSB_DSTB_50S
FSB_DSTB
FSB_DSTB1
FSB_DSTB_50S
FSB_DSTB
FSB_DATA_GROUP2
FSB_50S
FSB_DATA
FSB_DATA_GROUP2
FSB_50S
FSB_DATA
FSB_DSTB2
FSB_DSTB_50S
FSB_DSTB
FSB_DSTB2
FSB_DSTB_50S
FSB_DSTB
FSB_DATA_GROUP3
FSB_50S
FSB_DATA
FSB_DATA_GROUP3
FSB_50S
FSB_DATA
FSB_DSTB3
FSB_DSTB_50S
FSB_DSTB
FSB_DSTB3
FSB_DSTB_50S
FSB_DSTB
FSB_ADDR_GROUP0
FSB_50S
FSB_ADDR
FSB_ADDR_GROUP0
FSB_50S
FSB_ADDR
FSB_ADSTB0
FSB_50S
FSB_ADSTB
FSB_ADDR_GROUP1
FSB_50S
FSB_ADDR
FSB_ADSTB1
FSB_50S
FSB_ADSTB
FSB_1X
FSB_50S
FSB_1X
FSB_BREQ0_L
FSB_50S
FSB_1X
FSB_BREQ1_L
FSB_50S
FSB_1X
FSB_1X
FSB_50S
FSB_1X
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=1:1_DIFFPAIR
=1:1_DIFFPAIR
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
SPACING_RULE_SET
LAYER
WEIGHT
TABLE_SPACING_RULE_ITEM
FSB_DATA
=2x_DIELECTRIC
FSB_DSTB
=3x_DIELECTRIC
FSB_DATA
TOP,BOTTOM
=4x_DIELECTRIC
FSB_DSTB
TOP,BOTTOM
=5x_DIELECTRIC
FSB_ADDR
=STANDARD
FSB_ADDR
TOP,BOTTOM
=3x_DIELECTRIC
FSB_ADSTB
=2x_DIELECTRIC
FSB_ADSTB
TOP,BOTTOM
=4x_DIELECTRIC
FSB_1X
=STANDARD
FSB 4X Signal Groups
FSB_DSTB_50S
FSB_1X
TOP,BOTTOM
=3x_DIELECTRIC
All 4x/2x/1x FSB signals with impedance requirements are 50-ohm single-ended.
FSB 2X
Signals
FSB 4X signals / groups shown in signal table on right.

Signals within each 4x group should be matched within 5 ps of strobe.
DSTB# complementary pairs should be matched within 1 ps of each other, all DSTB#s matched to +/- 300 ps.
Spacing is 2x dielectric between DATA#, DINV# signals, with 3x dielectric spacing to the DSTB#s.
DSTB# complementary pairs are spaced normally and are NOT routed as differential pairs.
FSB 2X signals / groups shown in signal table on right.
Signals within each 2x group should be matched within 20 ps. ADTSB#s should be matched +/- 300 ps.
Spacing is 1x dielectric between ADDR#, REQ# signals, with 2x dielectric spacing to ADSTB#.
FSB 1X signals shown in signal table on right.
Signals within each 1x group should be matched to CPU clock, +0/-1000 mils.
FSB 1X Signals
Design Guide recommends each strobe/signal group is routed on the same layer.
Intel Design Guide recommends FSB signals be routed only on internal layers.
NOTE: Intel Design Guide allows closer spacing if signal lengths can be shortened.
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2
SOURCE: Santa Rosa Platform DG, Rev 1.5 (#22294), Sections 4.2 & 4.3
CPU Signal Constraints
PHYSICAL_RULE_SET
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

CPU_50S
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
FSB_50S
FSB_1X
FSB_50S
FSB_1X
FSB_1X
FSB_50S
FSB_1X
FSB_1X
FSB_50S
FSB_1X
FSB_1X
FSB_50S
FSB_1X
FSB_1X
FSB_50S
FSB_1X
FSB_1X
FSB_50S
FSB_1X
FSB_CPURST_L
FSB_50S
FSB_1X
FSB_1X
FSB_50S
FSB_1X
FSB_1X
FSB_50S
FSB_1X
CPU_ASYNC
CPU_50S
CPU_AGTL
CPU_BSEL
CPU_50S
CPU_AGTL
CPU_FERR_L
CPU_50S
CPU_8MIL
CPU_ASYNC
CPU_50S
CPU_AGTL
=STANDARD
CPU_27P4S
=27P4_OHM_SE
=27P4_OHM_SE
=27P4_OHM_SE
=27P4_OHM_SE
7 MIL
7 MIL
NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.
SPACING_RULE_SET
LAYER
WEIGHT
SPACING_RULE_SET
LAYER
WEIGHT
CPU_AGTL
=STANDARD
CPU_AGTL
TOP,BOTTOM
=2x_DIELECTRIC
m
il
CPU_8MIL
8 MIL
?
CPU_COMP
25 MIL
?
CPU_GTLREF
25 MIL
SR DG recommends at least 25 mils, >50 mils preferred
?
CPU_ITP
=2:1_SPACING
CPU_VCCSENSE
25 MIL
Most CPU signals with impedance requirements are 55-ohm single-ended.

Some signals require 27.4-ohm single-ended impedance.
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2
SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4
e
r
MCP FSB COMP Signal Constraints
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MCP_50S
=50_OHM_SE
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
WEIGHT
MCP_FSB_COMP
8 MIL
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.4
FSB Clock Constraints
PHYSICAL_RULE_SET
LAYER
CLK_FSB_100D
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
=100_OHM_DIFF
MINIMUM NECK WIDTH
=100_OHM_DIFF
=100_OHM_DIFF
SPACING_RULE_SET
LAYER
WEIGHT
SPACING_RULE_SET
CLK_FSB
=3x_DIELECTRIC
CLK_FSB
MAXIMUM NECK LENGTH

=100_OHM_DIFF
LAYER
TOP,BOTTOM
DIFFPAIR NECK GAP
=100_OHM_DIFF
=4x_DIELECTRIC
CPU_INIT_L
CPU_50S
CPU_AGTL
CPU_ASYNC_R
CPU_50S
CPU_AGTL
CPU_ASYNC_R
CPU_50S
CPU_AGTL
CPU_PROCHOT_L
CPU_50S
CPU_AGTL
CPU_PWRGD
CPU_50S
CPU_AGTL
CPU_ASYNC
CPU_50S
CPU_AGTL
CPU_ASYNC
CPU_50S
CPU_AGTL
PM_THRMTRIP_L
CPU_50S
CPU_8MIL
FSB_CPUSLP_L
CPU_50S
CPU_AGTL
CPU_FROM_SB
CPU_50S
CPU_AGTL
CPU_DPRSTP_L
CPU_50S
CPU_AGTL
CPU_ASYNC
CPU_50S
CPU_AGTL
MCP_CPU_COMP
MCP_50S
MCP_FSB_COMP
MCP_CPU_COMP
MCP_50S
MCP_FSB_COMP
MCP_CPU_COMP
MCP_50S
MCP_FSB_COMP
MCP_CPU_COMP
MCP_50S
MCP_FSB_COMP
FSB_CLK_CPU
CLK_FSB_100D
CLK_FSB
FSB_CLK_CPU
CLK_FSB_100D
CLK_FSB
FSB_CLK_ITP
CLK_FSB_100D
CLK_FSB
FSB_CLK_ITP
CLK_FSB_100D
CLK_FSB
FSB_CLK_MCP
CLK_FSB_100D
CLK_FSB
FSB_CLK_MCP
CLK_FSB_100D
CLK_FSB
CPU_IERR_L
CPU_50S
PM_DPRSLPVR
CPU_50S
CPU_AGTL
(See above)
CPU_50S
CPU_AGTL
CPU_GTLREF
CPU_50S
CPU_GTLREF
CPU_COMP
CPU_50S
CPU_COMP
CPU_COMP
CPU_27P4S
CPU_COMP
CPU_COMP
CPU_50S
CPU_COMP
CPU_COMP
CPU_27P4S
CPU_COMP
XDP_TDI
CPU_50S
CPU_ITP
XDP_TDO
CPU_50S
CPU_ITP
XDP_TMS
CPU_50S
CPU_ITP
XDP_TCK
CPU_50S
CPU_ITP
XDP_TRST_L
CPU_50S
CPU_ITP
XDP_BPM_L
CPU_50S
CPU_ITP
XDP_BPM_L5
CPU_50S
CPU_ITP
(FSB_CPURST_L)
CPU_50S
CPU_ITP
CPU_50S
CPU_8MIL
CPU_50S
CPU_8MIL
CPU_27P4S
CPU_VCCSENSE
FSB_D_L<47..32>
FSB_DINV_L<2>
FSB_DSTB_L_P<2>
FSB_DSTB_L_N<2>
FSB_D_L<63..48>
FSB_DINV_L<3>
FSB_DSTB_L_P<3>
FSB_DSTB_L_N<3>
FSB_A_L<16..3>
FSB_REQ_L<4..0>
FSB_ADSTB_L<0>
FSB_A_L<35..17>
FSB_ADSTB_L<1>
FSB_ADS_L
FSB_BREQ0_L
FSB_BREQ1_L
FSB_BNR_L
FSB_BPRI_L
FSB_DBSY_L
FSB_DEFER_L
FSB_DRDY_L
FSB_HIT_L
FSB_HITM_L
FSB_LOCK_L
FSB_CPURST_L
FSB_RS_L<2..0>
FSB_TRDY_L
CPU_A20M_L
CPU_BSEL<2..0>
CPU_FERR_L
CPU_IGNNE_L
CPU_INIT_L
CPU_INTR
CPU_NMI
CPU_PROCHOT_L
CPU_PWRGD
CPU_SMI_L
CPU_STPCLK_L
PM_THRMTRIP_L
FSB_CPUSLP_L
CPU_DPSLP_L
CPU_DPRSTP_L
FSB_DPWR_L
MCP_BCLK_VML_COMP_VDD
MCP_BCLK_VML_COMP_GND
MCP_CPU_COMP_VCC
MCP_CPU_COMP_GND
FSB_CLK_CPU_P
FSB_CLK_CPU_N
FSB_CLK_ITP_P
FSB_CLK_ITP_N
FSB_CLK_MCP_P
FSB_CLK_MCP_N
CPU_IERR_L
=100_OHM_DIFF
WEIGHT
FSB_D_L<31..16>
FSB_DINV_L<1>
FSB_DSTB_L_P<1>
FSB_DSTB_L_N<1>
7 10 14
7 10 14
7 10 14
7 10 14
7 10 14
7 10 14
7 10 14
7 10 14
7 10 14
y
r
7 10 14
7 10 14
7 10 14
7 10 14
7 10 14
7 10 14
7 10 14
7 10 14
7 10 14
7 10 14
a
n
i
FSB_1X
FSB_1X
ALLOW ROUTE
ON LAYER?
FSB_D_L<15..0>
FSB_DINV_L<0>
FSB_DSTB_L_P<0>
FSB_DSTB_L_N<0>
7 10 14
7 10 14
7 10 14
9 10 14
14
10 14
10 14
7 10 14
10 14
7 10 14
7 10 14
7 10 14
7 10 14
9 10 13 14
10 14
10 14
10 14
9 10
10 14
10 14
10 14
9 10 14
9 10 14
10 14 42 61
10 13 14
10 14
10 14
10 14 42
10 14
10 14
9 10 14 61
10 14
14
14
14
14
10 14
10 14
13 14
13 14
14
14
10
PM_DPRSLPVR
IMVP_DPRSLPVR
CPU_GTLREF
CPU_COMP<3>
CPU_COMP<2>
CPU_COMP<1>
CPU_COMP<0>
21 61
61
10 26
10
10
10
10
CPU_VCCSENSE
CPU_VCCSENSE
CPU_27P4S
CPU_VCCSENSE
(CPU_VCCSENSE)
(CPU_VCCSENSE)
CPU_27P4S
CPU_VCCSENSE
CPU_27P4S
CPU_VCCSENSE
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TCK
XDP_TRST_L
XDP_BPM_L<4..0>
XDP_BPM_L<5>
XDP_CPURST_L
CPU_VID<6..0>
IMVP6_VID<6..0>
CPU_VCCSENSE_P
CPU_VCCSENSE_N
IMVP6_VSEN_P
IMVP6_VSEN_N
6 10 13
6 10
6 10 13
6 10 13
6 10 13
10 13
10 13
13
9 11
CPU/FSB Constraints
9 61
11 61
SYNC_MASTER=M98_MLB
11 61
61
61

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
100
123
Memory Bus Constraints
Memory Net Properties

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
MEM_40S
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=STANDARD
=STANDARD
NET_TYPE
PHYSICAL
SPACING
MEM_A_CLK
MEM_70D_VDD
MEM_CLK
MEM_A_CLK
MEM_70D_VDD
MEM_CLK
MEM_A_CNTL
MEM_40S_VDD
MEM_CTRL
MEM_A_CNTL
MEM_40S_VDD
MEM_CTRL
MEM_A_CNTL
MEM_40S_VDD
MEM_CTRL
MEM_A_CMD
MEM_40S_VDD
MEM_CMD
MEM_A_CMD
MEM_40S_VDD
MEM_CMD
MEM_A_CMD
MEM_40S_VDD
MEM_CMD
MEM_A_CMD
MEM_40S_VDD
MEM_CMD
MEM_A_CMD
MEM_40S_VDD
MEM_CMD
MEM_A_DQ_BYTE0
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE1
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE2
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE3
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE4
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE5
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE6
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE7
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE0
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE1
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE2
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE3
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE4
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE5
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE6
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE7
MEM_40S
MEM_DATA
MEM_A_DQS0
MEM_70D
MEM_DQS
MEM_A_DQS0
MEM_70D
MEM_DQS
MEM_A_DQS1
MEM_70D
MEM_DQS
MEM_A_DQS1
MEM_70D
MEM_DQS
MEM_A_DQS2
MEM_70D
MEM_DQS
MEM_A_DQS2
MEM_70D
MEM_DQS
MEM_A_DQS3
MEM_70D
MEM_DQS
MEM_A_DQS3
MEM_70D
MEM_DQS
MEM_A_DQS4
MEM_70D
MEM_DQS
MEM_A_DQS4
MEM_70D
MEM_DQS
MEM_A_DQS5
MEM_70D
MEM_DQS
MEM_A_DQS5
MEM_70D
MEM_DQS
MEM_A_DQS6
MEM_70D
MEM_DQS
MEM_70D
MEM_DQS
MEM_40S_VDD
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=STANDARD
=STANDARD
MEM_A_CLK_P<5..0>
MEM_A_CLK_N<5..0>
15 27
15 27
MEM_70D
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
MEM_70D_VDD
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
SPACING_RULE_SET
LAYER
WEIGHT
=4:1_SPACING
MEM_CLK2MEM
MEM_CTRL2CTRL
=2:1_SPACING
MEM_A_CKE<3..0>
MEM_A_CS_L<3..0>
MEM_A_ODT<3..0>
MEM_A_A<14..0>
MEM_A_BA<2..0>
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L
15 27
15 27
15 27
15 27
15 27
15 27
15 27
y
r
15 27
MEM_CTRL2MEM
=2.5:1_SPACING
MEM_CMD2CMD
=1.5:1_SPACING
MEM_CMD2MEM
=3:1_SPACING
?
MEM_DATA2DATA
=1.5:1_SPACING
?
MEM_DATA2MEM
=3:1_SPACING
?
MEM_DQS2MEM
=3:1_SPACING
MEM_A_DQ<7..0>
MEM_A_DQ<15..8>
MEM_A_DQ<23..16>
MEM_A_DQ<31..24>
MEM_A_DQ<39..32>
MEM_A_DQ<47..40>
MEM_A_DQ<55..48>
MEM_A_DQ<63..56>
15 27
15 27
15 27
15 27
15 27
15 27
15 27
15 27
MEM_2OTHER
25 MIL
Memory Bus Spacing Group Assignments

TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_CLK
MEM_CLK
MEM_CLK2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CMD
MEM_CLK
MEM_CMD2MEM
MEM_CLK
MEM_CTRL
MEM_CLK2MEM
MEM_CLK
MEM_CMD
MEM_CLK2MEM
MEM_CMD
MEM_CTRL
MEM_CMD2MEM
MEM_CMD
MEM_CMD
MEM_CMD2CMD
MEM_CMD
MEM_DATA
MEM_CMD2MEM
MEM_CMD
MEM_DQS
MEM_CMD2MEM
MEM_CLK
MEM_DATA
MEM_CLK2MEM
MEM_CLK
MEM_DQS
MEM_CLK2MEM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_CTRL
MEM_CLK
MEM_CTRL2MEM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_DATA
MEM_CLK
MEM_DATA2MEM
MEM_CTRL
MEM_CTRL
MEM_CTRL2CTRL
MEM_CTRL
MEM_CMD
MEM_CTRL2MEM
MEM_DATA
MEM_CTRL
MEM_DATA2MEM
MEM_DATA
MEM_CMD
MEM_DATA2MEM
MEM_CTRL
MEM_DATA
MEM_CTRL2MEM
MEM_DATA
MEM_DATA
MEM_DATA2DATA
MEM_CTRL
MEM_DQS
MEM_CTRL2MEM
MEM_DATA
MEM_DQS
MEM_DATA2MEM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_DQS
MEM_CLK
MEM_DQS2MEM
MEM_DQS
MEM_CTRL
MEM_DQS2MEM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_CLK
MEM_2OTHER
MEM_CTRL
MEM_2OTHER
MEM_CMD
MEM_DQS2MEM
MEM_CMD
MEM_2OTHER
MEM_DQS
MEM_DATA
MEM_DQS2MEM
MEM_DATA
MEM_2OTHER
MEM_DQS
MEM_DQS
MEM_DQS2MEM
m
il
MEM_DQS
MEM_A_DQS6
MEM_DQS
MEM_2OTHER
Need to support MEM_*-style wildcards!
DDR2:
DQ signals should be matched within 20 ps of associated DQS pair.

DQS intra-pair matching should be within 1 ps, no inter-pair matching requirement.
All DQS pairs should be matched within 100 ps of clocks.
CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 140 ps.
A/BA/cmd signals should be matched within 75 ps, no CLK matching requirement.
All memory signals maximum length is 1.005 ps. CLK minimum length is 594 ps (lengths include substrate).
DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric.
e
r
DDR3:
DQ signals should be matched within 5 ps of associated DQS pair.
DQS intra-pair matching should be within 1 ps, inter-pair matching shoulw be within 180 ps
No DQS to clock matching requirement.
CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 2 ps.
A/BA/cmd signals should be matched within 5 ps of CLK pairs.
All memory signals maximum length is 1.005 ps. CLK minimum length is 594 ps (lengths include substrate).
DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric.
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3
SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2
MCP MEM COMP Signal Constraints

PHYSICAL_RULE_SET
LAYER
MCP_MEM_COMP
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
7 MIL
7 MIL
SPACING_RULE_SET
LAYER
WEIGHT
MCP_MEM_COMP
8 MIL
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3.4
MAXIMUM NECK LENGTH

=STANDARD

=STANDARD
MEM_A_DQS7
MEM_70D
MEM_DQS
MEM_A_DQS7
MEM_70D
MEM_DQS
MEM_B_CLK
MEM_70D_VDD
MEM_CLK
MEM_B_CLK
MEM_70D_VDD
MEM_CLK
MEM_B_CNTL
MEM_40S_VDD
MEM_CTRL
MEM_B_CNTL
MEM_40S_VDD
MEM_CTRL
MEM_B_CNTL
MEM_40S_VDD
MEM_CTRL
MEM_B_CMD
MEM_40S_VDD
MEM_CMD
MEM_B_CMD
MEM_40S_VDD
MEM_CMD
MEM_B_CMD
MEM_40S_VDD
MEM_CMD
MEM_B_CMD
MEM_40S_VDD
MEM_CMD
MEM_B_CMD
MEM_40S_VDD
MEM_CMD
MEM_B_DQ_BYTE0
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE1
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE2
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE3
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE4
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE5
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE6
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE7
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE0
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE1
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE2
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE3
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE4
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE5
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE6
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE7
MEM_40S
MEM_DATA
MEM_B_DQS0
MEM_70D
MEM_DQS
MEM_B_DQS0
MEM_70D
MEM_DQS
MEM_B_DQS1
MEM_70D
MEM_DQS
MEM_B_DQS1
MEM_70D
MEM_DQS
MEM_B_DQS2
MEM_70D
MEM_DQS
MEM_B_DQS2
MEM_70D
MEM_DQS
MEM_B_DQS3
MEM_70D
MEM_DQS
MEM_B_DQS3
MEM_70D
MEM_DQS
MEM_B_DQS4
MEM_70D
MEM_DQS
MEM_B_DQS4
MEM_70D
MEM_DQS
MEM_B_DQS5
MEM_70D
MEM_DQS
MEM_B_DQS5
MEM_70D
MEM_DQS
MEM_B_DQS6
MEM_70D
MEM_DQS
DIFFPAIR NECK GAP
15 27
a
n
i
MEM_A_DM<0>
MEM_A_DM<1>
MEM_A_DM<2>
MEM_A_DM<3>
MEM_A_DM<4>
MEM_A_DM<5>
MEM_A_DM<6>
MEM_A_DM<7>
=STANDARD
MEM_B_DQS6
MEM_70D
MEM_DQS
MEM_B_DQS7
MEM_70D
MEM_DQS
MEM_B_DQS7
MEM_70D
MEM_DQS
MCP_MEM_COMP
MCP_MEM_COMP
MCP_MEM_COMP
MCP_MEM_COMP
MCP_MEM_COMP
MCP_MEM_COMP
15 27
15 27
15 27
15 27
15 27
15 27
15 27
MEM_A_DQS_P<0>
MEM_A_DQS_N<0>
MEM_A_DQS_P<1>
MEM_A_DQS_N<1>
MEM_A_DQS_P<2>
MEM_A_DQS_N<2>
MEM_A_DQS_P<3>
MEM_A_DQS_N<3>
MEM_A_DQS_P<4>
MEM_A_DQS_N<4>
MEM_A_DQS_P<5>
MEM_A_DQS_N<5>
MEM_A_DQS_P<6>
MEM_A_DQS_N<6>
MEM_A_DQS_P<7>
MEM_A_DQS_N<7>
MEM_B_CLK_P<5..0>
MEM_B_CLK_N<5..0>
MEM_B_CKE<3..0>
MEM_B_CS_L<3..0>
MEM_B_ODT<3..0>
MEM_B_A<14..0>
MEM_B_BA<2..0>
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
MEM_B_DQ<7..0>
MEM_B_DQ<15..8>
MEM_B_DQ<23..16>
MEM_B_DQ<31..24>
MEM_B_DQ<39..32>
MEM_B_DQ<47..40>
MEM_B_DQ<55..48>
MEM_B_DQ<63..56>
MEM_B_DM<0>
MEM_B_DM<1>
MEM_B_DM<2>
MEM_B_DM<3>
MEM_B_DM<4>
MEM_B_DM<5>
MEM_B_DM<6>
MEM_B_DM<7>
15 27
15 27
15 27
15 27
15 27
15 27
15 27
15 27
15 27
15 27
15 27
15 27
15 27
15 27
15 27
15 27
15 28
15 28
15 28
15 28
15 28
15 28
15 28
15 28
15 28
15 28
15 28
15 28
15 28
15 28
15 28
15 28
15 28
15 28
15 28
15 28
15 28
15 28
15 28
15 28
15 28
15 28
MEM_B_DQS_P<0>
MEM_B_DQS_N<0>
MEM_B_DQS_P<1>
MEM_B_DQS_N<1>
MEM_B_DQS_P<2>
MEM_B_DQS_N<2>
MEM_B_DQS_P<3>
MEM_B_DQS_N<3>
MEM_B_DQS_P<4>
MEM_B_DQS_N<4>
MEM_B_DQS_P<5>
MEM_B_DQS_N<5>
MEM_B_DQS_P<6>
MEM_B_DQS_N<6>
MEM_B_DQS_P<7>
MEM_B_DQS_N<7>
MCP_MEM_COMP_VDD
MCP_MEM_COMP_GND
15 28
15 28
15 28
15 28
15 28
15 28
15 28
15 28
15 28
15 28
15 28
Memory Constraints
15 28
15 28
SYNC_MASTER=M98_MLB
15 28
15 28
15 28

16
16

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
101
123
PCI-Express
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
PCIE_90D
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
NET_TYPE
PHYSICAL
SPACING
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
CLK_PCIE_100D
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
PEG_R2D
SPACING_RULE_SET
LAYER
WEIGHT
SPACING_RULE_SET
LAYER
WEIGHT
PEG_D2R
PCIE
=3X_DIELECTRIC
PCIE
TOP,BOTTOM
=4X_DIELECTRIC
CLK_PCIE
20 MIL
PEG_R2D_P<15..0>
PEG_R2D_N<15..0>
PEG_R2D_C_P<15..0>
PEG_R2D_C_N<15..0>
PEG_D2R_P<15..0>
PEG_D2R_N<15..0>
PEG_D2R_C_P<15..0>
PEG_D2R_C_N<15..0>
69
69
9 69
9 69
9 69
9 69
69
69
8 MIL
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.4

PCIE_MINI_R2D
Analog Video Signal Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
=50_OHM_SE
=50_OHM_SE
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
PCIE_MINI_D2R
DIFFPAIR NECK GAP
PCIE_MINI_R2D_P
PCIE_MINI_R2D_N
PCIE_MINI_R2D_C_P
PCIE_MINI_R2D_C_N
PCIE_MINI_D2R_P
PCIE_MINI_D2R_N
7 30
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
WEIGHT
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
CRT
=4:1_SPACING
PCIE_FW_R2D
CRT
CRT
CRT_2CRT
PCIE_FW_D2R
CRT_2CRT
=STANDARD
a
n
i
CRT_2CLK
50 MIL
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
?
CRT_2SWITCHER
250 MIL
?
CRT_SYNC
16 MIL
?
MCP_DAC_COMP
=2:1_SPACING
PCIE_EXCARD_R2D
CRT signal single-ended impedence varies by location:

- 37.5-ohm from MCP to first termination resistor.
- 50-ohm from first to second termination resistor.
- 75-ohm from output of three-pole filter to connector (if possible).
R/G/B signals should be matched as close as possible and < 10 inches.
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.1 & 2.5.2.
PCIE_EXCARD_D2R
MCP_PE0_REFCLK
MCP_PE1_REFCLK
MCP_PE2_REFCLK
Digital Video Signal Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
MCP_PE3_REFCLK
DP_100D
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
LVDS_100D
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
MCP_PEX_CLK_COMP
MCP_PEX_COMP
CRT_RED
CRT_50S
CRT
CRT_GREEN
CRT_50S
CRT
CRT_BLUE
CRT_50S
CRT
MCP_DV_COMP
20 MIL
20 MIL
=STANDARD
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
WEIGHT
SPACING_RULE_SET
LAYER
WEIGHT
DISPLAYPORT
=3x_DIELECTRIC
DISPLAYPORT
=4x_DIELECTRIC
TOP,BOTTOM
LVDS
=3x_DIELECTRIC
m
il
LVDS
TOP,BOTTOM
=4x_DIELECTRIC
LVDS intra-pair matching should be 5 mils. Pairs should be within 100 mils of clock length.
DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 150 ps.
DIsplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals.
Max length of LVDS/DisplayPort/TMDS traces: 12 inches.
SATA Interface Constraints

LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
SATA_100D
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
DIFFPAIR NECK GAP
e
r
SPACING_RULE_SET
WEIGHT
SATA
LAYER
*
=4x_DIELECTRIC
SATA_TERMP
8 MIL
=100_OHM_DIFF
SPACING_RULE_SET
LAYER
WEIGHT
=3x_DIELECTRIC
SATA
TOP,BOTTOM
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.7.1.
CRT_50S
CRT_SYNC
CRT_SYNC
CRT_50S
CRT_SYNC
MCP_DAC_VREF
PHYSICAL_RULE_SET
CRT_SYNC
MCP_DAC_RSET
PCIE_FW_R2D_P
PCIE_FW_R2D_N
PCIE_FW_R2D_C_P
PCIE_FW_R2D_C_N
PCIE_FW_D2R_P
PCIE_FW_D2R_N
PCIE_FW_D2R_C_P
PCIE_FW_D2R_C_N
MCP_DAC_COMP
MCP_DAC_COMP
TMDS_IG_TXC
DP_100D
DISPLAYPORT
TMDS_IG_TXC
DP_100D
DISPLAYPORT
TMDS_IG_TXD
DP_100D
DISPLAYPORT
TMDS_IG_TXD
DP_100D
DISPLAYPORT
DP_ML
DP_100D
DISPLAYPORT
DP_ML
DP_100D
DISPLAYPORT
DP_AUX_CH
DP_100D
DISPLAYPORT
DP_AUX_CH
DP_100D
DISPLAYPORT
MCP_HDMI_RSET
MCP_DV_COMP
MCP_HDMI_VPROBE
MCP_DV_COMP
LVDS_IG_A_CLK
LVDS_100D
LVDS
LVDS_IG_A_CLK
LVDS_100D
LVDS
LVDS_IG_A_DATA
LVDS_100D
LVDS
LVDS_IG_A_DATA
LVDS_100D
LVDS
LVDS_IG_A_DATA3
LVDS_100D
LVDS
LVDS_IG_A_DATA3
LVDS_100D
LVDS
LVDS_IG_B_CLK
LVDS_100D
LVDS
LVDS_IG_B_CLK
LVDS_100D
LVDS
LVDS_IG_B_DATA
LVDS_100D
LVDS
LVDS_IG_B_DATA
LVDS_100D
LVDS
LVDS_IG_B_DATA3
LVDS_100D
LVDS
LVDS_IG_B_DATA3
LVDS_100D
LVDS
MCP_IFPAB_RSET
MCP_DV_COMP
SATA_HDD_D2R
SATA_ODD_R2D
SATA_ODD_D2R
MCP_SATA_TERMP
PEG_CLK100M_P
PEG_CLK100M_N
PCIE_CLK100M_MINI_P
PCIE_CLK100M_MINI_N
PCIE_CLK100M_FW_P
PCIE_CLK100M_FW_N
MCP_PEX_CLK_COMP
CRT_IG_R_C_PR
CRT_IG_G_Y_Y
CRT_IG_B_COMP_PB
CRT_IG_HSYNC
CRT_IG_VSYNC
MCP_TV_DAC_RSET
MCP_TV_DAC_VREF
DP_IG_ML_P<3..0>
DP_IG_ML_N<3..0>
DP_IG_AUX_CH_P
DP_IG_AUX_CH_N
LVDS_IG_A_CLK_P
LVDS_IG_A_CLK_N
LVDS_IG_A_DATA_P<2..0>
LVDS_IG_A_DATA_N<2..0>
LVDS_IG_A_DATA_P<3>
LVDS_IG_A_DATA_N<3>
LVDS_IG_B_CLK_P
LVDS_IG_B_CLK_N
LVDS_IG_B_DATA_P<2..0>
LVDS_IG_B_DATA_N<2..0>
LVDS_IG_B_DATA_P<3>
LVDS_IG_B_DATA_N<3>
MCP_IFPAB_RSET
MCP_IFPAB_VPROBE
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_TERMP
17 30
17 30
7 17 30
7 17 30
35
35
17 35
17 35
17 35
17 35
35
35
7 31
7 31
17 31
17 31
7 17 31
7 17 31
17 69
17 69
17 30
17 30
17 35
17 35
17 31
17 31
17
18 24
18 24
18 24
18 24
18 24
18 24
18 24
TMDS_IG_TXC_P
TMDS_IG_TXC_N
TMDS_IG_TXD_P<2..0>
TMDS_IG_TXD_N<2..0>
MCP_HDMI_RSET
MCP_HDMI_VPROBE
MCP_IFPAB_VPROBE
SATA_HDD_R2D
PCIE_EXCARD_R2D_P
PCIE_EXCARD_R2D_N
PCIE_EXCARD_R2D_C_P
PCIE_EXCARD_R2D_C_N
PCIE_EXCARD_D2R_P
PCIE_EXCARD_D2R_N
7 30
y
r
CRT_50S
MCP_PEX_COMP
SATA_HDD_R2D_C_P
SATA_HDD_R2D_C_N
SATA_HDD_R2D_P
SATA_HDD_R2D_N
SATA_HDD_D2R_P
SATA_HDD_D2R_N
SATA_HDD_D2R_C_P
SATA_HDD_D2R_C_N
SATA_ODD_R2D_C_P
SATA_ODD_R2D_C_N
SATA_ODD_R2D_P
SATA_ODD_R2D_N
SATA_ODD_D2R_P
SATA_ODD_D2R_N
SATA_ODD_D2R_C_P
SATA_ODD_D2R_C_N
MCP_SATA_TERMP
9 81
9 81
18 81
18 81
18 24
18 24
18 84
18 84
18 84
18 84
9 18
9 18
9 18
9 18
18 84
18 84
9 18
9 18
18 24
18 24
20 38
20 38
7 38
7 38
20 38
20 38
7 38
7 38
20 38
20 38
7 38
MCP Constraints 1
7 38
20 38
SYNC_MASTER=M98_MLB
20 38
7 38
7 38

20

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
102
123
PCI Bus Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
PCI_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
NET_TYPE
PHYSICAL
SPACING
MCP_DEBUG
PCI_55S
PCI
PCI_AD
PCI_55S
PCI
PCI_AD24
PCI_55S
PCI
PCI_AD
PCI_55S
PCI
PCI_AD
PCI_55S
PCI
PCI_C_BE_L
PCI_55S
PCI
PCI_CNTL
PCI_55S
PCI
PCI_CNTL
PCI_55S
PCI
PCI_CNTL
PCI_55S
PCI
PCI_CNTL
PCI_55S
PCI
PCI_CNTL
PCI_55S
PCI
PCI_CNTL
PCI_55S
PCI
PCI_CNTL
PCI_55S
PCI
PCI_REQ0_L
PCI_55S
PCI
PCI_GNT0_L
PCI_55S
PCI
PCI_REQ1_L
PCI_55S
PCI
PCI_GNT1_L
PCI_55S
PCI
PCI_INTW_L
PCI_55S
PCI
PCI_INTX_L
PCI_55S
PCI
PCI_INTY_L
PCI_55S
PCI
PCI_INTZ_L
PCI_55S
PCI
MCP_PCI_CLK2
CLK_PCI_55S
CLK_PCI
CLK_PCI_55S
CLK_PCI
LPC_AD
LPC_55S
LPC
LPC_FRAME_L
LPC_55S
LPC
LPC_RESET_L
LPC_55S
LPC
CLK_PCI_55S
SPACING_RULE_SET
LAYER
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
WEIGHT
PCI
=STANDARD
?
CLK_PCI
8 MIL
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.8.
LPC Bus Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

LPC_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
CLK_LPC_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
WEIGHT
6 MIL
LPC
CLK_LPC
8 MIL
USB 2.0 Interface Constraints

ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

MCP_USB_RBIAS
=STANDARD
8 MIL
8 MIL
=STANDARD
=STANDARD
=STANDARD
USB_90D
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
MCP_LPC_CLK0
SPACING_RULE_SET
LAYER
WEIGHT
=2x_DIELECTRIC
SPACING_RULE_SET
LAYER
WEIGHT
=4x_DIELECTRIC
USB
USB_EXTA
TOP,BOTTOM
USB_MINI
SMBus Interface Constraints
USB_EXTD
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
=55_OHM_SE
=55_OHM_SE
CLK_LPC_55S
CLK_LPC
CLK_LPC_55S
CLK_LPC
CLK_LPC_55S
CLK_LPC
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB
PHYSICAL_RULE_SET
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

USB_CAMERA
SMB_55S
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
USB_BT
SPACING_RULE_SET
LAYER
m
il
WEIGHT
USB_TPAD
SMB
=2x_DIELECTRIC
USB_IR
USB_EXTB
HD Audio Interface Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

HDA_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
LAYER
WEIGHT
HDA
=2x_DIELECTRIC
MCP_HDA_COMP
8 MIL
e
r
SIO Signal Constraints
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
CLK_SLOW_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
SPACING_RULE_SET
LAYER
WEIGHT
8 MIL
CLK_SLOW
SPI Interface Constraints
=STANDARD
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
SPI_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
WEIGHT
SPI
8 MIL
LPC_AD<3..0>
LPC_FRAME_L
LPC_RESET_L
LPC_CLK33M_SMC_R
LPC_CLK33M_SMC
LPC_CLK33M_LPCPLUS
USB_EXTA_P
USB_EXTA_N
USB_EXTA_MUXED_P
USB_EXTA_MUXED_N
USB_MINI_P
USB_MINI_N
USB_EXTD_P
USB_EXTD_N
USB_CAMERA_P
USB_CAMERA_N
USB_BT_P
USB_BT_N
USB_TPAD_P
USB_TPAD_N
USB_IR_P
USB_IR_N
USB_EXTB_P
USB_EXTB_N
USB_EXCARD_P
USB_EXCARD_N
USB_EXTC_P
USB_EXTC_N
MCP_USB_RBIAS_GND
MCP_USB_RBIAS
SMBUS_MCP_0_CLK
SMB_55S
SMB
SMBUS_MCP_0_DATA
SMB_55S
SMB
SMBUS_MCP_1_CLK
SMB_55S
SMB
SMBUS_MCP_1_DATA
SMB_55S
SMB
HDA_BIT_CLK
HDA_55S
HDA
HDA_55S
HDA
HDA_55S
HDA
HDA_55S
HDA
HDA_55S
HDA
HDA_55S
HDA
HDA_55S
HDA
HDA_55S
HDA
HDA_55S
HDA
HDA_55S
HDA
HDA_BIT_CLK
HDA_BIT_CLK_R
HDA_SYNC
HDA_SYNC_R
HDA_RST_R_L
HDA_RST_L
HDA_SDIN0
HDA_SDIN_CODEC
HDA_SDOUT
HDA_SDOUT_R
MCP_HDA_COMP
MCP_HDA_PULLDN_COMP
CLK_SLOW_55S
CLK_SLOW
CLK_SLOW_55S
CLK_SLOW
PM_CLK32K_SUSCLK_R
PM_CLK32K_SUSCLK
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
HDA_SYNC
HDA_RST_L
HDA_SDIN0
HDA_SDOUT
MCP_HDA_PULLDN_COMP
MCP_SUS_CLK
PCI_CLK33M_MCP_R
PCI_CLK33M_MCP
MCP_USB_RBIAS
PHYSICAL_RULE_SET
USB_EXCARD
USB_EXTC
SPACING_RULE_SET
y
r
19
19
a
n
i
LAYER
13 19
PHYSICAL_RULE_SET
MCP_DEBUG<7..0>
PCI_AD<23..8>
PCI_AD<24>
PCI_AD<31..25>
PCI_PAR
PCI_C_BE_L<3..0>
PCI_IRDY_L
PCI_DEVSEL_L
PCI_PERR_L
PCI_SERR_L
PCI_STOP_L
PCI_TRDY_L
PCI_FRAME_L
PCI_REQ0_L
PCI_GNT0_L
PCI_REQ1_L
PCI_GNT1_L
PCI_INTW_L
PCI_INTX_L
PCI_INTY_L
PCI_INTZ_L
SPI_CLK
SPI_MOSI
SPI_MISO
SPI_CS0
SMBUS_MCP_0_CLK
SMBUS_MCP_0_DATA
SMBUS_MCP_1_CLK
SMBUS_MCP_1_DATA
SPI_CLK_R
SPI_CLK
SPI_MOSI_R
SPI_MOSI
SPI_MISO
SPI_MISO_R
SPI_CS0_R_L
SPI_CS0_L
19
19
7 19 41 43 84
7 19 41 43 84
19 25 84
19 25
25 41
7 25 43
20 39
20 39
9 20
9 20
9 20
9 20
20 30
20 30
20 30
20 30
20 49
20 49
20 40
20 40
20 39
20 39
20 31
20 31
20 96 98
20 96 98
20
7 13 21 44
7 13 21 44
21 44
21 44
9 21
21
21 53
21
21
21 53
21 53
21 53
21
21
21 25
25 41
21 43
52
21 43
52
21 43
52
21 43
MCP Constraints 2
SYNC_MASTER=M98_MLB

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
103
123
MCP RGMII (Ethernet) Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
MCP_MII_COMP
=STANDARD
7.5 MIL
7.5 MIL
=STANDARD
=STANDARD
=STANDARD
NET_TYPE
PHYSICAL
SPACING
MCP_MII_COMP_VDD
MCP_MII_COMP_GND
MCP_MII_COMP
MCP_MII_COMP
MCP_MII_COMP
MCP_MII_COMP
MCP_CLK25M_BUF0
ENET_MII_55S
MCP_BUF0_CLK
ENET_MII_55S
MCP_BUF0_CLK
ENET_INTR_L
ENET_MII_55S
ENET_MII
ENET_MDIO
ENET_MII_55S
ENET_MII
ENET_MDC
ENET_MII_55S
ENET_MII
ENET_PWRDWN_L
ENET_MII_55S
ENET_MII
ENET_MII_55S
ENET_MII
ENET_MII_55S
ENET_MII
ENET_MII_55S
ENET_MII
ENET_MII_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
WEIGHT
MCP_CLK25M_BUF0_R
18
18
18 33
32 33
MCP_BUF0_CLK
=3:1_SPACING
ENET_MII
12 MIL
SOURCE: MCP73 Interface DG (DG-02974-001_v01), Sections 2.7.2 & 2.7.4
88E1116R (Ethernet PHY) Constraints
ENET_RXCLK
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
ENET_MDI_100D
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
ENET_INTR_L
ENET_MDIO
ENET_MDC
ENET_PWRDWN_L
ENET_CLK125M_RXCLK_R
ENET_CLK125M_RXCLK
ENET_RXD_R<3..0>
ENET_RXD<0>
ENET_RXD<3..1>
ENET_RX_CTRL
ENET_RXD
ENET_MII_55S
ENET_MII
ENET_RXD_STRAP
ENET_MII_55S
ENET_MII
ENET_RXD
ENET_MII_55S
ENET_MII
ENET_TXCLK
ENET_MII_55S
ENET_MII
ENET_TXD0
ENET_MII_55S
ENET_MII
ENET_TXD
ENET_MII_55S
ENET_MII
ENET_TXD
ENET_MII_55S
ENET_MII
ENET_CLK125M_TXCLK
ENET_TXD<0>
ENET_TXD<3..1>
ENET_TX_CTRL
ENET_MII_55S
ENET_MII
ENET_RESET_L
18 32
18 32
y
r
18 32
32
18 32
18 32
18 32
SPACING_RULE_SET
LAYER
WEIGHT
25 MIL
ENET_MDI
32
18 32
18 32
18 32
18 32
18 32
a
n
i
ENET_MDI
ENET_MDI_100D
ENET_MDI
ENET_MDI_100D
ENET_MDI
ENET_MDI_P<3..0>
ENET_MDI_N<3..0>
32 34
32 34
m
il
e
r
Ethernet Constraints
SYNC_MASTER=M98_MLB

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
104
123
FireWire Interface Constraints
FireWire Net Properties

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
FW_110D
=110_OHM_DIFF
=110_OHM_DIFF
=110_OHM_DIFF
=110_OHM_DIFF
=110_OHM_DIFF
=110_OHM_DIFF
NET_TYPE
PHYSICAL
SPACING
FW_P0_TPA
FW_110D
FW_TP
FW_P0_TPA
FW_110D
FW_TP
FW_P0_TPB
FW_110D
FW_TP
FW_P0_TPB
FW_110D
FW_TP
FW_P1_TPA
FW_110D
FW_TP
FW_P1_TPA
FW_110D
FW_TP
FW_P1_TPB
FW_110D
FW_TP
FW_P1_TPB
FW_110D
FW_TP
SPACING_RULE_SET
LAYER
WEIGHT
FW_TP
=3:1_SPACING
FW_P0_TPA_P
FW_P0_TPA_N
FW_P0_TPB_P
FW_P0_TPB_N
FW_P1_TPA_P
FW_P1_TPA_N
FW_P1_TPB_P
FW_P1_TPB_N
35 37
35 37
35 37
35 37
35 37
35 37
35 37
35 37
D
Port 2 Not Used
y
r
a
n
i
m
il
e
r
FireWire Constraints
SYNC_MASTER=M98_MLB

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
105
123
SMC SMBus Net Properties

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
1TO1_DIFFPAIR
=STANDARD
=STANDARD
=STANDARD
=STANDARD
0.1 MM
0.1 MM
NET_TYPE
SPACING
PHYSICAL
SMBUS_SMC_A_S3_SCL
SMB_55S
SMB
SMBUS_SMC_A_S3_SDA
SMB_55S
SMB
SMBUS_SMC_B_S0_SCL
SMB_55S
SMB
SMBUS_SMC_B_S0_SDA
SMB_55S
SMB
SMBUS_SMC_0_S0_SCL
SMB_55S
SMB
SMBUS_SMC_0_S0_SDA
SMB_55S
SMB
SMBUS_SMC_BSA_SCL
SMB_55S
SMB
SMBUS_SMC_BSA_SDA
SMB_55S
SMB
SMBUS_SMC_MGMT_SCL
SMB_55S
SMB
SMBUS_SMC_MGMT_SDA
SMB_55S
SMB
SMBUS_SMC_A_S3_SCL
SMBUS_SMC_A_S3_SDA
SMBUS_SMC_B_S0_SCL
SMBUS_SMC_B_S0_SDA
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_BSA_SCL
SMBUS_SMC_BSA_SDA
SMBUS_SMC_MGMT_SCL
SMBUS_SMC_MGMT_SDA
7 44
7 44
44
44
44
44
7 44
7 44
44
y
r
SMBus Charger Net Properties

NET_TYPE
PHYSICAL
CHGR_CSI
1TO1_DIFFPAIR
1TO1_DIFFPAIR
CHGR_CSO
1TO1_DIFFPAIR
1TO1_DIFFPAIR
44
SPACING
CHGR_CSI_P
CHGR_CSI_N
60
60
CHGR_CSO_P
CHGR_CSO_N
60
60
a
n
i
m
il
e
r
SMC Constraints
SYNC_MASTER=M98_MLB

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
106
123
GDDR3 Frame Buffer Signal Constraints
GDDR3 FB A/B Net Properties
GDDR3 FB C/D Net Properties
PHYSICAL_RULE_SET
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
NET_TYPE
NET_TYPE
GDDR3_40R55SE
=55_OHM_SE
=40_OHM_SE
0.095 MM
12.7 MM
=STANDARD
=STANDARD
GDDR3_40SE
=40_OHM_SE
=40_OHM_SE
0.095 MM
=40_OHM_SE
=STANDARD
=STANDARD
PHYSICAL
SPACING
GDDR3_80D
GDDR3_CLK
FB_A_CLK_P<0>
71 72 79
GDDR3_80D
GDDR3_CLK
FB_A_CLK_N<0>
71 72 79
FB_A_CLK_P
FB_C_CLK_P
PHYSICAL
SPACING
GDDR3_80D
GDDR3_CLK
FB_B_CLK_P<0>
71 73 80
GDDR3_80D
GDDR3_CLK
FB_B_CLK_N<0>
71 73 80
GDDR3_80D
GDDR3_CLK
FB_B_CLK_P<1>
71 73 80
GDDR3_80D
GDDR3_CLK
FB_B_CLK_N<1>
71 73 80
GDDR3_CMD
FB_B_MA<1..0>
71 73 80
GDDR3_80D
=80_OHM_DIFF
=80_OHM_DIFF
0.095 MM
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
GDDR3_80D
GDDR3_CLK
FB_A_CLK_P<1>
71 72 79
GDDR3_80D
GDDR3_CLK
FB_A_CLK_N<1>
71 72 79
FB_AB_CMD
GDDR3_40R55SE
GDDR3_CMD
FB_A_MA<1..0>
71 72 79
FB_CD_CMD
GDDR3_40R55SE
FB_B_CLK_P
FB_D_CLK_P
FB_AB_CMD
GDDR3_40R55SE
GDDR3_CMD
FB_A_MA<12..6>
71 72 79
FB_CD_CMD
GDDR3_40R55SE
GDDR3_CMD
FB_B_MA<12..6>
7 71 73 80
FB_AB_CMD
GDDR3_40R55SE
GDDR3_CMD
FB_A_BA<2..0>
71 72 79
FB_CD_CMD
GDDR3_40R55SE
GDDR3_CMD
FB_B_BA<2..0>
7 71 73 80
FB_AB_CMD
GDDR3_40R55SE
GDDR3_CMD
FB_A_RAS_L
71 72 79
FB_CD_CMD
GDDR3_40R55SE
GDDR3_CMD
FB_B_RAS_L
71 73 80
FB_AB_CMD
GDDR3_40R55SE
GDDR3_CMD
FB_A_CAS_L
71 72 79
FB_CD_CMD
GDDR3_40R55SE
GDDR3_CMD
FB_B_CAS_L
7 71 73 80
71 72 79
FB_CD_CMD
71 73 80
71 73 80
SPACING_RULE_SET
LAYER
WEIGHT
GDDR3_CLK
=2.5:1_SPACING
?
GDDR3_CMD
=2.5:1_SPACING
GDDR3_DATA
=2.5:1_SPACING
FB_AB_CMD
GDDR3_40R55SE
GDDR3_CMD
FB_A_WE_L
FB_AB_CMD_PD
GDDR3_40R55SE
GDDR3_CMD
FB_A_CKE
71 72 79
FB_CD_CMD_PD
FB_AB_CS0
GDDR3_40R55SE
GDDR3_CMD
FB_A_CS0_L
71 72
FB_CD_CS0
FB_AB_CMD_PD
GDDR3_40R55SE
GDDR3_CMD
FB_A_DRAM_RST
71 72 79
FB_CD_CMD_PD
FB_A_CMD
GDDR3_40SE
GDDR3_CMD
FB_A_LMA<5..2>
71 72 79
FB_C_CMD
FB_B_CMD
GDDR3_40SE
GDDR3_CMD
FB_A_UMA<5..2>
71 72 79
FB_D_CMD
FB_A_WDQS0
GDDR3_40SE
GDDR3_DQS
FB_A_WDQS<0>
71 72 79
FB_C_WDQS0
FB_A_WDQS1
GDDR3_40SE
GDDR3_DQS
FB_A_WDQS<1>
71 72 79
FB_C_WDQS1
FB_A_WDQS2
GDDR3_40SE
GDDR3_DQS
FB_A_WDQS<2>
71 72 79
FB_C_WDQS2
FB_A_WDQS3
GDDR3_40SE
GDDR3_DQS
FB_A_WDQS<3>
71 72 79
FB_C_WDQS3
FB_A_RDQS0
GDDR3_40SE
GDDR3_DQS
FB_A_RDQS<0>
FB_A_RDQS1
GDDR3_40SE
GDDR3_DQS
FB_A_RDQS<1>
FB_A_RDQS2
GDDR3_40SE
GDDR3_DQS
FB_A_RDQS<2>
=2.5:1_SPACING
From T18 MXM:

Digital Video Signal Constraints
FB_A_RDQS3
GDDR3_40SE
GDDR3_DQS
FB_A_RDQS<3>
FB_A_DQ_BYTE0
GDDR3_40SE
GDDR3_DATA
FB_A_DQ<7..0>
FB_A_DQ_BYTE1
GDDR3_40SE
GDDR3_DATA
FB_A_DQ<15..8>
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
DP_100D
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
LVDS_100D
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
a
n
i
LAYER
WEIGHT
LAYER
WEIGHT
DISPLAYPORT
=3x_DIELECTRIC
LVDS
=3x_DIELECTRIC
DISPLAYPORT
TOP,BOTTOM
=4x_DIELECTRIC
LVDS
TOP,BOTTOM
=4x_DIELECTRIC
I204
MUXGFX Net Properties
FB_C_RDQS2
71 72 79
FB_C_RDQS3
7 71 72 79
FB_C_DQ_BYTE0
7 71 72 79
FB_C_DQ_BYTE1
7 71 73
GDDR3_40R55SE
GDDR3_CMD
FB_B_DRAM_RST
71 73 80
GDDR3_40SE
GDDR3_CMD
FB_B_LMA<5..2>
71 73 80
GDDR3_40SE
GDDR3_CMD
FB_B_UMA<5..2>
71 73 80
GDDR3_40SE
GDDR3_DQS
FB_B_WDQS<0>
71 73 80
GDDR3_40SE
GDDR3_DQS
FB_B_WDQS<1>
71 73 80
GDDR3_40SE
GDDR3_DQS
FB_B_WDQS<2>
71 73 80
GDDR3_40SE
GDDR3_DQS
FB_B_WDQS<3>
71 73 80
GDDR3_40SE
GDDR3_DQS
FB_B_RDQS<0>
71 73 80
GDDR3_40SE
GDDR3_DQS
FB_B_RDQS<1>
71 73 80
GDDR3_40SE
GDDR3_DQS
FB_B_RDQS<2>
71 73 80
GDDR3_40SE
GDDR3_DQS
FB_B_RDQS<3>
71 73 80
GDDR3_40SE
GDDR3_DATA
FB_B_DQ<7..0>
7 71 73 80
GDDR3_40SE
GDDR3_DATA
FB_B_DQ<15..8>
7 71 73 80
GDDR3_40SE
GDDR3_DATA
FB_B_DQ<23..16>
7 71 73 80
GDDR3_40SE
GDDR3_DATA
FB_B_DQ<31..24>
7 71 73 80
GDDR3_40SE
GDDR3_DATA
FB_B_DQM_L<0>
71 73 80
GDDR3_40SE
GDDR3_DATA
FB_B_DQM_L<1>
71 73 80
GDDR3_40SE
GDDR3_DATA
FB_B_DQM_L<2>
71 73 80
GDDR3_40SE
GDDR3_DATA
FB_B_DQM_L<3>
71 73 80
71 73 80
GDDR3_DATA
7 71 72 79
FB_C_DQ_BYTE2
GDDR3_40SE
GDDR3_DATA
FB_A_DQ<31..24>
7 71 72 79
FB_C_DQ_BYTE3
FB_A_DQM0
GDDR3_40SE
GDDR3_DATA
FB_A_DQM_L<0>
71 72 79
FB_C_DQM0
FB_A_DQM1
GDDR3_40SE
GDDR3_DATA
FB_A_DQM_L<1>
71 72 79
FB_C_DQM1
FB_A_DQM2
GDDR3_40SE
GDDR3_DATA
FB_A_DQM_L<2>
71 72 79
FB_C_DQM2
FB_A_DQM3
GDDR3_40SE
GDDR3_DATA
FB_A_DQM_L<3>
71 72 79
FB_C_DQM3
FB_B_WDQS0
GDDR3_40SE
GDDR3_DQS
FB_A_WDQS<4>
71 72 79
FB_D_WDQS0
GDDR3_40SE
GDDR3_DQS
FB_B_WDQS<4>
FB_B_WDQS1
GDDR3_40SE
GDDR3_DQS
FB_A_WDQS<5>
71 72 79
FB_D_WDQS1
GDDR3_40SE
GDDR3_DQS
FB_B_WDQS<5>
71 73 80
FB_B_WDQS2
GDDR3_40SE
GDDR3_DQS
FB_A_WDQS<6>
71 72 79
FB_D_WDQS2
GDDR3_40SE
GDDR3_DQS
FB_B_WDQS<6>
71 73 80
FB_B_WDQS3
GDDR3_40SE
GDDR3_DQS
FB_A_WDQS<7>
71 72 79
FB_D_WDQS3
GDDR3_40SE
GDDR3_DQS
FB_B_WDQS<7>
71 73 80
FB_B_RDQS0
GDDR3_40SE
GDDR3_DQS
FB_A_RDQS<4>
71 72 79
FB_D_RDQS0
GDDR3_40SE
GDDR3_DQS
FB_B_RDQS<4>
71 73 80
FB_B_RDQS1
GDDR3_40SE
GDDR3_DQS
FB_A_RDQS<5>
FB_B_RDQS2
GDDR3_40SE
GDDR3_DQS
FB_A_RDQS<6>
FB_B_RDQS3
GDDR3_40SE
GDDR3_DQS
FB_A_RDQS<7>
FB_B_DQ_BYTE0
GDDR3_40SE
GDDR3_DATA
FB_B_DQ_BYTE1
GDDR3_40SE
FB_B_DQ_BYTE2
GDDR3_40SE
FB_B_DQ_BYTE3
71 72 79
FB_D_RDQS1
GDDR3_40SE
GDDR3_DQS
FB_B_RDQS<5>
71 73 80
71 72 79
FB_D_RDQS2
GDDR3_40SE
GDDR3_DQS
FB_B_RDQS<6>
71 73 80
71 72 79
FB_D_RDQS3
GDDR3_40SE
GDDR3_DQS
FB_B_RDQS<7>
71 73 80
FB_A_DQ<39..32>
7 71 72 79
FB_D_DQ_BYTE0
GDDR3_40SE
GDDR3_DATA
FB_B_DQ<39..32>
7 71 73 80
GDDR3_DATA
FB_A_DQ<47..40>
7 71 72 79
FB_D_DQ_BYTE1
GDDR3_40SE
GDDR3_DATA
FB_B_DQ<47..40>
7 71 73 80
GDDR3_DATA
FB_A_DQ<55..48>
7 71 72 79
FB_D_DQ_BYTE2
GDDR3_40SE
GDDR3_DATA
FB_B_DQ<55..48>
7 71 73 80
GDDR3_40SE
GDDR3_DATA
FB_A_DQ<63..56>
7 71 72 79
FB_D_DQ_BYTE3
GDDR3_40SE
GDDR3_DATA
FB_B_DQ<63..56>
7 71 73 80
FB_B_DQM0
GDDR3_40SE
GDDR3_DATA
FB_A_DQM_L<4>
71 72 79
FB_D_DQM0
GDDR3_40SE
GDDR3_DATA
FB_B_DQM_L<4>
71 73 80
FB_B_DQM1
GDDR3_40SE
GDDR3_DATA
FB_A_DQM_L<5>
FB_B_DQM2
GDDR3_40SE
GDDR3_DATA
FB_A_DQM_L<6>
FB_B_DQM3
GDDR3_40SE
GDDR3_DATA
FB_A_DQM_L<7>
FB_AB_CS1
GDDR3_40R55SE
GDDR3_CMD
FB_A_CS1_L
71 79
LVDS intra-pair matching should be 5 mils. Pairs should be within 100 mils of clock length.
DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 150 ps.
DIsplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals.
Max length of LVDS/DisplayPort/TMDS traces: 12 inches.
71 72 79
FB_B_CS0_L
GDDR3_40SE
SPACING_RULE_SET
FB_C_RDQS1
FB_B_CKE
GDDR3_CMD
FB_A_DQ_BYTE3
SPACING_RULE_SET
71 72 79
GDDR3_CMD
GDDR3_40R55SE
FB_A_DQ_BYTE2
FB_C_RDQS0
GDDR3_40R55SE
FB_A_DQ<23..16>
PHYSICAL_RULE_SET
71 72 79
GDDR3_CMD
y
r
GDDR3_DQS
GDDR3_40R55SE
FB_B_WE_L
m
il
71 72 79
FB_D_DQM1
GDDR3_40SE
GDDR3_DATA
FB_B_DQM_L<5>
71 73 80
71 72 79
FB_D_DQM2
GDDR3_40SE
GDDR3_DATA
FB_B_DQM_L<6>
71 73 80
71 72 79
FB_D_DQM3
GDDR3_40SE
GDDR3_DATA
FB_B_DQM_L<7>
71 73 80
FB_CD_CS1
GDDR3_40R55SE
GDDR3_CMD
FB_B_CS1_L
71 80
I205
G96 Net Properties

NET_TYPE
NET_TYPE
PHYSICAL
SPACING
e
r
I148
I149
LVDS_A_CLK
LVDS_A_CLK
LVDS_100D
LVDS
LVDS_100D
LVDS
LVDS_A_CLK_P
81 84
LVDS_A_CLK_N
I199
LVDS_A_DATA
LVDS_100D
LVDS
LVDS_A_DATA_P<2..0>
I198
LVDS_A_DATA
LVDS_100D
LVDS
LVDS_A_DATA_N<2..0>
I152
LVDS_B_CLK
LVDS_100D
LVDS
LVDS_B_CLK_P
I153
LVDS_B_CLK
LVDS_100D
LVDS
LVDS_B_CLK_N
I201
LVDS_B_DATA
LVDS_100D
LVDS
LVDS_B_DATA_P<2..0>
I200
LVDS_B_DATA
LVDS_100D
LVDS
LVDS_B_DATA_N<2..0>
LVDS_100D
LVDS
LVDS_CONN_A_CLK_F_P
I182
LVDS_100D
LVDS
LVDS_CONN_A_CLK_F_N
I184
LVDS_100D
LVDS
LVDS_CONN_B_CLK_F_P
I185
LVDS_100D
LVDS
LVDS_CONN_B_CLK_F_N
I190
LVDS_100D
LVDS
LVDS_CONN_A_CLK_P
CLK_SLOW_55S
CLK_SLOW
GPU_CLK27M
75
CK505_CLK27MSS
CLK_SLOW_55S
CLK_SLOW
GPU_CLK27M_SS
75
LVDS_EG_A_CLK
LVDS_100D
LVDS
LVDS_EG_A_CLK_P
76 84
LVDS_EG_A_CLK
LVDS_100D
LVDS
LVDS_EG_A_CLK_N
76 84
LVDS_EG_A_DATA
LVDS_100D
LVDS
LVDS_EG_A_DATA_P<2..0>
76 84
LVDS_EG_A_DATA
LVDS_100D
LVDS
LVDS_EG_A_DATA_N<2..0>
7 76 84
7 81 84
LVDS_EG_B_DATA
LVDS_100D
LVDS
LVDS_EG_B_DATA_P<2..0>
76 84
81 84
LVDS_EG_B_DATA
LVDS_100D
LVDS
LVDS_EG_B_DATA_N<2..0>
76 84
I142
DP_ML
DP_100D
DISPLAYPORT
I144
DP_ML
DP_100D
DISPLAYPORT
7 78
I145
DP_AUX_CH
DP_100D
DISPLAYPORT
7 78
I143
DP_AUX_CH
DP_100D
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
7 81 84
7 81 84
7 81 84
7 81 84
7 78
I139
DP_100D
7 78
I138
DP_100D
I191
LVDS_100D
LVDS
I192
LVDS_100D
LVDS
LVDS_CONN_A_DATA_P<2..0>
I193
LVDS_100D
LVDS
LVDS_CONN_A_DATA_N<2..0>
I194
LVDS_100D
LVDS
LVDS_CONN_B_CLK_P
I195
LVDS_100D
LVDS
LVDS_CONN_B_CLK_N
I196
LVDS_100D
LVDS
LVDS_CONN_B_DATA_P<2..0>
7 78 81
I197
LVDS_100D
LVDS
LVDS_CONN_B_DATA_N<2..0>
7 78 81
DP_ML
I160
I155
DP_ML
I157
I202
DP_ML
I203
DP_100D
DISPLAYPORT
DP_100D
DISPLAYPORT
DP_100D
DISPLAYPORT
DP_100D
DISPLAYPORT
DP_100D
DISPLAYPORT
DP_100D
DISPLAYPORT
DP_ML_C_P<3..0>
DP_ML_C_N<3..0>
DP_ML_P<3..0>
DP_ML_N<3..0>
DP_ML_CONN_P<3..0>
DP_ML_CONN_N<3..0>
DP_EG_ML_P<3..0>
DP_EG_ML_N<3..0>
DP_EG_AUX_CH_P
DP_EG_AUX_CH_N
DP_EG_AUX_CH_C_P
DP_EG_AUX_CH_C_N
76 81
76 81
76 81
76 81
81
81
78 81
LVDS_CONN_A_CLK_N
I161
SPACING
(CK505_DOT96)
81 84
I183
PHYSICAL
78 81
7 78 81
7 78 81
78 81
78 81
GPU (G96) Constraints

SYNC_MASTER=M98_MLB
82
82
81 82

81 82
82
82

I159
DP_AUX_CH
DP_100D
DISPLAYPORT
I158
DP_AUX_CH
DP_100D
DISPLAYPORT
DP_AUX_CH_C_P
DP_AUX_CH_C_N
SIZE
81 82
DRAWING NUMBER
81 82
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
107
123
PHYSICAL_RULE_SET
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
5
M99 Specific Net Properties
M99 Specific Net Properties

NET_TYPE
NET_TYPE
SENSE_1TO1_55S
=55_OHM_SE
=1:1_DIFFPAIR
=55_OHM_SE
=55_OHM_SE
=1:1_DIFFPAIR
=1:1_DIFFPAIR
SPACING
PHYSICAL
THERM_1TO1_55S
=55_OHM_SE
=1:1_DIFFPAIR
=55_OHM_SE
=55_OHM_SE
=1:1_DIFFPAIR
ENET_MDI_100D
ENETCONN
ENETCONN_P<3..0>
34
ENET_MDI_100D
ENETCONN
ENETCONN_N<3..0>
34
I146
SATA_100D
SATA
SATA_ODD_R2D_UF_P
38
I145
SATA_100D
SATA
SATA_ODD_R2D_UF_N
38
I144
SATA_100D
SATA
SATA_ODD_D2R_UF_P
38
I142
SATA_100D
SATA
SATA_ODD_D2R_UF_N
38
SATA
SATA_HDD_D2R_UF_P
38
PHYSICAL
SPACING
=1:1_DIFFPAIR
DIFFPAIR
=1:1_DIFFPAIR
=1:1_DIFFPAIR
=1:1_DIFFPAIR
=1:1_DIFFPAIR
NET_SPACING_TYPE1
SPACING_RULE_SET
LAYER
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
WEIGHT
SENSE
=2:1_SPACING
THERM
=2:1_SPACING
CLK_FSB
GND
SATA_100D
I143
GND_P2MM
SATA_100D
I140
CPU_COMP
GND
GND_P2MM
CPU_GTLREF
GND
GND_P2MM
CPU_VCCSENSE
GND
GND_P2MM
AUDIO
SATA
I141
SATA_100D
SATA
I139
SATA_100D
SATA
SATA_HDD_D2R_UF_N
SATA_HDD_R2D_UF_P
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
I168
1TO1_DIFFPAIR
I166
1TO1_DIFFPAIR
I167
1TO1_DIFFPAIR
I165
1TO1_DIFFPAIR
38
SENSE_1TO1_55S
SENSE
MCPCOREISNS_P
46 64
SENSE_1TO1_55S
SENSE
MCPCOREISNS_N
46 64
THERM_1TO1_55S
THERM
CPUTHMSNS_D2_P
47
I182
(USB_EXTA)
I181
(USB_EXTA)
I179
(USB_EXTA)
I180
(USB_EXTA)
I177
(USB_EXTD)
I178
(USB_EXTD)
I176
(USB_CAMERA)
I175
(USB_CAMERA)
FSB_DSTB
FSB_DSTB
GND_P2MM
SPACING_RULE_SET
LAYER
I124
WEIGHT
CPUTHMSNS_D2_DP
ENETCONN
25 MILS
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
ENET_MDI
GND
GND_P2MM
I125
I127
SPACING_RULE_SET
LAYER
I128
WEIGHT
GND
=STANDARD
PP1V8_MEM
=STANDARD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
CLK_PCIE
GND
GND_P2MM
I129
I138
PCIE
GND
GND_P2MM
SATA
GND
GND_P2MM
GPU_THERMD_DP
WEIGHT
MCPTHMSNS_D_DP
I135
CPUTHMSNS_D2_N
47
THERM_1TO1_55S
THERM
CPU_THERMD_P
10 47
THERM_1TO1_55S
THERM
CPU_THERMD_N
10 47
MCP_THERMD_DP
THERM
0.20 MM
47
THERM_1TO1_55S
THERM
GPU_TDIODE_P
47 75
THERM_1TO1_55S
THERM
GPU_TDIODE_N
THERM
USB
GND
GND_P2MM
I156
PWR_P2MM
0.20 MM
1000
I157
CLK_PCIE
SB_POWER
PWR_P2MM
SATA
SB_POWER
PWR_P2MM
I155
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
I153
GND
USB
SB_POWER
THERM
MCPTHMSNS_D_N
THERM_1TO1_55S
THERM
MCP_THMDIODE_P
I152
I151
GND
GND_P2MM
MEM_CTRL
GND
GND_P2MM
SENSE_DIFFPAIR
I149
SENSE_DIFFPAIR
MEM_DATA
GND
I148
GND_P2MM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
I158
MEM_DQS
GND
SENSE_DIFFPAIR
GND_P2MM
I147
GND
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
LVDS
SENSE
SENSE_1TO1_55S
I150
SENSE_DIFFPAIR
SENSE_1TO1_55S
PWR_P2MM
GND_P2MM
MEM_CMD
SENSE_DIFFPAIR
I154
SPACING_RULE_SET
MEM_CLK
SENSE_DIFFPAIR
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
GND_P2MM
I186
SENSE_DIFFPAIR
I185
MCP_THMDIODE_N
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
OVERRIDE
OVERRIDE
0.09 MM
OVERRIDE
OVERRIDE
DIFFPAIR NECK GAP
GND
OVERRIDE
OVERRIDE
GND
OVERRIDE
OVERRIDE
MEM_70D
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
0.09 MM
100 MIL
OVERRIDE
OVERRIDE
0.09 MM
100 MIL
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
I131
SENSE_DIFFPAIR
MEM_70D_VDD
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
0.09 MM
100 MIL
OVERRIDE
OVERRIDE
I132
OVERRIDE
OVERRIDE
I134
SENSE_DIFFPAIR
PCIE_90D
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
0.09 MM
100 MIL
OVERRIDE
OVERRIDE
I133
OVERRIDE
OVERRIDE
USB_90D
TOP
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
0.1 MM
500 MIL
OVERRIDE
OVERRIDE
OVERRIDE
MCP_DV_COMP
TOP
OVERRIDE
OVERRIDE
TOP
OVERRIDE
OVERRIDE
0.1 MM
500 MIL
OVERRIDE
OVERRIDE
0.1 MM
500 MIL
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
MCP_MII_COMP
TOP
OVERRIDE
OVERRIDE
0.1 MM
500 MIL
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
0.1 MM
500 MIL
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
MCP_USB_RBIAS
TOP
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
MCP_DV_COMP
OVERRIDE
OVERRIDE
0.25 MM
250 MIL
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
0.23 MM
100 MIL
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
CPU_27P4S
BOTTOM
OVERRIDE
OVERRIDE
PHYSICAL_RULE_SET
LAYER
MEM_40S
ISL4,ISL9
OVERRIDE
OVERRIDE
MEM_40S_VDD
ISL3,ISL10
OVERRIDE
OVERRIDE
MEM_70D
ISL4,ISL9
OVERRIDE
OVERRIDE
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
MEM_70D_VDD
ISL3,ISL10
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
P
OVERRIDE
OVERRIDE
MAXIMUM NECK LENGTH
OVERRIDE
OVERRIDE
OVERRIDE
Alternate diffpair width/gap through BGA fanout areas (95-ohm diff)

TABLE_PHYSICAL_ASSIGNMENT_HEAD
NET_PHYSICAL_TYPE
AREA_TYPE
PHYSICAL_RULE_SET
LVDS_100D
BGA
100_DIFF_BGA
DP_100D
BGA
100_DIFF_BGA
SATA_100D
BGA
100_DIFF_BGA
TABLE_PHYSICAL_ASSIGNMENT_ITEM
I170
I183
21 47
I184
46
I187
MCP_PE4_REFCLK
46
I188
46
I189
PCIE_FC_R2D
46
I190
46
I191
PCIE_FC_D2R
46
I192
46 65
I193
46 65
I194
46
I195
SPK_OUT
P1V8GPUISNS_R_N
FLSH_55S
ASIC_CNTRLMEM1
FLSH_55S
I242
ASIC_CNTRLMEM1
FLSH_55S
I241
ASIC_CNTRLMEM1
FLSH_55S
I239
ASIC_CNTRLMEM2
FLSH_55S
I240
ASIC_CNTRLMEM2
FLSH_55S
I238
ASIC_CNTRLMEM2
FLSH_55S
I237
ASIC_CNTRLMEM2
FLSH_55S
I236
ASIC_CNTRLMEM2
FLSH_55S
I235
ASIC_CNTRLMEM2
FLSH_55S
I234
ASIC_CNTRLMEM3
FLSH_55S
I233
ASIC_CNTRLMEM3
FLSH_55S
I232
ASIC_CNTRLMEM3
FLSH_55S
I231
ASIC_CNTRLMEM3
FLSH_55S
I230
ASIC_CNTRLMEM3
FLSH_55S
I229
ASIC_CNTRLMEM3
FLSH_55S
I228
ASIC_CNTRLMEM2
FLSH_55S
I227
ASIC_CNTRLMEM2
FLSH_55S
I226
ASIC_CNTRLMEM2
FLSH_55S
I225
ASIC_CNTRLMEM2
FLSH_55S
I224
ASIC_CNTRLMEM2
FLSH_55S
I223
ASIC_CNTRLMEM2
FLSH_55S
NF_CLE_R
NF_ALE_R
NF_CE0_L_R
NF_CE1_L_R
NF_RE0_L_R
NF_WE0_L_R
NF_CLE_R
NF_ALE_R
NF_CE0_L_R
NF_CE1_L_R
NF_RE0_L_R
NF_WE0_L_R
NF_CLE
NF_ALE
NF_CE0_L
NF_CE1_L
NF_RE0_L
NF_WE0_L
USB
USB2_EXTA_MUXED_P
39
USB
USB2_EXTA_MUXED_N
39
USB_90D
USB
USB_90D
USB
USB2_LT1_P
USB2_LT1_N
USB_90D
USB
CONN_TPAD_USB_P
USB_90D
USB
CONN_TPAD_USB_N
USB_90D
USB
USB_CAMERA_CONN_P
7 30
USB_90D
USB
USB_CAMERA_CONN_N
7 30
USB_90D
USB
CONN_USB2_BT_P
7 30
USB_90D
USB
CONN_USB2_BT_N
7 30
7 39
SPK_OUT
USB
USB_90D
USB
USB_90D
USB
USB2_EXCARD_CONN_P
7 31
USB
USB2_EXCARD_CONN_N
7 31
USB_90D
DP_100D
DP_100D
DISPLAYPORT
DISPLAYPORT
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
DIFFPAIR
AUDIO
DIFFPAIR
AUDIO
DIFFPAIR
AUDIO
DIFFPAIR
AUDIO
DIFFPAIR
AUDIO
DIFFPAIR
AUDIO
DIFFPAIR
AUDIO
DIFFPAIR
AUDIO
45
SPK_OUT
I206
7 8
I207
7 8 9
I247
SPK_OUT
SPK_OUT
PHYSICAL_RULE_SET
LAYER
FLSH_55S
DIFFPAIR
AUDIO
DIFFPAIR
AUDIO
46
I210
USB_90D
USB
USB_EXTC_P
46
I209
USB_90D
USB
USB_EXTC_N
I212
USB_90D
USB
I211
USB_90D
USB
MEM_70D
BOTTOM
MINIMUM LINE WIDTH
7 56 57
7 56 57
7 56 57
7 56 57
7 56 57
7 56 57
7 56 57
7 56 57
7 56 57
20 91 98
20 91 98
7 98
7 98
96
96
96
96
96
96
96
96
96
96
96
96
96
96
96
96
OVERRIDE
OVERRIDE
NF_CLE
NF_ALE
NF_CE0_L
NF_CE1_L
NF_RE0_L
NF_WE0_L
96
96
96
96
96
96
Project Specific Constraints

SYNC_MASTER=M98_MLB
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD

MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
0.127 MM
6.35 MM
SIZE
DIFFPAIR NECK GAP
DRAWING NUMBER
APPLE INC.
REV.
051-7656
SCALE
SHT
NONE
7 31
7 31
7 56 57
96
ALLOW ROUTE
ON LAYER?
81
96
Allow 0.127 mm necks for >0.127 mm lines for GMCH fanout.

LAYER
81
USB_LT3_P
USB_LT3_N
Memory Constraint Relaxations

PHYSICAL_RULE_SET
7 39
DP_IG_AUX_CH_C_P
DP_IG_AUX_CH_C_N
PCIE_CLK100M_FC_P
PCIE_CLK100M_FC_N
PCIE_FC_R2D_C_P
PCIE_FC_R2D_C_N
PCIE_FC_D2R_P
PCIE_FC_D2R_N
PCIE_FC_R2D_P
PCIE_FC_R2D_N
SPKRAMP_L1_OUT_P
SPKRAMP_L1_OUT_N
SPKRAMP_L2_OUT_P
SPKRAMP_L2_OUT_N
SPKRAMP_R1_OUT_P
SPKRAMP_R1_OUT_N
SPKRAMP_R2_OUT_P
SPKRAMP_R2_OUT_N
SPKRAMP_LFE_OUT_P
SPKRAMP_LFE_OUT_N
I248
FLASH MEMORY BUS CONSTRAINTS
7 39
USB_90D
45
I201
7 39
USB_LT2_P
USB_LT2_N
46
I197
45 60
USB_90D
46
I198
45 60
USB_90D
46
I196
60
Ground-referenced memory signals (DQ,DQM,DQS) MAY route on ISL9 (VDD-referenced plane)but not next to VDD island.
Forces power-referenced memory signals (CLK,ADDR,CTRL) to not route on ISL3, ISL4 & ISL10(GND-referenced planes).
Graphics ,SATA Constraint Relaxations
P1V8GPUISNS_R_P
SENSE
ASIC_CNTRLMEM1
OVERRIDE
P1V8GPUISNS_N
SENSE
SENSE_1TO1_55S
I243
OVERRIDE
SENSE
SENSE_1TO1_55S
I244
DIFFPAIR NECK GAP
OVERRIDE
SENSE_1TO1_55S
FLSH_55S
OVERRIDE
P1V8GPUISNS_P
FLSH_55S
PP3V3_S0
PP1V5_S0
ASIC_CNTRLMEM1
SB_POWER
SENSE
ASIC_CNTRLMEM1
e
r
OVERRIDE
PP3V3_S5
SB_POWER
I246
OVERRIDE
SB_POWER
SENSE_1TO1_55S
I245
OVERRIDE
MCP_MEM_COMP
7 47
21 47
I199
m
il
OVERRIDE
MEM_40S_VDD
I169
I202
100 MIL
OVERRIDE
7 47
I200
MEM_40S
I171
1V05CPUISNS_R_P
1V05CPUISNS_R_N
DDRISNS_R_P
DDRISNS_R_N
GPUISENS_P
GPUISENS_N
1V05CPU_P
1V05CPU_N
DDRISNS_P
DDRISNS_N
P1V8GPU_P
P1V8GPU_N
ISNS_CPU_P
ISNS_CPU_N
PHYSICAL_RULE_SET
I173
a
n
i
MCPTHMSNS_D_P
THERM_1TO1_55S
THERM
I172
47 75
7 30
60
y
r
I174
GPUTHMSNS_D_N
THERM_1TO1_55S
I136
1000
47
THERM
GND_P2MM
GPUTHMSNS_D_P
THERM_1TO1_55S
THERM_1TO1_55S
I137
LAYER
THERM
THERM_1TO1_55S
SPACING_RULE_SET
GPUTHMSNS_D_DP
I130
CPU_THERMD_DP
I126
THERM_1TO1_55S
7 30
CHGR_CSI_R_P
CHGR_CSI_R_N
CHGR_CSO_R_P
CHGR_CSO_R_N
38
SATA_HDD_R2D_UF_N
SENSE_DIFFPAIR
CLK_PCIE_100D
I159
38
=2:1_SPACING
I160
31
OF
108
123
M99 Board-Specific Spacing & Physical Constraints

TABLE_BOARD_INFO
BOARD LAYERS
BOARD AREAS
BOARD UNITS
(MIL or MM)
ALLEGRO
VERSION
TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM
NO_TYPE,BGA
MM
15.5.1
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
SPACING_RULE_SET
LAYER
WEIGHT
DEFAULT
=50_OHM_SE
=50_OHM_SE
10 MM
0 MM
0 MM
DEFAULT
0.1 MM
=DEFAULT
=DEFAULT
10 MM
=DEFAULT
=DEFAULT
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
BGA
BGA_P1MM
MEM_CLK
BGA
BGA_P2MM
CLK_FSB
BGA
BGA_P2MM
CLK_PCIE
BGA
BGA_P2MM
CLK_SLOW
BGA
BGA_P2MM
FSB_DSTB
FSB_DSTB
BGA
BGA_P3MM
STANDARD
NET_SPACING_TYPE1
STANDARD
=DEFAULT
BGA_P1MM
=DEFAULT
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
55_OHM_SE
TOP,BOTTOM
0.090 MM
0.090 MM
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
BGA_P2MM
=DEFAULT
BGA_P3MM
=DEFAULT
WEIGHT
y
r
55_OHM_SE
0.076 MM
0.076 MM
=STANDARD
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
TOP,BOTTOM
0.15 MM
1.8:1_SPACING
0.18 MM
NOTE:From T18 MLB, changed to reflect M99 stackup.
50_OHM_SE
1.5:1_SPACING
DIFFPAIR NECK GAP
0.110 MM
SPACING_RULE_SET
LAYER
WEIGHT
0.095 MM
50_OHM_SE
0.090 MM
0.090 MM
=STANDARD
=STANDARD
2:1_SPACING
0.2 MM
2X_DIELECTRIC
0.140 MM
3X_DIELECTRIC
0.210 MM
0.280 MM
=STANDARD
2.5:1_SPACING
0.25 MM
3:1_SPACING
0.3 MM
4:1_SPACING
0.4 MM
4X_DIELECTRIC
a
n
i
5X_DIELECTRIC
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
40_OHM_SE
TOP,BOTTOM
0.165 MM
0.095 MM
40_OHM_SE
0.135 MM
0.135 MM
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
27P4_OHM_SE
TOP,BOTTOM
0.310 MM
0.095 MM
27P4_OHM_SE
0.250 MM
0.250 MM
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
70_OHM_DIFF
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

ISL3,ISL4
0.160 MM
0.160 MM
0.175 MM
0.175 MM
ISL9,ISL10
0.160 MM
0.160 MM
0.175 MM
0.175 MM
70_OHM_DIFF
ISL2,ISL11
0.170 MM
0.170 MM
0.150 MM
0.150 MM
70_OHM_DIFF
TOP,BOTTOM
0.170 MM
0.095 MM
0.150 MM
0.150 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
80_OHM_DIFF
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
80_OHM_DIFF
ISL3,ISL4
0.125 MM
0.125 MM
0.180 MM
0.180 MM
80_OHM_DIFF
ISL9,ISL10
0.125 MM
0.125 MM
0.180 MM
0.180 MM
80_OHM_DIFF
ISL2,ISL11
0.140 MM
0.140 MM
0.190 MM
80_OHM_DIFF
TOP,BOTTOM
0.140 MM
0.095 MM
0.190 MM
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
=STANDARD
=STANDARD
=STANDARD
0.1 MM
0.1 MM
m
il
e
r
0.190 MM
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
90_OHM_DIFF
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
90_OHM_DIFF
ISL3,ISL4
0.102 MM
0.102 MM
0.220 MM
0.220 MM
90_OHM_DIFF
ISL9,ISL10
0.102 MM
0.102 MM
90_OHM_DIFF
ISL2,ISL11
0.115 MM
0.115 MM
90_OHM_DIFF
TOP,BOTTOM
0.115 MM
0.095 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
100_OHM_DIFF
ISL3,ISL4
100_OHM_DIFF
ISL9,ISL10
100_OHM_DIFF
ISL2,ISL11
100_OHM_DIFF
TOP,BOTTOM
=STANDARD
=STANDARD
0.080 MM
0.080 MM
0.080 MM
0.080 MM
0.089 MM
0.089 MM
0.089 MM
0.089 MM
0.230 MM
0.230 MM
MAXIMUM NECK LENGTH

=STANDARD

=STANDARD
0.200 MM
0.200 MM
0.220 MM
0.220 MM
LAYER
100_OHM_DIFF
0.190 MM
PHYSICAL_RULE_SET
0.220 MM
LAYER
1:1_DIFFPAIR
70_OHM_DIFF
0.350 MM
PHYSICAL_RULE_SET
70_OHM_DIFF
0.220 MM
0.230 MM
0.230 MM
DIFFPAIR NECK GAP
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
100_DIFF_BGA
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
100_DIFF_BGA
ISL3,ISL4
0.075 MM
0.075 MM
0.125 MM
0.125 MM
100_DIFF_BGA
ISL9,ISL10
0.075 MM
0.075 MM
0.125 MM
0.125 MM
=STANDARD
0.200 MM
0.200 MM
PCB Rule Definitions
SYNC_MASTER=M98_MLB
NOTE: 100_DIFF_BGA is 100-ohms differential impedance on outer layers and 95-ohms on inner layers.
0.220 MM
0.220 MM

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
110_OHM_DIFF
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD


110_OHM_DIFF
ISL3,ISL4
0.077 MM
0.077 MM
0.330 MM
0.330 MM
110_OHM_DIFF
ISL9,ISL10
0.077 MM
0.077 MM
0.330 MM
0.330 MM
110_OHM_DIFF
ISL2,ISL11
0.077 MM
0.077 MM
0.330 MM
0.330 MM
SIZE
APPLE INC.
110_OHM_DIFF
TOP,BOTTOM
0.077 MM
0.077 MM
0.330 MM
DRAWING NUMBER
SCALE
SHT
0.330 MM
NONE
REV.
051-7656
31
OF
109
123
Port Power Switch
LEFT USB PORT C
ENABLE TIED LOW SO INPUT POWER SOURCE MUST BE S3!!!

CRITICAL
CRITICAL
LC325
UC380
FERR-220-OHM-2.5A
TPS2068
39 8
=PP5V_S3_RTUSB
OUT1 6
IN1
PP5V_S3_RTUSB_C_ILIM
VOLTAGE=5V
MSOP
IN2
CC325
OUT2 7
20
OUT
USB_EXTC_OC_L
CC380
10UF
20%
6.3V
X5R
603
CC381
0.1UF
20%
10V
CERM
402
20%
16V
CERM
402
OUT3 8
GND
TPAD
PP5V_S3_RTUSB_C_F
VOLTAGE=5V
CRITICAL
USB
CRITICAL
2
F-RT-TH-M97-3
5
LC320
y
r
90-OHM-100MA
DLP11S
SYM_VER-1
CRITICAL
CC385
10UF
20%
6.3V
X5R
603
96 7
USB_LT3_N
96 7
USB_LT3_P
OMIT
1
2
CC386
100UF
20%
2 6.3V
POLY-TANT
CASE-B2-SM
JC320
0.01uF
OC*
EN*
2
0603
3
4
6 VBUS
NC
IO
NC
IO
1 GND
96 91 20
BI
96 91 20
BI
a
n
i
USB_EXTC_N
USB_EXTC_P
DC320
RCLAMP0502N
SLP1210N6
CRITICAL
PLACE LC320 AND LC325 AT CONNECTOR PIN
PART NUMBER
514-0638
QTY
1
DESCRIPTION
CONN,RCPT,USB,HB,4P
REFERENCE DES
JC320
CRITICAL
BOM OPTION
CRITICAL
m
il
e
r
PROJECT SPECIFIC CONNS

SYNC_MASTER=N/A
SYNC_DATE=N/A

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7656
31
OF
123
123

Apple Macbook Pro A1297 Cannaregio k20 Dvt1 051-7656 Rev31

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8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

System Block Diagram

Power Block Diagram

JTAG Scan Chain

Functional / ICT Test

CPU Power & Ground

CPU Decoupling & VID

eXtended Debug Port(MiniXDP)

MCP CPU Interface

MCP Memory Interface

MCP Memory Misc

MCP PCIe Interfaces

MCP Ethernet & Graphics

MCP PCI & LPC

MCP SATA & USB

MCP HDA & MISC

MCP Power & Ground

MCP Standard Decoupling

MCP Graphics Support

FSB/DDR3/FRAMEBUF Vref Margining

DDR3 SO-DIMM Connector A

DDR3 SO-DIMM Connector B

Right Clutch Connector

Ethernet PHY (RTL8211CL)

Ethernet & AirPort Support

FireWire LLC/PHY (FW643)

FireWire Port Power

External USB Connectors

Front Flex Support

LPC+SPI Debug Connector

K20 SMBUS CONNECTIONS

Current & Voltage Sensing

Sudden Motion Sensor (SMS)

AUDIO: HEADPHONE AMP

AUDIO: JACK TRANSLATORS

DC-In & Battery Connectors

GPU (G96) Constraints

Project Specific Constraints

PCB Rule Definitions

PROJECT SPECIFIC CONNS

PBus Supply & Battery Charger

IMVP6 CPU VCore Regulator

5V / 3.3V Power Supply

1.5V DDR3 Supply

5V_S0 / MCP CORE REGULATOR

CPU VTT Power Supply

Misc Power Supplies

NV G96 CORE/FB POWER

NV G96 FRAME BUFFER I/F

GDDR3 Frame Buffer A (Bottom)

GDDR3 Frame Buffer B (Bottom)

G96 GPIOs & Straps

NV G96 Video Interfaces

GPU (G96) CORE SUPPLY

LVDS Display Connector

GDDR3 Frame Buffer A (Top)

GDDR3 Frame Buffer B (Top)