Low Power LO Generation Based on Frequency Multiplication Technique

A Thesis Submitted for the Degree of

Master of Science (Engineering) in the Faculty of Engineering

by

Jagdish Narayan Pandey

Electrical Communication Engineering Indian Institute of Science, Bangalore Bangalore 560 012 (INDIA) July, 2007

i I, hereby declare that the work reported in this thesis has been carried out in the Circuits and Systems Lab, Department of Electrical Communication Engineering, Indian Institute of Science, Bangalore under the supervision of Dr. Bharadwaj Amrutur. I also declare that this work has not formed the basis for the award of any Degree, Diploma, Fellowship, Associateship or similar title of any University or Institution.

Jagdish Narayan Pandey, Circuits and Systems Lab, Department of Electrical Communication Engineering, Indian Institute of Science, Bangalore-560 012, INDIA. July 2007.

Abstract

O achieve high level of integration in order to reduce cost, heterodyne architecture has made way for low-IF and zero-IF (direct conversion) receiver ar-

chitectures. However, a very serious issue in implementing both zero and low-IF receiver is of local oscillator (LO) pulling. Another challenge is on-chip generation of high-precision quadrature LO signals for image-rejection. We have addressed both these issues in this thesis. Regarding the rst problem, we have developed a lowpower frequency multiplication technique which uses a low frequency ring oscillator and multiplies its frequency in power ecient way to generate the desired frequency. We then use this dierential LO signal to generate high-precision quadrature phases by using polyphase lter and an injection-locked quadrature oscillator. Design examples are presented for 2.4 GHz band of IEEE 802.15.4 standard which is a low-data rate WPAN standard. The standard oers relaxed performance specications in order to help achieve low power of operation.

Contributions in the thesis

The problem of local oscillator (LO) pulling can be addressed by running LO at a much reduced frequency and use a frequency multiplier (FM) to generate the desired frequency. Also, use of low-frequency LO saves power in VCO and helps eliminate rst few dividers leading to signicant power savings. In addition, the entire frequency synthesizer can be run at a lower supply voltage saving additional power. The frequency multiplier involves combining edges from the lower frequency

ii

Abstract

iii

ring oscillator. It improves upon the prior work by proposing a new lower-power edge-combiner. The overall power is reduced by exploiting the relaxed phase noise specication of IEEE 802.15.4 standard. Simulations using SpectreRF show that the circuit consumes only 550 W of power in 0.13 m RF-CMOS technology with 1.2 V supply voltage, and provides 950 VPP sinusoidal output with phase noise of -85.5 dBc/Hz at 1 MHz oset. An injection-locking based quadrature desensitization circuit is designed for precision quadrature generation. The dierential (two phase) output of the frequency multiplier is fed to a polyphase lter to generate nearly quadrature signals. Output of polyphase lter is in turn fed to the desensitizer circuit to obtain high-precision quadrature signals. Designed for 2.4 GHz band in 0.13 m RF-CMOS technology, it achieves a phase error of 0.5 for 1% mismatch in LC tanks. It achieves a phase noise of -84.3 dBc/Hz at 1 MHz oset and provides quadrature sinusoids of 475 mV amplitude while consuming 1.56 mW of power. We have analyzed the popular cross-coupled LC-VCOs to generate quadrature sinusoids. In practical LC-oscillators built using low/moderate quality factor on chip inductors, the actual frequency of oscillation is a little less than 1/2 LC. This is known as Groszkowski eect. On the other hand, in quadrature oscillator topologies, consisting of two, cross-coupled, negative resistance LC-VCOs using parallel coupling transistors, an upward shift in frequency of oscillation from the free-running frequency of each LC-VCO is observed. This is because in order to satisfy the Barkhausens criteria, the LC-tanks have to operate at a frequency away from the frequency of resonance. This eect called as quadrature detuning eect results in higher phase noise and reduced amplitude. We have shown that the old treatment given in literature is quite inaccurate for practical LC oscillators that are built using low/moderate Q on-chip inductors. Also the prior work ignores Groszkowski eect which could be signicant for low

Abstract

iv

Q LC tanks. We have provided simple, accurate and closed-form expressions of associated frequency-shifts and amplitude of oscillation including both the eects. Our results show excellent match with results obtained from SpectreRF and Matlab simulations.

List of Publications
1. J. N. Pandey, Sudhir Kudva and Bharadwaj Amrutur, A low-power frequency multiplication technique for ZigBee transceiver, IEEE Int. Conf. on VLSI Design, Jan 2007 Submitted and in preparation 1. J. N. Pandey, Sudhir Kudva and Bharadwaj Amrutur, A low power GHzrange frequency multiplier for low-data date applications Submitted to IEEE Transactions on circuits and systems-I 2. J. N. Pandey and Bharadwaj Amrutur, On frequency shifts in cross-coupled LC-VCOs Submitted to IEEE Transactions on Circuits and Systems-II 3. J. N. Pandey and Bharadwaj Amrutur, Comparison of quadrature generation methods for frequency multiplication based oscillators In preparation

To Shri Ram

Acknowledgement
I would like to thank my advisor Dr. Bharadwaj Amrutur for encouraging me to do creative research, his invaluable guidance and for his patience with me. His wisdom will continue to be the guiding light for me in years to come. I profusely thank Dr. Shantanu Mahapatra for being examiner in my Comprehensive Exam. I thank Dr. Navakanta Bhat for teaching me the fundamentals of CMOS Analog Circuits through his course. Thanks are also due to Dr. K. J. Vinoy for his useful comments on the testing of our chip and lending the equipment. I thank Dr. Shanthi Pavan and Dr. Nagendra Krishnapura at IIT Madras for teaching a wonderful short course on RF Circuit Design. Special thanks are due to Sudhir Kudva and Raghavendra R.G. whose generosity and patience with me knew no limits. Sincere thanks to Cadence India for Cadence licenses and Ms. J. Vedavalli for taking care of software issues. Life would have been tougher without the support of two great friends: Vishal Saxena and Satyam Dwivedi. I would also like to single out Basavraj Talwar and Pratap Kumar Das for helping me in a hundred dierent ways. Thanks are due aplenty to Madhusudan, Rakesh, Balaji, Vijay, Anmol, Harish, Deepak, Venkatesh, Chaitanya, Arvind, Fazeel, Reddy, Kannan and Janakiraman for being such a good company.

vi

Contents
Abstract ii v Acknowledgement 1 Introduction 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Background 2.1 Introduction . . . . . . . . . . . . . . . . . 2.1.1 Maximum Transmit Power . . . . . 2.1.2 Receiver jamming resistance . . . . 2.1.3 Eect of local oscillator phase noise References . . . . . . . . . . . . . . . . . . vi 1 1 6

7 . . . . . . . . . . . . . . . 7 . . . . . . . . . . . . . . . 10 . . . . . . . . . . . . . . . 10 on receiver and transmitter 10 . . . . . . . . . . . . . . . 14 Low-Data Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 15 18 21 25 31 31 32 34 35 36 38 40 42

3 A Low Power GHz-Range Frequency Multiplier for Applications 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . 3.2 Frequency Multiplication by Edge-Combining . . . . 3.3 A new method of edge-combining . . . . . . . . . . . 3.3.1 Dierential Operation . . . . . . . . . . . . . 3.4 Discussions . . . . . . . . . . . . . . . . . . . . . . . 3.4.1 Eect of ground bounce . . . . . . . . . . . . 3.4.2 Eect of mismatches in the ring oscillator . . 3.4.3 Choice of multiplication number, M . . . . . . 3.4.4 Voltage scaling . . . . . . . . . . . . . . . . . 3.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . .

4 Layout Issues 4.1 Simulation of layout extracted netlist . . . . . . . . . . . . . . . . . .

vii

Contents

viii

5 Quadrature Generation Methods For Frequency Multiplication Based Oscillators 44 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.2 Quadrature Frequency Multiplication Using Even-Stage Ring Oscillator 46 5.2.1 Combining Current Pulses . . . . . . . . . . . . . . . . . . . . 46 5.3 Quadrature generation based on poly-phase lters . . . . . . . . . . . 50 5.4 High-precision quadrature generation based on injection-locking . . . 55 5.4.1 Injection-locking as a desensitizer for I-Q imbalance . . . . . . 55 5.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6 On 6.1 6.2 6.3 Frequency Shifts in Cross-Coupled LC-VCOs Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Behavioral modeling of LC-oscillators and Groszkowski Eect . . . . Behavioral modeling of cross-coupled LC-VCOs and Quadrature Detuning Eect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.1 Treatment in literature . . . . . . . . . . . . . . . . . . . . . . 6.3.2 Our approach . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 61 62 67 67 70 76 77 78 80 84

7 Conclusion A Injection-Locking Basics References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Tables
2.1 3.1 4.1 5.1 6.1 Frequency bands and data-rates . . . . . . . . . . . . . . . . . . . . . Performance Comparison . . . . . . . . . . . . . . . . . . . . . . . . . Performance Summary . . . . . . . . . . . . . . . . . . . . . . . . . . Performance Comparison . . . . . . . . . . . . . . . . . . . . . . . . . Summary of Expressions . . . . . . . . . . . . . . . . . . . . . . . . . 8 32 43 57 75

ix

Figures
1.1 1.2 1.3 2.1 2.2 2.3 2.4 2.5 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 Local oscillator pulling . . . . . . . . . . . . . . . . . . . . . . . . . . Local oscillator pulling in direct conversion transmitter architecture [4] Oset LO architecture for direct conversion transmitter [4] . . . . . . 2.4 GHz frequency band in IEEE 802.15.4 . . . . . . . . . . . . . . . . 2.4 GHz frequency band in IEEE 802.15.4; The transmitter, in part . Low-IF receiver block diagram . . . . . . . . . . . . . . . . . . . . . . Eect of local oscillator phase noise on (a) Receiver (b) Transmitter . Calculation of phase noise from receiver side; Sn (f ) represents the phase noise prole of the interferer channel . . . . . . . . . . . . . . . Block diagram of an Integer-N PLL . . . . . . . . . . . . . . . . . . . DLL-based frequency multiplier [5] . . . . . . . . . . . . . . . . . . . PLL with a Frequency Multiplier; Here the PLL runs at fout /M where fout is the desired frequency . . . . . . . . . . . . . . . . . . . . . . . Frequency multiplication scheme of Chien et al. (M=9) . . . . . . . . Frequency multiplication scheme of Shwetabh Verma et al. . . . . . . 3-Stage Ring Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage waveforms of a 3-stage ring oscillator; T is the time period of the VCO shown in Fig. 5 . . . . . . . . . . . . . . . . . . . . . . . . . (a) An edge-combining switch for M=3 and (b) A symmetric arm . . A single-ended frequency multiplier for M=3; Sizes are shown for target frequency of 2.4 GHz implemented in 0.13 m technology . . . . . . . Various voltage and current waveforms in circuit shown in Fig. 3.9. (a) shows the three phases of the ring oscillator for the multiplication factor M=3. (b) shows the current through the tail transistor MCS and (c) contains the voltage waveforms at Node N and tail node P . . (a) Dierential 3-Stage Ring Oscillator [6] (b) A unit inverter . . . . Frequency multiplier with dierential output. Component values shown are for 0.13m technology and 2.4GHz center frequency. S and S represent the complementary switches . . . . . . . . . . . . . . . . . . . (a) Amplitude (b) Tuning curve and (c) Phase Noise for circuit shown in Fig. 3.12 for 2.4 GHz ZigBee band, M=3 using symmetric arms (Fig. 3.8(b))and dierential realization (Fig. 3.12) . . . . . . . . . . . . . . Spurs at the frequency multiplied output. fRO is ring oscillator frequency and M, the multiplication factor . . . . . . . . . . . . . . . . x 2 3 4 8 9 9 11 12 16 16 17 19 20 21 22 22 23

3.11 3.12

25 26

28

3.13

30 33

3.14

Figures 3.15 Carrier to Spur Ratio (CSR) for circuit shown in Fig. 3.9 using Monte Carlo analysis, N=1000, VT ,N = 5.5%, VT ,P = 2%, ,N = 10% ,P = 6% and M=3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.16 Carrier to Spur Ratio (CSR) for circuit shown in Fig. 3.9 using Monte Carlo analysis, N=2000, VT ,N = 5.5%, VT ,P = 2%, ,N = 10% ,P = 6% and M=3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 (a) Single-ended frequency multiplier for M=3 and (b) The low frequency ring oscillator; NMOS is sized 2 m/0.2 m and PMOS is sized 4 m/0.2 m. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Symmetric oor plan for layout of the multiply-by-3 circuit. . . . . . Layout of the ring oscillator and cascaded switches; Inductor, capacitor and tail current source in the full multiplier circuit are not shown here in order to clearly display the arrangement of inverters and switches.

xi

33

34

4.2 4.3

41 41

42 46

Six stage dierential ring oscillator of Junfeng Xu et al. [8]. Size ratio of cross-coupling inverters to ring inverters is kept at 0.6. . . . . . . . 5.2 Frequency multiplier of Xu et al. [8] that combines current pulses from a low-frequency ring oscillator. The 12 inverters in the ring oscillator are grouped into 4 sets with each having 3 inverters. Power nodes of each inverter in a set are connected to an LC-tank. . . . . . . . . . . 5.3 Regenerative, inductive-peaked buer to amplify the output of frequency multiplier of Xu et al. It provides a voltage gain of about 4.5 at a bias current of 500 A. . . . . . . . . . . . . . . . . . . . . . . . 5.4 6-stage dierential ring oscillator phases to generate I and Q signals; Gray phases are complementary to Black ones to achieve dierential operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 Composite switches to achieve quadrature edge-combining. Each NMOS is sized 6 m/0.12m . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6 Quadrature edge-combiner circuit. SI and SI are the in-phase complementary edge-combining switches. Similarly, SQ and SQ are the quadrature-phase complementary edge-combining switches. . . . . . . 5.7 Frequency multiplier that combines edges from a low-frequency ring oscillator. S and S are the complementary edge-combining circuits. A, B and C are the three phases from a 3-stage ring oscillator. A, B and C denote the complementary phases. . . . . . . . . . . . . . . . . 5.8 (a) A constant resistance lattice network and (b) Allpass lter of Shaeer et al. [11] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.9 (a) 1-stage poly-phase filter (PPF) and (b) A 2-stage PPF with staggered poles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.10 Injection-locked QVCO and frequency multiplier. (I2 , Q2 ) have smaller quadrature imbalance than that in (I1 , Q1 ). . . . . . . . . . . . . . . .

5.1

46

48

49 49

50

51 52 53 56

Figures 5.11 A connected-source QVCO with parallel cross-coupling PMOS transistors, MCP,1 and MCP,1 . Parallel NMOS devices MIP,inj and MIN,inj are used to injection lock the QVCO. N1 and N2 directly come from frequency multiplier described in Fig. 5.7, without any intermediate buers. One stage of PPF generates the approximate quadrature signals that are added to a suitable common-mode voltage before injection locking the PQVCO. VC provides the common-mode level. . . . . . . 6.1 6.2 A conventional disconnected-source quadrature-coupled LC oscillator (a) RS is the extra-series resistance of the inductor. Capacitor is assumed to have high Q (b) Negative resistance LC-oscillator . . . . . . 6.3 f0 = 2.4 GHz, fn , the natural frequency of oscillation = 2.3508 GHz, fg the Groszkowski frequency=2.3412 GHz. = 2.25 and Q=5. . . . . . 6.4 Equivalent model of the oscillator; Gmc is the transconductance of the coupling transistors M3 M4 and Gmc that of oscillator core transistors M1 M 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 Series to parallel tranformation; Rp = Rs (1 + Q2 ) and Lp = Ls (1 + 1/Q2 ) 6.6 Phasor diagram of cross-coupled LC-VCO topology of Fig. 6.1. m = Gmc /Gm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7 Simple model of a cross-coupled LC oscillator. The coupling transistors M3 M4 (Fig.6.1) are modeled as VCCS with i v equation, i = Sc tanh(v Gnc /Sc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8 Solutions of (6.8) showing three positive roots for ; a = tan() where is is the phase shift at Groszkowsi frequency fg ; 1 = 0.23960 , 2 = 0.83780 , 3 = 1.06480 . Also note that compared to 2 , 3 , the dominant frequency is much closer to = 0 line. . . . . . . . . . . . 6.9 Frequency response of the resonator and dominant mode selection; The phase shift due to Growszkowski eect is = 2.25 and Q = 5. The three modes of oscillations are at frequencies f1 = 526.3 MHz, f2 = 2.010 GHz, f3 = 2.555 GHz . . . . . . . . . . . . . . . . . . . . . . . . 6.10 Preformance comparison of both the methods. Dashed lines represents Prior work and solid lines this work. Circles represent the results obtained from SpectreRF. The dierence in results of both methods increase as m increases and narrows down for higher Q. . . . . . . . 6.11 Comparison of amplitude obtained using both the methods versus the SpectreRF results. Good match is observed over a wide range of m. . A.1 Simple additive feedback model of the injection-locked oscillator . . . A.2 (a) Phasor diagram of signals shown in Fig. A.1, (b) Position of phasers at the edge of injection-locking when = 90 . . . . . . . . . . . . . .

xii

56 63 65 66

68 68 70

70

72

73

74 75 80 81

Chapter 1 Introduction

1.1

Introduction
EVELOPMENT of viable wireless sensor networks (WSNs) calls for a large reduction in cost, power and form factor of radio transceivers, achievable today.

The call for low-power is primarily due to the fact that, most often, the nature of environment in which the WSNs operate, makes battery replacement very hard, if not impossible. Also applications such as environmental monitoring over large areas, may require a very large number of devices that make battery replacement impractical. Development of truly energy-harvesting sensor nodes is yet a long way to go as the typical power harvested from common surroundings is of the order of 100W [1]. The research is on for an on-chip, low-cost and high-quality resonator, and a higheciency energy-scavenger that can make self-powered sensor nodes a possibility. At the same time, circuit-techniques are being constantly explored in order to prolong the life of currently used batteries. The radios usually employ phase or frequency modulation scheme to allow for a non-linear and ecient Power Amplier (PA) at the cost of spectral eciency. Lowdata rate and relatively large bandwidth of transmission translate to lower power of transmission for comparable SNR. Low transmitted and received power levels allow for a less linear receive chain which in turn allows for stacking of transistors to save power by current re-using or using lower supply voltage [2]. Spreading is employed to help relax Noise Figure (NF) specication of the receive chain, therefore saving 1

1.1. Introduction power.

A less stringent EVM (error vector magnitude, a measure of modulation accuracy of the transmitter) encourages the use of a direct conversion transmitter (DCT) that allows for high-level of integration. Furthermore, lter attenuation and image rejection specications are also kept moderate by requiring a rather benign receiver jamming resistance test. This leads to moderate receiver LO I/Q quadrature accuracy, easily realizable in modern CMOS processes. To achieve high level of integration in order to reduce cost, heterodyne receiver is not a favourable candidate as it uses bulky o-chip surface acoustic wave (SAW) lters for image-rejection. Also intermediate frequency (IF) being high, a separate PLL is required to generate IF signal. As a result, low-IF and zero-IF (direct conversion) receiver architectures have become more attractive. A moderate rejection of adjacent channel (which becomes the image signal in low-IF receiver) in WSNs, helps overcome the most serious design issue for Low-IF architecture and makes it a serious competitor to zero-IF which has the simplest architecture (i.e. low complexity, cost and power [3]).

Mixer

Signal

Large inband interferer

LNA

LO

Figure 1.1: Local oscillator pulling

However, a very serious issue in implementing both zero and low IF receiver is

1.1. Introduction

of LO pulling. As illustrated in Fig. 1.1, large interferer signals in the signal band that are unaected by the band-select lter are very close to LO frequency. These interferers get amplied by the LNA and couple to LO through substrate, and mixer due to nite isolation between its LO and RF ports. This phenomenon is called injection pulling of receive LO [4]. Receive LO pulling is typically alleviated using two techniques. (1) Placing a good reverse isolation buer betwen LO and Mixer. (2) Running LO at twice the desired frequency and divide it by two, which also generates quadrature signals. However, both these methods entail higher power dissipation. To save some power, the LO buer is usually resonator-loaded which, in addition to larger area, is prone to common mode instability problem when used with Gilbert mixer [5]. Also for very high-frequency LOs, generating a doubly fast oscillator may not be possible technologically. An interesting solution to the problem could be running LO at a much reduced frequency and use a frequency multiplier (FM) to generate the desired frequency. Also, use of low-frequency LO saves power in VCO and helps eliminate rst few dividers leading to signicant power savings.
Mixer I
sin0t

LO BPF
900 cos0t

PA

LO

Figure 1.2: Local oscillator pulling in direct conversion transmitter architecture [4]

On the transmitter side, a high level of integration is achieved using the DCT

1.1. Introduction

Mixer
sin0t

1 + 2 1

BPF
90

PA

BPF
2

LO

VCO1

cos0t

VCO2
Figure 1.3: Oset LO architecture for direct conversion transmitter [4]

architecture. Here the PA output, a modulated waveform with large power, has a spectrum centered around LO frequency. This strong signal couples to LO and disturbs its frequency (Fig 1.2). The situation is usually amended by using sum or dierence frequencies of two VCOs whose individual frequencies are far dierent from the desired sum or dierence frequency (Fig 1.3) [6]. This method ia called osetLO architecture. Another solution is to go for a two step transmitter. Both these methods, in addition to extra mixers, necessitate steep bandpass lters which may have to go o-chip, coming in the way of integration [4]. Frequency multiplier can be used in DCTs without any additional BPF required. Also only a single VCO and PLL is needed. The rest of the thesis is organized as follows. Chapter 2 gives a brief description of IEEE 802.15.4 standard, and presents its important and relevant specications. Although the circuits developed in the following chapters are applicable to any lowdata rate application, the design examples are made compliant with IEEE 802.15.4 standard. Development of a low-power FM with design issues/trade-os involved, is the subject of Chapter-3. Chapter 4 discusses in brief the layout issues critical to the

1.1. Introduction

performance of FM circuit. Layout extracted results for the frequency-multiplier are compared with those obtained from the simulation of the schematic. Generation of low-power and moderate/high-precision quadrature sinusoidal signals for oscillators based on the concept of frequency multiplication is described in Chaper 5. We evaluate a number of architectures and identify an optimal topology. A complete analytical treatment for our quadrature LO generator requires an accurate modeling of the QVCO. Chapter 6 models the frequency shifts associated with modern CMOS QVCO circuits that consist of cross-coupled LC-VCOs. These LC oscillators use low/moderate quality factor on-chip inductors to facilitate higher integration and because of their low-Q, the involved frequency shifts could be fairly big and their calculation not amenable to approximations that presume high-Q. Chapter 7 presents the conclusions drawn from the work covered in this thesis.

References
[1] S. Roundy, E.S. Leland, J. Baker, E. Carleton, E. Reilly, E. Lai, B. Otis, J.M. Rabaey, P.K. Wright, V. Sundararajan, Improving power output for vibrationbased energy scavengers, IEEE Pervasive Computing, vol. 4, no. 1, pp. 28-36, Jan.-March 2005 [2] Behzad Razavi, Analog integrated circuit design, Prentice Hall [3] Ilku Nam, Kyudon Choi, Joonhee Lee, Hyouk-Kyu Cha, Bo-Ik Seo, Kuduck Kwon, Kwyro Lee, A 2.4 GHz low-power low-IF receiver and direct conversion transmitter in 0.18 m CMOS for IEEE 802.15.4 WPAN application, IEEE Transactions on Microwave Theory and Techniques, vol. 55, no. 4, pp. 682-689 April 2007 [4] Behzad Razavi, RF Microelectronics, Prentice Hall [5] S. Gueorguiev, S. Lindfors, T. Larsen, Common-mode stability in Low-power LO drivers, IEEE International Symposium on Circuits and Systems, pp. 5505-5508 vol. 6, May 23-26, 2005 [6] T.D. Stetzler, I.G. Post, J.H. Havens, M. Koyama, A 2.7-4.5 V single chip GSM transceiver RF integrated circuit, IEEE Journal of Solid-State Circuits vol. 30, no. 12, pp. 1421-1429, December 1995

Chapter 2 Background
This chapter briey descibes the relevant features of IEEE 802.15.4 LR-WPAN standard. Design specications are obtained to be used in the subsequent chapters.

2.1

Introduction

EEE 802.15.4 WPAN standard released a preliminary draft in 2003, targetted at low-data rate applications such as low-cost pervasive wireless sensor networks,

with extremely low duty-cycle capability (< 10 ppm) [1]. It is the rst global wireless standard aimed at low-power remote monitoring and control applications. While IEEE 802.15.4 has dened physical (PHY) and media access control (MAC) layers, ZigBee alliance [3] has added Network, Security and Application layers above it. IEEE 802.15.4 operates in three unlicensed industrial, scientic and medical (ISM) bands of 868/915 MHz and 2.4 GHz with a total of 27 channels. Table 2.1 summarizes the information on various bands, their data-rates, availability and modulation schemes. Of the 3 bands, 2.42.4835 GHz band is most attractive as it is the only worldwide allocation of spectrum that does not have restrictions on the application and transmit duty-cycling. The center frequencies in this band are given by

fc = 2405 + 5(k 11) MHz, k=11. . . 26

2.1. Introduction Table 2.1: Frequency bands and Phy Frequency Spreading parameters (MHz) band (MHz) Chip rate Modulation (Kcps) 868 915 2450 868868.6 902928 2400 2483.5 300 600 2000 BPSK BPSK O-QPSK data-rates Data parameters

Bit rate (Kbps) 20 40 250

Symbol rate (Ksps) 20 40 62.5

Symbols

Binary Binary 16-ary Orthogonal

The band contains 16 channels, each 5 MHz wide with 3 MHz of guard band between 2 MHz wide data bands (Fig. 2.1).

5 MHz

2.4 GHz

5 MHz

2 MHz

2.4835 GHz

Figure 2.1: 2.4 GHz frequency band in IEEE 802.15.4

The 2450 MHz PHY has data-rate of 250 Kbps and uses 16-ary quasi-orthogonal modulation technique. This modulation technique is a power-ecient one that achieves low SNR at the expense of large bandwidth that is signicantly larger than its symbol rate. Fig. 2.2 depicts the baseband part of transmitter. Four information bits are used to generate one symbol resulting in 62.5 Ksymbols per second symbol rate. Each symbol is converted to 32-chip pseudo-random noise sequence leading to chip-rate of 2 Mchips per second. Alternate chips are delayed by one chip period Tc and seperated

2.1. Introduction
Half sine pulse shaping I

Bits 250 Kbps Bit to symbol mapping

62.5 Ksymbols/s Chip to symbol mapping

2 Mchips/s Serial to parallel

Offset delay,TC

Half sine pulse shaping

Figure 2.2: 2.4 GHz frequency band in IEEE 802.15.4; The transmitter, in part

into I and Q streams. Each baseband chip is represented by a half-sine pulse. After being translated to designated carrier frequency, the I and Q branches are summed up at the input of power amplier.
B A S E B A N D S I G N A L P R O C

I
ADC I Duplexer Antenna LNA
900

VCO

Q
ADC Channel Select Filter

From Tx

Figure 2.3: Low-IF receiver block diagram

IEEE 802.15.4 PHY dictates receiver sensitivity to be -85 dBm or better. DSSS with chip rate of 2 Mcps results in 10log(Chip rate/Bit rate) 9 dB of processing gain. Fig. 2.3 shows block-diagram of a low-IF receiver as an example. The RF signal is amplied and translated to a suitable intermediate frequency whereafter it

2.1. Introduction

10

is digitized. The demodulation to baseband, image rejection and despreading takes place in digital domain.

2.1.1

Maximum Transmit Power

The 802.15.4 PHY standard says that the maximum transmit power shall conform to the local regulations. In United States, the FCC rules provide for 0 dBm of eective radiated power (ERP) for narrow-band operation and 1 mW/MHz for wideband operation above 1000 MHz, upto 1 W ERP. While an IEEE 802.15.4 equipment is generally supposed to transmit upto 0 dBm of power, international community usually allows for a maximum of +10 dBm. At the lower end, an IEEE 802.15.4 compliant device must be able to transmit at least -3 dBm of power.

2.1.2

Receiver jamming resistance

Adjacent channel rejection 0 dB Alternate channel rejection 30 dB

Compare this with IEEE 802.11a WLAN standard [2] that requires 16 dB of adjacent channel and 32 dB of alternate channel rejection for 6 Mbps data rate. The adjacent channel rejection is measured under the following conditions. The desired signal is 2450 MHz IEEE 802.15.4 compliant pseudo-random data. The desired signal is input to the receiver at a level 3 dB above the maximum receiver sensitivity.

2.1.3

Eect of local oscillator phase noise on receiver and transmitter

Figures 2.4 (a) and (b) describe the eect of oscillator phase noise on the receiver and transmitter respectively. In receiver, it leads to a larger interferer in the nearby channel downconverting to the desired signal band. This eect is called reciprocal self-mixing. While in transmitter, a large phase noise LO results in signicantly large

2.1. Introduction

11

Signal

Large inband interferer

LO

LO profile

Downconverted signal

LO

(a)

Nearby transmitter

Desired signal
1 2

(b)

Figure 2.4: Eect of local oscillator phase noise on (a) Receiver (b) Transmitter

power in the neighbouring band that makes the detection of a weak signal in that band very hard [1]. Phase noise also corrupts the information carried in the phase and frequency of the carrier. LO phase noise specication is derived from the knowledge of interferer prole for both receive and transmit case. Let us assume that phase noise of the interferer in the desired band is constant at PNc (narrowband approximation), its value at the center frequency of the adjacent channel (Fig. 2.5). On the receive side,

2.1. Introduction

12

Sn ( f )
Large interferer

PNc

fc
BW

Wanted Signal

Figure 2.5: Calculation of phase noise from receiver side; Sn (f ) represents the phase noise prole of the interferer channel

Total noise power in the signal band = Pint + PNc + 10log(BW ) Where Pint is the power of interferer and BW, the bandwidth of the signal (2 MHz). Allowing for some margin in SNR,

PNc (dBc/Hz) = Psig Pint SNR min 10log(BW ) margins

(2.1)

Where Psig is the power of the signal. With minimum signal power of -85 dBm, SNRmin of 0.5 dB, 10 dB margin, and adjacent channel interferer rejection of 0 dB (section 2.1.2), phase noise turns out to be -75.5 dBc/Hz at 5 MHz oset. For alternate adjacent channel interferer rejection of 30 dB, required phase noise is -103.5 dBc/Hz at 10 MHz oset. On the transmit side, maximum spurious emission level is provided by the FCC in US and ESTI in Europe. The U.S. requirement, more restrictive than the European one, limits the spurious emission level to -41.2 dBm/MHz or an average of -101.2 dBm/MHz for 2.4 GHz operation. Since the nearest channel at the edge is centered at 2.48 GHz, using the spreading gain of about 9 dB, the allowed phase noise at

2.1. Introduction

13

3.5 MHz oset is -92.2 dBc/Hz. The European requirement puts it at -71 dBc/Hz at 3.5 MHz oset [5].

References
[1] IEEE 802.15.4-2003 Part 15.4: Wireless Medium Access Control (MAC) and Physical Layer (PHY) specication for Low-Rate Wireless Personal Area Network (LRWPANs) [2] IEEE 802.11a-1999(R2003) Part 11: Wireless Medium Access Control (MAC) and Physical Layer (PHY) specication [3] www.zigbee.org [4] Behzad Razavi, RF Microelectronics, Prentice Hall [5] Nam-Jin Oh, Sang-Gug Lee, Building a 2.4 GHz Radio Transceiver Using IEEE 802.15.4, IEEE Circuits and Devices Magazine, pp. 43-51, Nov/Dec 2005.

14

Chapter 3 A Low Power GHz-Range Frequency Multiplier for Low-Data Rate Applications
This chapter presents a new method of generating high frequency sinusoidal signal based on the technique of frequency multiplication. The method is suitable for wireless sensor networks (WSN) application where low-power operation takes precedence over high delity. The chapter discusses various existing techniques of frequency multiplication, and proposes a new technique which has lower power. It involves combining edges from a lower frequency ring oscillator. This technique is suitable for applications which have relaxed phase noise specications. Finally, an example design is presented for 2.4 GHz IEEE 802.15.4 standard. Simulations using SpectreRF show that the circuit consumes only 550 W of power in 0.13 m RF-CMOS technology with 1.2 V supply voltage, and provides 950 mV PP sinusoidal output with phase noise of -85.5 dBc/Hz at 1 MHz oset.

3.1

Introduction
Locked Loop (Fig. 3.1). Here the output of the VCO which generates the desired

YNTHESIS of high frequency on-chip clock signals is usually done via a Phase

clock, is divided by a factor of N and phase-locked to a low frequency reference clock signal. In the frequency synthesizer, the largest fraction of power is consumed by the components working at RF carrier frequencies namely the VCO and the Prescaler. Reduction of power consumption in VCOs and Prescalers therefore has been the subject of several publications [13]. The power in prescalers based on master-slave

15

3.1. Introduction

16

ip-ops is dominated by the rst two dividers which account for 75% of the total power in the divider chain. This power cost increases dramatically as the VCO oscillation frequency approaches close to the fT of the technology.

in
@N fref

fref

PD

CP+LF

VCO

out
@N fref

/2

/2

/2

/2

@N fref @N fref /2

Figure 3.1: Block diagram of an Integer-N PLL

Feedback

Vctrl fref
VCDL

Edge Combiner

Figure 3.2: DLL-based frequency multiplier [5]

An alternative to using high power dividers at such high frequencies, is to use the idea of frequency multiplication [46]. Here many equally spaced phases of a lower frequency clock signal are combined to generate the higher frequency clock signal. Razavi et al. realized a 6 GHz PLL in 20 GHz BiCMOS process wherein no conventional ring oscillator could achieve this frequency [4]. Chien et al. demonstrate a similar idea but use the phases from a delay locked loop [5] (Fig. 3.2).

3.1. Introduction

17

In this chapter, we explore this idea of frequency multiplication for low-power applications like wireless sensor networks (WSN). Since, the phase noise requirement of the frequency synthesizer can be as high as -71 dBc/Hz at 3.5 MHz oset [7], an optimal design should take advantage of these relaxed specications to trade-o power versus performance. In the case of the frequency synthesizer, lower power can be achieved by trading it o with increased phase noise or jitter, while still meeting the overall system level specications.

fref

Nfref /M

Frequency
Multiplier

PD

CP+LF

VCO

@ Nfref = fout

@N fref /M

/2

/2

/2

/2

@N fref /M @N fref /2M

Figure 3.3: PLL with a Frequency Multiplier; Here the PLL runs at fout /M where fout is the desired frequency

RF applications typically use LC-VCOs as they oer good phase noise performance. While the DC current in the LC-VCO can be reduced to trade-o power and phase noise, it also reduces the signal amplitude, which adversely aects the mixer gain. Also for a desired amplitude, the DC bias current cannot be reduced beyond a point due to the coupled requirements on phase noise, amplitude, frequency of operation, tuning range and reliable start-up for a given type of oscillator [2, 3]. The idea of using a low frequency PLL along with frequency multiplication using a phase combining technique, suggests an alternative approach to achieve lower power, as it eliminates the high frequency VCO and the high frequency dividers. A low-frequency ring oscillator based VCO generates multiple phases which can then be combined to generate the high frequency carrier signal. The drawback is an increased phase noise from the ring oscillator based VCO, hence limiting its usage to applications which can tolerate this higher noise.

3.2. Frequency Multiplication by Edge-Combining

18

The approaches presented in the literature so far, for achieving this phase combining, are not power ecient and their limitations are discussed in detail in Section 3.2. In Section 3.3, we propose a new, power-ecient edge-combining technique, which enables a low-power frequency multiplication architecture based on simple digital ring VCOs operating at frequencies much lower than the desired carrier frequency. Additionally, the lower frequency VCO and PLL can now be operated at a reduced power supply, saving even more power. We discuss both single-ended and dierential realizations and present some analysis and simulation results quantifying their performance, followed by discussions on their limitations and applicability in Section 3.4 and conclusions in Section 3.5.

3.2

Frequency Multiplication by Edge-Combining

f0 M

The PLL in Fig. 3.3 operates at a reduced frequency

where f0 is the desired fre-

quency. The VCO generates multiple phases, and these are combined to generate the carrier at f0 . The VCO operates at f0 /M and the rst [log2 M ] number of dividers are not required leading to power-savings in this PLL. However, the frequency multiplier has to be designed in a power ecient way so as not to squander away the power advantage obtained thus. Ring oscillator based VCOs can conveniently generate multiple phases, but suffer from degraded phase noise compared to LC-VCOs. The phase noise of the frequency multiplied output is further worsened by an amount 20log10 M which compensates for the improved phase-noise of the VCO running at a reduced frequency. Therefore, for cellular applications, frequency-multiplier based PLL employing a Ring VCO may not be able to meet their stringent phase noise requirements. However for WSN applications where one can live with much degraded phase noise, a digital ring oscillator can be used in the PLL. Digital inverter (DI) based ring oscillators have only dynamic power-dissipation and provide rail-to-rail swing which simplies the

3.2. Frequency Multiplication by Edge-Combining

L

19

Out+

Out

1P

1N

2P

2N

8P

8N

9P

9N

ISS

Figure 3.4: Frequency multiplication scheme of Chien et al. (M=9)

design of a low-power edge-combiner. In addition, DI based ring oscillator can use supply voltage scaling to save power greatly as the dynamic power in such a VCO
2 varies as N CVDD f , while for LC-VCOs, the overall power varies only proportionately

with supply voltage. Razavi [4] and Chien [5] have used dierential amplier based VCOs for which the edge-combiner becomes power hungry. Fig. 3.4 describes the edge-combiner used by Chien et al. Here, each dierential amplier has a DC tail current source of its own leading to static power dissipation. Dierential ampliers also do not provide rail-to-rail swings. As a result, the edge-combiner has to employ a dierential MOS transistor pair as a unit for commutating the tail current. The tail current sources in all these dierential pairs lead to increased static and therefore overall power. Recently in a paper by Verma and Lee [6], an innovative method to perform frequency multiplication was presented. Consider the circuit shown in Fig. 3.5. As a rising edge propagates through an inverter, for the duration of propagation delay tp

3.2. Frequency Multiplication by Edge-Combining

20

N N odd

Figure 3.5: Frequency multiplication scheme of Shwetabh Verma et al.

of the inverter, a current surge passes from the output to the ground node. Here, one is eectively combining the edges of the input and output waveforms of the inverter. In one time-period of the ring oscillator, there are N such occasions when a current pulse is sent to ground. If we tie the ground node of all the inverters, and make the combined current pulse pass through a LC tank as shown in Fig. 3.5, we can achieve a frequency N times that of the ring oscillator. The LC tank tuned at N fRO lters out the out-of-band components producing a sinusoidal waveform of frequency N fRO . The primary drawback of this technique, however, is that of a poor amplitude. As one tries to make the inverters wider to increase the magnitude of current pulse (by reducing series resistance of the NMOS switch), a larger ground bounce reduces the gate overdrive and increases ON resistance of the switch. When implemented in 0.13 m RF-CMOS process, it is dicult to achieve even 150 mV of voltage swing using this method and hence, an additional amplier is needed to get the desired voltage swing. But amplifying a high-frequency LO signal is costly both in terms of area and power [8]. In the next section, we will present a new technique to achieve phase combining in a power ecient way. This technique also provides large amplitude sinusoidal signals which can be directly used in the mixer without any further amplication.

3.3. A new method of edge-combining

21

Performance comparison of the proposed circuit vis-a-vis the circuit shown in Fig. 3.5 is presented in section 3.4.

3.3

A new method of edge-combining

Clearly, to work around the above problem of low output amplitude, one has to decouple the ground node of the ring oscillator from the LC tank [8]. This can be easily achieved at the expense of some extra power. Consider a 3-stage ring oscillator shown in Fig. 3.6. The voltage waveforms at nodes A, B and C are shown in Fig. 3.7. The signals AB, BC and CA, represent the logical ANDing of the waveforms, and are displaced from each other by T /3, where T is the time period of the ring oscillator. If we combine the equally spaced signals (by wire-ORing them), the resultant waveform will not only be periodic with period T /3 but will also carry the same power as either of the waveforms at A, B or C. However, the actual power will be somewhat less considering the nite rise and fall time of the voltages at A, B and C.
A B C

Figure 3.6: 3-Stage Ring Oscillator

An easy technique to perform this logical ANDing with low-power and area cost is to use MOS switches in cascade as shown in Fig. 3.8(a). Various phases are used symmetrically so as to present equal load to all ring oscillator phases and preserve the phase symmetry. Fig. 3.8(b) shows a symmetric realization of an arm which helps realize a uniform ON resistance of each switch cascade. The current from each pair of switches is made to ow though the LC tank tuned to 3fRO , where fRO is frequency of the ring oscillator. The tank lters out the frequency components other than the fundamental. Even though we have illustrated this technique for N = 3, it can be

3.3. A new method of edge-combining

22

VA VB VC
Combined
AB T/3
Figure 3.7: Voltage waveforms of a 3-stage ring oscillator; T is the time period of the VCO shown in Fig. 5

AC

BC

AB

Current Waveform

easily extended to any odd number greater than 3. Fig. 3.9 shows the complete schematic of multiply-by-3 edge-combiner circuit.

(a)

(b)

Figure 3.8: (a) An edge-combining switch for M=3 and (b) A symmetric arm Another thing to observe here is that the tail node P oscillates at frequency f0 =

3.3. A new method of edge-combining

23

11nH
N A B C
C

314f F

A
P

6m 0.12m

CGD
Vbias

Iin CDB MCS

120m 0.25m

CGS

Figure 3.9: A single-ended frequency multiplier for M=3; Sizes are shown for target frequency of 2.4 GHz implemented in 0.13 m technology

M fRO unlike 2f0 in a LC-VCO. For large tail transistor MCS , the oscillations at point P at frequency f0 get coupled to the gate of MCS through large CGD , modulating the tail current. At large amplitudes, the oscillations at point P get big enough to drive MCS periodically into saturation (maximum current) and triode region (minimum current) giving the tail current a square shape. However, a large tail transistor, due to large CDB to ground, will degrade PSRR. The circuit will pick more noise from the substrate and also will inject more switching noise into it (both leading to self-mixing and saturation of RF-demodulation chain). But, a large tail current source will help reduce 1/f noise which is upconverted by the switching transistors to 1/f 3 close-in phase noise due to AM-PM conversion mechanism in non-linear varactors [9]. The modulated current waveform along with drain voltage of the tail transistor is shown in Fig. 3.10. Fig. 3.10(a) shows the 3 phases of the 3-stage ring oscillator. The voltage waveforms at points P and N are shown in Fig. 3.10(c). The current injected into the switches (Fig. 3.9) is shown in Fig. 3.10(b). The amplitude of oscillation, going by the square shape of the current, can be

3.3. A new method of edge-combining estimated from the magnitude of the fundamental harmonic as VAmp = 2IPeak RP

24

(3.1)

where RP is Tank impedance at resonance. For RP = 1.25 ks and IPeak = 550 A. (3.1) gives VAmp =475 mV which is close to the simulation results of VPP = 950 mV shown in Fig. 3.10. For any multiplication factor, the average current drawn from the supply is about 465 A. The average current consumed by the ring oscillator is 171 A and that used (Iavg ) by the multiplier is 278 A. To compare it with current-reuse LC-VCO for the same value of L and center frequency [2], VAmp,LCVCO = 4Iavg RP = 442.5 mV (3.2)

Equivalently, this structure is as power ecient as the current-reuse LC-VCO for conversion of DC current to output amplitude. Due to extra power in the ring oscillator, for the same output swing of 450 mV, the proposed structure consumes a total of 465 A as against 278 A of LC-VCO. In other words, for M=5, eectively, we are replacing the dividers working at 2.4 GHz and 1.2 GHz with a 5-stage ring oscillator working at 480 MHz. Phase noise of the LC-VCO is -110 dBc/Hz as against -85.5 dBc/Hz of frequency-multiplying oscillator at 1 MHz oset for the same output amplitude of 475 mV. At 3.5 MHz oset, the phase noise is -99.7 dBc/Hz. The degraded phase noise is due to the poor phase noise characterstic of ring oscillators. Size of switch MOSFETs is chosen as a compromise between small IR drop (larger swing) and higher power dissipation in the ring oscillator (due to larger load capacitance.) Also with large switches, parasitic capacitances (CGD and CDB of top NMOSes become a signicant part of the total capacitance and it being timedependent distorts the waveform at node N. The voltage swing at point N cannot be increased arbitrarily due to reliability

3.3. A new method of edge-combining

25

1 0.5 0 5.1 5.12 5.14 5.16 5.18 5.2

A B C
8 5.22 10

(in As)

Voltage (in volts) I

Tank

500

0 5.1 2
Voltage (in volts)

5.12

5.14

5.16
N

5.18

5.2
950mV 950mV

5.22 108

1
P

0 5.1

5.12

5.14

5.16

5.18

5.2

Time (in seconds)

5.22 108

Figure 3.10: Various voltage and current waveforms in circuit shown in Fig. 3.9. (a) shows the three phases of the ring oscillator for the multiplication factor M=3. (b) shows the current through the tail transistor MCS and (c) contains the voltage waveforms at Node N and tail node P

concerns. The common mode voltage at N is VDD (to be precise, little less than VDD , allowing for small drop in small series resistance of the inductor). A VGD for the top NMOS switch much larger than VDD will cause gate oxide breakdown. In 0.13 m technology with 1.2 V supply voltage, one should limit the amplitude to about 450 mV.

3.3.1

Dierential Operation

To avail the inherent benets of rejection of common mode noise and even harmonics, dierential or balanced operation is always preferred over the single-ended one. To

3.3. A new method of edge-combining

26

A1

A1

B1

B1

(a)

0.8m 0.2m

In

Out
0.4m 0.2m

(b)

Figure 3.11: (a) Dierential 3-Stage Ring Oscillator [6] (b) A unit inverter generate dierential high frequency signals, low-frequency RO must also generate dierential signals. There are two ways to do this. 1. Dierential ring oscillator with two or more dierential ampliers in feedback loop or 2. Coupled digital inverterbased ring oscillators. Razavi [4] and Chien [5] used the rst choice. Here the edgecombiner has to employ a dierential MOS transistor pair as a unit to switch the tail current. These tail currents lead to static power dissipation and therefore increase overall power. On the other hand, digital inverter-based cross coupled ring oscillators only dissipate dynamic power and provide rail to rail swing which can be used to completely turn-ON and OFF the simple MOS switches in the frequency multiplier. A simple MOSFET based switch being the highest speed switch available in a given technology,

3.3. A new method of edge-combining

27

the circuit can be used for very high frequencies with a suitable microwave resonator replacing the LC-tank. The N-stage (N-odd) dierential RO consists of 2, N-stage single-ended ROs, with each stage comprising of 3 inverters. One inverter from each stage is crosscoupled to force corresponding nodes in the two ring oscillators to be mutually complementary. It is clear that for the same frequency of operation, increased number of inverters (3-times in this case) compared to a 3-stage oscillator, does not lead to higher power as the load driven by each inverter reduces by the same factor. This also allows for lowering the VCO gain as one of the three inverters in very stage can be tuned without disturbing the symmetry of the various phase of the ing oscillator. In addition, the larger number of inverters will average out the random component of process mismatch helping in improving the carrier-to-spur ratio (CSR) in the multiplied output and is further discussed in the next section. Eect of this choice on the phase noise will also be discussed in the next section. A simple dierential realization will have two copies of the circuit in Fig. 3.9 with each switch bank driven by complementary nodes of the dierential ring oscillator of Fig. 3.11(a). Since the two switch banks are complementary, switching the tail current alternately, a single tail current source can be used leading to an important power saving (current re-use). We can also reuse a single inductor by connecting it across the two dierential nodes N1 and N2 saving an inductor (reducing area, therefore cost, to half) leading to the nal dierential structure shown in Fig. 3.12 which is both area and power ecient. The cross-coupled PMOS pair at the top helps limit the oscillations at nodes N1 and N2 below the supply voltage. However in this conversion, we have lose one advantage of single-ended structure viz. the tail node being a common mode point now oscillates at frequency 2f0 . And a large current source transistor (big drain junction-capacitance) used to reduce 1/f noise provides a small impedance at 2f0 to ground which degrades the LC-tank by allowing gds of the triode region switch MOS to load the tank [10].

3.3. A new method of edge-combining

28

M1

M2
20m 0.18m

L
N1 N2

607f F
C

Cpar

11nH S

Cpar

607f F
C

A B

IDC = 300A
VBias

MCS

36m 0.18m

Figure 3.12: Frequency multiplier with dierential output. Component values shown are for 0.13 m technology and 2.4 GHz center frequency. S and S represent the complementary switches

A signicant advantage of this structure is that unlike LC-VCO, it does not require a minimum bias current for reliable start-up. The NMOS switches, S and S, will ensure the current switching irrespective of the value of the current and size of the cross-coupled PMOS pair at the top. Output voltage amplitude as in the case of LC-VCO is given by VAmp = 4 IDC RP (3.3)

For the circuit shown in Fig. 3.12 working at 2.4 GHz, total current drawn from the supply is 595 A of which 201 A is spent in the ring oscillator of Fig. 3.11(a). The inverters in the ring oscillator are sized as (W/L)PMOS = 0.8 m/0.2 m and (W/L)NMOS = 0.4 m/0.2 m. Average current drawn by the intermediate buers is 73 A. The buers have the same size as that of the inverters in the ring oscillator. As one increases the size of cross-coupled PMOS pair to reduce its gate over-

3.3. A new method of edge-combining

29

drive for supporting the IDC and therefore delay the onset of the voltage-controlled regime, an interesting thing happens; The cross-coupled PMOS pair M1 M2 generates enough negative resistance to more than compensate the losses in the LC-tank creating an LC oscillator by providing sucient start-up gain. However, the circuit continues to function faithfully as a frequency multiplier as the strong switchedcurrent signal at 3fRO will injection-lock the LC-VCO. Injection-locking being a narrow-band phenomenon would restrict the correct operation to its lock-bandwidth. Therefore one must restrict the size of M1 M2 to have sucient bandwidth of operation. For example, a 70 m/0.18 m sized PMOS pair limits the injection lock range to 2.112.64 GHz frequency band. It should be noted that nothing prevents the use of this frequency multiplication scheme for a wideband operation. A small varactor can be used to tune the ring oscillator (with, say, f as tuning range). However frequencies away from the centre frequency of the LC-tank (tuned at 3fRO ) will suer attenuation. For wideband operation, a strong varactor or a switched-capacitor bank [11] can be used in the LC-tank. A strong varactor has problems related to high sensitivity (large gain) to noise on the control voltage signal. It also gives rise to AM-to-PM conversion owing to large VCO swing pushing the operation of varactor deep into the non-linear regions of its C V curve [12]. Switched-capacitor bank scheme, on the other hand, degrades the Q of the LC-tank due to nite on-resistance of the MOS switches [13]. For large amplitudes of the oscillation, we run into instability problems due to back-coupling (CPar in Fig. 3.12) from multiplier-oscillator to the ring VCO though CGD of the top switch transistors as shown. The circuit is a two-way coupled system of two oscillators and has more than one solution (frequency and amplitude pairs). This is analogous to the case of familiar cross-coupled LC-VCOs generating quadrature phases, where we encounter three possible solutions (three frequency and amplitude pairs) [14] and the highest frequency is chosen as it leads to highest loop gain due to largest tank impedance at this frequency (discussed in detail in Chapter-6). In

3.3. A new method of edge-combining

Amplitude of high frequency output
541mV

30
Tuning Curve

600

500 Amplitude (in mVs)

501mV

479mV

Band of Interest

400
Band of Interest

Frequency (in GHZ)

448mV

VDD=1.2V

2.5

2.485 GHz Band of Interest 2.405 GHz VDD=1.0V

300

VDD=1.2V

200

100

VDD=1.0V

0 0

0.2

0.4 0.6 Tuning voltage (in volts)

0.8

1.5 0

0.2

0.4 0.6 Tuning voltage (in volts)

0.8

(a)
Phase Noise at high frequency output
Band of Interest VDD=1.2V VDD=1.0 V 10dB VDD=1.2V

(b)

70 Phase Noise (in dBc/Hz) at 1MHz offset

80

Output of frequency multiplier

85

90

Output of ring oscillator

95 0

0.2

0.4 0.6 Tuning voltage (in volts)

Band of Interest

75

0.8

(c)

Figure 3.13: (a) Amplitude (b) Tuning curve and (c) Phase Noise for circuit shown in Fig. 3.12 for 2.4 GHz ZigBee band, M=3 using symmetric arms (Fig. 3.8(b))and dierential realization (Fig. 3.12) our case as the amplitude of oscillations is increased, a point comes when the system suddenly switches to the other mode of the oscillation (even though, frequency multiplication still holds good) with a dierent pair of frequency and amplitude. Clearly, this is an undesirable situation. To eliminate such possibility, one must provide sucient reverse isolation, i.e. from multiplier to the ring oscillator. This is easily done by putting buer inverters after the ring oscillator, driving the switch MOSFETS.

3.4. Discussions

31

RO buers are anyway necessary to avoid disturbing the phase symmetry that would otherwise be caused due to loading by the frequency divider in the PLL [15].

3.4

Discussions

All the circuits were simulated in SpectreRF using a commercial 0.13 m RF-CMOS technology with MIM capacitor option. Fig. 3.13 shows the amplitude, tuning and phase noise curves for dierential realization of Fig. 3.12 and multiplying factor M=3, for the example case of 2.4 GHz ZigBee band. The dierential ring oscillator (Fig. 3.11(a)) is tuned using inversion-mode MOS capacitors. The 2.4 GHz ZigBee band is covered by varying the tuning voltage from 0.5 to 0.58 V. For 2.45 GHz output frequency, M=3, and IDC = 300 A, the peak amplitude is 550 mV and phase noise of the frequency multiplied output is -84 dBc/Hz at 1 MHz oset which is about 20log10 3 10 dB worse as compared to the ring oscillator. The thermal noise of the switches is upconverted to fRO and is ltered out by the LC-tank tuned at 3fRO and therefore does not degrade the phase noise at the output further. Table 3.1 summarizes the performance of a single-ended multiplier versus that of the S. Verma et al. for the same center frequency of 2.45 GHz, identical LCtank and 0.13 m RF-CMOS technology. For the comparable phase noise and same multiplying factor of 3, the total current required by our approach is 458 A which is 2.86 times that needed by [6]. However the output voltage amplitude in our case is 451 mV which is 5.8 times that obtained by Shwetabh Verma et al. which underlines the power eciency of the proposed technique.

3.4.1

Eect of ground bounce

An important issue to be considered in high-frequency single-ended realizations is the eect of ground bounce resulting from large bond-wire inductance. Since the single-ended circuts do not enjoy the presence of virtual ground, their performance

3.4. Discussions Table 3.1: Performance Comparison [6], M=3 This Work, M=3 Amplitude 77.8 mV 451 mV Current drawn from 160 A 45 8A supply Phase Noise (dBc/Hz -85.7 -83.3 at 1 MHz oset) Phase Noise (dBc/Hz -100.1 -97.5 at 3.5 MHz oset)

32

This Work, M=5 457.7 mV 465.8 A -88.5 -102.8

Frequency 2.45 GHz, L=11 nH and 0.13 m technology

is adversely aected by the supply and ground bounces. While the bounce on the VDD line can be alleviated by tuning out the bond-wire inductance by placing large de-coupling capacitors, nothing can be done about the ground bounce. For the circuit shown in Fig. 3.9, since the current at 2.4 GHz is just 272 A, the bounce due to 5 nH bond-wire is L I = 21 mV which is quite small. The current injected by the ring oscillator working at 800 MHz causes only 172 A 2 800 MHz 5 nH = 4.3 mV oscillations on the ground node which is again negligible.

3.4.2

Eect of mismatches in the ring oscillator

Mismatches between the inverters of the ring oscillator lead to delay mismatches between various adjacent phases of the ring oscillator. This in turn leads to spurs in the frequency multiplied output. Fig. 3.14 illustrates the various tones present at the output of the multiplier. Even though the tone at 2M fRO is largest in power after the desired signal, tones at (M 1)fRO are most dangerous as RF signal at these frequencies suers much less attenuation by the band-select lter compared to that at 2M fRO . Fig. 3.15 shows the Carrier-to-spur ratio (CSR) in dB for circuit shown in Fig. 3.12, obtained using Monte-Carlo analysis and mismatch data provided by the foundry. For N=1000, VT ,N = 5.5%, VT ,P = 2%, ,N = 10% and ,P = 6%,

3.4. Discussions

33

a minimum CSR of 40 dB (only for 0.8% cases) was obtained. CSR for dierential circuit (Fig. 3.12) is presented in Fig. 3.16 for the same values of process variations and N=2000. Here the minimum CSR was found to be 42 dB (only for 0.44% cases).

CSR Spurs
fRO fRO

M fRO

2M fRO

Figure 3.14: Spurs at the frequency multiplied output. fRO is ring oscillator frequency and M, the multiplication factor

Mismatch Analysis 180 160 140 No. of occurences 120 100 80 60 40 20 0 30

40

50 60 CarriertoSpur Ratio (in dB)

70

80

Figure 3.15: Carrier to Spur Ratio (CSR) for circuit shown in Fig. 3.9 using Monte Carlo analysis, N=1000, VT ,N = 5.5%, VT ,P = 2%, ,N = 10% ,P = 6% and M=3

3.4. Discussions
Mismatch analysis for differential realization 350

34

300

250 No. of occurances

200

150

100

50

0 30

40

50 60 Carriertospur (in dB)

70

80

Figure 3.16: Carrier to Spur Ratio (CSR) for circuit shown in Fig. 3.9 using Monte Carlo analysis, N=2000, VT ,N = 5.5%, VT ,P = 2%, ,N = 10% ,P = 6% and M=3

3.4.3

Choice of multiplication number, M

As discussed in section 2, values of M greater than 5 do not result in any signicant power saving. A large M rather leads to a larger number of phases in ring oscillator leading to increased level of spurs (at fRO due to more mismatches. Also as the spurs come closer to the desired frequency (as shown in Fig. 3.14), it suers lesser attenuation by the LC tank. It is therefore sucient to discuss the case of M = 3 and 5. The amplitude, phase noise and the tuning curves for dierential realization, M=3 and ZigBee band of 2.4 GHz are shown in Fig. 3.13. The expressions of SSB phase noise for a ring oscillator due to white and icker noise are respectively given by [16] 2kT L(f ) = I 1 1 (N + P ) + VDD Vt VDD f0 f
2

(3.4)

3.4. Discussions 1 4M (VDD Vt )2 KfN KfP + WN LN WP LP

2 f0 f3

35

L(f ) =

(3.5)

where f0 is the frequency of ring oscillator, approximated by f0 assuming square law f0 Cox W (VDD Vt )2 2CLM VDD (3.6) I/C M VDD

Where N and P are thermal noise coecients and KN and KP stand for icker noise coecients. C is the total load on each ring oscillator node and M, the number of stages in the ring oscillator. For M = 5, RO runs at a lower frequency f0 /5 leading to reduction of phase noise (caused by both icker and white noise) by 10log10 (5) 15 dB. When multiplied in frequency, it worsens by the same factor leading to no net change in the phase noise. Also observe that the use of larger number of inverters (3 per stage) does not aect the phase noise of the ring oscillator; The number of stages, M , does not appear in equation (3.5) while in (3.6) the product M W L (total capacitative load) remains constant for any other M but the same frequency. In addition, the noise current sources of switch transistors get modulated by their gate voltage at frequency f RO , which gets ltered out by the LC-tank tuned at 3fRO .

3.4.4

Voltage scaling

The large tuning range of ring oscillator can be alternatively utilized to reduce power by lowering the supply voltage. As the supply voltage is lowered, a larger tuning voltage can be used to restore the ring oscillator to the old frequency. The circuit in Fig. 3.12 can be run down to 1 V supply voltage for 2.4 GHz frequency band of ZigBee transceiver. For this circuit and M=3, at VDD = 1 V and 2.4 GHz, the total

3.5. Summary average current from the supply is 475 A resulting in 20% saving in power.

36

Fig. 3.13 also captures the eect of supply voltage scaling on the amplitude, tuning curve and phase noise for circuit shown in Fig. 3.12 and M=3. For VDD = 1.0 V, the amplitude reduces due to higher IR drop in the switches as their resistance (1/(n (VGate Vt VDS ))) goes up due to lower voltage on their gates (Fig. 3.13(a)). (3.6) predicts that f1.0 = 0.75 f1.2 . For VDD = 1.0 V, the ring oscillator slows down and the band of interest (2.4052.485 GHz) is now covered by applying higher tuning voltage (0.850.95 V)(Fig. 3.13(b)). As the switches contribute little to the phase noise of the multiplied output, their increased resistance at VDD = 1.0 V does not degrade the output phase noise (Fig. 3.13(c)). Since the icker noise corner frequency is around 5 MHz, phase noise at the output at 1 MHz oset has 1/f 3 characterstic. Assuming square law (ID (VGS Vt )2 ) for transistors in the ring oscillator, (3.5) predicts that for a given tuning voltage, phase noise of the ring oscillator at 1 MHz oset will vary as proportional
2 to f0 /(VDD Vt )2 . Since (from (3.6)) f0 varies as (VDD Vt )2 /VDD , L(f ) will vary 2 roughly as (VDD Vt )2 /VDD . This predicts that L1.0 is lower than L1.2 by 0.47 dB

for the same Vtune as seen in the (Fig. 3.13(c)). Near the peak of the LC tank, the phase noise curve takes a slight dip for both VDD = 1.2 V and 1.0 V. For the same output frequency of 2.45 GHz, L varies as 1/(VDD Vt )2 and therefore L1.0 is worse than L1.2 by 2.0 dB.

3.5

Summary

We have proposed a new low-power frequency multiplication technique based on edgecombining. The technique can be used to reduce power in a PLL based frequency synthesizer. Design trade-os involved in design of a low-power edge-combiner have been developed. Also a design example is presented for 2.4 GHz ZigBee transceiver which consumes only 550 W of power from 1.2 V supply. Both single-ended and

3.5. Summary

37

dierential realizations have been developed. Using mismatch data provided by a commercial technology, Monte-Carlo simulations carried out in SpectreRF show that spur suppression upto 40 dB can be easily achieved. The edge-combiner being based on simple MOS transistor (MOST) switches controlled by a digital ring oscillator, voltage scaling can be employed to save power upto 20%. Use of simple MOST switches as against current-commuting dierential MOST pair allows not only lower power, but also high speed and can be used to design oscillators close to fT of a technology with a suitable resonator replacing the LC-tank.

References
[1] Marc Tiebout, A CMOS direct injection-locked oscillator topology as highfrequency low-power frequency divider, IEEE Journal of Solid-State Circuits, vol. 39, no. 7, July 2004 [2] Ali Hajimiri, Thomas H. Lee, Design issues in CMOS dierential LC Oscillators, IEEE Journal of Solid-State Circuits vol. 34, no. 5, pp. 717-724,May 1999 [3] Donhee Ham, Ali Hajimiri, Concepts and methods in optimization of integrated LC VCOs, IEEE Journal of Solid-State Circuits vol. 36, no. 5, pp. 896-909, June 2001 [4] Behzad Razavi and JanMye James Sung, A 6 GHZ 60 mW BiCMOS phase-locked loop, IEEE Journal of Solid-State Circuits vol. 29, no. 12, pp. 1560-1565, Dec 1994 [5] George Chien and Paul R. Gray, A 900 MHz local oscillator using a DLL-based frequency multiplier technique for PCS applications, IEEE Journal of Solid-State Circuits vol. 35, no. 12, Dec 2000 [6] Shwetabh Verma, Jenfung Xu, Thomas Lee, A multiply-by-3 coupled-ring oscillator for low-power frequency synthesis, IEEE Journal of Solid-State Circuits vol. 39, no. 4, April 2004 [7] Nam-Jin Oh, Sang-Gug Lee, Building a 2.4 GHz Radio Transceiver Using IEEE 802.15.4, IEEE Circuits and Devices Magazine, pp. 43-51, Nov/Dec 2005. [8] J. N. Pandey, Sudhir Kudva and Bharadwaj Amrutur, A low-power frequency multiplication technique for ZigBee transceiver, IEEE Int. Conf. on VLSI Design Jan 2007 [9] J. J. Rael and A. A. Abidi, Physical processes of phase noise in dierential LC oscillators, IEEE Custom Integrated Circuits Conference 2000 [10] Emad Hegazi, Henrik Sjoland, Asad A. Abidi, A ltering technique to lower LC oscillator phase noise,IEEE Journal of Solid-State Circuits vol. 36, no. 12, pp. 1921-1930, Dec 2001 [11] A Kral, F. Behbahani and Asad A. Abidi, RF-CMOS oscillators with switched tuning Proc. IEEE Custom Integrated Circuits Conference, Santa Clara, CA, 1998 pp. 555-558 38

References

39

[12] Emad Hegazi, Asad A. Abidi, Varactor characterstics, oscillator tuning curves, and AM-FM conversion, IEEE Journal of Solid-State Circuits vol. 38, no. 6, pp. 1033-1039, June 2003 [13] Henrik Sjoland, Improved switched tuning of dierential CMOS VCOs, IEEE Transactions of Circuits and SystemsII vol. 49 no. 5 May 2002 [14] Rofougaran, Single-chip 900 MHz spread-spectrum wireless transceiver in 1 m CMOSPart 1: Architecture and transmitter design, IEEE Journal of SolidState Circuits vol. 33, no. 4, April 1998 [15] Shenggao Li, Issy Kipnis and Mohammed Ismail, A 10 GHz CMOS quadrature LC-VCO for multirate optical applications, IEEE Journal of Solid-State Circuits vol. 38, no. 10, pp. 1626-1634, April 1998 [16] Asad A. Abidi, Phase noise and jitter in ring oscillators, IEEE Journal of Solid-State Circuits vol. 41, no. 8, pp. 1803-1816, August 2006

Chapter 4 Layout Issues

Various issues involved in layout of the frequency multiplier circuit developed in the previous chapter are discussed. Particularly important is the issue of degradation in carrier-to-spur ratio (CSR) due to layout related asymmetries in the ring oscillator.

S brought out in the chapter-3, asymmetries in the ring oscillator (RO) lead to spurs at frequency-multiplied output. These asymmetries are caused by

process-induced mismatches in the inverters in the ring oscillator and layout related issues such as interconnect length between successive stages of the ring oscillator. The use of long lengths of interconnects to keep the wirelength same between two inverters is not the correct way to achieve symmetry as it slows down the ring oscillator which has be compensated with extra power in the RO. Fig. 4.1 shows the schematic of a M = 3 frequency multiplier. A digital ring oscillator with 9-stages is used to obtain three equally spaced phases, A, B and C. Thus the phase spacing between any adjacent pair of phases is governed by the delay of 3 inverters. The three phases are then combined using a switch network shown in Fig. 4.1(a). Fig. 4.2 describes the oor plan of the inverter stages in the ring and the cascaded switches that aims at minimizing the interconnect length while targetting layout symmetry. The three switching legs are interleaved in circular fashion between the three stages of the ring oscillator where each stage consists of three inverters. Fig. 4.3 is the cropped layout of multiplier-by-3 circuit of Fig. 4.1. Inductor, capacitor and tail current source have been omitted in order to clearly display the 40

41

11nH

314f F

A1

B1

C1

B1

C1

A1

6m 0.12m

P2
Vbias P1
120m MCS 0.25m

A1

A2

B1

B2

C2

C1

(a)

(b)

Figure 4.1: (a) Single-ended frequency multiplier for M=3 and (b) The low frequency ring oscillator; NMOS is sized 2 m/0.2 m and PMOS is sized 4 m/0.2 m.

A1

B1

A1

A2

B1

B2

A1

C1 C2 C1

C1

B1

Figure 4.2: Symmetric oor plan for layout of the multiply-by-3 circuit.

arrangement of inverters and switches. Foundry supplied circular planar inductor has been used. Common centroid layout of the current source has been done.

4.1. Simulation of layout extracted netlist

42

Figure 4.3: Layout of the ring oscillator and cascaded switches; Inductor, capacitor and tail current source in the full multiplier circuit are not shown here in order to clearly display the arrangement of inverters and switches.

4.1

Simulation of layout extracted netlist

To compensate for the extra layout parasitics, we had to increase the size of inverters from (PMOS 1.5 m/0.2 m, NMOS 0.75 m/0.2 m) to (PMOS 4 m/0.2m,

4.1. Simulation of layout extracted netlist

43

NMOS 2 m/0.2 m) in order to cover the tuning range of 2.0 GHz to 3.0 GHz. Consequently the power consumption has gone up to 766 A from 478 A obtained from the schematic simulation. This of course has improved the phase noise to 104.2 dBc/Hz at 3.5 MHz oset and has helped with CSR since the larger area of inverters leads to less mismatch. The whole multiplier is able to run down to 1 V of VDD while meeting the desired frequency and phase noise targets. Table-4.1 summarizes the performance of the circuit obtained from SpectreRF simulation of the layout-extracted netlist. The circuit is able to operate from supply voltage upto 1.0 V while covering the 80 MHz wide ZigBee band at 2.4 GHz center frequency. At VDD = 1.0 V, the circuit draws 495 A of current from the supply while the amplitude at the FM output drops to 317 mV due to larger IR drop in the switches. Table 4.1: Performance Summary This Work, M=3, This Work, M=3, VDD =1.2 V VDD =1.0 V Amplitude 452 mV 317 mV Current drawn from 766 A 495 A supply Phase Noise (dBc/Hz at -90.4 -82.5 1 MHz oset) Phase Noise (dBc/Hz at -102.4 -94.6 3.5 MHz oset) Frequency 2.45 GHz, L=11 nH and 0.13 m technology

After considering the worst case mismatch between inverters, the worst-case CSR is found to be 34 dB which is 6 dB lower than that obtained from the schematic simulation.

Chapter 5 Quadrature Generation Methods For Frequency Multiplication Based Oscillators

This chapter compares two methods of generating low-power quadrature sinusoids for oscillators based on frequency multiplication. The rst method involves an even stage ring oscillator running at lower frequency and uses appropriate edge-combining to generate the quadrature signals. The second method simply employs a polyphase lter after the dierential frequency multiplier. To achieve low-power of operation, power-hungry buers are excluded by design optimization. For high quadrature precision, injection-locking property of quadrature oscillators which desensitizes the I Q imbalance, as originally proposed by Kinget et al. is exploited. SpectreRF simulations indicate that the second method uses moderately high power and area for comparable amplitude and phase noise, and yields very small phase error which is unachievable using the rst method.

5.1

Introduction

N image-reject radio receiver architectures, precision of the quadrature LO often limits the achievable image cancellation. The accuracy of amplitude and phases of

quadrature signals is limited due to the presence of process variations in both active and passive devices in modern CMOS technologies. This has made the task of on-chip high-precision RF LO generation very hard. A measure of quadrature amplitude and phase accuracy is given by Image-reject Ratio (IRR) dened as (Pim /Psig )Out normalized to (Pim /Psig )In , where Pim and Psig

44

5.1. Introduction

45

are image and signal powers respectively. For small mismatch in amplitude, A and phase imbalance, , IRR can be written as [1] (A/A)2 + 2 4 (5.1)

An IRR of about 35 dB is found sucient which translates to roughly 2.5% of amplitude mismatch and 1.5 of phase imbalance. However (5.1) is valid for an ideal multiplicative mixer and small A and . For a hard-switching mixer, eect of A is much reduced and phase error, limits the IRR. Ignoring the eect of amplitude mismatch, phase mismatch must be limited to 2 to achieve 35 dB of IRR. This chapter compares two methods of quadrature generation for oscillators based on the concept of frequency multiplication that works on the principle of edgecombining. The rst method involves using an even-stage ring oscillator [8] which generates a set of low-frequency edges that can be judiciously combined by two edgecombiners to generate the respective multiplied I and Q signals. The second method uses a polyphase lter following the edge-combiner to generate the quadrature phases. This can be optionally followed an injection-locked QVCO (IL-QVCO) to achieve better quadrature accuracy [9]. Section 5.2 evaluates the method of quadrature generation based on edgecombining the phases from an even-stage ring oscillator. Section 5.3 discusses the technique of using polyphase lter for quadrature LO generation and brings out the issues involved in its design, particularly the eect of exclusion of buers. Section 5.4 addresses the issue of high-precision quadrature generation and discusses I-Q imbalance desensitization scheme based on injection locking, originally proposed by Kinget et al. [9]. Conclusions are drawn in section 5.5.

5.2. Quadrature Frequency Multiplication Using Even-Stage Ring Oscillator

A1 A2 A3

46
I7

I2

I3

I4

A4

I5

A5

I6

A6

I8
A7 A8

I9
A9

I10
A10

I11
A11

I12
A12

I1

Figure 5.1: Six stage dierential ring oscillator of Junfeng Xu et al. [8]. Size ratio of cross-coupling inverters to ring inverters is kept at 0.6.

5.2

Quadrature Frequency Multiplication Using Even-Stage Ring Oscillator

5.2.1

Combining Current Pulses

VDD

L=11 nH C=320 fF

L
IP QP IN QN

159

2 6 10

3 7 11

12 4 8

Coupled Inverter Ring Oscillators @ 800 MHz

Figure 5.2: Frequency multiplier of Xu et al. [8] that combines current pulses from a low-frequency ring oscillator. The 12 inverters in the ring oscillator are grouped into 4 sets with each having 3 inverters. Power nodes of each inverter in a set are connected to an LC-tank.

To generate I and Q signals from a edge-combiner, one would require N equally

5.2. Quadrature Frequency Multiplication Using Even-Stage Ring Oscillator

47

spaced phases from the ring oscillator where N is the minimum-common factor of 4 and M , M being the desired factor of multiplication. While even stage RO is convenient to design using diential amplier as a unit, the edge-combiner for such RO, as brought out in chapter-3 is not power ecient. Recently Xu et al. [8] have published even-stage RO based on digital inverters that makes the design of lowpower quadrature edge-combiner a feasibility. Fig. 5.1 shows a 6-stage dierential ring oscillator (DRO) intended to achieve quadrature multiplication by a factor of 3. The quadrature frequency multiplier (QFM) proposed by Xu et al. [8] is shown in Fig. 5.2. It uses four sets of top nodes (VDD ) of 3 inverters each in the ring oscillator, each tied to an LC-tank. Current pulses from each of the 3 inverters are drawn from the supply as the corresponding inverters go through a 1 0 transition. Each tank is tuned at frequency M fRO which lters out the harmonics in the combined current pulse. Even though the edge-combiner is built into the ring oscillator itself and does not require any extra transistors, the circuit suers from the fundamental limitation of small voltage swing at the high-frequency output. When implemented in 0.13 m technology, it could only achieve a amplitude of 104 mV operating from 1.2 V power supply. Additional power and area is required to amplify this signal which makes it a power hungry scheme. Table-5.1 compares the performance of quadrature frequency multiplier based on 12-stage ring oscillator using our approach and that of Xu et al. To amplify the signals obtained from the approach of [8], we have used inductive peaked cascode buers each consuming 500 A of current for amplication by a factor of 4.5 (Fig. 5.3). The buer uses additional positive feedback to boost gain by enhancing Q of the LCtank. Size ratio of cross-coupled PMOS pair, M7 M8 , to current-source load transistors M5 M6 is kept at 0.25 to prevent oscillations. Cascode transistors have been used to provide good reverse isolation. Performance of both these circuits is given in Columns 2 and 3 of Table-5.1. QFM-1 is the method of Xu, and QFM-2 is simply Xus QFM followed by the I and Q ampliers of Fig. 5.3. The worst case

5.2. Quadrature Frequency Multiplication Using Even-Stage Ring Oscillator

48

VB,1 M7 M5 M6 M8

VB,1

L=11nH C
N1 N2

C=450fF

VB,2

M3

M4

VB,2

In1 M1 M2

In2

P
VBias,tail

MCS

Figure 5.3: Regenerative, inductive-peaked buer to amplify the output of frequency multiplier of Xu et al. It provides a voltage gain of about 4.5 at a bias current of 500 A.

phase error due to mismatches in the LC-tanks of both multiplier and buer, becomes very large. The method also has a huge area penalty (6 inductors). Fig. 5.4 describes the combination of phases that lead to dierential and quadrature implementation of the multiplier circuit. Fig. 5.5 shows the composite switches for a 6-stage DRO, arranged to achieve edge-combining as illustrated in Fig. 5.4. The dierential currents through composite switch pais (SI , SI ) and (SQ , SQ ) are shifted from each other by by T /12 where T is the time period of the 6-stage DRO (Fig. 5.4) At the FM output, this time-shift is equivalent to T /4 or 90 where T , the time period of the frequency multiplied output, equal to T /3, giving rise to quadrature voltage signals at nodes (IP , IN ) and (QP , QN ). Here, there is no fundamental limitation on the achievable voltage swing. Performance of this circuit (labeled as QFM-3) is given in Column 4 of Table-5.1.

5.2. Quadrature Frequency Multiplication Using Even-Stage Ring Oscillator

49

A1

A2 A3 A4 A5 A6

A7 A8 A9 A10 A11

A12 A1 A9 A3 A11 A4 A8 A5 A1 A7 A3 A5 A9 A2 A6 A11 A7

A10 A6

A12 A8

For I phase For Q phase

A4 A12

A2 A6

Figure 5.4: 6-stage dierential ring oscillator phases to generate I and Q signals; Gray phases are complementary to Black ones to achieve dierential operation

A1

A5

A9

A7

A3

A11

A2

A6

A10

A8

A12

A4

A9

A1

A5

A3

A11

A7

A10

A2

A6

A4

A8

A12

SI

SI

SQ

SQ

Figure 5.5: Composite switches to achieve quadrature edge-combining. Each NMOS is sized 6 m/0.12m

5.3. Quadrature generation based on poly-phase lters

50

M1

M2

20m 0.18m

M3

M4

20m 0.18m

L
IP IN QP

L
QN

607f F
C

11nH SI SI

607f F
C

11nH SQ SQ

607f F
C

IDC = 300A
VBias

IDC = 300A
VBias

MCS,1
36m 0.18m

MCS,2
36m 0.18m

Figure 5.6: Quadrature edge-combiner circuit. SI and SI are the in-phase complementary edge-combining switches. Similarly, SQ and SQ are the quadrature-phase complementary edge-combining switches.

Fig. 5.6 shows the schematic of quadrature FM circuit. An important thing to note here is that the multiplied output is likely to exhibit much higher levels of spurs as 12 edges as against 6 of Fig. 5.7 are utilized to generate the frequency multiplied signal. Section 5.4 describes a quadrature desensitization scheme that could be used in association with the quadrature FM to help reduce the eect of quadrature imbalance arising out of mismatches present in active and passive components in the multiplier circuit.

5.3

Quadrature generation based on poly-phase lters

Poly-phase lters can be used as a quadrature splitter after the dierential frequency multiplier of [3] shown in Fig. 5.7. Here one could opt for an allpass or a RC-CR polyphase network with dierent power-area-performance trade-os. Traditionally this solution is found to be power-hungry as buers are needed between VCO and

5.3. Quadrature generation based on poly-phase lters

51

M1

M2

20m 0.18m

L
N1 N2

607f F
C

11nH S S

607f F
C
A B

IDC = 300A
VBias

MCS

36m 0.18m

Figure 5.7: Frequency multiplier that combines edges from a low-frequency ring oscillator. S and S are the complementary edge-combining circuits. A, B and C are the three phases from a 3-stage ring oscillator. A, B and C denote the complementary phases.

the lter network, and lter and the mixer load. Polyphase lters are certainly a very attractive solution if we could eliminate at least some of the buers. RC CR polyphase lters also oer reduced-area (hence cost) advantage over other methods. Allpass passive network and RC CR sequence asymmetric lters, the two categories of lters used for quadrature generation, are briey described below covering various trade-os involved in their design: 1. Allpass passive network A rst order all-pass lter transfer function is given by H(s) = H0 1 s/p 1 + s/p (5.2)

at = p , H(s) = H0 90 A salient feature of all-pass network is that there is no loss in the lter. H(s) can be implemented either with constant-resistance lattice

5.3. Quadrature generation based on poly-phase lters symmetric network or using miller capacitance in a cascode amplier [11].

52

Q+

Cm

Vb

Cm

ZA ZB

M1

M2

I+
P
V2
ZL

V1 Zin
ZB ZA

VBias
TCS

(a)

(b)

Figure 5.8: (a) A constant resistance lattice network and (b) Allpass lter of Shaeer et al. [11] For circuit shown in Fig. 5.8(a) Zin = 1 (ZA ZB )2 (ZA + ZB ) 2 ZA + ZB + 2ZL V2 ZL (ZB ZA ) = V1 2ZA ZB + ZL (ZA + ZB ) (5.3)

(5.4)

When ZA + ZB = 0 and ZL = |ZA | = R equations 5.3 and 5.4 lead to V2 /V1 = 1 90 and Zin = R. In other words, input impedance is equal to load resistance and lter loss is 0 dB. For circuit shown in Fig. 5.8(a), 1 Vout = g m RP Vin 1+
sCm gm sCm gm

(5.5)

Where RP represents losses in the tank. When gm RP = 1 and = gm /Cm , Vout /Vin =

5.3. Quadrature generation based on poly-phase lters

V+
IP

53

QP

V+

R C R

I
V
IN

QN

Q
R1 , C 1 R2 , C 2

(a)

(b)

Figure 5.9: (a) 1-stage poly-phase filter (PPF) and (b) A 2-stage PPF with staggered poles 1 90 For constant resistance lattice network, the output load has to be resistive for which 2 extra inductors have to be used to cancel out the capacitative load of the mixer input transistors. Also, inductor has large parasitic capacitance and series resistence leading to disturbance of quadrature relation. Even though the amplitude and phase errors resulting from parasitics can be compensated by putting equivalent series resistance in capacitative branch [12], the method takes just too many inductors and hence is not cost-eective. Method of Shaeer et al. requires precise values of Miller capacitance and gm , both hard to control in modern CMOS processes. 2. RC-CR polyphase network For 5.9(a) 1 V+ 1 + sCR sCR V 1 + sCR

VQ = and VI =

5.3. Quadrature generation based on poly-phase lters VI = sCR VQ

54

It is clear that only at a single frequency 1/2RC, do we get perfect quadrature. For the unloaded lter, at = 1/RC, VQ /V+ = 1/ 2, there is 3 dB loss. With PPF loaded with an R or C load, this loss would be bigger. Even for narrowband operation, large process variations in resistors and capacitors force one to use several (at least 2) stages of polyphase lter with staggered poles, leading to large attenuation in the LO signal. This leads to larger power dissipation in the buers used to drive the mixer load. To save some power, the LO buer is usually resonator-loaded which, in addition to larger area, is prone to common mode instability problem when used with Gilbert mixer [2]. Traditionally, buers are also placed between VCO and the lter to avoid lter loading the tank and degrading its Q. However this approach is the legacy of discrete component radio design where highly optimized and standardized o-the-shelf components are assembled to design the radio. In IC technology, there is no need to go for standardized interfaces and the whole radio can be designed as one unit for maximum returns on power, area and performance [13]. In case of quadrature VCO design using polyphase lter (PPF), one could consider removing the intermediate buer if the extra power spent in regaining the unloaded oscillator amplitude and phase noise is less than what is spent in the buer. For 2.4 GHz VCO, RC = 1/2f0 = 6.63 1011 s, choosing C = 100 f F, R = 663 . If RP = 1.25 k for dierential operation (5.9(b)) RP R = 643 RP /2. This means that by doubling the bias current in the VCO, we can replenish the amplitude thereby completely removing the buer. For a constant-resistance lattice network (Fig. 5.8 (b)), Rin = Rload = |ZA | = L. For the commercial technology that we have used, the maximum value of high-Q circular planar inductor is 11nH. At 2.4 GHz this leads to Rin 166 and the loaded VCO tank impedance at f0 is RP R = 146.5 RP /8.5. Removing buer would mean exorbitant price of 750% increase in power. Apart from their area advantage,

5.4. High-precision quadrature generation based on injection-locking

55

RC-CR PPFs, therefore, score over their passive allpass counterparts in this respect. Even though the allpass lters have zero loss, their input impedance is lower resulting in disproportionately high power penalty. In the rest of this chapter, we will therefore only deal with RC-CR PPFs. Considering a mixer load of roughly 100 f F, and a two-stage PPF with staggered pole frequencies around 2.4 GHz, the VCO signal is attenuated by 70-75%. This necessitates amplifying buers to drive the mixer load. Please note that a small LO signal will not only reduce the mixer gain, but will also worsen its noise performance [14]. The high-frequency amplifying buers increase both area and power. The most important issue in the use of LO ampliers for quadrature signals is that they also amplify the amplitude error by the same factor. Also their nite linearity contributes to LO spurs. Mismatches in the active devices and passive components in I and Q buers further degrade the quadrature amplitude and phase relationship. The solution to quadrature imbalance contributed by mismatches in I and Q LO buers is to employ injection-locked oscillators that have the useful property of desensitizing I Q imbalance caused due to variation in both the injection signal and its own components. In the next section, we describe design of a quadrature error desensitization circuit that does the dual job of providing good LO swing as well as improved quadrature balance.

5.4

High-precision quadrature generation based on injection-locking

5.4.1

Injection-locking as a desensitizer for I-Q imbalance

Recently Kinget et al. [9] have demonstrated that more than an order of reduction in both amplitude and phase error can be achieved by injection-locking a QVCO even when the QVCO itself has some mismatches in its I and Q parts. A brief introduction

5.4. High-precision quadrature generation based on injection-locking to phenomenon of injection locking is given in appendix-A.

56

In this scheme, roughly quadrature signals are generated using PPF (I1 , Q1 ). Output of PPF is used to injection-lock a quadrature VCO that itself might have a small I Q imbalance. Due to desensitization eect of injection-locking, (I2 , Q2 ), the output of QVCO, will have smaller amplitude and phase errors.
P P F
I1 I1
Injection

Frequency

@f
Ring VCO

Multiplier XM

@M f

I2 I2
locked QVCO

Q1 Q1

Q2 Q2

Highprecision quadrature output

Figure 5.10: Injection-locked QVCO and frequency multiplier. (I2 , Q2 ) have smaller quadrature imbalance than that in (I1 , Q1 ).

Mcp,1
IP,inj
QN

Mcp,2
QP IP IN

M3

M4

N1
VC
L1 L1
IN

QP,inj
C VC
IP

QP

QN

IN,inj

IP,inj
M1 M2

IN,inj

QP,inj

QN,inj

N2
VC

MIP,inj
P1

MIN,inj

MQP,inj
P2

MQN,inj

QN,inj

VBias
VC

I
MCS,1

VBias
MCS,2

RF , C F

Figure 5.11: A connected-source QVCO with parallel cross-coupling PMOS transistors, MCP,1 and MCP,1 . Parallel NMOS devices MIP,inj and MIN,inj are used to injection lock the QVCO. N1 and N2 directly come from frequency multiplier described in Fig. 5.7, without any intermediate buers. One stage of PPF generates the approximate quadrature signals that are added to a suitable common-mode voltage before injection locking the PQVCO. VC provides the common-mode level.

However, a valid criticism of injection-locking is that it is essentially a narrowband process and a large lock bandwidth is required to cover the required frequency

5.4. High-precision quadrature generation based on injection-locking

57

range due to large variations in modern CMOS processes. A large lock bandwidth in turn means a stronger injection signal. However as discussed earlier, due to large attenuation in two-stage polyphase lter, the amplitude of the output of PPF is too small ( 100 mV) to reliably injection-lock the quadrature VCO. However, since the desensitization process yields a large quadrature improvement, only one stage of polyphase filter can be used to generate the quadrature injection signal. The amplitude of output of one-stage PPF is suciently large ( 200 250 mV) to achieve a lock bandwidth of over 200 MHz. Fig. 5.10 depicts the use of single-stage polyphase lter and injection-locked QVCO. Fig. 5.11 contains the schematic of PPF and IL-QVCO combination which follows the dierential FM of Fig. 5.7. Column-5 of Table-5.1 contains the performance summary of the circuit (labeled as QFM-4). The phase error of 0.5 is achieved for the worst case mismatch in the polyphase lter and 1% mismatch in QVCO LC-tanks. Table 5.1: Performance Comparison QFM-1, Fig. 5.2 Amplitude 104 mV Phase noise (dBc/Hz -88.1 @ 1 MHz) Phase mismatch (in 2.8 degrees) Carrier-to-spur ratio 37 (in dB) Current drawn from 188 A supply No. of inductors 4 No of stages in RVCO 12 Use of IL-QVCO Not used QFM-2, Fig. 5.2, 5.3 468 mV -88.2 9.8 56 1188 A 6 12 Not used QFM-3, Fig. 5.6 460 mV -89.4 4.9 43 1039 A 2 12 Not used QFM-4, Fig. 5.7, 5.11 480 mV -84.3 0.5 61 1300 A 3 3 Used

Frequency 2.45 GHz, M = 3 and 0.13 m technology

Comparing the results summarized in Table-5.1, we can draw the following

5.5. Summary

58

conclusions. QFM-4 (Column-5 of Table-5.1) needs three inductors, has moderate power consumption achieved by elimination of intervening power-hungry buers and yields very high-precision quadrature sinusoids unachievable using other methods. The method of Xu et al. (Column-2, QFM-1) is area intensive and has severe constraint on the achievable voltage swing. Use of ampliers (Column-3, QFM-2) leads to large increase in both power and area and a simultaneous degradation in the quadrature precision.

5.5

Summary

We have explored quadrature generation techniques for oscillators based on the concept of frequency multiplication. We have compared two primary techniques for their power and performance. We have demonstrated a low power, high-precision quadrature generation method that is based on polyphase lter and uses injection-locked quadrature VCO that serves both as buer and reduces the quadrature phase error. For the worst case mismatch in the polyphase lter and 1% mismatch in the LCtanks of the QVCO, phase error is below 0.5 . The circuit draws 1.3 mA from 1.2 V supply and provides quadrature sinusoids of amplitude 480 mV with a phase noise of -84.3 dBc/Hz at 1 MHz oset.

References
[1] Behzad Razavi, RF Microelectronics, Prentice Hall [2] S. Gueorguiev, S. Lindfors, T. Larsen, Common-mode stability in Low-power LO drivers, IEEE International Symposium on Circuits and Systems, pp. 5505-5508 vol. 6, May 23-26, 2005 [3] J. N. Pandey, Sudhir Kudva and Bharadwaj Amrutur, A low-power frequency multiplication technique for ZigBee transceiver, IEEE Int. Conf. on VLSI Design Jan 2007 [4] T.D. Stetzler, I.G. Post, J.H. Havens, M. Koyama, A 2.7-4.5 V single chip GSM transceiver RF integrated circuit, IEEE Journal of Solid-State Circuits vol. 30, no. 12, pp. 1421-1429, December 1995 [5] George Chien and Paul R. Gray, A 900 MHz local oscillator using a DLL-based frequency multiplier technique for PCS applications, IEEE Journal of Solid-State Circuits vol. 35, no. 12, Dec 2000 [6] Behzad Razavi and JanMye James Sung, A 6 GHZ 60 mW BiCMOS phase-locked loop, IEEE Journal of Solid-State Circuits vol. 29, no. 12, pp. 1560-1565, Dec 1994 [7] Shwetabh Verma, Jenfung Xu, Thomas Lee, A multiply-by-3 coupled-ring oscillator for low-power frequency synthesis, IEEE Journal of Solid-State Circuits vol. 39, no. 4, April 2004 [8] Junfeng Xu, Shwetabh Verma, and Thomas H. Lee, Coupled inverter ring I/Q oscillator for low power frequency synthesis, IEEE Symp. on VLSI Digest of Technical Papers, 2006 [9] Peter Kinget, Robert Melville, David Long and Venugopal Gopinathan, An injection-locking scheme for precision quadrature, IEEE Journal of Solid-State Circuits vol. 37, no. 7, pp. 845 - 851, July 2002 [10] Sherif H. Galal, Hani F. Ragaie, and Mohamed S. Tawfik, RC sequence asymmetric polyphase networks for RF integrated transceivers, IEEE Transactions of Circuits and SystemsII vol. 47 no. 1 January 2000

59

References

60

[11] Shaeer, D.K. et al., A 115 mW, 0.5 m CMOS GPS receiver with wide dynamic-range active filters, IEEE Journal of Solid-State Circuits vol. 33, no. 12, pp. 2219 - 2231, December 1998 [12] Christensen, K.T., LC quadrature generation in integrated circuits, IEEE International Symposium on Circuits and Systems vol. 1, 6-9 May 2001 [13] M. Borremans, B. De Muer, and M. Steyaert, The optimization of GHz integrated CMOS quadrature VCOs based on a polyphase filter loaded dierential oscillator, IEEE Int. Symp. on Circuits and Systems, May 28-31, 2000, Geneva, Switzerland [14] Hooman Darabi, and Asad A. Abidi, Noise in RF-CMOS mixers: A simple physical model, IEEE Journal of Solid State Circuits, vol. 35, no. 1, pp. 15-25 January 2000

Chapter 6 On Frequency Shifts in Cross-Coupled LC-VCOs

This chapter analyzes the observed shifts in frequency of oscillation from 1/2 LC in conventional cross-coupled parallel LC-VCOs (PQVCO). Very accurate and closed-form expressions of the frequency shifts caused due to twin eects of Groszkowski eect and quadrature detuning eect are derived for practical PQVCOs that are built using low/moderate-Q on-chip inductors. Judicious approximations are made to keep the expressions simple yet accurate. Three possible modes of oscillations are derived and the dominant mode selection is demonstrated. Expression for amplitude of oscillation is also evaluated. The results obtained from the expressions are validated against the behavioral model simulation of the PQVCO in SpectreRF and Matlab.

6.1

Introduction
ERY stringent requirement on local-oscillator phase noise in commercial wireless standards, and development of on-chip inductor have led to emergence of

LC-oscillator as the foremost choice for on-chip LO generation. Albeit at the cost of much larger area, these LC-VCOs oer much superior noise and power performance, unattainable in ring oscillators. Due to its simple yet robust operation, negative resistance cross-coupled MOS transitor circuit has become the most popular on-chip LC-VCO. To a good approximation, the frequency of oscillation of this VCO can be written as 1/2 LC. However, due to the moderate quality factor (Q) of the on-chip inductor, the actual frequency is a little less than it. This eect is known as

61

6.2. Behavioral modeling of LC-oscillators and Groszkowski Eect Groszkowski eect named after its eponymous discoverer.

62

Generation of high precision quadrature LO signals is a pre-requisite for imagereject receiver architectures [1]. Quadrature oscillator topologies are a very attractive approach to realize quadrature sinusoids [2] [3]. It consists of two dierential negative resistance LC oscillators that are coupled using coupling transistors (M3 M4 ) in parallel to core negative resistance MOS pair (M1 M2 ) to force quadrature (Fig. 1). But in order to satisfy the Barkhausens criteria, the LC-tanks operate at a frequency away from the frequency of resonance. In other words, the equivalent quality factor gets degraded. This eect called as quadrature detuning eect results in higher phase noise and reduced amplitude. The existing models to predict the frequency shifts are inaccurate for moderate Qs [3] [4] [5]. This is because the approximation of series-toparallel transformation of lossy inductor is a narrowband one while the actual shifts for practical circuits can be quite large depending upon the coupling strength and Q. Also the shift due to Groszkowski eect is usually not taken into consideration which can again be signicant for low Q oscillators. In this chapter, we have have addressed both these issues and developed accurate and closed-form expressions for frequency shift and amplitude of oscillation. The rest of the chapter is organized as follows. Section 6.2 covers the behavioral modeling of LC-oscillators and Groszkowski Eect. Section 6.3 presents the analysis of quadrature-detuning eect and developes closed-form expressions for frequency shifts and amplitude of oscillation. Conclusions are drawn in section 6.4.

6.2

Behavioral modeling of LC-oscillators and Groszkowski Eect

In negative resistance LC oscillators built using moderate quality factor LC-tanks, the actual frequency of oscillation is somewhat less than 1/2 LC. This is due to the fact that the current pulse injected into the tank is rich in harmonics and these

6.2. Behavioral modeling of LC-oscillators and Groszkowski Eect

63

L C
QN QP

L C C
IN IP

IP

M3

M4

IN

M1

M2

QN

QP

Gmc mIBias IBias

Gmc mIBias IBias

Figure 6.1: A conventional disconnected-source quadrature-coupled LC oscillator

harmonics suer only moderate attenuation due to not-so-high Q of the tank. These current harmonics ow into the capacitance branch and disturb the energy balance in the tank. This leads to reduction in frequency of oscillation that restores the energybalance. This phenomenon is known as Groszkowski eect [6]. The authors in [7] present an equation for frequency shift f as 1 f = f0 2Q2

k=2

k 2 (1 k 2 ) p2 (1 k 2 )2 + k 2 /Q2 k

(6.1)

Here Q is the quality factor of the tank, and pk is the normalized level of k th current harmonic (Ik /I1 ). f0 = 1/2 LC and f = fg f0 where fg denotes the nal frequency of oscillations after the Groszkowski eect has been taken into account. However (6.1) assumes high Q inductor and capacitor. While the assumption is somewhat justiable for on-chip capacitors, on-chip inductors exhibit only moderate Qs which leads to substantial error in predicting fg using (6.1). We will now derive a more accurate expression that holds good for tanks comprising of low/moderate Q inductors. The fundamental equation given by Groszkowski is

1+
k=2

k p2 k

Zk Z1

=0
im

(6.2)

6.2. Behavioral modeling of LC-oscillators and Groszkowski Eect

64

Where |Zk |im is the imaginary part of tank impedance for k th harmonic frequency. Transfer function of the tank is (Fig. 6.2(a))
sQ 0 s2 2 0

H(j) = Rs

+1 +1

s Q0

(6.3)

Where 0 = 1/ LC and Q = 0 L/Rs . Using (6.3) Zk Z1 k2 1

1 Q2
2

=
im

k2 2 2 0 k 2 0 Q

1 k 2 2 +
0

2 2 2 0 1 Q2

2 0 Q 2 2 0

(6.4)

Assuming Q >> 1 and 0 (4) can be reduced to Zk Z1 =

im

k 2 (1 k 2 ) 1/Q2 2 (1 k 2 )2 + k 2 /Q2 1 2
0

(6.5)

Anticipating a small frequency shift, in derivation of (6.1), 1

1 Q2

2 2 0

in (6.4) is

approximated as 2/0 which when substituted in (6.2), leads to (6.1). However since the frequency shifts are very small and Q only moderate, the error in approximating 1
2 2 0

as 2/0 is comparable to 1/Q2 (denominator of (6.4)) which

gives an inaccurate answer to frequency shift. A much better approximation is to perturb the equation around n for which the Zim , imaginary part of tank transfer function is zero. Zim = j RS Qn 1 0 1
2 n 2 2 0

1 Q2

2 n 2 0 n 2 0 Q

=0

(6.6)

Simplifying and substituting Q2 = L/CR2 , n = 1 LC R2 C L

(6.7)

6.2. Behavioral modeling of LC-oscillators and Groszkowski Eect Let = n . Now, 1

1 Q2

65

2 2 0

can be better approximated as n 2 0

2 Substituting in (6.2), f0 1 f = f0 fn 2Q2

k=2

k 2 (1 k 2 ) p2 (1 k 2 )2 + k 2 /Q2 k

(6.8)

fg = fn + f

(6.9)

This frequency is considerably lower than the natural frequency of oscillations fn for which the tank producs zero phase shift. At fg the phase curve of the LC-tank will exhibit a positive angle. Fig. 6.3 illustrates the same.

V -R LP
C

Ls RS
(a)

(b)

Figure 6.2: (a) RS is the extra-series resistance of the inductor. Capacitor is assumed to have high Q (b) Negative resistance LC-oscillator

Assuming that the cross-coupled MOS transistor pair (used to realize negative resistance) switches the tail current almost abruptly such that the current injected into the tank is a square wave (of amplitude IT /2 where IT is the tail current).

6.2. Behavioral modeling of LC-oscillators and Groszkowski Eect

66

|H(j)| (in s)

850
(f ,821.85)
g

(fn,829.16)

(f0,845.58)

800 750 9.36 10

10

9.37

10

9.38

10

9.39

Frequency (in Hz)

H(j) (in Degrees)

50
(fg,)

0
(f ,0)
n

(f ,tan (1/Q))
0

50 9.36 10

10

9.37

10

9.38

10

9.39

Frequency (in Hz)

Figure 6.3: f0 = 2.4 GHz, fn , the natural frequency of oscillation = 2.3508 GHz, fg the Groszkowski frequency=2.3412 GHz. = 2.25 and Q=5.

Amplitude of k th current harmonic, pk is 2 1 cos(k) IT k 2 which results in pk,odd = 1/k; pk,even = 0 (6.11) (6.10)

The nonlinear negative resistance in Fig. 6.2(b) is modeled as an i v equation, i = S tanh(Gn v/S) where Gn is the small signal negative conductance. S is a measure of nonlinearity of the negative resistance and is analogous to the tail current source in LC-VCOs. |Gn | is greater than 1/RP for start-up. Let L=11nH, C=400fF so that f0 = 1/2 LC = 2.4 GHz. Let Q = 5 (at f0 ), S = 0.01, and Gn = 0.01 for an almost abrupt switching. fn = 2.3508 GHz (6.6).

6.3. Behavioral modeling of cross-coupled LC-VCOs and Quadrature Detuning Eect 67 Taking 3rd , 5th , 7th and 9th harmonics, (6.9) predicts the frequency of oscillations as 2.3411 GHz while (6.1) yields 2.3904 GHz. SpectreRF simulation gives 2.3412 GHz which is almost identical to our results. Also notice that (6.1) is in gross error. Let be the phase shift caused by Groszkowski eect. Fig. 6.3 depicts the three frequencies, f0 , fn and fg and phase shift for the above descibed parameters for the negative resistance oscillator of Fig. 6.2 (b).

6.3

Behavioral modeling of cross-coupled LC-VCOs and Quadrature Detuning Eect

The biggest drawback of this class of quadrature oscillators is that the frequency of coupled-oscillators diers from the natural frequency of oscillations of each oscillator where Tank impedance is maximum. Since the Tank is no longer operating at frequency where its impedance is largest and phase characterstics steepest, amplitude of oscillations decreases and phase noise goes up. A simple model of coupled-oscillators as shown in Fig. 6.1 will help illustrate this. Here, Gmc is the equivalent transconductance of the coupling transistors M3 M4 . Total DC current used in each stage is (m + 1)Ibias where coupling ratio, m = Gmc /Gm . The varactor is assumed to have high Q compared to that of the inductor.

6.3.1

Treatment in literature

Anticipating a small frequency shift, series LR network is transformed to its parallel counterpart (Fig. 6.5) such that Rp = Rs (1 + Q2 ) and Lp = Ls (1 + 1/Q2 ). The ambiguity of whether V1 leads V2 or vice versa, leads to the two possible angles tan1 (m), resultant current vector can make with the reference phasor (Fig. 6.6).

6.3. Behavioral modeling of cross-coupled LC-VCOs and Quadrature Detuning Eect 68

Gm

Gm

Gmc
L

V2 I2

Gmc
C L

V1 I1

RS Tank-1
1

RS Tank-2

Figure 6.4: Equivalent model of the oscillator; Gmc is the transconductance of the coupling transistors M3 M4 and Gmc that of oscillator core transistors M1 M2

Ls RS

C LP

RP

Figure 6.5: Series to parallel tranformation; Rp = Rs (1 + Q2 ) and Lp = Ls (1 + 1/Q2 )

Transfer function of each tank in Fig. 6.5 is given by (3). From Fig. 6.6, 0 Q = tan1 (m) + tan1 2 2 1 2
0

(6.12)

where is the phase contribution due to Groszkowsi eect. Ignoring and simplifying (6.12), 2 m 1=0 2 0 Q 0

6.3. Behavioral modeling of cross-coupled LC-VCOs and Quadrature Detuning Eect 69 Solving for positive roots, one gets [3] [4] 0 2 m + Q m2 +4 Q2

1,2 = Assuming m/Q << 1

(6.13)

1,2 0 1

m 2Q

(6.14)

Owing to asymmetric frequency response of the band-pass lter around 0 , higher frequency osc = 1 = 0 1 + of oscillation. |H(j1 )| Assuming almost abrupt switching, 2 1 + m2 Ibias |H(j1 )| A= (6.16)
2 m 2Q

is selected as it leads to higher amplitude

2 H0 1 + m Q +m Q

m2 + 1

(6.15)

But for high coupling factor m and moderate quality factor, this frequency deviation becomes quite signicant so that the approximation of RP as (1 + Q2 )Rs , Rs involves signicant error. This leads to erroneous values of and tank impedance at this frequency that decides the amplitude of oscillations. For example, for unit coupled oscillators (m = 1) and Q = 5, (6.13) yields = 0.1 0 while the actual value obtained from Matlab and SpectreRF simulation of behavioral model (Fig. 6.7) is 0.0648 0 . Also the value of equivalent resistance at this frequency is Rp = R s Q 0
2

+ 1 = 1.20 Rs (1 + Q2 )

Here, for the approximation of RP as (1 + Q2 )Rs , RP , there is an error of 20%. In reality this error is much more considering the fact that itself is in error. Also for such frequency shifts, the inductive and capacitative impedances dont cancel each other leading to much higher tank impedance that should be used in the calculation

6.3. Behavioral modeling of cross-coupled LC-VCOs and Quadrature Detuning Eect 70 of amplitude.

V2

I2

Gm V 2 GmcV2 I1 tan1m Gm V 1 V1

-V1

-Gmc V1

Figure 6.6: Phasor diagram of cross-coupled LC-VCO topology of Fig. 6.1. m = Gmc /Gm

N1 -R LS
C

N2

N1

N2
C

LS

-R

RS

RS

Figure 6.7: Simple model of a cross-coupled LC oscillator. The coupling transistors M3 M4 (Fig.6.1) are modeled as VCCS with i v equation, i = Sc tanh(v Gnc /Sc )

6.3.2

Our approach

We use the tank impedance of (3) without making the series-to-parallel transformation. From Fig. 6.6 for coupled oscillators,
1

tan

Q 0 Q tan1 2 0 1 2
0

= tan1 (m) +

(6.17)

6.3. Behavioral modeling of cross-coupled LC-VCOs and Quadrature Detuning Eect 71 where is the phase contribution due to Groszkowsi eect. For roots greater than unity, negative sign in (6.17) is taken. Let m1 be am 1 + ma where a = tan. For roots smaller than unity, positive sign in (6.17) is selected and let m2 be dened as a+m 1 ma . Simplifying (17), 0
3

1 1 2 0 Q

m1,2 =0 Q

(6.18)

The exact expression for the roots of the equation is too unwieldy to be used to estimate the dominant frequency of oscillation. However with the help of suitable approximations, we can derive a closed-form expression for the roots of practical interest. Fig. 6.8 pictorially depicts the 3 unique and physical solutions of the equation. Of the three values 3 is the dominant mode as it results in the highest loop gain (smallest attenuation by the tank). Fig. 6.9 illustrates this for Q = 5, m = 1, f0 = 2.4 = GHz. For 3 = 1.0648 0 , the tank impedance is highest at 714.3 . Let /0 be x. x3 x 1 m1,2 1 + =0 2 Q Q (6.19)

Considering that the frequencies of interest f2 and f3 are quite close to f0 , let x = 1 + be a solution where is a small number. For solutions x > 1 or > 0, taking m1 in equation (19) will be yield a real solution. Substituting this value of x

6.3. Behavioral modeling of cross-coupled LC-VCOs and Quadrature Detuning Eect 72

4 3 2 1 0 1 2 3 4 1.5
( 0 ) 3 1 0 (1- Q2 )

m1 =

a -m 1+ma

a+m m2 = 1-ma 1 0 (1- Q2 )

3
m1 Q

1
m2 Q

2 =0

0.5

0 /0

0.5

1.5

Figure 6.8: Solutions of (6.8) showing three positive roots for ; a = tan() where is is the phase shift at Groszkowsi frequency fg ; 1 = 0.23960 , 2 = 0.83780 , 3 = 1.06480 . Also note that compared to 2 , 3 , the dominant frequency is much closer to = 0 line.

in (6.19) and neglecting 3 term, we get 1 2 2 + 1 + 3 2Q2 + 1 1 m1 + 2 3 Q Q =0 (6.20)

Let me be the equivalent coupling factor equal to m1 . me = ma 1 + ma (6.21)

Solving it with the condition that > 0 and assuming Q to be moderately high, = 1 1 1+ 3 2Q2 + 1+ 3me 2 2 Q Q (6.22)

For large Q, small m, and ignoring , can approximated as m/2Q which is the same as that obtained after making the series-to-parallel transformation and neglecting the Groszkowski eect [3] [5]. For the example case of Q = 5 and m = 1,

6.3. Behavioral modeling of cross-coupled LC-VCOs and Quadrature Detuning Eect 73

|H(j)| (in s)

800 600 400 200 0

Q=5 m=1 f0=2.4GHz (f1,54.8)

(f3,714.3) (f2,414.7)

Dominant Mode

10
H(j) (in Degrees)

10
Frequency (in Hz)
1

10

100 0 100
f1 f2

tan (m)+

tan (m)+ f3

10

10
Frequency (in Hz)

10

Figure 6.9: Frequency response of the resonator and dominant mode selection; The phase shift due to Growszkowski eect is = 2.25 and Q = 5. The three modes of oscillations are at frequencies f1 = 526.3 MHz, f2 = 2.010 GHz, f3 = 2.555 GHz

= 0.0648 (corresponding to f3 in Fig. 6.9) while the exact solution from Matlab is also 0.0648. Compare this with the value of 0.1 that equation (6.14) provides. While for real solutions 0 < x < 1 or < 0, m2 in equation (6.19) is used. = 1 1 1+ 3 2Q2 + 1 3m2 2 2 Q Q (6.23)

For Q = 5 and m = 1, = 0.1665 (corresponding to f2 in Fig. 6.9) while the exact solution from Matlab is -0.1622. Fig. 6.10 compares the frequency shifts obtained for Q values of 5 and 10 and coupling factor m between 0.5 and 2. We observe almost exact match between our results and that obtained from SpectreRF.

6.3. Behavioral modeling of cross-coupled LC-VCOs and Quadrature Detuning Eect 74

0.25

Fractional frequency shift

0.2

0.15 Q=5 0.1 Q=10

0.05

0 0.5

1.5

Coupling factor (m)

Figure 6.10: Preformance comparison of both the methods. Dashed lines represents Prior work and solid lines this work. Circles represent the results obtained from SpectreRF. The dierence in results of both methods increase as m increases and narrows down for higher Q.

We next derive the modied expression for amplitude. 1 + (1 + )2 Q2 4 2 Q2 + (1 + )2

|H(j3 )| Rs Q

(6.24)

For Q = 5 and m = 1, (24) gives |H(j3 )| as 721.0 (as against 714.3 from Matlab) Assuming almost abrupt switching, 2 1 + m2 Ibias |H(j3 )| A= (6.25)

Where Ibias is represents the tail current. For unit coupled oscillators (m = 1), Ibias = 2S = 20 mA. Amplitude = 12.99 V which matches closely with SpectreRF simulation (12.74 V) of the behavioral model (Fig. 6.7). Compare this with (6.16) which leads to 11.74 V as the answer.

6.3. Behavioral modeling of cross-coupled LC-VCOs and Quadrature Detuning Eect 75 Table 6.1: Summary of Expressions Old treatment Frequency shift = 0 Tank Impedance |H(j)| Amplitude A= 2 1 + m2 Ibias |H(j1 )| |H(j1 )| = H0 1+
m Q m Q

This work 1 1 1+ 3 2Q2 3me 2 2 Q Q

m + 2Q

m2 +11 4Q2

1+

where me is given by (6.21)

m2 + 1 +

|H(j3 )| = Rs Q

1 + (1 + )2 Q2 4 2 Q2 + (1 + )2

2 1 + m2 Ibias |H(j3 )| A=

16 SpectreRF simulation This work Prior work

15
Amplitude (volts)

14

13 Q=5 12

11 0.5

1.5

Coupling factor (m)

Figure 6.11: Comparison of amplitude obtained using both the methods versus the SpectreRF results. Good match is observed over a wide range of m.

6.4. Summary

76

Fig. 6.11 compares the amplitudes calculated using (6.15) and (6.25) against that obtained from SpecteRF for Q values of 5 and 10 and coupling factor m between 0.5 and 2. We observe good match between our results and that obtained from SpectreRF. Table-6.1 summarizes the important expressions. The Groszkowski eect and quadrature detuning eect are observed clearly in practical circuits but the exact calculation of frequency shifts are hard to make. This is because the precise values of parasitic capacitances are never known and also these capacitances are time varying, making the exact calculation of the equivalent value very hard, if not impossible. Also the precise value of loaded tank quality factor is equally hard to determine.

6.4

Summary

We nd that previous expressions of frequency shifts and amplitude in PQVCOs are quite inaccurate because the series-to-parallel transformation of LR network for such shifts is not justied. Also the neglect of Groszkowski eect adds to this error. We have obtained accurate closed-form expressions for associated frequency shifts taking both the issues into account. We do this by making judicious approximations to keep the expressions simple yet accurate. Graphical analysis is also used to demonstate the involved shifts and three possible modes of oscillations. Expression for amplitude of oscillation is evaluated based on the analysis developed in this chapter. To show their accuracy, the expressions derived are compared against those obtained from the simulation of the behavioral model using SpectreRF and Matlab.

References
[1] Behzad Razavi, RF Microelectronics, Prentice Hall [2] Rofougaran, Single-chip 900 MHz spread-spectrum wireless transceiver in 1 m CMOSPart 1: Architecture and transmitter design, IEEE Journal of SolidState Circuits vol. 33, no. 4, April 1998 [3] Pietro Andreani, Andrea Bonfanti, and Carlo Samori, Analysis and design of a 1.8 GHz CMOS LC quadrature VCO, IEEE Journal of Solid-State Circuits vol. 37, no. 12, pp. 1737 - 1747, December 2002 [4] A. Mazzanti, F. Svelto, P. Andreani, On the amplitude and phase errors of quadrature LC-tank CMOS oscillators,IEEE Journal of Solid-State Circuits vol. 41, no. 6, pp. 1305-1313, June 2006 [5] Ibrahim R. Chamas, Sanjay Raman, A comprehensive analysis of quadrature signal synthesis in cross-coupled RF VCOs,IEEE Journal of Solid-State Circuits vol. 54, no. 4, pp. 689-704, April 2007 [6] J. Groszkowski, The interdependence of frequency variation and harmonic content, and the problem of constant-frequency oscillators,Proc. of the IRE vol. 21, no. 7, pp. 958-981, 1934 [7] J. J. Rael and A. A. Abidi, Physical processes of phase noise in dierential LC oscillators, IEEE Custom Integrated Circuits Conference 2000

77

Chapter 7 Conclusion

O generation based on frequency multiplication (FM) helps in two ways. 1. It solves the problem of LO pulling, experienced prominently in low and zero-IF

receivers. 2. It helps save power in the PLL. We have presented a power-ecient, FM based local oscillator generation technique that combines edges from a lowerfrequency ring oscillator. Techniques found in literature to achieve the same suer from important shortcomings such as constraint on achievable voltage swing, large power and area. We have discussed both single-ended and dierential versions. SpectreRF simulations of layout-extracted netlist of our circuit show that it draws 766 A of current working from 1.2 V supply and provides 450mV of amplitude at 2.4 GHz, and oers phase noise of -90 dBc/Hz at 1 MHz oset. The circuit is operational down to 1.0 V supply. We have next addressed the important topic of quadrature LO generation for oscillators based on frequency multiplication technique. Given the inevitable variation in both passive and active components in modern CMOS processes, high-precision integrated quadrature LO generation is a big challenge. Quadrature error reduction property of injection-locked QVCOs, rst observed by Kinget et al. is a powerful remedy for this. We have discussed the important possibilities and have brought out the pros and cons of each of them. We have developed a low power and low area QFM circuit based on polyphase lter and injection-locked QVCO that generates high-precision, large amplitude I Q sinusiods. The example circuit developed for 2.4 GHz band of 78

79 IEEE 802.15.4 standard, draws 1.3 mA of current from 1.2 V supply and has 0.5 of worst case phase error. However, a comprehensive understanding of quadrature error reduction property is still not developed in literature. Injection-locking (Appendix A) being a nonlinear process, the problem of modeling and quantifying the phenomenon is a dicult problem. Also, one needs to fully grasp the operation of practical cross-coupled QVCOs, to be injection-locked, as a rst step towards modeling the process of their locking. We nd that the existing models predicting their frequency and amplitude of oscillation are in substantial error due to unjustiable assumption on the quality factor of the on-chip inductor. In this line, we have developed an accurate model of quadrature LCoscillator for its frequency shifts and amplitude of oscillations that also accounts for the Groszkowski Eect usually but untenably ignored. This thesis ends with this discussion.

Appendix A Injection-Locking Basics

Injection locking is the phenomenon of a self-oscillatory system (with natural frequency of oscillations, say, f0 ) oscillating at a frequency finj when a signal of such frequency and suciently high amplitude is injected into the system. The amplitude of the input signal (called injection level), quality of the embedded resonator and amplitude of self-oscillations determine the maximum |finj f0 | over which locking still occurs. This maximum value of |finj f0 | is called one-sided lock range. Injection-locking is essentially a non-linear phenomenon but some useful design insights can be obtained from linearized model valid, only for small injection level and small |finj f0 |. Assuming small injection signal Einj and small f = |finj f0 |, we can linearize the system around the natural frequency of oscillation, f0 .

Einj

ET
Saturating Nonlinearity Resonator

Eout

Figure A.1: Simple additive feedback model of the injection-locked oscillator

Let the transfer function of the resonator be

s H0 Q0 s2 2 0

H(j) =

s Q0

+1

80

81

inj Eout ET inj Einj

(a) (b)

Eout

ET Einj

Figure A.2: (a) Phasor diagram of signals shown in Fig. A.1, (b) Position of phasers at the edge of injection-locking when = 90

For frequencies close to 0 , H(j) can be approximated as H(j) = H0 1 + 2Q 0 (A.1)

where Q is the quality factor of the resonator. Taking phasor Einj as a reference, Eout will make an angle with Einj such that the resultant vector ET subtends extacly an angle with Eout , where = tan1 2Q 0 (A.2)

This angle serves to nullify the phase shift caused by the bandpass nature of the resonator. From Fig. A.2(a), sin = Einj sin Eout (A.3)

Near the edge of injection-locking i.e. for the maximum value of f or , sin becomes 1. For larger f or , no orientation of Eout and Einj will be able to generate

82 this angle needed to compensate for the phase-shift in the resonator (Barkhausens criterian). Fig. A.2(b) depicts this situation. For small , tan sin 2Q f . In other words, using (A.3), the lock f0 bandwidth f0 Einj 2Q Eout

f =

(A.4)

This equation originally derived by Adler [1], though oversimplied, gives vital insights into the phenomemon. It says that the lock bandwidth is proportional to the strength of the injected signal, is inversely prortional to quality factor Q of the resonator and amplitude of the self-oscillation. Adler also derived the basic equation governing the dynamics of the system. Let be equal to + . For successful locking, frequency of Eout should be same as that of Einj . Also let inj and out be the instantaneous frequencies of the phasors Einj and Eout respectively. d = out inj dt = 0 inj + out 0 For small injection and f , Eout ET and = 2Q . Also from Fig. A.3(a) 0 sin = Using (A.2), = out 0 = = 0 2Q Einj Einj sin sin ET Eout (A.5)

0 Einj sin 2Q Eout

83 Substituting in A.5, we get d 0 Einj = 0 inj + sin dt 2Q Eout Equation A.6 is analytically solved and vividly interpreted in [2]. (A.6)

References
[1] R. Adler, A study of locking phenomenon in oscillators, Proc. IEEE vol. 61, pp. 1380-1385, October 1973 [2] Behzad Razavi, A study of Injection-Locking and pulling in oscillators, IEEE Journal of Solid State Circuits, vol. 39, no. 9, pp. 1419-1424 September 2004

84