Dfta Ref

Tessent DFTAdvisor Reference Manual
Software Version 9.0 June 2010
1991-2010 Mentor Graphics Corporation All rights reserved.

This document contains information that is proprietary to Mentor Graphics Corporation. The original recipient of this document may duplicate this document in whole or in part for internal business purposes only, provided that this entire notice appears in all copies. In duplicating any part of this document, the recipient agrees to make every reasonable effort to prevent the unauthorized use and distribution of the proprietary information.
This document is for information and instruction purposes. Mentor Graphics reserves the right to make changes in specifications and other information contained in this publication without prior notice, and the reader should, in all cases, consult Mentor Graphics to determine whether any changes have been made. The terms and conditions governing the sale and licensing of Mentor Graphics products are set forth in written agreements between Mentor Graphics and its customers. No representation or other affirmation of fact contained in this publication shall be deemed to be a warranty or give rise to any liability of Mentor Graphics whatsoever. MENTOR GRAPHICS MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS MATERIAL INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL NOT BE LIABLE FOR ANY INCIDENTAL, INDIRECT, SPECIAL, OR CONSEQUENTIAL DAMAGES WHATSOEVER (INCLUDING BUT NOT LIMITED TO LOST PROFITS) ARISING OUT OF OR RELATED TO THIS PUBLICATION OR THE INFORMATION CONTAINED IN IT, EVEN IF MENTOR GRAPHICS CORPORATION HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. RESTRICTED RIGHTS LEGEND 03/97 U.S. Government Restricted Rights. The SOFTWARE and documentation have been developed entirely at private expense and are commercial computer software provided with restricted rights. Use, duplication or disclosure by the U.S. Government or a U.S. Government subcontractor is subject to the restrictions set forth in the license agreement provided with the software pursuant to DFARS 227.72023(a) or as set forth in subparagraph (c)(1) and (2) of the Commercial Computer Software - Restricted Rights clause at FAR 52.227-19, as applicable. Contractor/manufacturer is: Mentor Graphics Corporation 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. Telephone: 503.685.7000 Toll-Free Telephone: 800.592.2210 Website: www.mentor.com SupportNet: supportnet.mentor.com/ Send Feedback on Documentation: supportnet.mentor.com/user/feedback_form.cfm
TRADEMARKS: The trademarks, logos and service marks ("Marks") used herein are the property of Mentor Graphics Corporation or other third parties. No one is permitted to use these Marks without the prior written consent of Mentor Graphics or the respective third-party owner. The use herein of a thirdparty Mark is not an attempt to indicate Mentor Graphics as a source of a product, but is intended to indicate a product from, or associated with, a particular third party. A current list of Mentor Graphics trademarks may be viewed at: www.mentor.com/terms_conditions/trademarks.cfm.
Table of Contents
Chapter 1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inputs and Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . File Redirection Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 11 11 12
Chapter 2 Command Dictionary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Command Line Syntax Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Command Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Add Black Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Add Buffer Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Add Cell Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Add Clock Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Add Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Add Mapping Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Add Nofaults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Add Nonscan Instances. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Add Nonscan Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Add Notest Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Add Output Masks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Add Pin Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Add Pin Equivalences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Add Primary Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Add Primary Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Add Read Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Add Scan Chains. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Add Scan Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Add Scan Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Add Scan Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Add Scan Partition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Add Scan Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Add Seq_transparent Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Add Sub Chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Add Subchain Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Add Subchain Group. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Add Test Points. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Add Tied Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Add Write Controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Alias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Analyze Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Tessent DFTAdvisor Reference Manual, V9.0 June 2010
Table of Contents
Analyze Input Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analyze Output Observe. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analyze Testability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Delete Black Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Delete Buffer Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Delete Cell Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Delete Clock Groups. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Delete Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Delete Mapping Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Delete Nofaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Delete Nonscan Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Delete Nonscan Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Delete Notest Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Delete Output Masks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Delete Pin Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Delete Pin Equivalences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Delete Primary Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Delete Primary Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Delete Read Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Delete Scan Chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Delete Scan Groups. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Delete Scan Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Delete Scan Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Delete Scan Partitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Delete Scan Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Delete Seq_transparent Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Delete Sub Chains. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Delete Subchain Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Delete Subchain Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Delete Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Delete Tied Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Delete Write Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dofile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Echo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Find Design Names. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Help. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Insert Test Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Printenv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Procfile. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Report Black Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Report Buffer Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Report Cell Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Report Circuit Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Related Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Report Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Report Clock Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Report Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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103 104 105 108 109 111 113 114 115 118 120 122 124 126 127 129 130 132 134 135 136 137 139 140 141 142 143 144 145 146 148 150 151 152 154 155 160 161 163 170 171 172 174 175 177 180 181 183 184
Table of Contents
Report Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Report Dft Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Report DRC Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Report Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Report Feedback Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Report Flatten Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Report Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Report Loops. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Report Mapping Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Report Nofaults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Report Nonscan Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Report Notest Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Report Output Masks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Report Wrapper Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Report Pin Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Report Pin Equivalences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Report Primary Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Report Primary Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Report Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Report Read Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Report Scan Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Report Scan Chains. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Report Scan Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Report Scan Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Report Scan Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Report Scan Partitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Report Scan Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Report Seq_transparent Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Report Sequential Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Report Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Report Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Report Sub Chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Report Subchain Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Report Subchain Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Report Test Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Report Test Points. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Report Testability Analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Report Tied Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Report Timeplate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Report Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Report Write Controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ripup Scan Chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Run . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Save History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Set Bidi Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Set Capture Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Set Command Editing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Set Contention Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
185 187 190 195 197 199 201 207 209 212 214 215 216 217 220 222 223 224 225 226 227 231 232 233 234 235 237 238 239 246 248 250 251 252 253 255 257 260 261 262 264 265 266 268 269 270 273 274 275
5
Table of Contents
Set Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Set Dofile Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Set DRC Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Set Fault Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Set File Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Set Flatten Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Set Gate Level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Set Gate Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Set Gzip Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Set Identification Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Set Internal Fault. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Set Internal Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Set Io Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Set Latch Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Set Lockup Cell. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Set Logfile Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Set Net Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Set Nonscan Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Set Scan Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Set Scan_enable Sharing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Set Scan Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Set Screen Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Set Sensitization Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Set Shadow Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Set Stability Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Set System Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Set Test Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Set Trace Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Set Transient Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Set Tristate Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setup Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setup EDT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setup Naming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setup Output Masks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setup Pin Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setup Registered IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setup Scan Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setup Scan Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setup Scan Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setup Shift_register Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setup Test_point Identification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setup Test_point Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setup Tied Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setup Wrapper Chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Atpg Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Formal_verification Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
277 278 279 282 283 285 287 288 295 297 299 300 301 303 304 309 311 312 313 318 322 323 324 325 326 327 328 330 331 332 335 338 339 342 344 346 350 356 359 361 362 365 372 373 379 380 383 385 386
Table of Contents
Write Primary Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Primary Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Procfile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Scan Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Scan Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Subchain Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 3 Shell Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Shell Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dftadvisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . stil2mgc. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
390 391 392 393 395 404 405 405 406 409
Appendix A Using Tessent DFTVisualizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 Appendix B Getting Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413 Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413 Mentor Graphics Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413 Index Third-Party Information
End-User License Agreement
List of Examples
Example 1-1. File Redirection Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example 2-1. Add Buffer Insertion Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example 2-2. Generated dofile Tracing Back to Primary Input . . . . . . . . . . . . . . . . . . . . . . Example 2-3. Generated dofile Tracing Forward to Primary Input. . . . . . . . . . . . . . . . . . . . Example 2-4. Add Seq_transparent Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 31 75 76 78
List of Figures
Figure 2-1. Control Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2-2. Observe Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2-3. Control Point Example for -None and -Model . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2-4. Control Point Example for -New_scan_cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2-5. Observe Point Example for -None and -Model. . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2-6. Observe Point Example with -New_scan_cell . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2-7. Observe Point Example with -Existing_scan_cell . . . . . . . . . . . . . . . . . . . . . . . Figure 2-8. I/O Identification Default Tracing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2-9. All Input Logic Tracing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2-10. Control and Observe Point Insertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 92 366 367 367 368 369 374 375 375
List of Tables
Table 1-1. DFTAdvisor Commands Supporting File Redirection Operators . . . . . . . . . . . . Table 2-1. Conventions for Command Line Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 2-2. Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 2-3. Subchain Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 2-4. Available Information Displays and Arguments . . . . . . . . . . . . . . . . . . . . . . . . . Table 2-5. Report Gate Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 2-6. Output Format Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 2-7. Lockup Cell(s) Used Between Different Clock/Edge Transitions . . . . . . . . . . . Table 2-8. Default Scan Enable Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 2-9. Instance Type Prefix Defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 3-1. Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table A-1. DFTVisualizer-Related Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 15 16 87 190 203 240 305 313 339 405 411
10
Chapter 1 Introduction
Use Tessent DFTAdvisor to identify and insert scan and test circuitry to your design. For more information, see the Inserting Internal Scan and Test Circuitry section in the Scan and ATPG Process Guide.
Features
Tessent DFTAdvisor (hereafter referred to as DFTAdvisor) contains many features, including the following: Supports both full and partial-scan identification and insertion. Supports common scan methodologies including Mux-scan, Clocked-scan, and LSSD. Provides both automatic and manual scan identification capabilities allowing for an optimal partial-scan solution. Contains a powerful design rules checker. Automatically generates the scan setup dofile and the test procedure files for use downstream in your flow with the Tessent FastScan and Tessent TestKompress ATPG tools. Displays a variety of informationfrom design and debugging information to statistical reports for the test set you generate.
Inputs and Outputs

DFTAdvisor requires a gate-level netlist as input. DFTAdvisor reads and writes the Verilog format. Before you add internal scan or test circuitry to your design, you can analyze your design to ensure it does not contain problems that may impact test coverage. DFTAdvisor can then identify sequential elements for conversion to scan cells and then stitch those scan cells into scan chains. DFTAdvisor supports insertion of mux-DFF, clocked-scan, and LSSD scan types. It performs design rules checking to ensure scan setup and operation are correct, before scan is actually inserted. It does not alter the original netlist when it inserts test logic. The tool creates an internal copy of the original netlist, and then makes all required modifications to this copy. When finished, the tool writes out the modified copy as a new scan-inserted gate-level netlist.
11
Introduction Inputs and Outputs
Inputs
Design Netlist in Verilog format. Test Procedure File required if you have existing scan circuity in your design. The test procedure file defines the operation of existing scan circuitry. See also Specifying Existing Scan Information. DFT Library contains the model descriptions for all library cells used in your design, along with the model descriptions for all the scan replacement cells. Command Dofile File a set of commands that gives DFTAdvisor information on how the tool inserts scan chains. Alternatively, you can enter these commands interactively. See Command Dictionary for a listing and descriptions of the commands available for your use with DFTAdvisor.
Outputs
Design Netlist a scan version of your design netlist; can be in Verilog format. ATPG Setup Files the test procedure file defining the operation of the scan circuitry in your design, and a dofile for setting up the design and scan circuitry information for ATPG.
File Redirection Operators

You can redirect the output of selected Report commands to a file, or append an existing file. Table 1-1 lists the DFTAdvisor commands supporting redirection operators: Table 1-1. DFTAdvisor Commands Supporting File Redirection Operators Echo History Report Black Box Report Circuit Components Report Dft Check Report DRC Rules Report Environment Report Flatten Rules Report Nofaults Report Primary Inputs Report Primary Outputs Report Procedure Report Scan Cells Report Scan Chains Report Scan Groups Report Scan Pins Report Sequential Instances Report Statistics Report Sub Chains Report Test Points Report Tied Signals Report Timeplate
12
DFTAdvisor uses the following mechanisms for redirecting the output of these: > file_pathname Creates or replaces an existing file_pathname. >> file_pathname Appends the contents of file_pathname. You add the create and append semantics (>, >>) at the end of a commands argument list. The Example 1-1 command sequence redirects the output from the Report Scan Cells and Report Scan Chains commands into a single output file, my_scan_report. Example 1-1. File Redirection Example
echo "----------- scan cells ------------" > my_scan_report //creates the my_scan_report file report scan cells >> my_scan_report //appends my_scan_report echo "----------- scan chains ----------" >> my_scan_report //appends my_scan_report report scan chains >> my_scan_report //appends my_scan_report
13
14
Chapter 2 Command Dictionary

This chapter contains descriptions of the DFTAdvisor commands in alphabetical order.
Command Line Syntax Conventions

This manual uses the following command usage line syntax conventions. Table 2-1. Conventions for Command Line Syntax Convention UPPercase Example REPort ENvironment (substitute product-specific examples throughout) Usage Required command letters are in uppercase; in most cases, you may omit lowercase letters when entering commands or literal arguments and you need not enter in uppercase. Command names and options are normally case insensitive. Commands usually follow the 3-2-1 rule: the first three letters of the first word, the first two letters of the second word, and the first letter of the third, fourth, etc. words.
Boldface [ ] Italic { } |
SET COmmand Editing A boldface font indicates a required argument. -Off | -Vi | -Emacs | -Gmacs EXIt [-Discard] DOFile filename ADD CEll Library library {{-Model name} | -All} ADD CEll Library library {{-Model name} | -All} Square brackets enclose optional arguments. Do not enter the brackets. An italic font indicates a user-supplied argument. Braces enclose arguments to show grouping. Do not enter the braces. The vertical bar indicates an either/or choice between items. Do not include the bar in the command.
Underline
SET DOfile Abort ON | OFf An underlined item indicates either the default argument or the default value of an argument. ADD CLocks off_state primary_input_pin [-Internal] [-pin_name user_pinname] [-top_name existing_pin [-inverted]] An ellipsis follows an argument that may appear more than once. Do not include the ellipsis when entering commands.
15
Command Dictionary Command Summary
Command Summary
Table 2-2 contains a summary of the commands described in this manual. Table 2-2. Command Summary Command Add Black Box Add Buffer Insertion Description Defines black boxes, and sets the constrained value on output or bidirectional black box pins. Specifies for DFTAdvisor to place buffer cells between the primary input of the specific test pin and the gates driving the test pin. Specifies the DFT library cells for user-defined test points, system-generated test points, and system-generated test logic. Specifies the grouping of scan cells controlled by different clocks onto one chain. Specifies the names and inactive states of the primary input pins controlling the clocks in the design. Overrides the non-scan to scan model mapping defined by DFTAdvisor. Places nofault settings either on a pin or on all pins of a specified instance or module. Specifies for DFTAdvisor to ignore the specified instances, all instances controlled by the specified control pin, or all instances within the specified module, when identifying and inserting the required scan elements and test logic. Instructs DFTAdvisor to ignore all instances of the specified sequential DFT library model when identifying and inserting the required scan elements and test logic into the design. Adds circuit points to list for exclusion from testability insertion. Instructs DFTAdvisor to mask, and optionally maintain a constant logic level on, the specified primary output pins during the scan identification analysis. Specifies that DFTAdvisor hold the input pin at a constant state during the rules checking and loop cutting processes.
Add Cell Models
Add Clock Groups Add Clocks Add Mapping Definition Add Nofaults Add Nonscan Instances
Add Nonscan Models
Add Notest Points Add Output Masks
Add Pin Constraints
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Table 2-2. Command Summary (cont.) Command Add Pin Equivalences Description Specifies to hold the specified primary input pins at a state either equal to or inverted in relationship to the state of another primary input pin during rules checking. Adds a primary input to the net. Adds a primary output to the net. Adds an off-state value to specified RAM read control lines. Specifies a name for a pre-existing scan chain within the design. Adds one scan chain group to the system. Specifies that DFTAdvisor add the specified instance, all instances controlled by the specified control pin, or all instances within the specified module, to the scannable instance list. Specifies that DFTAdvisor is to flag every instance of the named DFT library model for inclusion into the identified scan list. Specifies a grouping of scan cells (a partition) in which scan chains are inserted separately from the remaining scan cells in the design. Declares the name of a scan chain at the top-level module and assigns the corresponding scan input pin, scan output pin, and optionally, the scan clock pin you associate with the chain. Specifies the enable value of a clock enable that internally gates the clock input of a non-scan cell for sequential transparent scan identification. Specifies the name of a pre-existing scan chain that exists entirely within a module, library model, or instance within a hierarchical design. Specifies the clock pins for a scan chain within a module, library model, instance, blackbox, or empty module of a hierarchical design. Adds one subchain group to the system.
Add Primary Inputs Add Primary Outputs Add Read Controls Add Scan Chains Add Scan Groups Add Scan Instances
Add Scan Models
Add Scan Partition
Add Scan Pins
Add Seq_transparent Constraints Add Sub Chains
Add Subchain Clocks
Add Subchain Group
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Table 2-2. Command Summary (cont.) Command Add Test Points Description Specifies explicitly where DFTAdvisor places a userdefined test point to improve the designs testability either through better controllability or observability. Specifies for DFTAdvisor to hold the named floating objects (nets or pins) at the given state value. Specifies the off-state value of the write control lines for RAMs. Specifies the shorthand name for a DFTAdvisor command, UNIX command, or existing command alias, or any combination of the three. Identifies and optionally defines the primary inputs of control signals. Specifies for DFTAdvisor to calculate and display the effects of constraining primary input pins to an unknown value on those pins control capability. Specifies for DFTAdvisor to calculate and display the effects on the observability of masked primary output pins. Reports general scannability and testability information, along with calculating the controllability and observability values for gates. Undoes the effect of the Add Black Box command. Specifies the type of scan test pins on which you want to remove the fanout limit. Specifies the name of the DFT library cell that DFTAdvisor is to remove from the active list of cells that the user can access when adding test points or that DFTAdvisor can access when inserting test logic. Specifies the name of the group that you want to remove from the clock groups list. Removes primary input pins from the clock list. Returns the non-scan to scan model mapping to the mapping defined by DFTAdvisor. Removes the no-fault settings from either the specified pin or instance pathnames.
Add Tied Signals Add Write Controls Alias
Analyze Control Signals Analyze Input Control
Analyze Output Observe Analyze Testability
Delete Black Box Delete Buffer Insertion Delete Cell Models
Delete Clock Groups Delete Clocks Delete Mapping Definition Delete Nofaults
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Table 2-2. Command Summary (cont.) Command Delete Nonscan Instances Delete Nonscan Models Delete Notest Points Delete Output Masks Delete Pin Constraints Delete Pin Equivalences Delete Primary Inputs Delete Primary Outputs Delete Read Controls Delete Scan Chains Delete Scan Groups Delete Scan Instances Delete Scan Models Delete Scan Partitions Delete Scan Pins Delete Seq_transparent Constraints Delete Sub Chains Delete Subchain Clocks Description Removes the specified sequential instances from the nonscan instance list. Removes from the non-scan model list the specified sequential DFT library models. Removes the specified pins from the list of notest points which the tool cannot use for testability insertion. Removes the masking of the specified primary output pins. Removes the pin constraints from the specified primary input pins. Removes the pin equivalence specifications for the designated primary input pins. Removes the specified primary inputs from the current netlist. Removes the specified primary outputs from the current netlist. Removes the read control line off-state definitions from the specified primary input pins. Removes the specified scan chain definitions from the scan chain list. Removes the specified scan chain group definitions from the scan chain group list. Removes the specified, sequential instances from the useridentified scan instance list. Removes the specified sequential models from the scan model list. Removes the user specified scan partitions. Removes any previously-assigned scan input, output, and clock names from the specified scan chains. Removes the pin constraints from the specified DFT library model input pins. Removes the definition of a pre-existing scan subchain. Deletes a specified subchain clock.
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Table 2-2. Command Summary (cont.) Command Delete Subchain Groups Delete Test Points Delete Tied Signals Delete Write Controls Dofile Echo Exit Find Design Names Help History Insert Test Logic Printenv Read Procfile Report Black Box Report Buffer Insertion Report Cell Models Report Circuit Components Report Clock Gating Description Removes a scan subchain group. Remove the test point definitions at the specified locations. Removes the assigned (tied) value from the specified floating nets or pins. Removes the RAM write control line off-state definitions from the specified primary input pins. Executes the commands contained within the specified file. Issues a user-defined string to the transcript. Terminates the current DFTAdvisor session. Displays design object hierarchical names matched by an input regular expression. Displays the usage syntax and system mode for the specified command. Displays a list of previously-executed commands. Inserts the test structures that you define into the netlist to increase the designs testability. Prints out the values of the UNIX variables in the environment. Reads the specified test procedure file. Displays information on blackboxes and undefined models. Displays a list of all the different scan test pins and the corresponding fanout limit. Displays a list of either all cell models or the DFT library models associated with the specified cell type. Displays information about the components of the circuit as either modules or instances. Reports either the clock gating instances that were identified as having unconnected ports and were connected to either the Scan enable signal or a user-specified signal or, reports the unconnected ports of the specified clock gating cells only.
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Table 2-2. Command Summary (cont.) Command Report Clock Groups Report Clocks Report Control Signals Report Dft Check Report DRC Rules Report Environment Report Feedback Paths Report Flatten Rules Report Gates Report Loops Report Mapping Definition Report Nofaults Report Nonscan Models Report Notest Points Report Output Masks Report Pin Constraints Report Pin Equivalences Report Primary Inputs Report Primary Outputs Report Procedure Report Read Controls Description Displays a list of all clock group definitions. Displays a list of all clock definitions. Displays the rules checking results for the specified control signals. Generates the scannability check results for non-scan instances. Displays either a summary of DRC violations (fails) or violation occurrence message(s). Displays the current values of all the set commands and the default names of the scan type pins. Displays a textual report of the currently identified feedback paths. Displays either a summary of all the flattening rule violations or the data for a specific violation. Displays the netlist information for the specified gates. Displays information about circuit loops. Reports the non-scan to scan model mapping defined in the design. Displays the no-fault settings for the specified pin or instance pathnames. Displays the sequential non-scan model list. Displays all the circuit points for which you do not want DFTAdvisor to insert controllability and observability. Displays a list of the currently masked primary output pins. Displays the pin constraints of the primary inputs. Displays the pin equivalences of the primary inputs. Displays the specified primary inputs. Displays the specified primary outputs. Displays the specified procedure. Displays all of the currently defined read control lines.
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Table 2-2. Command Summary (cont.) Command Report Scan Cells Report Scan Chains Report Scan Enable Report Scan Groups Report Scan Models Report Scan Partitions Report Scan Pins Report Seq_transparent Constraints Report Sequential Instances Report Statistics Report Sub Chains Report Subchain Clocks Report Subchain Groups Report Test Logic Report Test Points Description Displays a report or writes a file on the scan cells that reside in the specified scan chains. Displays a report on all the current scan chains. Reports on the scan_enable signal for each scan_chain. Displays a report on all the current scan chain groups. Displays the sequential scan models currently in the scan model list. Displays scan partitions. Displays all previously assigned scan input, output, and clock names. Displays the seq_transparent constraints. Displays information and testability data for sequential instances. Displays a detailed report of the designs statistics. Displays a report on the scan subchains. Reports on subchain clocks defined for a specified subchain. Displays a report on the subchain groups. Displays the test logic that DFTAdvisor added during the scan insertion process. Displays the test point specifications you created with the Add Test Points command and any test points that you enabled DFTAdvisor to automatically identify. Displays the results of the Analyze Testability command. Displays a list of the tied floating signals and pins. Displays the specified timeplate. Displays user-defined variables and values. Reports the identified wrapper cells for each I/O pin that is traced for identification.
Report Testability Analysis Report Tied Signals Report Timeplate Report Variables Related Commands
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Table 2-2. Command Summary (cont.) Command Report Write Controls Reset State Description Displays the currently defined write control lines and their off-states. Removes all instances from both the scan identification and test point identification lists that DFTAdvisor identified during a run. Removes the specified scan chains from the design. Runs the scan or test point identification process. Saves the command line history file to the specified file. Specifies how bidirectional (bidi) pins are controlled during scan chain shifting. Specifies the capture clock name for random pattern simulation. Assigns a loading factor to the clock specified by the clock_name argument. Sets the command line editing mode. Specifies whether DFTAdvisor checks the gate types that you determine for contention. Sets the DISPLAY environment variable from the tools command line. Allows processing of all commands in a dofile regardless of an error detection. Specifies how DFTAdvisor globally handles design rule violations. Specifies the fault sampling percentage for scan identification. Controls whether the tools read and write files with .Z or .gz extensions as compressed files (the default). Specifies how DFTAdvisor globally handles flattening violations. Specifies the hierarchical level of gate reporting and displaying. Specifies the additional display information for the Report Gates command.
Ripup Scan Chains Run Save History Set Bidi Gating Set Capture Clock Set Command Editing Set Command Editing Set Contention Check Set Display Set Dofile Abort Set DRC Handling Set Fault Sampling Set File Compression Set Flatten Handling Set Gate Level Set Gate Report
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Table 2-2. Command Summary (cont.) Command Set Gzip Options Set Identification Model Description Specifies GNU gzip options to use with the GNU gzip command. Specifies the simulation model that DFTAdvisor uses to imitate the scan operation during the scan identification process. Specifies whether the tool allows faults within or on the boundary of library models. Specifies whether to delete or keep pin names of library internal pins containing no-fault attributes. Inserts I/O buffers. Specifies whether the tool considers non-transparent latches for scan insertion while test logic is turned on. Sets DFTAdvisor to automatically insert lockup cells between different clock/edge domains to synchronize the clocks within a scan chain. Specifies for DFTAdvisor to direct the transcript information to a file. Specifies the behavior of multi-driver nets. Specifies whether to check the non-scan instances for scannability. Assigns scan_enable signals to specific scan chains. Divides all scan chains into specified groups and assigns a unique scan_ enable signal to each group. Specifies the scan style design. Specifies whether DFTAdvisor writes the transcript to the session window. Specifies whether DRC checking attempts to verify a suspected C3 rules violation. Specifies whether DFTAdvisor will identify sequential elements as shadow elements when tracing existing scan chains. Specifies how the tool checks the effect of applying the shift procedure on non-scan cells.
Set Internal Fault Set Internal Name Set Io Insertion Set Latch Handling Set Lockup Cell
Set Logfile Handling Set Net Resolution Set Nonscan Handling Set Scan Enable Set Scan_enable Sharing Set Scan Type Set Screen Display Set Sensitization Checking Set Shadow Check
Set Stability Check
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Table 2-2. Command Summary (cont.) Command Set System Mode Set Test Logic Set Trace Report Set Transient Detection Set Tristate Gating Setup Clock Gating Description Specifies the next system mode for the tool to enter. Specifies which types of control lines DFTAdvisor makes controllable during the DFT rules checking. Specifies whether the tool displays gates in the scan chain trace. Specifies whether the tool detects all zero width events on the clock lines of state elements. Specifies how tri-state devices are controlled during scan shifting. Specifies clock gating cells whose unconnected scan enable ports need to be connected to either the Scan Enable signal or a specified signal (pin). Enables the Write ATPG Setup command to write out EDT-specific commands to the ATPG setup files. Explicitly defines the default names for nets and instances, and reports current or modified settings. Sets the default mask for all output and bidirectional pins. Sets the default pin constraint value for all input and bidirectional pins. Registers the primary inputs and outputs of a core design. Specifies the scan identification methodology and amount of scan that DFTAdvisor is to consider during the identification run. Sets up the parameters for the Insert Test Logic command. Changes the scan-in or scan-out pin naming parameters to index or bus format. Enables/disables shift register identification. Specifies the number of control and observe test points that DFTAdvisor flags during the identification run. Specifies how DFTAdvisor configures the inputs for the control test points and the outputs for the observe test points.
Setup EDT Setup Naming Setup Output Masks Setup Pin Constraints Setup Registered IO Setup Scan Identification
Setup Scan Insertion Setup Scan Pins Setup Shift_register Identification Setup Test_point Identification Setup Test_point Insertion
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Table 2-2. Command Summary (cont.) Command Setup Tied Signals Setup Pin Constraints System Write Atpg Setup Write Formal_verification Setup Write Loops Write Netlist Write Primary Inputs Write Primary Outputs Write Procfile Write Scan Identification Write Scan Order Write Subchain Setup Description Changes the default value for floating pins and floating nets that do not have assigned values. Specifies the scan chains for wrapper cells. Passes the specified command to the operating system for execution. Writes the test procedure and the dofile for inserted scan chains to the specified files. Writes a constraints driver file for the formal verification tool, FormalPro. Writes a list of all loops to the specified file. Writes the current design in the specified netlist format to the specified file. Writes primary inputs to the specified file. Writes primary outputs to the specified file. Writes existing procedure and timing data to the named test procedure file. Writes a list of the scan instances that DFTAdvisor has identified or you have defined as scan cells. Creates specified DEF file. Writes the appropriate Add Sub Chains commands to a file so that DFTAdvisor can understand the pre-existing scan subchains at the top-level of this module.
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Command Dictionary Command Descriptions
Command Descriptions
The remaining pages in this chapter describe, in alphabetical order, the DFTAdvisor commands. Each command description begins on a new page. The notational conventions in use here are the same as those in use in other parts of the manual. Do not enter any of the special notational characters (such as, {}, [], or |) when typing the command. You can use the line continuation character \ when application commands extend beyond the end of a line. The line continuation character improves the readability of dofiles and helps with the command line entry of multiple-argument commands.
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Command Dictionary Add Black Box
Add Black Box

Scope: Setup mode Usage ADD BLack Box {{{-Instance ins_pathname | -Module module_name} [0 | 1 | X | Z]} [-Pin pinname {0 | 1 | X | Z}]} | {-Auto [0 | 1 | X | Z]} [-FAUlt_boundary | -NOFAUlt_boundary | -NO_Boundary] Description Defines black boxes, and sets the constrained value on output or bidirectional black box pins. By default, DFTAdvisor does not automatically blackbox any instantiated module or component not defined in either the ATPG library or the design netlist. When an undefined model in encountered, a warning is issued. Additionally, the flatten model command verifies you have blackboxed all undefined models before flattening. Instance-Based Black Boxes: If you use Add Black Box with the -Auto switch, DFTAdvisor automatically blackboxes all instances of models the tool considers undefined. By default, instances the tool automatically blackboxes drive Xs on their outputsfaults propagating to the black box inputs are classified at ATPG_untestable (AU). You can also change the output values using the Add Black Box command. Module-Based Black Boxes: By default, modules the tool automatically blackboxes drive X on the outputs while the inputs are fault sinks. You can change the output values by issuing the Add Black Box command. You can also blackbox modules you have defined, but you do not want to include in the next run. If you issue two Add Black Box commands in tandem, where one is module-based and the other is instance-based, then you can globally blackbox all instances of a particular module while selectively blackboxing a particular instance of the same module with slightly different values. Arguments -Instance ins_pathname A switch and string pair specifying the full instance pathname (ins_pathname) for the tool to blackbox. Instance-based blackboxing always overrides module-based blackboxing. -Module module_name A switch and string pair specifying the name of the module (module_name) for which every instantiation the tool blackboxes. -Auto A switch specifying blackboxing of all referenced models without a defining netlist module or library model. The modules contain default output values. 0|1|X|Z An optional literal specifying pin tie values for use with the following switches:
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Command Dictionary Add Black Box o o o
-Instance or -Module specifies the tie value for any undefined pin. -Pin specifies the tie value for the pin. -Auto specifies the tie value for every pin.
If you specify no value for this option, then the application defaults to the Setup Tied Signals commands value. If you want a different value, then use the -Pin switch and specify the value. -Pin pinname An optional repeatable switch and string pair specifying the tie value of the particular pin. Valid values are 0, 1, X, and Z, where X is the default. Unspecified pins assume the default tie value in effect for the specified instance or module. May be used with -Instance or -Module switches. -FAUlt_boundary A switch specifying to keep pin pathnames at the boundaries of all blackboxed instances and allow boundary pins to become fault sites. This is the default behavior. -NOFAUlt_boundary A switch specifying to keep pin pathnames at the boundaries of all blackboxed instances, but not allow boundary pins to become fault sites. Note You must include this switch when you use the Add Black Box command to blackbox macros for Tessent FastScan MacroTest. -NO_Boundary A switch specifying to not keep pin pathnames at the boundaries of all blackboxed instances and to not allow boundary pins to become fault sites. Examples The following example creates a black box for module core with a tie value of 0, then core1.
add black box -module core 0 add black box -instance core1 -pin pin1 1
The following example creates a black box for all undefined models.
add black box -auto
The following example keeps the pin pathnames at the boundary of all instances of the blackboxed module named macro1, but nofaults the pins.
add black box -module macro1 -nofault_boundary
Related Commands Delete Black Box Report Black Box
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Command Dictionary Add Buffer Insertion
Add Buffer Insertion

Scope: All modes Usage ADD BUffer Insertion max_fanout test_pin [-Model modelname] Description Specifies for DFTAdvisor to place buffer cells between the primary input of the specific test pin and the gates driving the test pin. When DFTAdvisor inserts the scan circuitry into the design, the scan-related pins (enables and clocks) can fanout to drive multiple gates. When a pin has a large fanout, the pins increased load factor affects the quality of the pins output signal. If you want to avoid signal degradation of a primary input scan pin, you can use the Add Buffer Insertion command. This sets the fanout limit on all buffers used to buffer the specified signal. The fanout limit propagates down the buffer tree the tool inserts. Arguments max_fanout A required integer specifying the maximum number of gates the test_pin can drive before DFTAdvisor inserts buffers. The value must be greater than 1. By default, the tool assumes the test_pin can drive an infinite number of gates. This value overrides the default value set by the Add Cell Models command. test_pin A required repeatable literal specifying the type of the primary input scan pin to monitor for the maximum fanout. The following lists the default pin names for each type of scan pin. You can use the Setup Scan Insertion command to change the default names of the scan pins. SEN (scan enable; default name scan_en) a literal specifying the primary input pin enabling the scan chain. SCLK (scan clock; default name scan_clk) a literal specifying the primary input pin clocking the scan data through the scan chain when using the clocked-scan type. TEN (test logic enable; default name test_en) a literal specifying the primary input pin enabling the operation of the test logic circuitry. TCLK (test logic clock; default name test_clk) a literal specifying the primary input pin clocking the values DFTAdvisor requires for proper test logic functionality. SMCLK (master scan clock; default name scan_mclk) a literal specifying the primary input pin clocking the scan data into the master scan elements of the scan chain when using the LSSD scan type. SSCLK (slave scan clock; default name scan_sclk) a literal specifying the primary input pin for clocking the scan data into the slave scan elements of the scan chain when using the LSSD scan type.
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Command Dictionary Add Buffer Insertion
SET (scan set; default name scan_set) a literal specifying the new scan set for the scan cells. RESET (scan reset; default name scan_reset) a literal specifying the new scan reset for the scan cells. -Model modelname An optional switch and string pair specifying the name of a buffer in the library DFTAdvisor inserts when the scan pin reaches the maximum fanout. You must first identify the buffer with either the Add Cell Models command or with the cell_type library attribute. If you do not use the -Model switch, by default, the tool uses the first buffer model in the buffer cell model list, which you obtain with the Report Cell Models command. Examples Example 2-1 explicitly specifies the buffer model to use and sets the maximum fanout for the scan enable pin for a mux-DFF cell. Example 2-1. Add Buffer Insertion Example
add cell models buf2a -type buf -max_fanout 10 report cell models BUF : buf1a<infinity> buf2a<10>
add buffer insertion 5 sen -model buf2a
In this example, you must initially define the buf1a buffer model in the library using the cell_type library attribute with the value of BUF. The first command explicitly adds the buf2a cell to the buffer model list and defines its fanout to be 10. Next, the report shows the two buffers currently in the buffer model list. The last command specifies the maximum fanout of the scan enable pin and all buffers inserted to buffer the scan enable signal. This example uses the -Model switch to specify the buf2a model. Without this switch, the tool would use the buf1a model, because it is the first in the buffer model list. Related Commands Add Cell Models Delete Buffer Insertion Report Buffer Insertion Setup Scan Insertion
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Command Dictionary Add Cell Models
Add Cell Models

Scope: All modes Usage ADD CEll Models dftlib_model {-Type {INV | And | {Buf -Max_fanout integer} | OR | NAnd | NOr | Xor | INBuf | OUtbuf | {Mux selector data0 data1} | {Scancell clk data [-Active {High | Low}]} | {DFf clk data [-Active {High | Low}]} | {DLat enable data [-Active {High | Low}]} | {Wrapcell clk data}} [{-Noinvert | -Invert} output_pin] Description The Add Cell Models command specifies DFT library models for user-defined test points, system-generated test points, and system-generated test logic. When adding test logic circuitry, multiple models from the DFT library are used. The cell_type attribute in the library model description specifies the components available for use as test logic. You can use the Add Cell Models command instead of defining the cell_type attribute in the library model description. For more information on the design library attribute, see cell_type in the Tessent Common Resources Manual for ATPG Products. Arguments dftlib_model A required string that specifies the name of a cell model in the DFT library used for test logic, buffer tree, lockup cell, or test point insertion. -Type A required switch and argument pair that specifies a model type. Options include: INV a literal specifying a 1-input inverter gate. And a literal specifying a 2-input AND gate. Buf -Max_fanout integer a literal with a switch and integer pair specifying a 1-input buffer gate with an optional buffer fanout limit. OR a literal specifying a 2-input OR gate. NAnd a literal specifying a 2-input NAND gate. NOr a literal specifying a 2-input NOR gate. Xor a literal specifying an exclusive OR gate. INBuf a literal specifying a primary input buffer gate DFTAdvisor inserts whenever the tool adds new input pins (for example, the scan input or scan enable pins). DFTAdvisor places the buffer between the primary input and the new pin.
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OUtbuf a literal specifying a primary output buffer gate DFTAdvisor inserts whenever the tool adds new output pins (such as the scan output pin). It places the buffer between the new pin and the primary output. Mux selector data0 data1 a literal and three strings specifying a 2-1 multiplexer and the names of the selector pin and both data pins. Scancell clk data [-Active {High | Low}] a literal and two strings specifying one of the following scan cells:
o
a mux-DFF scan cell with the following four input pins: clock, data, scan in, and scan enable a clocked-scan cell with the following four inputs: clock, data, scan clock, and scan enable a LSSD scan cell with the following five inputs: clock, data, scan in, master clock, and slave clock
You must specify the name of the clock and data pins of the DFT library cell model. You may also include an optional switch with a literal to specify the inversion on the clock pin. By default, DFTAdvisor uses an active-high polarity clock pin. This option works in conjunction with the Add Test Points and the Setup Registered IO commands. DFf clk data [-Active {High | Low}] a literal and two strings specifying a D flip-flop with two input pins, specifically, clock and data. You must specify the names of the clock and data pins of the DFT library cell model. This option works in combination with the Add Test Points command or Set Lockup Cell command. If you are defining this model for use with lockup cells, you may also use an optional switch and literal to specify the overall inversion on the clock pin. By default, an active-high polarity clock pin is used. DLat enable data [-Active {High | Low}] a literal and two strings specifying a D latch with two input pins, specifically enable and data. You must specify the names of the enable line and the data pin of the DFT library cell model. If you are defining this model for use with lockup cells, you may also use an optional switch and literal to specify the overall inversion on the clock pin. By default, an active-high polarity clock pin is used. Wrapcell clk data literal and two strings specifying a mux-scan cell with five input pins (clock, data, scan in, scan enable, and test enable). You must specify the names of the clock and data pins of the DFT library cell model. This option is meant to work in combination with the Setup Registered IO command. {-Noinvert | -Invert} output_pin An optional switch and string pair you can use with values of the cell model type that are sequential elements. This switch specifies whether the output_pin has an inversion relationship with the data input of the given sequential element. By default, DFTAdvisor assumes no inversion relationship between the output_pin and the data input. If you do not explicitly specify an inversion switch, by default, DFTAdvisor uses the first output_pin value it identifies on a DFF, ScanCell, or DLAT model.
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Example 1 The following example shows a typical use of test logic involving the set, reset, and clock pins on sequential elements (flip-flops). DFTAdvisor can usually ensure controllability of sequential elements with model types of And, Or, and, Mux.
add clocks 0 clk set test logic -set on -reset on -clock on set system mode dft report dft check add cell models and2 -type and add cell models or2 -type or add cell models mux21h -type mux si a b
Example 2 The following mux-DFF example adds the buf2a cell to the buffer model list, and then explicitly specifies the buffer model to use and sets the maximum fanout for the scan enable:
add cell models buf2a -type buf report cell models BUF : buf1a buf2a
add buffer insertion 5 sen -model buf2a
Related Commands Add Buffer Insertion Delete Cell Models Report Cell Models Set Io Insertion Set Lockup Cell Set Test Logic Setup Registered IO Setup Scan Identification
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Command Dictionary Add Clock Groups
Add Clock Groups

Scope: Dft mode Prerequisites: You must first define all the clocks with the Add Clocks command. Usage ADD CLock Groups group_name clk_pin [-Tclk] Description Specifies the grouping of scan cells controlled by different clocks onto one chain. If you are merging scan cells controlled by multiple shift clocks into one scan chain, you can place together scan cells sharing the same shift clock by using the Add Clock Groups command. DFTAdvisor groups scan cells controlled by the same clock in the chain. If you want to insert lockup cells between the different clock domains of the groups, you can use the Set Lockup Cell command. These latches synchronize the pulses to all the clock inputs of the scan cells within the same scan chain. As you define clock groups, the clocks in these groups are removed from the default clock group, all_clocks. Every clock is contained in either a user-defined clock group or the default clock group. Arguments group_name A required string naming the list of clock pins you provide with the clk_pin argument. clk_pin A required repeatable string identifying the names of all the clocks controlling the cells you group together. -Tclk An optional switch specifying the inclusion of the test clock in the clock group. Because DFTAdvisor adds the clock signal during test structure insertion, you cannot specify the actual clock name here. Examples The following example lists the clocks in the current clock list, splits those clocks into two different groups, and defines the latch DFTAdvisor uses for synchronizing the different clocks:
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Command Dictionary Add Clock Groups add clock 1 clk1 clk2 add clock 0 clk3 clk4 clk5 clk6 set system mode dft add clock groups group1 clk1 clk3 clk4 add clock groups group2 clk2 clk5 clk6 add cell models dlat1a -type dlat enable data add cell models inv -type inv set lockup cell on run insert test logic
This example also enables automatic lockup cell insertion, and subsequently performs the scan and latch placement. Note This example creates two scan chains and corresponding to the two clock groups.
Related Commands Add Cell Models Add Clocks Delete Clock Groups Report Clock Groups Set Lockup Cell
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Command Dictionary Add Clocks
Add Clocks
Scope: Setup mode Usage ADD CLocks off_state primary_input_pin [-internal] [-pin_name user_pinname] [-top_name existing_pin [-inverted]] Description Specifies the names and inactive states of the primary input pins controlling the clocks in the design. You must declare control signals (for example, clocks, sets, and resets) and the signals corresponding off-state with the Add Clocks command before entering the Dft mode. Otherwise, instances outside of the design rules checkers control fail the scannability check. If an instance fails the scannability check, then DFTAdvisor does not recognize it as a scannable instance, and cannot replace it with the corresponding scan cell. As you declare clocks, DFTAdvisor inserts the clocks into a default clock group, all_clocks. Arguments off_state A required literal specifying the pin value that cannot affect the output pin activity of the instance. For example, the off-state of an active low reset pin is 1 (high). For an edgetriggered control signal, the offstate is the value on the pin that results in the clock inputs being placed at the initial value of a capturing transition. The off-state choices are as follows: 0 A literal specifying the off-state value is 0. 1 A literal specifying the off-state value is 1. primary_input_pin A required repeatable string that lists the primary input pins that you want controlling the output pins of an instance. The list of primary input pins must all have the same off_state. If you declare a control pin with the Add Clocks command, DFTAdvisor also automatically declares all pins that are equal to that pin as control pins, by looking at the arguments of any Add Pin Equivalences commands. If the -Internal switch is used, primary_input_pin lists internal pin pathnames. If both the -Internal and -Pin_name switches are used, primary_input_pin lists internal pin pathnames to merge into a single, new primary input pin. -Internal An optional switch that specifies primary_input_pin is an internal pin that, for DRC analysis only, should be disconnected from its original driver and treated as if it were a clock primary input. If you use this switch, the primary_input_pin argument must be an internal pin, not an actual clock primary input pin. When writing out the modified netlist, this internal clock
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input is not added to the top level interface. Use this switch to define internal clock inputs normally driven by on-chip circuitry. -PIn_name user_pinname An optional switch and string pair that specifies the name of a new pseudo primary input pin that drives all of the internal pins specified with the primary_input_pin argument. The user_pinname is a name (wildcards are not allowed) given to the newly-created primary input pin. The -Pin_name switch is only valid when the -Internal switch is also specified. The -Pin_name switch is also allowed if the primary_input_pin argument specifies a single, internal pin pathname which ensures that a known pin name is used for the new primary input pin. -top_name existing_pin An optional switch and string pair that specifies the name of an existing top level pin that drives the internal node during scan chain shifting. The top level pin should be a clock signal; you do not need to define it using the Add Clocks command. Note: Although the top_name switch is optional, DFTAdvisor issues a warning message if it cannot automatically trace from the internal node to a primary input pin (the pin must not be a scan signal, and must not have any pin constraints). -inverted An optional switch that must be used in conjunction with the -top_name switch to indicate an inverting path; this may be necessary if the signals cannot be traced due to a black-boxed module. Example 1 The following example first lists the primary inputs of the design, a D flip-flop. The next two commands declare the preset, clear, and clock pins to be clocks, which means they have the ability to control the states on the output pins of that instance.
report primary inputs SYSTEM: SYSTEM: SYSTEM: SYSTEM: /CLK_INPUT /D_INPUT /PRE_INPUT /CLR_INPUT
add clock 1 /pre_input /clr_input add clock 0 /clk_input
Example 2 The following example defines the output of a PLL block as an internal clock and explicitly specifies the top level signal that can be used to generate a clock pulse at the internal node. The Write Atpg Setup command will refer to the top level signal instead of the internal net.
add clock 0 /pll_block/clock1 -internal -top_name /clock_trigger
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Related Commands Add Clock Groups Analyze Control Signals Delete Clocks Report Clocks
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Command Dictionary Add Mapping Definition
Add Mapping Definition

Scope: Setup and DFT modes Prerequisites: You can only override the mapping for scan models of the same scan type. For example, a mux-DFF scan model can only be replaced by another mux-DFF scan model. Usage ADD MApping Definition object_name [-Instance | -Module] [-Nonscan_model nonscan_model_name] [-Scan_model scan_model_name] [-Output scan_ouput_pin_name] Description Overrides the non-scan to scan model mapping defined by DFTAdvisor. The Add Mapping Definition command defines the mapping of non-scan models to scan models. You can change the scan model for an individual instance, all instances under a hierarchical instance, all instances in all occurrences of a module in the design, or all occurrences of the model in the entire design. Additionally, you can change the scan output pin of the scan model in the same manner. Note Use this command for changing the existing non-scan to scan model mapping, as defined in the library, and not to define the mapping. Refer to Defining Scan Cell and Scan Output Mapping in the Scan and ATPG Process Guide for conceptual information on this topic. Arguments object_name A required string that specifies the name of the non-scan model you want to map to a different scan model. If, instead of a non-scan model, you specify an instance, hierarchical instance, module, or scan model, then this is that objects name.
o
If this argument is the name of an instance or hierarchical instance, the -Instance switch is required and the model must be specified with the -Nonscan_model switch or -Scan_model switch. If this argument is the name of a module, then the -Module switch is required and the model must be specified with the -Nonscan_model or -Scan_model switch. If this argument is a scan model, then the -Output switch is required. Because you specified a scan model, you can only define the scan output pin mapping.
-Instance | -Module An optional switch that specifies the type of the object_name argument. If neither switch is specified, the object_name is a model (the default).
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Command Dictionary Add Mapping Definition o
If you specify -Instance and the instance is primitive, then only the named instance has its mapping changed. If you specify -Instance and the instance is hierarchical, then all instances under that instance matching the -Nonscan_model or (for output mapping) matching the -Scan_model have their mapping changed. If you specify -Module, then for all occurrences of that module, all instances within that module that match the -Nonscan_model or (for output mapping) matching the -Scan_model have their mapping changed.
-Nonscan_model nonscan_model_name A switch and string pair that specifies the name of the non-scan model for which you want to change the mapping. This argument is required if you specify -Instance or -Module switch. Otherwise, specify the name of the non-scan model in the object_name argument.
-Scan_model scan_model_name A switch and string pair that specifies the name of the scan model that you want to use for the specified non-scan model. This argument is required except when you are changing the mapping of the scan output pin, and specify the scan model in the object_name argument.
-Output scan_ouput_pin_name An optional switch and string pair that specifies the name of the scan output pin to use instead of the DFTAdvisor defined scan output pin. The port must have been declared as a scan-out port in the scan_definition section of the scan cell.
Examples The following example maps the fd1 non-scan model to the fd1s scan model for all occurrences of the model in the design:
add mapping definition fd1 -scan_model fd1s
The following example maps the fd1 non-scan model to the fd1s scan model and changes the scan output pin to qn for all occurrences of the model in the design:
add mapping definition fd1 -scan_model fd1s -output qn
The first command in the following example maps the fd1 non-scan model to the fd1s scan model for all matching instances in the counter module and for all occurrences of that module in the design. The second command maps the fd1 non-scan model to the fd1s2 scan model and changes the scan output pin to qn for all matching instances under the hierarchical instance /top/counter1. Note that counter1 is an instance of the module counter changed in the first command.
add mapping definition counter -module -nonscan_model fd1 -scan_model fd1s add mapping definition /top/counter1 -instance -nonscan_model fd1 -scan_model fd1s2 -output qn
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Command Dictionary Add Mapping Definition
The following example changes the scan output pin to qn for all occurrences of the fd1s scan model in the design:
add mapping definition fd1s -output qn
Related Commands Delete Mapping Definition Report Mapping Definition
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Command Dictionary Add Nofaults
Add Nofaults
Scope: Setup mode Usage ADD NOfaults {{{modulename -Module} | {object_expression [-PIN | -Instance]}} [-Stuck_at {01 | 0 | 1}] [-Keep_boundary]} Description Places nofault settings either on a pin or on all pins of a specified instance or module. The Add Nofaults command places a nofault setting on either a single specified pin, or on all pins of a specified instance or module. If the pathname is a pin, then DFTAdvisor ignores only the fault on that pin. If the pathname is an instance, then the tool ignores all pin faults on the top-level of that instance, along with all the pin faults underneath that instance (if it is a hierarchical instance). If the pathname is a module, then the tool ignores all pin faults on the top-level of the module, along with all the pin faults on all instances and pins underneath that module for every occurrence of that module in the design. Note The nofaults that you create with the Add Nofaults command only exist for the current DFTAdvisor session. DFTAdvisor recognizes the nofault setting on pins and instances through the following two mutually exclusive tagging processes: Interactively using the Add Nofaults command for pins and instances Using the nofault DFT library attribute for pins
Arguments modulename A repeatable string that specifies the name of a module to which you want to assign nofault settings. You must include the -Module switch when you specify a module name. -Module A switch that specifies to interpret the modulename argument as a module pathname. All instances of the module are affected. You can use the asterisk (*) and question mark (?) wildcards for the modulename argument, and the tool adds the nofault for all matching modules or library models.
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object_expression A string representing a list of pathnames of instances or pins for which you want to assign nofault settings. The string may include any number of embedded asterisk (*) or question mark (?) wildcard characters. The asterisk matches any sequence of characters (including none) in a name, and the question mark matches any single character. Pin pathnames must be ATPG library cell instance pins, also referred to as design level pins. If the object expression specifies a pin within an instance of an ATPG library model, the tool ignores it. By default, pin pathnames are matched first. If a pin pathname match is not found, the tool next tries to match instance pathnames. You can force the tool to match only pin pathnames or only instance pathnames by including the -Pin or -Instance switch after the object_expression.
-PIN An optional switch that specifies to use the preceding object expression to match only pin pathnames; the tool will then assign nofault settings to all the pins matched.
-Instance An optional switch that specifies to use the preceding object expression to match only instance pathnames; the tool will then assign nofault settings to all boundary and internal pins of the instances matched (unless you use the -Keep_boundary switch).
-Stuck_at 01 | 0 | 1 An optional switch and literal pair identifying the stuck-at values receiving the nofault setting. Choose from one of the following: 01 specifies the placement of a nofault setting on both the stuck-at-0 and stuck-at1 faults. This is the default. 0 specifies the placement of a nofault setting on the stuck-at-0 faults. 1 specifies the placement of a nofault setting on the stuck-at-1 faults.
-Keep_boundary An optional switch that specifies that nofaults are applied to the pins inside of the specified instance or module, but faults are still allowed at the boundary pins of the specified instances or modules. This option does not apply to nofaults on pin pathnames.
Examples The following example first tags all the pin faults on and below an instance, and then tags the fault on a specific pin.
add clocks 0 clock add nofaults i_1006 -instance add nofaults i_1_16/df0/q set system mode dft run
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Related Commands Delete Nofaults Report Nofaults
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Command Dictionary Add Nonscan Instances
Add Nonscan Instances

Scope: All modes, except only Dft mode for the -Control_signal option. Usage ADD NONscan Instances pathname... | instance_expression [-INStance | -Control_signal | -Module] Description Specifies for DFTAdvisor to ignore the specified instances, all instances controlled by the specified control pin, or all instances within the specified module, when identifying and inserting the required scan elements and test logic. The Add Nonscan Instances command causes DFTAdvisor to ignore the specified instances, instances controlled by the specified control signals, or all instances within the specified module when you execute both the scan identification process with the Run command and the scan insertion process with the Insert Test Logic command. Also, DFTAdvisor will not perform the scannability rule checks on non-scan instances unless you execute the Set Nonscan Handling command. If you want to flag all instances of a certain library model as non-scan, you can use the Add Nonscan Models command as a shortcut. When adding non-scan instances with control signals, DFTAdvisor adds all scannable instances controlled by the control signals to the non-scan instance list. Control pins can be any clock, set, or reset signal (primary input) that controls the contents of sequential instances. You can use the Report Control Signals command to see the pins that control the sequential instances in the design. If TIE0 and TIE1 non-scan cells are scannable, they are considered for scan. However, if these cells are used to hold off sets and resets of other cells so that another cell can be scannable, you must use this command to make them non-scan. Arguments pathname A required repeatable string that specifies the pathnames of the sequential instance or control signals (that control instances) which you want DFTAdvisor to ignore. If the instance is hierarchical, then all instances beneath it are also flagged as non-scan. instance_expression A string representing a list of instances within the design. The string instance_expression is defined as:
{ string | string * } ...
The asterisk (*) is a wildcard that allows you to match many instances in a design. Any expression that does not contain an asterisk (*) will match exactly zero or one instance.
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Command Dictionary Add Nonscan Instances
This argument does not support pathnames to objects below the instance level of an ATPG library model. You can use a pathname expression to select several instances and the tool will then add nonscan instances for all the pins on those instances; but if the expression specifies a location below the instance level of an ATPG library model, the tool will issue an error message. -INStance | -Control_signal | -Module An optional switch that specifies whether the pathnames are instances, pins (control signals), or modules. An example Verilog module is module clkgen (clk, clk_out, ) where clkgen is the module name. You can only use the -Control_signal option in Dft mode. The default is instances. Examples The following example specifies that DFTAdvisor ignore the sequential i_1006 instance when identifying and inserting the required scan circuitry:
add nonscan instances i_1006
Related Commands Delete Nonscan Instances Insert Test Logic Report Sequential Instances Run Set Nonscan Handling
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Command Dictionary Add Nonscan Models
Add Nonscan Models

Scope: All modes Usage ADD NONscan Models model_name Description Instructs DFTAdvisor to ignore all instances of the specified sequential DFT library model when identifying and inserting the required scan elements and test logic into the design. The Add Nonscan Models command causes DFTAdvisor to ignore the instances of the specified models, when you execute both the scan identification process with the Run command, and the scan insertion process with the Insert Test Logic command. DFTAdvisor does not check the scannability on the instances instantiated from the added nonscan models, unless you specify checking using the Set Nonscan Handling command. If you want to flag individual instances as non-scan, you can use the Add Nonscan Instances command. Arguments model_name A required repeatable string that specifies the model names that you want DFTAdvisor to ignore. You must enter the model names as they appear in the DFT library. Examples The following example specifies that DFTAdvisor should not substitute any of the instances of the DFT library model named d_flip_flop with the equivalent scan replacement DFT library model.
add nonscan models d_flip_flop
Related Commands Delete Nonscan Models Insert Test Logic Run Report Nonscan Models Set Nonscan Handling
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Command Dictionary Add Notest Points
Add Notest Points

Scope: Setup and Dft modes Usage ADD NOtest Points {pin_pathname | instance_pathname | instance_expression [-Observe_scan_cell]} | -Path filename Description Adds circuit points to list for exclusion from testability insertion. The Add Notest Points command excludes the specified cell output pins, excludes specified D input scan cells, excludes all output pins on the specified instance, or excludes delay paths from use as controllability and observability insertion points. If the selected pin is already a control or observe point, an error occurs when you issue this command. If you specify a path file that contains delay paths, DFTAdvisor marks each gate in the path; consequently, DFTAdvisor adds no test points to the output of that gate. This prevents control and observation points from being added to a critical path and thus prevents increasing the load on any of these gates in that path. The format of the file is the same as the file loaded into Tessent FastScan with the Load Paths command. For more information on the format, refer to The Path Definition File in the Scan and ATPG Process Guide. The Report Notest Points command displays all the pins in this list or can list the defined critical paths. Arguments pin_pathname A repeatable string that lists the output pins that you do not want to use for controllability and observability insertion. instance_pathname A repeatable string that lists the instances whose output pins you do not want to use for controllability and observability insertion. All output pins within that (hierarchical) instance are added to the list of pins that should be excluded from consideration. instance_expression A string representing a list of instances within the design. The string instance_expression is defined as:
The asterisk (*) is a wildcard that allows you to match many instances in a design. Any expression that does not contain an asterisk (*) will match exactly zero or one instance. This argument does not support pathnames to objects below the instance level of an ATPG library model. You can use a pathname expression to select several instances and the tool will then add notest points for all the pins on those instances; but if the expression specifies
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Command Dictionary Add Notest Points
a location below the instance level of an ATPG library model, the tool will issue an error message. -Observe_scan_cell An optional switch that excludes the instance named in the instance_pathname argument for use as an observation scan cell. -Path filename A switch and filename pair that specifies the pathname to a file that contains critical path information. For more information on the format of the file, refer to The Path Definition File in the Scan and ATPG Process Guide. Examples The following example first sets up the test point identification parameters, then specifies output pins tr_io and ts_i that DFTAdvisor cannot use for testability insertion:
setup test_point identification -control 9 -obs 20 -patterns 32000 -base simulation setup test_point insertion -cshare 16 -oshare 16 set system mode dft setup scan identification none add notest points tr_io ts_i run
Related Commands Delete Notest Points Report Notest Points Setup Test_point Insertion
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Command Dictionary Add Output Masks
Add Output Masks

Scope: Setup mode Usage ADD OUtput Masks {primary_output | -All} [-Nohold | -Hold {0 | 1}] Description Masks the specified primary output pins during the scan identification analysis. DFTAdvisor uses primary output pins as the observe points during the scan identification process. When you mask a primary output pin, you inform DFTAdvisor to mark that pin as an invalid observation point during the identification process. There are specific design practices that mask specific primary output pins in order to group the sequential elements associated with those primary outputs (for example, if you are using wrapper chains). For more information on wrapper chains, refer to Understanding Wrapper Chains in the Scan and ATPG Process Guide. You can set a default mask for all output and bidirectional pins using the Setup Output Masks command. You can add a hold value to a default mask with the Add Output Masks command, or remove a hold value using the Delete Output Masks command. To turn off the default masks for all output pins, you must use the Setup Output Masks command with the Off literal. Arguments primary_output A required repeatable string that specifies the names of the primary output pins to mask. When you enter the primary_output argument without the -Hold switch, DFTAdvisor marks the specified pins as invalid observation points during the identification process. If you specify the -Hold switch, then, in addition to masking the specified pins, DFTAdvisor also applies and maintains the specified (-Hold) state value on the pins. -All A required switch that masks all the primary output pins. -Nohold An optional switch that allows any state value on the specified primary output pin. This is the default. -Hold 0 | 1 An optional switch and literal pair that specifies the state to maintain on the primary output pin. If you use this switch, you can explicitly specify that the output pin is driving the inactive value. The choices for the hold literal value are as follows: 0 Maintains a low logic state on the primary output pin. 1 Maintains a high logic state on the primary output pin.
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Command Dictionary Add Output Masks
Examples The following example first sets up DFTAdvisor to recognize only the wrapper cells during the scan identification run. The invocation default identification type is sequential scan. Next, the example specifies the primary output pins that the Add Output Masks command associates with the wrapper cells.
setup scan identification wrapper_chains add output masks out1 out2 out3
When you issue the Run command later in the session, DFTAdvisor identifies all the sequential elements that are observable only through the masked primary output pin. Then, when you issue the Insert Test Logic command, DFTAdvisor stitches all those scan cells it previously identified as being wrapper cells into one wrapper chain. Related Commands Analyze Output Observe Delete Output Masks Report Output Masks Setup Output Masks Setup Scan Identification
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Command Dictionary Add Pin Constraints
Add Pin Constraints

Scope: Setup mode Usage ADD PIn Constraints primary_input_pin {C0 | C1 | CZ | CX} Description Holds the specified input pin at a constant state during the DRC and loop cutting processes. DFTAdvisor performs the DRC and loop cutting processes when you issue the Set System Mode Dft command. During the DRC process, you want to hold a pin at a constant state. For example, you may want to hold a test enable pin at the active state to keep the chip in test mode. Note This command affects other commands that relate to fault simulation, such as simulationbased test point selection. If you are using the wrapper chain type, DFTAdvisor also uses pin constraints set to unknown as a way to flag primary inputs that are uncontrollable from the higher chip-level primary inputs. When DFTAdvisor performs the scan identification process during the Run command, it adds to the scan candidate list the sequential cells that are controllable through the primary input pin; those that you constrained to an unknown value. For more information on wrapper chains, refer to Understanding Wrapper Chains in the Scan and ATPG Process Guide. You can set a default pin constraint value for all input and bidirectional pins using the Setup Pin Constraints command. The pin constraints set by the Setup Pin Constraints command are overridden by the values set with the Add Pin Constraints command. You can remove an override of a default pin constraint using the Delete Pin Constraints command. You can remove default pin constraint for all input pins, with the Setup Pin Constraints command. Arguments primary_input_pin A required string that specifies the primary input pin to hold at the constant_value. C0 | C1 | CZ | CX A literal that specifies the constant value to constrain the primary_input pin to. The constraint choices are as follows: C0 Applies a constant 0 to the specified primary input pins. C1 Applies a constant 1 to the specified primary input pins. CZ Applies a constant Z (high-impedance) to the specified primary input pins. CX Applies a constant X (unknown) to the specified primary input pins.
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Command Dictionary Add Pin Constraints
Example The following example illustrates how to hold two primary input pins to constant values:
add pin constraints kgmt c1 add pin constraints dsint c0
Related Commands Add Seq_transparent Constraints Analyze Input Control Delete Pin Constraints Report Pin Constraints Setup Pin Constraints
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Command Dictionary Add Pin Equivalences
Add Pin Equivalences

Scope: Setup mode Usage ADD PIn Equivalences primary_input_pin [-Invert] primary_input_pin_ref Description Specifies to hold the specified primary input pins at a state either equal to or inverted in relationship to the state of another primary input pin during rules checking. You cannot specify a constrained pin as an equivalent pin. That is, you cannot specify a constrained pin as either the primary_input_pin or the primary_input_pin_ref arguments. If you want to add a pin constraint to a group of equivalent pins, you must first delete the pin equivalence and manually add the pin constraint to each individual pin. Rules checking occurs when you use the Set System Mode Dft command. During these rule checks, there are times when a pin needs to be held at the same (or opposite) state in reference to another pin. Note This command has effects on other commands that relate to fault simulation, such as simulation-based test point selection. Arguments primary_input_pin A required, repeatable string that specifies a list of primary input pins whose values you want to either equal or invert with respect to primary_input_pin_ref. -Invert An optional switch that specifies for DFTAdvisor to hold the primary_input_pin value to the opposite state of the primary_input_pin_ref value. If you use this switch, you must enter it immediately prior to the primary_input_pin_ref value. primary_input_pin_ref A required string that specifies the name of the primary input pin whose value you want DFTAdvisor to use when determining the state value of primary_input_pin. You can immediately precede this string with the -Invert switch to cause DFTAdvisor to hold the primary_input_pin value to the opposite state of the primary_input_pin_ref value. Examples The following example restricts the first primary input (indata2) to have an inverted value with respect to the second primary input (indata4):
add pin equivalences indata2 -Invert indata4
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Command Dictionary Add Pin Equivalences
Related Commands Delete Pin Equivalences Report Pin Equivalences
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Command Dictionary Add Primary Inputs
Add Primary Inputs

Scope: Setup mode Usage ADD PRimary Inputs net_pathname [-Cut] [-Module] Description Adds a primary input to the net. The Add Primary Inputs command adds an additional primary input to each specified net path. Once added, the tool designates them as user-class primary inputs, as opposed to the primary inputs described in the original netlist, which it designates as system-class primary inputs. Use the -Cut option to disconnect the original drivers of the net, so that the added primary input becomes the only driver of the net. Otherwise, if there are other drivers besides the newly added primary input, the tool treats this net as a wired net. You can display the user class, system class, or full classes of primary inputs using the Report Primary Inputs command. Arguments net_pathname A required, repeatable string that specifies the pathname of the pins to which you want to add primary inputs. -Cut An optional switch that specifies disconnection of the original drivers of the net, making the added primary input the only driver of the net. -Module An optional switch that specifies addition of the primary input to the specified nets in all modules. Only one primary input is added to the design for that net when many occurrences of that net occurs in the modules.
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Command Dictionary Add Primary Inputs
Examples The following example adds two new primary inputs to the circuit and places it in the user class of primary inputs:
add primary inputs indata2 indata4
Related Commands Delete Primary Inputs Report Primary Inputs
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Command Dictionary Add Primary Outputs
Add Primary Outputs

Scope: Setup mode Usage ADD PRimary Outputs net_pathname Description Adds a primary output to the net. The Add Primary Outputs command adds an additional primary output to each specified net. Once added, the tool defines them as user class primary outputs. The tool defines the primary outputs described in the original netlist as system class primary outputs. You can display the user class, system class, or full classes of primary outputs using the Report Primary Outputs command. Arguments net_pathname A required, repeatable string that specifies the nets to which you want to add primary outputs. Examples The following example adds a new primary output to the circuit and places it in the user class of primary outputs:
add primary outputs outdata1
Related Commands Delete Primary Outputs Report Primary Outputs
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Command Dictionary Add Read Controls
Add Read Controls

Scope: Setup mode Usage ADD REad Controls {0 | 1} primary_input_pin Description Adds an off-state value to specified RAM read control lines. The Add Read Controls command defines the circuit read control lines and assigns their offstate values. The off-state value of the pins that you specify must be sufficient to keep the RAM outputs stable. You cannot use clocks, constrained pins, or equivalent pins as read control lines. Arguments 0 A literal that specifies 0 as the off-state value for the RAM read control lines. 1 A literal that specifies 1 as the off-state value for the RAM read control lines. primary_input_pin A required, repeatable string that lists the primary input pins you want to designate as RAM read control lines, and to which you are assigning the given off-state value. Examples The following example assigns an off-state value of 0 to two read control lines, r1 and r2:
add clocks 0 clk add read controls 0 r1 r2 set system mode dft run
Related Commands Analyze Control Signals Delete Read Controls Report Read Controls
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Command Dictionary Add Scan Chains
Add Scan Chains

Scope: Setup mode Prerequisites: Prior to using this command, you must define the scan chain group with the Add Scan Groups command. If multiple scan chains are in the same scan group, you must load the chains in parallel. Usage ADD SCan Chains chain_name group_name primary_input_pin primary_output_pin Description Specifies a name for a pre-existing scan chain within the design. The Add Scan Chains command defines a scan chain that exists in the design. A scan chain references the name of a scan chain group, which you must define prior to issuing this command. A pre-existing scan chain is a serially connected set of scan cells that has been stitched together in a previous scan insertion operation, or that you created manually. In order for DFTAdvisor to be able to correctly insert scan elements in the remainder of the design or to run rules checking on existing scan circuitry, you need to notify DFTAdvisor of this circuitry, so it can treat those elements in the chain differently than the elements in the rest of the design. When you use this command to notify DFTAdvisor of a pre-existing scan chain, DFTAdvisor removes the scan cells in the scan chain from the eligible scan elements list. Because the tool removes the scan cells in the scan chain from the scan candidate list, the rules checker does not perform the usual scannability checks on those scan cells. However, the rules checker does perform additional rules checking based on the declaration of pre-existing scan elements that pertain to the checking of the validity and the operation of that scan chain. If the design does have a pre-existing scan chain that you declare with the Add Scan Chains command, you need to provide information on the operation of that scan chain in a test procedure file. Arguments chain_name A required string that specifies the name of the pre-existing scan chain you want added to the scan group. group_name A required string that specifies the name of the scan chain group to which you are adding the scan chain. primary_input_pin A required string that specifies the primary input pin of the scan chain. primary_output_pin A required string that specifies the primary output pin of the scan chain.
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Command Dictionary Add Scan Chains
Examples The following example defines two scan chains (chain1 and chain2) that belong to the same scan group (group1):
add scan groups group1 scanfile add scan chains chain1 group1 indata2 testout2 add scan chains chain2 group1 indata4 testout4
Related Commands Add Scan Groups Delete Scan Chains Report Scan Chains Ripup Scan Chains
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Command Dictionary Add Scan Groups
Add Scan Groups

Scope: Setup mode Usage ADD SCan Groups group_name test_procedure_filename Description The Add Scan Groups command specifies a group name for a set of pre-existing scan chains in a design. Only one group name can be specified per DFTAdvisor session. If the design has pre-existing scan chains, those scan chains must belong to a scan group. The Add Scan Groups command also specifies the corresponding test procedure file for that scan group. A sequence of procedures in the test procedure file defines the operation of the scan chains within a scan group. The scan group must have a corresponding test procedure file. When needed, you can also use the Add Scan Groups command to provide initialization values for non-scan memory elements. If the design does not have pre-existing scan chains and you need to initialize some non-scan memory elements for scannability checking, you can specify dummy as the group_name along with a test_procedure_filename. Then, within the test procedure file, you can use the optional test_setup procedure to initialize the non-scan memory elements. As a result, DFTAdvisor models the non-scan memory elements as a TIE1 or TIE0. Note You must also define these same elements as non-scan using the Add Nonscan Instances command. Arguments group_name A required string that specifies the name for the scan chain group. test_procedure_filename A required string that specifies the name of the test procedure file that contains the information for controlling the scan chains in the specified scan chain group. Examples The following example defines a scan chain group, group1, which loads and unloads a set of scan chains, chain1 and chain2, by using the procedures in the file, scanfile:
add scan groups group1 scanfile add scan chains chain1 group1 indata2 testout2 add scan chains chain2 group1 indata4 testout4
Related Commands Add Scan Chains Delete Scan Groups Report Scan Groups
Read Procfile Write Procfile
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Command Dictionary Add Scan Instances
Add Scan Instances

Scope: All modes Usage ADD SCan Instances pathname | instance_expression [-INStance | -Control_signal | -Module] [-INPut | -Output | {-Hold {0 | 1}}] Description Adds specified instances to the scannable instance list. When inserting partial scan, the Add Scan Instances command ensures that DFTAdvisor includes specific sequential instances in the scan list. DFTAdvisor generates the scan list during the scan identification process (executed with the Run command in the Dft mode). If the specified instance does not pass the rules checking process, it is not included in the identified scan list. If you do not issue the Add Scan Instances command when inserting partial scan, DFTAdvisor chooses sequential instances included in the identified scan list based on the settings specified with the Setup Scan Identification command. If in Dft mode, the Add Scan Instances command can accept scannable instance pathnames, control signal pins, or module names as arguments. Scannable instances are sequential instances that pass all the scannability checks run by the Design Rule Checker when entering Dft mode. When adding scan instances with control signals, DFTAdvisor adds all scannable instances controlled by the control signals to the identified scannable instance list. Control pins can be any clock, set, or reset signal (primary input or output) that controls the contents of sequential instances. The Report Control Signals command displays the control pins for the sequential instances in the design. Sequential cells that have an S4 violation are not targeted for scan cell conversion. You can use this command in either Setup or Dft mode to override the default behaviorand mark this cell as a potentially scannable instance. When you force the conversion, the instance becomes an unknown value and DFTAdvisor propogates the effects of that change through the circuit looking for additional S1 rule violations. If you force the conversion of an instance while in Setup mode, those S1 violations are reported during the DRC check when you enter Dft mode. You can use the Delete Scan Instances command to remove the exception status that you have attached to an instance with the Add Scan Instances command. In this case, although the instance is converted back into a non-scan instance, the effects of its previous unknown state on downstream instances is not reset. Arguments pathname A required repeatable string that specifies the pathnames of the sequential instances or control signals (that control instances) to add to the scan instance list. If the specified
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Command Dictionary Add Scan Instances
instance is hierarchical, then all sequential instances beneath it are also added to the scan list. instance_expression A required string representing a list of instances within the design. The string instance_expression is defined as:
The asterisk (*) can be used as a wildcard character. Any expression that does not contain an asterisk (*) will match exactly zero or one instance. This argument does not support pathnames to objects below the instance level of an ATPG library model. If you use a pathname expression to select several instances, the tool will add scan instances for all the pins on those instances; but if the expression specifies a location below the instance level of an ATPG library model, an error message displays. -INStance | -Control_signal | -Module An optional switch that specifies whether the specified pathnames are instances, control signal pins, or modules. You can only use the -Control_signal option in Dft mode. The default is -INStance. -INPut | -Output | {-Hold {0 | 1}} An optional switch that adds scan instances as input or output wrapper cells. If you specify the -Hold option, then you must also supply a high (1) or low (0) literal to define hold 0 or hold 1 output wrapper cells. If none of these options are specified, the added scan instances are considered regular scan cells. Examples The following example adds two sequential instances to the identified scan list (assuming they pass rules checking), sets the identification process to use the 50 percent of the eligible scan elements that maximize the fault coverage, and then runs the scan identification process.
add scan instances i_1006 i_1007 set system mode dft setup scan identification sequential atpg -percent 50 run
The scan identification process chooses the optimal 50 percent of eligible scan instances but always includes i_1006 and i_1007 within that 50 percent. Related Commands Delete Scan Instances Report Sequential Instances Setup Scan Identification
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Command Dictionary Add Scan Models
Add Scan Models

Scope: All modes Usage ADD SCan Models model_name Description Specifies that DFTAdvisor is to flag every instance of the named DFT library model for inclusion into the identified scan list. If DFTAdvisor is inserting partial scan, then the Add Scan Models command ensures DFTAdvisor includes all instances of a specific sequential DFT library model in the scan list. DFTAdvisor generates the scan list during the scan identification process, which you initiate with the Run command in the Dft mode. DFTAdvisor subsequently replaces all instances in the scan list with the equivalent DFT library scan model during scan synthesis, which you initiate with the Insert Test Logic command while you are in Dft mode (Set System Mode). If you do not issue the Add Scan Models command with partial scan, DFTAdvisor chooses the sequential instances it includes in the scan list using the settings you specified with the Setup Scan Identification command, or, alternatively, the default argument values for the command. If DFTAdvisor is in the Dft mode, then the Add Scan Models command only flags the scannable instances of the specified library model for inclusion into the scan list. Scannable instances are those sequential instances previously passing all the scannability checks run by the Design Rule Checker when you placed DFTAdvisor into the Dft mode. DFTAdvisor omits library model instances from the scan list if the instance fails the design rule checks. The Add Scan Models command flags all instances of the specified sequential DFT library model, where the Add Scan Instances command only individually flags sequential design instance(s). Arguments model_name A required, repeatable string specifying the model names that you want to add to the scan model list. Enter the model names as they appear in the DFT library. Examples The following example flags all instances of the specified DFT library model for inclusion into the scan list.
add scan models dff1a set system mode dft setup scan identification sequential atpg -percent 50 run
Because of the previous setup in this example, when DFTAdvisor runs the scan identification process, it chooses the optimal 50 percent of eligible scan instances, ensuring that it includes all eligible instances of the dff1a model in that 50 percent of identified scan instances.
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Command Dictionary Add Scan Models
Related Commands Delete Scan Models Report Scan Models
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Command Dictionary Add Scan Partition
Add Scan Partition

Scope: DFT mode Usage ADD SCan PArtition object_name -INstance {pathname... | instance_expression...} -MOdule module_name... -LIbrary_model library_model_name... [-NUmber integer | -MAx_length integer] [-EDT] [-VErbose] Description Specifies a grouping of scan cells (a partition) in which scan chains are inserted separately from the remaining scan cells in the design. The remaining cells are placed into a default scan partition called default_scan_partition. If a module instance name is supplied in the list of instances, all sequential instances hierarchically under this given module instance are added to the scan partition. If a module name is supplied, all instances of that module and the sequential instances hierarchically under these instances are added to the scan partition. If a library model name is supplied, all instances of this library model are added to the scan partition if this library model is defined for a sequential instance. At least one of the -INstance, -MOdule, and -LIbrary_model switches should be supplied. They can also be supplied together in the same command line. The specified group of cells are placed in scan chains based on the number of chains or the maximum chain length option specified with this command, along with the -clock/-edge merge options with the Insert Test Logic command, and the clock groups with the Add Clock Groups command. The -number and -max_length options of the Insert Test Logic command apply only to the default scan partition, not to the user specified scan partitions. If the number of chains or the maximum chain length is not specified, a single chain is inserted for the partition, by default. The tool generates a single dofile and testprocedure file even if there are multiple scan partitions defined. However, in the dofile, the scan chain declarations of the same scan partition are separated from the other groups of scan chain declarations by a comment line which indicates the scan partition name. Also, the groups of scan chain declarations are in the same order as the defined scan partitions. If the -Edt switch is used, DFTAdvisor writes out the Tessent TestKompress command, Add Edt Block name, before every group of scan chain declarations, where name is the name of the scan partition specified by object_name. Default scan pin naming for each partition cannot be specified by means of the Setup Scan Pins command. However, individual scan pin naming per chain can be specified by means of the Add Scan Pins command. This gives the control over scan pin naming for each scan partition since scan chains are created in the order the scan partitions are defined and the number of scan chains for each scan partition is known.
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Note The scan cells of subchains cannot be included in scan partitions. This is because a subchain container can be a blackbox instance, the sequential cells of which do not exist in the netlist. Therefore, subchains can be included in scan partitions by specifying the pathname of their container module instances, or the module name of the container modules. Arguments object_name A required string that specifies a name for the scan partition. -INstance {pathname... | instance_expression...} A required switch and a repeatable string that specify the pathname(s) of the sequential instances that you want to place into the scan partition. If a module instance pathname is specified, all sequential instances hierarchically under that instance are added to the partition. This switch can be used along with the -Module and -Library_model switches (and their arguments) in the same command line. However, all three cannot be omitted. The repeatable string can be in the form of an absolute instance pathname or a pathname in regular expression form. This argument does not support pathnames to objects below the instance level of an ATPG library model. If the instance pathname/expression cannot be mapped to any sequential element in the design, the tool generates an error message. The string instance_expression is defined as: {string | string *} ... The asterisk (*) is a wildcard that allows you to match many instances in a design. Any expression that does not contain an asterisk (*) will match exactly zero or one instance. -MOdule module_name... A required switch and a repeatable string that specify the module name(s) of the instances that are the containers of the sequential instances that you want to place into the scan partition. All sequential instances hierarchically under these container instances are added to the partition. This switch can be used along with the -Instance and -Library_model switches (and their arguments) in the same command line. However, all three cannot be omitted. -LIbrary_model library_model_name... A required switch and a repeatable string that specify the library model name(s) of the sequential instances that you want to place into the scan partition. This switch can be used along with the -Instance and -Module switches (and their arguments) in the same command line. However, all three cannot be omitted. -NUmber integer An optional switch and integer pair that specify the exact number of scan chains that you want DFTAdvisor to insert for the scan partition specified. Final results depend upon the number of scan candidates. The default number of chains is 1. The -number and
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-max_length options of the Insert Test Logic command are ignored for the user added scan partitions. -MAx_length integer An optional switch and integer pair that specify the maximum number of scan cells that DFTAdvisor can stitch into a scan chain of the scan partition specified. DFTAdvisor evenly divides the scan cells into scan chains that are smaller than the max_length integer. Final results depend upon the number of scan candidates. The -number and -max_length options of the Insert Test Logic command are ignored for the user added scan partitions. -EDT An optional switch that specifies DFTAdvisor to write out the Tessent TestKompress command Add Edt Block name before each group of scan chain declarations in the dofile written out by the tool. In the dofile, the scan chain declarations of the same scan partition are grouped together and separated from the other groups of scan chain declarations by a comment line. The name string in the Tessent TestKompress command is the same as the scan partition name specified by object_name. -VErbose An optional switch that turns on verbose transcript printing. When specified, the pathnames of the sequential cells included in the scan partition are printed in the session transcript. Examples In the following example, two scan partitions are defined. The first partition, partA, is defined using exact pathnames of the sequential instances, and the second partition, partB, is defined by the container module instance of the sequential instances. A single scan chain is inserted by default for partA, whereas two scan chains are inserted for partB. Two scan chains are inserted for the remaining cells in the default scan partition, as specified by the -number argument of the Insert Test Logic command. The -Edt switch is used for partA, allowing the tool to write out the Tessent TestKompress command, Add Edt Block, in the dofile, in addition to the scan chain declarations. Also, Individual scan I/O pins per chain and default scan I/O pin naming are specified by means of the Add Scan Pins and Setup Scan Pins commands, respectively.
add clocks 0 clk1 set system mode dft add scan partition partA -instance udff1 umodA/udff32 umodB/udff5 -edt // 1 chain add scan partition partB -instance umodC -number 2 -edt // 2 chains run add scan pins chain1 partA_chain1_si partA_chain1_so add scan pins chain1 partB_chain1_si partB_chain1_so setup scan pins input -indexed -prefix mysi -initial 1 setup scan pins output -indexed -prefix myso -initial 1 insert test logic -number 2 // 2 chains inserted for the default scan partition write atpg setup fscan
So, a total of five scan chains are inserted. After mapping the individual scan I/O pins per chain, new scan I/O pin names are generated for the remaining chains based on the specified default pin naming. The dofile generated by the tool looks similar to the one below. Note that the scan chain declarations of each scan partition are denoted by a comment line. The order of the groups
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of declarations is the same as the order of the scan partition declarations. The default scan partition chains are printed as the last group. Also note that the Tessent TestKompress Add Edt Block commands are written out since the -Edt switch is used. For the default scan partition, the tool generates the name edt_top_block to use it as the edt block identifier string in the Add Edt Block command.
// // Generated by DFTAdvisor at Wed Jul 12 14:09:58 2006 // add scan groups grp1 fscan.testproc // The scan chains of scan partition partA add edt block partA add scan chains chain1 grp1 partA_chain1_si partA_chain1_so // The scan chains of scan partition partB add edt block partB add scan chains chain2 grp1 partB_chain1_si partB_chain1_so add scan chains chain3 grp1 mysi1 myso1 // The scan chains of scan partition default_scan_partition add edt block edt_top_block add scan chains chain4 grp1 mysi2 myso2 add scan chains chain5 grp1 mysi3 myso3 add clocks 0 clk1
Related Commands Delete Scan Partitions Insert Test Logic Report Scan Partitions Add Clock Groups
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Command Dictionary Add Scan Pins
Add Scan Pins

Scope: All modes Usage ADD SCan PIns chain_name scan_input_pin scan_output_pin [-CLock pin_name] [-CUt] [-Registered] [-Top primary_input_pin primary_out_pin] Description Declares the name of a scan chain at the top-level module and assigns the corresponding scan input pin, scan output pin, and optionally, scan clock pin you associate with the chain. Tip: For information on assigning scan pins to scan chains and the fixed-order file, refer to Naming Scan Input and Output Ports in the Scan and ATPG Process Guide. If you specify nonexistent signal names for the scan input or scan output pins, DFTAdvisor generates a warning and adds the appropriate pins when you perform scan synthesis with the Insert Test Logic command. For explicitly defining the primary scan input and scan output pins at the top-level of the design and specifing internal pin pathnames for the scan_input_pin and scan_output_pin arguments, you must use the -Top switch when you execute the Write Atpg Setup command. If you do not issue this command, DFTAdvisor uses the default names when generating the scan chain. The default name of the scan chain is chain1, with the corresponding scan input pin named scan_in1 and the corresponding scan output pin named scan_out1. If DFTAdvisor inserts multiple scan chains, the default naming increments the numerical suffix of each argument by one for each chain, such as chain2, scan_in2, and scan_out2. Each use of the Add Scan Pins command specifies the naming for a single scan chain. You can optionally use the Setup Scan Pins command to globally set the default naming conventions for scan chains that do not use existing design pins. Arguments chain_name A required string that specifies the name of the scan chain with which you want DFTAdvisor to associate the scan_input_pin and scan_output_pin names. scan_input_pin A required string that specifies the scan input pin name of the scan chain. This pin can be a top-level input pin, top-level bidirectional pin, or an internal signal. In addition to a primary input pin name (for example, scan_in), you can also specify an internal instance pin pathname as the scan_input_pin value. If you do so, that pin pathname must be an output pin of an instance. For example, you could use an internal instance pin pathname /I116/d, where I116 is the instance name of the I/O cell and d is the pin name. If the specified internal instance pin cannot be traced back to a primary input pin
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through a simple path (only inverters or/and buffers), when the Write Atpg Setup command is issued, a warning message is written to the top of the ATPG dofile and the following command is added prior to the Add Scan Chains command referencing the internal scan_input_pin argument:
add primary input -cut scan_input_pin
Example 1 shows the content written to the ATPG dofile in this case. If the pin is a top-level bidirectional pin, DFTAdvisor assumes that you configured the pin to operate as an input during the scan test and does not check for correct configuration. If -Registered is specified, the scan_input_pin is the output of the DFF head register. scan_output_pin A required string that specifies the scan output pin name of the scan chain. This pin can be any of the following:
o o o
a top-level output pin a top-level bidirectional pin (single driver) an internal signal
Note If the scan output pin you specify has a functional connection, DFTAdvisor multiplexes this connection with the connection line from the last scan cell of the scan chain. In addition to a primary output pin name (for example, scan_out), you can also specify an internal instance pin pathname (for example, /I116/q) for the scan_output_pin value, providing this pin pathname is an input pin of an instance. If the specified internal instance pin cannot be traced forward to a primary output pin through a simple path (only inverters or/and buffers), when the Write Atpg Setup command is issued, a warning message is written to the top of the ATPG dofile and the following command is added prior to the Add Scan Chains command referencing the internal scan_output_pin argument:
add primary output scan_output_pin
Example 2 shows the content written to the ATPG dofile in this case. If the pin is a top-level bidirectional pin, DFTAdvisor assumes that you configured the pin to operate as an output during the scan test and does not check for correct configuration. If -Registered is specified, the scan_output_pin is the input of the DFF tail register. -CLock pin_name An optional switch and string pair that specifies the pin name of the clock that you want DFTAdvisor to assign to the scan chain. You must have predefined this pin as a scan clock using the Add Clocks command.
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-CUt An optional switch that specifies to remove an existing functional connection, if there is one, to the specified scan output pin and to connect the last scan cell of the specified scan chain to this scan output pin.
-Registered An optional switch that identifies head and tail DFF registers for the scan chain. DFTAdvisor does not insert new scan cells as head and tail registers if it cannot find them in the circuit. For additional information, refer to Attaching Head and Tail Registers to the Scan Chain in the Scan and ATPG Process Guide.
-Top primary_input_pin primary_out_pin An optional switch and two strings that defines the corresponding top-level primary input/output pins for the scan in and scan out ports. DFTAdvisor uses these names when generating the ATPG dofile. Refer to the second example for clarification of how the contents of the ATPG dofile are created. Both pin names must be supplied. This option does not add pins to the top-level of the design.
Example 1 The following example specifies an internal pin pathname that DFTAdvisor cannot trace back to the primary input. See the resulting dofile contents in Example 2-2 on page 75.
add clocks 0 clk setup scan identification full_scan set tri gating bus -control ten set tri gating out1 out4 -control ten set tri gating out3 out2 set bidi gating on add scan pins c1 udff1/Q tbus2_drv1/A add scan pins c2 bidi_1/X tbus1_drv2/A -top io2 out2 set system mode dft report dft check -tri run insert test logic -number 2 report scan chains write atpg setup results/tri_on_ten -r write netlist results/tri_on_ten.v -verilog -r
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Example 2-2. Generated dofile Tracing Back to Primary Input // // Generated by DFTAdvisor at Fri Aug 29 18:45:24 2008 // // The generated dofile contains references to internal pins // The file may require editing to make it function properly. add scan groups grp1 results/tri_on_ten.testproc add primary input -cut udff1/Q // internal input pin add scan chains c1 grp1 udff1/Q out3 add scan chains c2 grp1 io2 out2 add clocks 0 clk add pin constraints test_en C1 Example 2 The following example specifies an internal pin pathname that DFTAdvisor cannot trace forward to the primary output. See the resulting dofile contents in Example 2-3 on page 76.
add clocks 0 clk setup scan identification full_scan set tri gating bus -control ten set tri gating out1 out4 -control ten set tri gating out3 out2 set bidi gating on add scan pins c1 bidi_2/X tbus2_drv1/A -top io3 out3 add scan pins c2 bidi_1/X udff1/D set system mode dft report dft check -tri run insert test logic -number 2 report scan chains write atpg setup results/tri_on_ten -r write netlist results/tri_on_ten.v -verilog -r
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Example 2-3. Generated dofile Tracing Forward to Primary Input // // Generated by DFTAdvisor at Fri Aug 29 18:57:57 2008 // // The generated dole contains references to internal pins // The le may require editing to make it function properly. add scan groups grp1 results/tri_on_ten.testproc add scan chains c1 grp1 io3 out3 add primary output udff1/D // internal output pin add scan chains c2 grp1 io2 udff1/D add clocks 0 clk add pin constraints test_en C1 Related Commands Delete Scan Pins Report Scan Pins Setup Scan Pins Write Atpg Setup
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Command Dictionary Add Seq_transparent Constraints
Add Seq_transparent Constraints

Scope: Setup mode Usage ADD SEq_transparent Constraints {C0 | C1} model_name pin_name Description Specifies the enable value of a clock enable that internally gates the clock input of a non-scan cell for sequential transparent scan identification. Designs sometimes contain circuitry where the clock enable signal internally gates the clock input of a non-scan cell. In these cases, the clock enable must hold at a certain value in order for the cells to behave as sequentially transparent. The clock enable input of a cell may come from primary inputs or other memory elements. If the sources of a clock enable input come from the output of other memory elements, DFTAdvisor identifies those memory elements for scan during the scan_sequential identification run. Arguments C0 | C1 A required literal that specifies the application of the constant 0 or 1 to the pin_name. model_name A required string that specifies the DFT library model to whose pin_name you want to apply the specified C0 or C1 constant. pin_name A required, repeatable string that specifies the clock enable pin name for the model_name specified and that to which DFTAdvisor will apply the specified constant. Example Example 2-4 shows an example usage of this command.
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Command Dictionary Add Seq_transparent Constraints
Example 2-4. Add Seq_transparent Constraints
Related Commands Add Pin Constraints Delete Seq_transparent Constraints Report Pin Constraints
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Command Dictionary Add Sub Chains
Add Sub Chains

Scope: Setup mode Usage ADD SUb Chains object_name subchain_name scan_input_pin scan_output_pin length scan_type [-Module | -Library_model | -Instance] [-TEN test_enable_pin {0 | 1}] [-TCLK test_clock_pin {0 | 1}] [-NO_Reordering] Description Specifies a pre-existing scan chain within a module, library model, instance, blackbox, or empty module in a hierarchical design (subchain). An empty module is a module defined in the netlist without any content; that is, it consists of only an input and output port definition. DFTAdvisor assumes that all scan cells within the subchain blocks are part of the specified subchains. Any scan cell that is floating in the subchain block and not part of the subchain is not considered for the top-level scan chain stitching. You can use the Add Sub Chains command to incorporate those scan subchains into the top-level scan chain(s) during the stitching process. DFTAdvisor can write subchain setup information to a file with the Write Subchain Setup command. You can then read in this setup file that contains the Add Sub Chains command as part of the setup and avoid having to manually define the pre-existing scan subchains at the higher design level. You can define subchains with their inputs (scan input and scan enable pins on their subchain container) tied to 0 or 1. You can also define subchains with their scan inputs connected to their scan output either directly or via buffers. DFTAdvisor removes such connections from the scan input pin and reuses the connection wire to connect the scan output port to the next scan cell. Any buffers lying along such feedback are then retained in scan output connection. To define clock information for subchains, see Add Subchain Clocks. Scannability analysis DRCs: S1, S2, and S3 validate the defined subchains when you exit Setup mode. Arguments object_name A required string that specifies either the pathname of an instance, the name of a module, or the name of a library model. The object_name is the container where the subchain resides. subchain_name A required string that specifies a name for the scan subchain. A unique subchain name should be used for each Add Sub Chains command. scan_input_pin A required string that specifies the scan input pin of the scan subchain.
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scan_output_pin A required string that specifies the scan output pin of the scan subchain. length A required integer that specifies the number of scan cells in the scan subchain. scan_type Scan type usage: {Mux_scan{scan_enable [INVerted]} [-CLock pin_name1 pin_name2] }| Clocked_scan scan_clock | Lssd master_clock slave_clock A required literal and multiple argument option that specifies the scan type and control of the scan subchain. Options include:
o
Mux_scan {-SEN_Core | -SEN_In | -SEN_Out} scan_enable [INVerted] Required switch, string, and literal that specifies the type, name, and internal inversion of the scan enable pin on the subchain container (module or library_model). Normally, DFTAdvisor inserts one type of scan enable signal, referred to as Sen_core. In a wrapper chain insertion flow, DFTAdvisor can also insert two more types of scan enable signals if I/O wrapper chains are specified. The scan enable signals inserted for separate input and output wrapper cells are referred to as Sen_in and Sen_out. For more information on I/O wrapper chains, see the Setup Wrapper Chains command. The default type of scan enable is -SEN_Core, if this literal is not specified in the subchain declaration. A subchain may contain all three types of scan enables, in which case you should repeat the triplet for each type of scan enable. -Clock pin_name1 pin_name2 Required switch and string pair that specifies the names of the clock pins on the top module that control the defined subchain. pin_name1 specifies the clocks for the first cell (closer to the scan input). pin_nam2 specifies the name of the clock pin for the last cell (closer to the scan output). The first and the last cell clock pins determine the transition of clock domains when the subchain is placed in a top-level scan chain, so lockup cells are inserted correctly at these transitions. During wrapper chain creation, only the first cell clock pin information is used to determine which top-level scan chain the subchain cell is placed in. If this switch is not specified, DFTAdvisor tries to find the top-level clock pins using the sub-clock pins via structural tracing, as described below. If DFTAdvisor cannot determine the top module clock pins, it places the defined subchain in separate scan chains in the top module, along with other subchains with undetermined top module clock pins.
Clocked_scan scan_clock A required literal and string pair that specifies the clocked-scan style of scan cells and the name of the scan clock for the scan subchain.
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Command Dictionary Add Sub Chains o
Lssd master_clock slave_clock A required literal and two-string triplet that specifies Level-Sensitive Scan Design and the names of the master and slave clocks, respectively, for the scan subchain.
-Module | -Library_model | -Instance An optional switch that specifies the type of the subchain container specified by the object_name argument. The container can then be a module (-Module), a library model (-Library_model), or an instance of a module/model (-Instance). The default type is -Module.
-TEN test_enable_pin {0 | 1} An optional switch, string, and literal pair that specifies the test enable pin added in the submodule that you want connected to the corresponding pin in the top module. The active value can be 0 or 1.
-TCLK test_clock_pin {0 | 1} An optional switch, string, and literal pair that specifies the test clock pin added in the submodule that you want connected to the corresponding pin in the top module. The off-state value can be 0 or 1.
[-NO_Reordering] An optional switch that specifies to keep the order of cells on the specified subchain's scan path intact when writing out the scanDEF file by placing them into an ORDERED section of the corresponding scan chain. When this switch is not specified, the subchain's sequential cells are written into a FLOATING section of the corresponding scan chain which allows them to be reordered.
Example 1 The following example defines a subchain on a sub-module:

add sub chains addr subc1 /scan_in1 /scan_out1 8 mux_scan -sen_core /scan_en inverted \ -clock /topclk1 /topclk2 report sub chains mux_scan: addr subc1 8 scan_in1 scan_out1 scan_en (inverted)
Example 2 The following example defines three subchains on an instance. Note that each subchain has a designated scan enable pin:
add sub chains /mytop/u1 subc1 si1 so1 150 mux_scan -sen_in senin add sub chains /mytop/u1 subc2 si2 so2 138 mux_scan -sen_out senout add sub chains /mytop/u1 subc3 si3 so3 1600 mux_scan -sen_core sen report sub chains mux_scan: /mytop subc1 150 si1 so1 senin mux_scan: /mytop subc2 138 si2 so2 senout mux_scan: /mytop subc3 1600 si3 so3 sen
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Example 2 The following example shows information written out by the Report Scan Cells command following by the same information as it appears when it is written to the scan DEF file.
report scan cells
--------------------------------------------------------------------------------Chain Group Clock CellNo Name Name Pathname CellName ScanOut Clock Polarity --------------------------------------------------------------------------------chain1 dummy /lckup1 latch Q clk2 (-) 0 chain1 (schi2) dummy /uB/f3 sff Q clk2 (+) 1 chain1 (schi2) dummy /uB/f2 sff Q clk2 (+) 2 chain1 (schi2 dummy /uB/f1 sff Q clk2 (+) chain1 dummy /lckup2 latch Q clk2 (+) 0 chain2 (schc1) dummy /uWA/uA/f21 sff Q clk (+) 1 chain2 dummy /ud sff Q clk (+) 2 chain2 dummy /us sff Q clk (+) 0 chain3 (scho1) dummy /uWA/uA/f31 sff Q clk (+) chain4 dummy /lckup3 latch Q clk (-) 0 chain4 (schi1) dummy /uWA/uA/f3 sff Q clk (+) 1 chain4 (schi1) dummy /uWA/uA/bb/f2 sff Q clk (+) 2 chain4 (schi1) dummy /uWA/uA/f1 sff Q clk (+) chain4 dummy /lckup4 latch Q clk (+) ---------------------------------------------------------------------------------
Contents of the scan DEF file:

# # # DESC: Generated by DFTAdvisor at Wed Mar 17 10:50:58 2010
VERSION 5.7 ; DIVIDERCHAR "/" ; BUSBITCHARS "[]" ; DESIGN top ; UNITS DISTANCE MICRONS 1000 ; SCANCHAINS 1 ; - chain1_sub0 + START lckup2 Q + FLOATING uB/f1 ( IN SI ) ( OUT Q ) uB/f2 ( IN SI ) ( OUT Q ) uB/f3 ( IN SI ) ( OUT Q ) + STOP lckup1 D # Partition for core chain in clock clk2 (pos-edge) domain + PARTITION partition_1 MAXBITS 3 ; - chain2_sub0 + START us Q + FLOATING ud ( IN SI ) ( OUT Q ) + STOP uWA/uA/f21 SI # Partition for core chain in clock clk (pos-edge) domain + PARTITION partition_2 MAXBITS 1 ;
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# The following chain segment with only 1 or 2 scan cells has been commented out for # compatibility with the layout tools. #- chain3_sub0 # + START uWA/uA/f31 SI # + STOP uWA/uA/f31 Q ; - chain4_sub0 + START lckup4 Q + FLOATING uWA/mux ( IN A1 ) ( OUT Y ) ( BITS 0 ) uWA/uA/f1 ( IN SI ) ( OUT Q ) uWA/uA/bb/f2 ( IN SI ) ( OUT Q ) uWA/uA/f3 ( IN SI ) ( OUT Q ) + STOP lckup3 D # Partition for core chain in clock clk (pos-edge) domain + PARTITION partition_2 MAXBITS 3 ; END SCANCHAINS END DESIGN
Related Commands Add Clocks Add Subchain Clocks Delete Sub Chains Report Scan Cells Report Sub Chains Setup Wrapper Chains Write Scan Order Write Subchain Setup
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Command Dictionary Add Subchain Clocks
Add Subchain Clocks

Scope: Setup mode Prerequisites: Subchains must be added with the Add Sub Chains command. Usage ADD SUbchain CLocks subchain_name off_state {clock_port_name...} {-Set | -Reset | -First_cell_clock [-LEading_edge | -Trailing_edge] | -LAst_cell_clock [-LEading_edge | -Trailing_edge]} Description Specifies the clock pins for scan chains within modules, library models, instances, blackboxes, or empty modules of a hierarchical design. The specified clock pins are added relative to the module edge, not the top-level of the design. Once you specify the clock pins, you must use Set Test Logic to enable the insertion of the test logic. The Add Sub Chains command adds subchains to a specific instance or all instantiations of a specific module. When you use the Add Subchain Clocks command to specify subchain clock pins for multiple instantiations of a module, the timing information is automatically adjusted for each instance based on the: Off state of the top-level clock Inversions in the clock path to the instance Off state at the edge of the module Timing (rising/falling) at the edge of the module Note In order to specify clock pins with the Add Subchain Clocks command, the clock path must be traceable from the module to the top-level. Scannability analysis DRCs: S1, S2, and S3 validate the defined subchains when you exit Setup mode. Arguments subchain_name A required string that specifies the name of a subchain previously defined with the Add Sub Chains command. off_state A required string that specifies the off state for sequential instances. Sequential instances maintain their state when the clock is at the specified value; either 1 or 0.
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Command Dictionary Add Subchain Clocks
clock_port_name A required, repeatable string that specifies the clock pins on the subchain that must be controlled during scan chain shifting.
-Set A required switch that specifies the clock pins listed by the clock_port_name argument are set signals for cells in the subchain and should be held in the off state during scan chain shifting.
-Reset A required switch that specifies the clock pins listed by the clock_port_name argument are reset signals for cells in the subchain and should be held in the off state during scan chain shifting.
-First_cell_clock A required switch that specifies the clock pin listed by the clock_port_name argument drives the first cell in the subchain.
-LAst_cell_clock A required switch that specifies the clock pin listed by the clock_port_name argument drives the last cell in the subchain.
-LEading_edge An optional switch that specifies the clock pin listed by the clock_port_name argument updates cells on the leading edge of the off-state to on-state transition. This value is used during scan chain stitching and is only valid for defining the first and/or last cell clocks.
-Trailing_edge An optional switch that specifies the clock pin listed by the clock_port_name argument updates cells on the trailing edge of the off-state to on-state transition. This value is used during scan chain stitching and is only valid for defining the first and/or last cell clocks.
Example 1 The following example defines a subchain on a library module.

add sub chains MULTIBITSFF3 chain1 SI SO 4 mux_scan S library_model add subchain clocks chain1 0 RESET -reset add subchain clocks chain1 0 SET -set add subchain clocks chain1 0 CK -first_cell_clock -leading_edge add subchain clocks chain1 0 CK -last_cell_clock -leading_edge report subchain clocks chain1 // // // // // // clock name type off_state ---------- -----------RESET reset 0 SET set 0 CK first cell clock 0 CK last cell clock 0 edge -----
leading edge leading edge
add subchain clocks chain1 1 SET -set
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Command Dictionary Add Subchain Clocks // Error: Duplicate clock definition for SET delete subchain clocks chain1 CK report subchain clocks chain1 // // // // clock name type off_state edge ---------- ----- --------- -----RESET reset 0 SET set 0
add subchain clocks chain1 0 CK -first_cell_clock -trailing_edge report subchain clocks chain1 // // // // // clock name ---------RESET SET CK type off_state edge ------------- -----reset 0 set 0 first cell clock 0 trailing edge
Example 2 The following example reports subchains defined within a blackbox. The subchain is treated as a single sequential instance, but it is listed once for each clock line that needs fixing.
DFT> report dft check SCANNABLE SUBCHAIN Testlogic Set: T /macro/SET1 SCANNABLE SUBCHAIN Testlogic Set: T /macro/SET2 SCANNABLE SUBCHAIN Testlogic Set: T /macro/SET3 SCANNABLE SUBCHAIN Testlogic Reset: T /macro/RESET1 /macro MULTIBITSFFX (1) /macro MULTIBITSFFX (1) /macro MULTIBITSFFX (1) /macro MULTIBITSFFX (1)
All the test logic issues for a specified subchain instance map to a single DRC rule violation. The Analyze Drc Violation command displays the entire macro (with an X on each clock line that requires test logic) and arbitrarily displays the driving gate for only one of the pins that requires fixing. Related Commands Add Sub Chains Delete Subchain Clocks Report Dft Check Report Sub Chains Report Subchain Clocks Write Subchain Setup
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Command Dictionary Add Subchain Group
Add Subchain Group

Scope: Setup mode Usage ADD Subchain Group object_name subchain_name [-FLexible | -FIxed] Description Adds one subchain group to the system. The Add Subchain Group command specifies a group of subchains in a design so that DFTAdvisor can stitch these subchains together. If you omit a subchain group, the Insert Test Logic command chooses which subchains DFTAdvisor stitches together. You must have added the subchains (using Add Sub Chains) before you specify them as subchains in the argument list. When adding the subchain groups, you choose one option from following: -Flexible Option (default) DFTAdvisor permits unassigned single flip-flops and subchains in the scan chain for better balancing of the top-level scan chains. Using this option also permits breaking up the subchain group into multiple scan chains when necessary. DFTAdvisor partitions the subchains of flexible subchain groups along with the scannable flip-flops of the design according to your Insert Test Logic commands Clock/Edge merge and -Number/Max_length options, along with any clock groups you identified with Add Clock Groups. -Fixed Option In contrast, the -Fixed option disallows either other flip-flops and subchains in the subchain group, or the breaking up the subchain group. When using this option, DFTAdvisor adds a new scan chain to the design and includes the subchains of a fixed subchain group. Consequently, your Insert Test Logic commands -Clock/Edge merge and -Number/Max_length options have no effect on the subchains of fixed subchain groups.
Table 2-3 summarizes the types of subchains that can exist in a design. Table 2-3. Subchain Types Subchain Group No subchain group Multiple Chain Support Yes Stitching Partitioning
Can be stitched with: single cells subchains that are not assigned to any subchain groups subchains that are assigned to flexible subchain groups
Insert Test Logic Clock/Edge merge Number/Max_length Add Clock Groups
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Command Dictionary Add Subchain Group
Table 2-3. Subchain Types Subchain Group Flexible Multiple Chain Support Yes Stitching Partitioning
Can be stitched with: single cells subchains that are not assigned to any subchain groups Can be stitched with: no other cells or subchains
Insert Test Logic Clock/Edge merge Number/Max_length Add Clock Groups
Fixed
No
A new scan chain is added per Add Subchain Group command
Arguments object_name A required string specifying the subchain group name. subchain_name A required repeatable string identifying the subchain name for inclusion into the subchain group. Before identifying the subchain, you must add it with Add Sub Chains. You can also report subchain information using Report Sub Chains. If you added a subchain to a subchain group on a module-based basis, and the module is instantiated multiple times, DFTAdvisor includes the subchains on all instances of the module in the subchain group when this subchain is specified in the list of subchains of the Add Subchain Group command. If the subchains on different instances of the module are to be put into different subchain groups, these subchains need to be added instance-based instead of module-based in order to be assigned a unique subchain name. -FLexible | -Fixed An optional switch that specifies the type of the subchain group. The default type, -Flexible, allows in its chain other flip-flops and subchains that are not a member of a subchain group. Also, the subchains of flexible subchain groups are partitioned along with the other flipflops in the design according to the options specified with the Insert Test Logic command. The subchains of a fixed type subchain group are placed in a single chain and are not partitioned according to Insert Test Logic command options. Also, no other flip-flops or subchains are allowed in the scan chain of this group. Examples The following example defines a pre-existing scan subchain:
add sub chain subblockA subchain1 /scan_in1 /scan_out1 250 \ mux_scan /scan_en -module add sub chain subblockC subchain2 /scan_in1 /scan_out1 120 \ mux_scan /scan_en -instance ... report sub chains
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Command Dictionary Add Subchain Group mux_scan: subblockA subchain1 scan_in1 scan_out1 scan_en mux_scan: subblockC subchain2 scan_in1 scan_out1 scan_en add subchain group subchaingroup1 subchain1 subchain2 -fixed
Related Commands Add Clock Groups Add Sub Chains Add Subchain Group Delete Sub Chains Delete Subchain Groups Insert Test Logic Report Subchain Groups Report Sub Chains
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Command Dictionary Add Test Points
Add Test Points

Scope: Setup and DFT mode Prerequisites: You must define the model_name with either the Add Cell Models command or the cell_type attribute within the DFT library. Usage ADD TEst Points tp_pin_pathname {{Control model_name [input_pin_pathname] [mux_sel_input_pin] [-New_scan_cell scancell_model_name]} | {Observe [output_pin_pathname] [-New_scan_cell scancell_model_name2]} | {Lockup lockup_latch_model_name clkpin [-INVert | -NOInvert]}} Description Specifies explicitly where DFTAdvisor places a user-defined test point to improve the designs testability either through better controllability or observability. Using the Add Test Points command, you can manually specify the location of a test point and whether that point is for control or observation. Additionally, you can specify whether to insert a scan cell for control or observe purposes at the test point location; this is in addition to the control logic. You can also control timing problems on merged scan chains by manually specify the location of lockup cells. Note The Add Test Points command operates independently of the Set Test Logic command.
The Add Test Points command also works independently of the automatically system-defined test pointsrefer to Understanding Test Points in the Scan and ATPG Process Guide. Arguments tp_pin_pathname A required string that specifies the location where you want DFTAdvisor to insert the control or observe test point. Control model_name [input_pin_pathname] [mux_sel_input_pin] [-New_scan_cell scancell_model_name] The Control test point argument specifies the test point is for control purposes. model_name A required string specifying the DFT library model you want DFTAdvisor to place an instance of at the location specified by tp_pin_pathname. Before you can use the Add Test Points command, you must use either the Add Cell Models command or the cell_type DFT library attribute to define the DFT library model that corresponds to the model type you want DFTAdvisor to insert. The valid cell model types include AND, OR, INV, BUF, NAND, NOR, XOR, and MUX. input_pin_pathname An optional string that specifies the pathname of the pin to which you want to connect the other input of the gate specified by the model_name
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argument. The pathname can be either to an existing primary input pin, an internal driver pin, or a currently nonexistent pin. If the pin does not currently exist in the design and -New_scan_cell option is not specified, DFTAdvisor transcripts a message when you issue this command, and then creates a new primary input pin with the specified name during the insertion of the scan chain(s). If -New_scan_cell option is specified, this string is used to specify an existing clock pin to be connected to the clock input of the new control point scan cell. If -New_scan_cell option is specified and this string is not provided, DFTAdvisor determines which clock to use for the new scan cell automatically. mux_sel_input_pin An optional string that is needed only when the model_name argument type is a MUX. This argument specifies where DFTAdvisor is to connect the selector input of the multiplexer. -New_scan_cell scancell_model_name An optional switch and string pair that specifies whether DFTAdvisor places a scan cell at the control test point and the DFT library SCANCELL type model that you want inserted. If you use this option, you must first define the scancell_model_name with the Add Cell Models command or the cell_type DFT library attribute. Figure 2-1 shows how DFTAdvisor automatically connects the new scan cell to the same clock as the scan cell it feeds in the chain. Figure 2-1. Control Example
Note that these are new scan cells, not scan replacements for existing sequential elements. They are connected into chain(s) during insertion of test logic along with the existing sequential elements in the design. If the design contains no scan, the test point scan cells are connected into one or more scan chains, depending on their clock pins.
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Observe [output_pin_pathname] [-New_scan_cell scancell_model_name2] The Observe test point argument specifies for DFTAdvisor to place an observe point at the location specified by the value of the tp_pin_pathname argument. output_pin_pathname An optional string that specifies the pathname of the primary output pin that you want DFTAdvisor to connect to the observe point. If the primary output pin does not currently exist in the design and -New_scan_cell option is not specified, DFTAdvisor creates a new primary output pin with the specified name during the insertion of the scan chain(s). If -New_scan_cell option is specified, this string is used to specify an existing clock pin to be connected to the clock input of the new observe point scan cell. If -New_scan_cell option is specified and this string is not provided, DFTAdvisor determines which clock to use for the new scan cell automatically. -New_scan_cell scancell_model_name2 An optional switch and string pair that specifies whether DFTAdvisor places a scan cell at the observe test point and the DFT library SCANCELL type model that you want inserted. If you use this option, you must first define the scancell_model_name2 with the Add Cell Models command or the cell_type DFT library attribute. Figure 2-2 illustrates how DFTAdvisor automatically connects the new scan cell to the same clock as the scan cell it feeds in the chain. Figure 2-2. Observe Example
Note that these are new scan cells, not scan replacements for existing sequential elements. They are connected into chain(s) during insertion of test logic along with the existing sequential elements in the design. If the design contains no scan, the test point scan cells are connected into one or more scan chains, depending on their clock pins.
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Lockup lockup_latch_model_name clkpin [-INVert | -NOInvert] If you enable Set Lockup Cell on, then DFTAdvisor normally inserts lockup cells where necessary to control timing problems between cells in merged scan chains. This Lockup argument lets you specify for DFTAdvisor to add a lockup cell at any specified location. If the location (tp_pin_pathname) is a primary output or an instance input pin, the latch is inserted in front of the pin. If the location is a primary input or an instance output pin, the latch is inserted after the pin, and will drive all fanouts that were originally driven by the pin. lockup_latch_model_name A string that specifies the library latch model name. If you use this option, you must first define the model with the Add Cell Models command. clkpin A string that specifies the pathname of the clock pin to which the clock pin of the latch is connected. -INVert | -NOInvert A switch that specifies whether to insert an inverter between the specified clkpin and the clock input to the latch. The default is -NOInvert.
Examples The following example first defines a DFT library model (and2a) of type AND, and then defines a control test point, which DFTAdvisor then generates as part of the Insert Test Logic command:
add cell models and2a -type and add test point /I_6_16/cp control and2a control1 set system mode dft run insert test logic
Related Commands Add Cell Models Delete Test Points Insert Test Logic Report Test Points Set Lockup Cell Set Test Logic
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Command Dictionary Add Tied Signals
Add Tied Signals

Scope: Setup mode Usage ADD TIed Signals {0 | 1 | X | Z} floating_object_name [-Pin] Description Specifies for DFTAdvisor to hold the named floating objects (nets or pins) at the given state value. DFTAdvisor creates a tied simulation gate (depending on the tied value) for each tied signal during the design flattening process. If you do not assign a specific value to a floating object, DFTAdvisor ties the object to the default value for all tied objects. Tip: Use the Setup Tied Signals command for changing the value of a tied object from the default value of unknown (X). When you add tied signals or pins, the tool places them into the user class. This includes instance-based blackbox tied signals. When the netlist ties signals or pins to a value, the tool places them into the system class. Note The tool does not tie a signal connected to I/O pins. This causes a problem if you are considering VDD as an I/O pin. Arguments 0 A literal that specifies to tie the floating nets or pins to logic 0 (low to ground). 1 A literal that specifies to tie the floating nets or pins to logic 1 (high to voltage source). X A literal that specifies to tie the floating nets or pins to unknown. Z A literal that specifies to tie the floating nets or pins to high-impedance floating_object_name A required, repeatable string that specifies the floating nets or pins to which you want to assign a specific value. The tool assigns the tied value to all floating nets or pins in all modules that have the specified names.
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Command Dictionary Add Tied Signals
If you do not specify the -Pin option, the tool assumes the name is a net name. If you do specify the -Pin option, the tool assumes the name is a pin name. If you specify a net pathname, you cannot use the -Pin option. -Pin An optional switch specifying that the floating_object_name argument that you provide is a floating pin name. Examples The following example ties all floating signals in the circuit that have the net names vcc and vdd, to logic 1 (tied to high):
add tied signals 1 vcc vdd
Related Commands Add Black Box Delete Tied Signals Report Tied Signals Setup Tied Signals
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Command Dictionary Add Write Controls
Add Write Controls

Scope: Setup mode Usage ADD WRite Controls {0 | 1} primary_input_pin Description Specifies the off-state value of the write control lines for RAMs. The Add Write Controls command defines the circuit write control lines and assigns their offstate values. The off-state value of the pins you specify must be sufficient to keep the RAM contents stable. You may not use clocks, constrained pins, or equivalent pins as write control lines. Arguments 0 A literal specifying 0 is the off-state value for the RAM primary_input_pin. 1 A literal specifying 1 is the off-state value for the RAM primary_input_pin. primary_input_pin A required, repeatable string specifying the primary input pins that are write control lines for the RAM and to which you want to assign an off-state value. Examples The following example assigns an off-state to two write control lines, w1 and w2:
add write controls 0 w1 w2 set system mode dft run
Related Commands Analyze Control Signals Delete Write Controls Report Write Controls
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Command Dictionary Alias
Alias
Scope: All modes Usage ALIas [synonym {!unix_command; | tool_command; | alias_synonym;}] Description Specifies the shorthand name for a DFTAdvisor command, UNIX command, or existing command alias, or any combination of the three. Issuing the Alias command with no parameters will list the current aliased commands, using the same format that the Korn-shell alias commands use:
<alias_cmd1>=<alias_definition1> <alias_cmd2>=<alias_definition2>
...
<alias_cmdN>=<alias_definitionN>
If you specify a shorthand name (synonym) and one of the command types, that shorthand name can substitute for the command and any arguments you specify. You utilize the full power of the Alias command when you take advantage of the repeatable nature of the second string, intermixing any number of command types, and separating them with semicolons. In addition, the command strings can be parameterized by using the formal parameters, $1 thorough $9, inserted in the command string in any order. When you issue the synonym as a command, you must supply the actual arguments, which are substituted into the command prior to its execution. You can also include an optional file, .dftadvisor_startup, that contains commands to be executed prior to any other batch or interactive commands. The primary purpose of this file is to execute Alias commands that tailor the tools command language to your needs. Upon invocation, the tool searches for the startup file in the following locations and in order of precedence: 1. The local invocation directory 2. Your home directory The first startup file encountered will be the only one executed if you have startup files in both locations. Using the Alias command with a single argument will, if the argument is an aliased command name, report the name and definition of that command, using Korn-shell syntax:
<alias_cmd>=<alias_definition>
Issuing the command Help <aliased_cmd> will report the name of the command and the definition which you specified via the Alias command when <aliased_cmd> was created. Using
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Command Dictionary Alias
the help command with an aliased command name will generate an Alias report of the following format:
// alias: <alias_cmd>=<alias_definition>
Arguments synonym {!unix_command; | tool_command; | alias_synonym;} An optional string with a repeatable string that specifies a shorthand name, synonym, for the specified UNIX or tool command or for a previously-defined alias synonym (which has the effect of a command). You must separate repeated commands with semicolons. !unix_command An optional, repeatable string that consists of any well-formed UNIX command, with its arguments, or script. You must precede this string with an exclamation point to differentiate it from a tool-specific command. tool_command An optional, repeatable string that consists of any well-formed DFTAdvisor command and its arguments. alias_synonym An optional, repeatable string that consists of any synonym previously defined with the Alias command. Examples The following example defines an aliased command, watch, which uses a formal parameter. The next line invokes it and supplies the actual parameter:
alias watch !ps -e | egrep $1; watch netscape
The result of issuing this alias is to list all the process IDs associated with Netscape processes on the host machine. The next example defines the new command, findlockup, which searches the current directory for Verilog files and invokes egrep on each one in turn, looking for and displaying any lckup names:
alias findlockup !find . -name \*.v -print -exec egrep lckup {} \;
You could then use that new command within another Alias command that writes out the current design:
alias findit write netlist -verilog temp.v -replace; findlockup
This final example defines two aliased commands, invokes them, and requests help on them:
alias wibble !echo arg1 arg2 $1 $2 $3 $4 alias wobble report black box -undefined wibble one_1 two_2 three_3 four_4 arg1 arg2 one_1 two_2 three_3 four_4 wobble // Undefined Modules: // foo alias wobble
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Command Dictionary Alias // alias: wobble=report black box -undefined alias // List of aliased commands: // wobble=report black box -undefined // wibble=!echo arg1 arg2 $1 $2 $3 $4 help wobble // alias: wobble=report black box -undefined help wibble // alias: wibble=!echo arg1 arg2 $1 $2 $3 $4
Related Commands Dofile Help History System
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Command Dictionary Analyze Control Signals
Analyze Control Signals

Scope: All modes Usage ANAlyze COntrol Signals [-Report_only | -Auto_fix] [-Verbose] Description Identifies and optionally defines the majority of primary inputs that are control signals. The Analyze Control Signals command analyzes each control signal (clocks, set, reset, writecontrol, and read-control) of every sequential element (DFF, latch, RAM, ROM, and so on) and optionally defines its primary input as a control signal. The purpose of analyzing the control signals is to identify the primary inputs that need to be defined as a clock, read-control, or writecontrol for DFTAdvisor. This analysis also considers pin constraints, but only traces through simple, combinational gates. Because it is not possible to completely identify all control signals, you should only use the results of this command as a starting point in creating a dofile that defines the clock control signals, read and write controls in a design. You should use this dofile when DFTAdvisor is being used for production scan and test logic insertion. Situations where DFTAdvisor may not be able to identify particular control signals include the following: When DFTAdvisor is unable to trace or simulate through complex logic, the tool cannot identify a top-level pin as a clock. These cases include clocks driven by PLLs or clock gaters that require simulating a test setup procedure to obtain a sensitizable path to a top-level pin. DFTAdvisor cannot accurately predict the off-state of a clock by observing the flip-flops it is driving and, therefore, requires the user to verify that the off-state of the clock/set/reset lines is correct.
Because of these types of issues, this command does not identify all clocks, their offstates, or controls signals. In this case, you should explicitly add the unidentified clocks using the Add Clocks command. If the -Verbose option is specified, the tool issues messages indicating why certain control signals are not reported as controllable. At the end of the analysis, statistical information displays, listing the number of primary inputs identified as control signals, their types, and additional information. If the -Auto_fix option is specified, all identified primary inputs of control signals are automatically defined. For example, when a clock is identified, an implicit Add Clocks command is performed to define the primary input. The default for control signals is report only.
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Command Dictionary Analyze Control Signals
Note This command performs the flattening process automatically, if executed prior to performing flattening. Caution This command does not support gated clocks. If a netlist has a gated clock going to two flip-flops, the tool does not recognize the gated clock when using the command the -Auto_fix option. Arguments -Report_only An optional literal that specifies to only identify control signals (does not define the primary inputs as control signals). This is the invocation default. -Auto_fix An optional literal that specifies to define the primary inputs of all identified control signals as control signals. For example, when a clock is identified, an implicit Add Clocks command is performed to define that primary input. -Verbose An optional literal that specifies to display information on control signals (whether they are identified or not, and why) while the analysis is performed. Examples The following example analyzes the control signals, then only provides a verbose report on the control signals in the design. After examining the transcript, you can then perform another analysis of the control signals to add them.
analyze control signals -verbose
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Command Dictionary Analyze Control Signals // command: analyze control signals -reports_only -verbose // -----------------------------------------------------------------------// Begin control signals identification analysis. // -----------------------------------------------------------------------// Warning: Clock line of /cc01/tim_cc1/add1/post_latch_29/WRITEB_reg/r/ (7352) is uncontrolled at /IT12 (4). . . . // Identified 2 clock control primary inputs. // /IT23 (5) with off-state = 0. // /IT12 (4) with off-state = 0. // Identified 0 set control primary inputs. // Identified 1 reset control primary inputs. // /IRST (1) with off-state = 0. // Identified 0 read control primary inputs. // Identified 0 write control primary inputs. ----------------------------------------------------------------------// Total number of internal lines is 105 (35 clocks, 35 sets , 35 resets, 0 reads, 0 writes). // Total number of controlled internal lines is 25 (17 clocks, 0 sets , 8 resets, 0 reads, 0 writes). // Total number of uncontrolled internal lines is 80 (18 clocks, 35 sets, 27 resets, 0 reads, 0 writes). // Total number of added primary input controls 0 (0 clocks, 0 sets , 0 resets, 0 reads, 0 writes). ----------------------------------------------------------------------analyze control signals -auto_fix -verbose
Related Commands Add Clocks Add Read Controls Add Write Controls Report Clocks Report Read Controls Report Write Controls
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Command Dictionary Analyze Input Control
Analyze Input Control

Scope: Dft mode Usage ANAlyze INput Control Description Analyzes and reports the effects of constraining primary input pins to an unknown value. When creating wrapper chains, you must constrain uncontrollable primary inputs at the chip-level with the Add Pin Constraints command. DFTAdvisor then uses the constrained inputs when identifying non-scan cells to place in the input wrapper chains. Sometimes there is combinational logic between the constrained pin and the sequential element that gets converted to an input wrapper cell, constraining the primary input pin can impact the fault detection of this combinational logic. The Analyze Input Control command determines the controllability factor of an input pin by removing the X constraint, and calculating the controllability improvement on the affected combinational gates. If a constrained input pin has a significant impact on the fault coverage within that combinational logic, you should consider making that pin a test point or adding a new scan cell either inside or outside of that wrapper chain to improve fault detection. DFTAdvisor reports the results of the analysis with the primary input having the largest controllability gain listed first. For more information on wrapper chains, refer to Understanding Wrapper Chains in the Scan and ATPG Process Guide. Examples The following example adds three pin constraints and then reports the constrained pins in descending order based on controllability gain:
add pin constraints data1 cx add pin constraints addr4 cx add pin constraints addr7 cx analyze input control addr4 addr7 data1
Related Commands Add Pin Constraints Analyze Output Observe Report Testability Analysis Setup Scan Identification
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Command Dictionary Analyze Output Observe
Analyze Output Observe

Scope: Dft mode Usage ANAlyze OUtput Observe Description Analyzes and reports the observabilty effects of masked primary output pins. When creating wrapper chains, you must mask unobservable primary outputs at the chip-level with the Add Output Masks command. DFTAdvisor then uses the masked outputs when identifying the non-scan cells to place in the output wrapper chains. When there is combinational logic between the masked pin and the sequential element that gets converted to an output wrapper cell, masking the primary output pin can impact the fault detection of this combinational logic. The Analyze Output Observe command determines the observability factor of an output pin by removing the mask and calculating the observability improvement on the affected combinational gates. If a masked output pin has a significant impact on the fault coverage within that combinational logic, you should consider making that pin a test point or adding a new scan cell either inside or outside of that wrapper chain to improve fault detection. DFTAdvisor reports the results of the analysis with the primary output put having the largest observability gain listed first. For more information on wrapper chains, refer to Understanding Wrapper Chains in the Scan and ATPG Process Guide. Examples The following example masks three primary outputs, analyzes the observability, and reports the masked output pins in descending order based on observability gain:
add output masks qout1 -hold 1 add output masks addr_res<1> -hold 0 add output masks addr_res<4> -hold 1 analyze output observe addr_res<1> qout1 addr_res<4>
Related Commands Add Output Masks Analyze Input Control Report Testability Analysis Setup Scan Identification
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Command Dictionary Analyze Testability
Analyze Testability
Scope: Dft mode Usage ANAlyze TEstability [-Scoap_only] Description Reports general scannability and testability information, along with calculating the controllability and observability values for gates. The Analyze Testability command reports general scannability and testability information which can help you determine how much partial scan the design may need to achieve high test coverage. The scannability and testability information reported includes: Statistics about the total number of sequential elements, number of scannable sequential elements, number of non-scannable sequential elements, and so on Number of scannable sequential elements that need to be scanned to break all global sequential loops Number of scannable sequential elements with self loops Number of scannable sequential elements required to scan RAM boundaries (if the design contains RAMs) Number of scannable sequential elements required to limit sequential depth and consecutive self loops Note If the design contains sequential loops, the reported sequential depth is estimated.
Number of uncontrollable and unobservable scannable sequential elements
The information reported is mainly related to the structure of the circuit. If you are using structure-based scan selection, you can use the report to correlate structural criteria with the amount of scan required. For example, you will see a report on how much scan is required to break all sequential loops or to limit sequential depth to a given number. This can help you in determining what parameters to provide to structure-based scan selection. If you want to use partial scan, it is recommended that you use the more automated, automatic scan-selection method. The information provided by this report can also give you a measure of how testable the circuit is at any given time, which can help you in determining whether more scan needs to be selected. For example, if all global loops are broken and the sequential depth is small, this indicates that the circuit is likely to achieve high test coverage and that the scan selected thus far may be sufficient.
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Command Dictionary Analyze Testability
In addition, this command uses SCOAP testability measures to calculate the controllability and observability of individual gates which can be reported using the Report Testability Analysis command. If you use the -Scoap_only switch, this command only calculates the controllability and observability values. Arguments -Scoap_only An optional switch that specifies to only compute SCOAP controllability and observability numbers for use with the Report Testability Analysis command. If this switch is not specified, these numbers are still calculated, but in addition, scannability and testability information is calculated and reported. Examples The following example shows the default output from the Analyze Testability command. The controllability and observability numbers are also calculated, but must be reported using the Report Testability Analysis command (as shown in the next example).
DFT> analyze testability // // // // // // // // // // // // // // // // // // // // // // // // Number of sequential instances: Total Scannable Identified Targets Uncontrollable Unobservable Maximum sequential depth Scannable instances with self loops Scan to break global loops Scan RAM boundaries Scan to limit consecutive self loops: To 32 = 28 ( 3.73%) To 16 = 52 ( 6.92%) To 8 = 56 ( 7.46%) To 4 = 78 ( 10.39%) To 2 = 104 ( 13.85%) Scan to limit sequential depth: To 64 = 80 ( 10.65%) To 32 = 122 ( 16.25%) To 16 = 150 ( 19.97%) To 8 = 150 ( 19.97%) To 4 = 165 ( 21.97%) To 2 = 248 ( 33.02%) = 751 = 319 ( 42.48%) = 0 ( 0.00%) = = = = = = = 319 319 319 115 165 98 74 ( 42.48%) ( 42.48%) ( 42.48%) ( 21.97%) ( 13.05%) ( 9.85%)
The following example shows the flow of displaying only the controllability values. The report displays the controllability value for the low logic state (where NC means non-controllable), the controllability value for the high logic state, the primitive gate type, the gate identification number, and the pathname to the gate.
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Command Dictionary Analyze Testability set system mode dft . . analyze testability -scoap_only report testability analysis -control -percent 5 0 NC 1 5672 NC 0 7001 1 TIE0 TIE1 INV BUF 32 53 95 382 /addr/U15 /addr/U35 /cntr/U45 /blk1/U85
Related Commands Add Test Points Report Testability Analysis Setup Scan Identification
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Command Dictionary Delete Black Box
Delete Black Box

Scope: Setup mode Usage DELete BLack Box -Instance [ins_pathname] | -Module [module_name] | -All Description Undoes the effect of the Add Black Box command. For a module that was originally modeled, removing the effect of the Add Black Box command reinstates the original model. Specified tied values are no longer set on the output pins. For a module that was empty or undefined in the input netlist, the output pins revert to the default tied value of X. Note The tool releases the flattened model if one exists at the time you issue this command.
Arguments -Instance [ins_pathname] A switch that specifies for the tool to undo the effect of the Add Black Box command on all instance-based blackboxes. This is the default if no ins_pathname is given. You can optionally specify an instance pathname to undo a single instance-based blackbox. -Module [module_name] A switch that specifies for the tool to undo the effect of the Add Black Box command on all module-based blackboxes. This is the default if no module_name is given. You can optionally specify a module name to undo a single module-based blackbox. -All A switch that specifies for the tool to undo the effect of the Add Black Box command on all blackboxes. Example The following example adds the black box for module core then undoes all blackboxes that were defined.
add black box -module core 1 delete black box -all
Related Commands Add Black Box Delete Tied Signals Report Black Box
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Command Dictionary Delete Buffer Insertion
Delete Buffer Insertion

Scope: All modes Usage DELete BUffer Insertion test_pin | -ALL Description Specifies the type of scan test pins on which you want to remove the fanout limit. The default fanout limit on all types of scan test pins is infinity. You can limit the fanout with the Add Buffer Insertion command, and you can remove that limit with the Delete Buffer Insertion command. If you remove the limit, DFTAdvisor resets the limit to the default of infinity. Arguments test_pin A repeatable literal that specifies the type of the primary input scan pin from which you want DFTAdvisor to remove the fanout limit. The following shows the default pin names for each type of scan pin, but you can change the default names using the Setup Scan Insertion command. SEN (scan enable; default name scan_en) A literal that specifies the primary input pin that enables the scan chain. SCLK (scan clock; default name scan_clk) A literal that specifies the primary input pin that clocks the scan data through the scan chain; the clocked scan type uses this pin. TEN (test logic enable; default name test_en) A literal that specifies the primary input that enables the operation of the test logic circuitry. TCLK (test logic clock; default name test_clk) A literal that specifies the primary input pin that clocks the values DFTAdvisor requires for proper functionality of the test logic. SMCLK (master scan clock; default name scan_mclk) A literal that specifies the primary input that clocks the scan data into the master scan elements of the scan chain when using the LSSD scan type. SSCLK (slave scan clock; default name scan_sclk) A literal that specifies the primary input that clocks the scan data into the slave scan elements of the scan chain when using the LSSD scan type. -ALL A switch that removes the fanout limits from all the primary input scan pins and returns each to its default setting of infinity.
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Command Dictionary Delete Buffer Insertion
Examples The following example changes the default settings for test logic and then removes those settings. The following two reports show the results of each command.
add buffer insertion 5 ten tclk -model buf1a report buffer insertion scan_enable scan_clock test_enable test_clock scan_master_clock scan_slave_clock hold_enable <infinity> <infinity> 5 buf1a 5 buf1a <infinity> <infinity> <infinity>
delele buffer insertion -all report buffer insertion scan_enable scan_clock test_enable test_clock scan_master_clock scan_slave_clock hold_enable <infinity> <infinity> <infinity> <infinity> <infinity> <infinity> <infinity>
Related Commands Add Buffer Insertion Report Buffer Insertion
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Command Dictionary Delete Cell Models
Delete Cell Models

Scope: All modes Usage DELete CEll Models dftlib_model | {-Type {INV | And | Buf | OR | NAnd | NOr | Xor | INBuf | OUtbuf | Mux | Scancell | DFf | DLat}} | -All Description Specifies the name of the DFT library cell that DFTAdvisor is to remove from the active list of cells that the user can access when adding test points or that DFTAdvisor can access when inserting test logic. You originally added the cells to the active list with either the Add Cell Models command or with the cell_type library attribute. If you remove a cell model from the active list, you only remove the cell from that list and do not change the DFT library. If you accidently delete a DFT library cell from the active list with the Delete Cell Models command, you can add the specified cell back into the active list with the Add Cell Models command. Arguments dftlib_model A repeatable string that specifies the names of the particular DFT library models that you want DFTAdvisor to remove from the active list. -Type INV | And | Buf | OR | NAnd | NOr | Xor | INBuf | OUtbuf | Mux | Scancell | DFf | DLat A switch and argument pair that specifies the cell model type of all DFT library models that you want DFTAdvisor to remove from the active list. The valid cell model types are as follows: INV A literal that specifies a one-input inverter gate. And A literal that specifies a two-input AND gate. Buf A literal that specifies a one-input buffer gate. OR A literal that specifies a two-input OR gate. NAnd A literal that specifies a two-input NAND gate. NOr A literal that specifies a two-input NOR gate. Xor A literal that specifies a exclusive OR gate. INBuf A literal that specifies a primary input buffer gate. OUtbuf A literal that specifies a primary output buffer gate. Mux A literal that specifies a 2-1 multiplexer. Scancell A literal that specifies a mux-scan D flip-flop.
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Command Dictionary Delete Cell Models
DFf A literal that specifies a D flip-flop. DLat A literal that specifies a D latch. -All A switch that removes all cell models from the active list, including those tagged in the DFT library with the cell_type attribute. This switch does not change the contents of the DFT library, only the active list within DFTAdvisor. Examples The following example removes a DFT library model from the active list:
add clocks 0 clk set test logic -set on -reset on set system mode dft add cell models and2 -type and add cell models or2 -type or add cell models mux21h -type mux s a b add cell models nor2 -type nor delete cell models or2 insert test logic
Related Commands Add Cell Models Report Cell Models Set Test Logic
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Command Dictionary Delete Clock Groups
Delete Clock Groups

Scope: Dft mode Usage DELete CLock Groups group_name | -All Description Specifies the name of the group that you want to remove from the clock groups list. If you are going to merge multiple shift clocks together to form one scan chain, you can use the Add Clock Groups command to place the shift clocks in the same clock group. If you make a mistake when defining the clocks within a clock group, you can use the Delete Clock Groups command. As you delete clock groups, the specified clocks are returned to the default clock group, all_clocks. Arguments group_name A repeatable string that specifies the names of the clock groups that you want to remove. The value of the group_name argument is the same as that which you specified with the Add Clock Groups command. -All A switch that specifies to remove all the clock groups. Examples The following example defines the current clocks, splits those clocks incorrectly into two different groups, removes the clock group that was incorrectly defined, and then continues defining the clock groups:
add clock 1 clk1 clk2 add clock 0 pre1 clr1 pre2 clr2 set system mode dft . . add clock groups group1 clk1 pre2 clr1 delete clock groups group1 add clock groups group1 clk1 pre1 clr1 add clock groups group2 clk2 pre2 clr2
Related Commands Add Clock Groups Add Clocks Report Clock Groups Report Clocks
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Command Dictionary Delete Clocks
Delete Clocks
Scope: Setup mode Usage DELete CLocks primary_input_pin | -All Description Removes primary input pins from the clock list. The Delete Clocks command removes the specified primary input pins from the clock list. Deleted clocks are also removed from the default clock group, all_clocks. If you remove an equivalence pin from the clock list, DFTAdvisor automatically removes all of the equivalent pins from the clock list. Arguments primary_input_pin A repeatable string that specifies the list of primary input pins that you want to delete from the clock list. -All A switch that deletes all pins from the clock list. Examples The following example deletes an incorrect clock from the clock list:
add clocks 1 clock1 add clocks 1 clock2 delete clocks clock1
Related Commands Add Clocks Report Clocks
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Command Dictionary Delete Mapping Definition
Delete Mapping Definition

Scope: Setup and DFT modes Usage DELete MApping Definition -All | {object_name [-Instance | -Module] [-Nonscan_model nonscan_model_name] [-Scan_model scan_model_name] [-Output [scan_ouput_pin_name]]} Description Returns the non-scan to scan model mapping to the mapping defined by DFTAdvisor. The Delete Mapping Definition command deletes the mapping of non-scan models to scan models. Using this command, you can perform the following: Remove the scan model mapping for an individual instance. Remove all instances under a hierarchical instance. Remove all instances in all occurrences of a module in the design. Remove all occurrences of the model in the entire design. Remove the mapping the scan output pin of the scan models.
To return the scan mapping back to the library default, you can specify the non-scan model; DFTAdvisor removes the scan mapping and output mapping from the model. When specifying both the non-scan and scan model, DFTAdvisor removes the scan and output mapping for those instances matching the non-scan and scan model. When only removing the scan output pin mapping, you specify the scan model. If you also specify the output scan pin, then only scan candidates matching the scan model and output pin have their output pin mapping removed. Arguments -All A switch that specifies to remove all scan and output mapping in the entire design. object_name A string that specifies the name of the non-scan model you want to remove the mapping. You can also specify an instance, hierarchical instance, module, or scan model.
o
If this argument is the name of an instance or hierarchical instance, the -Instance switch is required and the model must be specified with the -Nonscan_model switch or -Scan_model switch. If this argument is the name of a module, then the -Module switch is required, and the model must be specified with the -Nonscan_model or -Scan_model switch.
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Command Dictionary Delete Mapping Definition o
If this argument is a scan model, then the -Output switch is required. Because you specified a scan model, you can only remove the scan output pin mapping.
o
If you specify -Instance and the instance is primitive, then only the named instance has its mapping changed. If you specify -Instance and the instance is hierarchical, then all instances under that instance matching the -Nonscan_model or (for output mapping) matching the -Scan_model have their mapping changed. If you specify -Module, then for all occurrences of that module, all instances within that module that match the -Nonscan_model or (for output mapping) matching the -Scan_model have their mapping changed.
-Nonscan_model nonscan_model_name An optional switch and string pair that specifies the name of the non-scan model that you want to remove the scan and pin mapping. This argument is required only if you specify -Instance or -Module switch; otherwise, you can specify the non-scan model in the object_name argument.
-Scan_model scan_model_name An optional switch and string pair that specifies the name of the scan model that is mapped to the specified non-scan model. This argument is required only if you want to constrain the removing of the scan mapping or are just removing the scan output pin mapping based on -Instance or -Module.
-Output [scan_ouput_pin_name] An optional switch and optional string pair that specifies to remove the scan output pin. Specifying just the -Output switch removes all changed scan output pins for the specified scan model, while specifying the switch with a pin name removes the mapping for only scan models that use that pin for the scan output.
Examples The following example removes the scan and output mapping for all occurrences of the fd1 nonscan model in the design:
delete mapping definition fd1
The following example removes the scan and output mapping for each occurrence of the fd1 non-scan model that is mapped to the fd1s scan model and has the scan output pin mapped to qn:
delete mapping definition fd1 -scan_model fd1s -output qn
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Command Dictionary Delete Mapping Definition
The following example removes the scan and output mapping for each occurrence of the fd1 non-scan model under the hierarchical instance /top/counter1:
delete mapping definition /top/counter1 -instance -nonscan_model fd1
The following example removes the scan and output mapping for each occurrence the fd1 nonscan model that is mapped to the fd1s2 scan model in the counter module and for all occurrences of that module in the design:
delete mapping definition counter -module -nonscan_model fd1 -scan_model fd1s2
The following example removes the scan output pin mapping and returns it to the library default for all occurrences of the fd1s scan model in the design:
delete mapping definition fd1s -output
The following example removes the scan output pin mapping and returns it to the library default for all occurrences of the fd1s scan model in the design with the scan output pin set to qn:
delete mapping definition fd1s -output qn
Related Commands Add Mapping Definition Report Mapping Definition
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Command Dictionary Delete Nofaults
Delete Nofaults
Scope: Setup mode Usage DELete NOfaults {-All | {modulename -Module} | {object_expression [-PIN | -Instance]}} [-Stuck_at {01 | 0 | 1}] Description Removes the no-fault settings from either the specified pin or instance pathnames. The Delete Nofaults command deletes the nofault settings which were previously specified with the Add Nofaults command. You can optionally specify nofault settings that have a specific stuck-at value. If you do not specify a stuck-at value when deleting a nofault setting, the command deletes both the stuck-at-0 and stuck-at-1 nofault settings. If the pathname is a pin, then DFTAdvisor removes the nofault on only that pin. If the pathname is an instance, then the tool removes all pin nofaults on the top-level of that instance, along with all the pin faults underneath that instance (if it is a hierarchical instance). If the pathname is a module, then the tool removes all pin nofaults on the top-level of the module, along with all the pin nofaults on all instances and pins underneath that module for every occurrence of that module in the design. You can use the Report Nofaults command to display all the current nofault settings. Arguments -All A switch that deletes all nofault settings. modulename A string that specifies the name of a module from which you want to delete nofault settings. You must include the -Module switch when you specify a module name. -Module A switch that specifies interpretation of the modulename argument as a module pathname. All instances of these modules are affected. You can use the asterisk (*) and question mark (?) wildcards for the modulename argument, and the tool deletes the nofault for all matching modules or library models. object_expression A string representing a list of pathnames of instances or pins from which you want to delete nofault settings. The string may include any number of embedded asterisk (*) or question mark (?) wildcard characters. The asterisk matches any sequence of characters (including none) in a name, and the question mark matches any single character. Pin pathnames must be ATPG library cell instance pins, also referred to as design level pins. If the object expression specifies a pin within an instance of an ATPG library model, the tool ignores it. By default, pin pathnames are matched first. If a pin pathname match is not
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Command Dictionary Delete Nofaults
found, the tool next tries to match instance pathnames. You can force the tool to match only pin pathnames or only instance pathnames by including the -Pin or -Instance switch after the object_expression. -Pin An optional switch that specifies to use the preceding object expression to match only pin pathnames; the tool will then delete nofault settings from all the pins matched. -Instance An optional switch that specifies to use the preceding object expression to match only instance pathnames; the tool will then delete nofault settings from all boundary and internal pins of the instances matched. -Stuck_at 01 | 0 | 1 An optional switch and literal pair that specifies the stuck-at values that you want to delete. The valid stuck-at literals are as follows: 01 A literal that specifies to delete both the stuck-at-0 and stuck-at-1 nofault settings. This is the default. 0 A literal that specifies to only delete the stuck-at-0 nofault settings. 1 A literal that specifies to only delete the stuck-at-1 nofault settings. Examples The following example will delete an extra added no fault instance.
add nofaults i_1006 i_1007 i_1008 -instance report nofaults USER USER USER USER USER USER : : : : : : 01 01 01 01 01 01 i_1006/IN i_1006/OUT i_1007/IN i_1007/OUT i_1008/IN i_1008/OUT
delete nofaults i_1007 -instance report nofaults USER USER USER USER : : : : 01 01 01 01 i_1006/IN i_1006/OUT i_1008/IN i_1008/OUT
Related Commands Add Nofaults Report Nofaults
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Command Dictionary Delete Nonscan Instances
Delete Nonscan Instances

Scope: All modes Usage DELete NONscan Instances {{pathname | instance_expression [-INStance | -Control_signal | -Module]} | -All} [-Class {User | System | Full}] Description Removes the specified sequential instances from the non-scan instance list. The Delete Nonscan Instances command deletes sequential instances, instances specified by control signals, or all instances within the specified module that were previously added to the non-scan instance list by using either the Add Nonscan Instances command or the Dont_touch property in a Genie netlist. You can delete either a specific list of instance names or all instances. Note If these non-scan instances are ignored for scannability checks and then the Delete Nonscan Instances command is entered in Dft mode, these specified instances will not be eligible for scan. You must go back to the Setup mode and then re-enter Dft mode to have scannability checks performed on these instances, which can make them eligible for scan. To display the current non-scan instance list, use the Report Sequential Instances command. Arguments pathname A repeatable string that specifies either the pathnames of the instances or signals that control instances that you want DFTAdvisor to delete from the non-scan instance list. instance_expression A string representing a list of instances within the design. The string instance_expression is defined as:
The asterisk (*) is a wildcard that allows you to match many instances in a design. Any expression that does not contain an asterisk (*) will match exactly zero or one instance. This argument does not support pathnames to objects below the instance level of an ATPG library model. You can use a pathname expression to select several instances and the tool will then delete nonscan instances for all the pins on those instances; but if the expression specifies a location below the instance level of an ATPG library model, the tool will issue an error message.
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Command Dictionary Delete Nonscan Instances
-INStance | -Control_signal | -Module A switch that specifies whether the pathnames are instances, pins (control signals), or modules. An example Verilog module is module clkgen (clk, clk_out, ) where clkgen is the module name. You can only use the -Control_signal option in Dft mode. The default is -Instance.
-All A switch that specifies to delete all instances from the non-scan instance list. -Class User | System | Full An optional switch and literal pair that specifies the source (or class) of the non-scan instance that you want to delete. The valid literals are as follows: User A literal that specifies to only delete the non-scan instances entered by the user using the Add Nonscan Instances command. This is the default. System A literal that specifies to only delete the non-scan instances described in the Genie netlist with the Dont_touch property. Full A literal that specifies to delete all the non-scan instances in the user and system class.
Examples The following example deletes an extra sequential non-scan instance called i_1007, then performs a full scan identification run thereby allowing DFTAdvisor to treat the non-scan instance i_1007 as a scan cell during the identification process:
set system mode dft add nonscan instances i_1006 i_1007 i_1008 delete nonscan instances i_1007 setup scan identification full_scan run
Related Commands Add Nonscan Instances Report Sequential Instances Setup Scan Identification Set Nonscan Handling
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Command Dictionary Delete Nonscan Models
Delete Nonscan Models

Scope: All modes Usage DELete NONscan Models model_name | -All [-Class {User | System | Full}] Description Removes from the non-scan model list the specified sequential DFT library models. When you issue the Add Nonscan Models command on a DFT library model, DFTAdvisor places all instances of that DFT library model into the user-specified, non-scan instance list. Once you remove a model from the non-scan model list with the Delete Nonscan Models command, DFTAdvisor then has the freedom to decide whether to place those instances of that model in the scan instance list. Note If these non-scan instances (models) are ignored for scannability checks and then the Delete Nonscan Models command is entered in Dft mode, these specified instances (models) will not be eligible for scan. You must go back to the Setup mode and then reenter Dft mode to have scannability checks performed on these instances (models) which can make them eligible for scan. DFTAdvisor decides whether to place individual instances in the scan instance list based on many parameters including the scan setup settings. For example, if the scan setup has been changed to All with the command, then DFTAdvisor is forced to place all available sequential instances into the scan instance list. Arguments model_name A repeatable string that specifies the model names that you want to delete from the non-scan model list. Enter the model names as they appear in the DFT library. -All A switch that specifies to delete all models from the non-scan model list. -Class User | System | Full An optional switch and literal pair that specifies the class code of the non-scan model that you specify. The valid literal names are as follows: User A literal that specifies that the list of non-scan models were previously added by using the Add Nonscan Models command. This is the default class. System A literal that specifies that the list of non-scan models were added by DFTAdvisor. Full A literal that specifies that the list of non-scan models consist of both the user and system class.
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Command Dictionary Delete Nonscan Models
Examples The following example deletes an extra sequential non-scan model called d_flip_flop2, then performs a full scan identification run thereby allowing DFTAdvisor to treat the non-scan model d_flip_flop2 as a scan cell during the identification process:
set system mode dft add nonscan models d_flip_flop1 d_flip_flop2 delete nonscan models d_flip_flop2 setup scan identification full_scan run
Related Commands Add Nonscan Instances Add Nonscan Models Report Nonscan Models Set Nonscan Handling
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Command Dictionary Delete Notest Points
Delete Notest Points

Scope: Setup and Dft modes Prerequisites: You must add circuit points with the Add Notest Points command before you can delete them. Usage DELete NOtest Points {pin_pathname | instance_pathname | instance_expression [-Observe_scan_cell]} | -ALL | {-Path critical_pathname} | -ALL_Paths Description Removes the specified pins from the list of notest points which the tool cannot use for testability insertion. The Delete Notest Points command deletes the definition of pins, all pins within an instance, scan cell, or paths that you have previously added using the Add Notest Points command. These notest circuit points identify output pins of cells or paths within the circuit that DFTAdvisor is not to use for insertion of controllability and observability circuitry. You can display a list of these current circuit points and their associated pins by using the Report Notest Points command. When you delete a critical path, the critical path is removed from the list of active paths (paths read in using Add Notest Points). For each gate in a removed path, which is in no other remaining active paths, the no test point restriction is removed. Arguments pin_pathname A repeatable string that specifies a list of pins for which you want to delete the circuit points that DFTAdvisor cannot use for testability insertion. instance_pathname A required repeatable string that lists the instances whose output pins you want to delete the circuit points that DFTAdvisor cannot use for testability insertion. All output pins within that (hierarchical) instance are removed from the list of pins that should be excluded from consideration. instance_expression A string representing a list of instances within the design. The string instance_expression is defined as:
The asterisk (*) is a wildcard that allows you to match many instances in a design. Any expression that does not contain an asterisk (*) will match exactly zero or one instance. This argument does not support pathnames to objects below the instance level of an ATPG library model. You can use a pathname expression to select several instances and the tool will then delete notest points for all the pins on those instances; but if the expression
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Command Dictionary Delete Notest Points
specifies a location below the instance level of an ATPG library model, the tool will issue an error message. -Observe_scan_cell An optional switch that specifies the scan cell instance named in the instance_pathname argument is to be removed from the no test point list. -ALL A switch that deletes all previously-added circuit points and critical paths. -Path critical_pathname A required switch and name pair that specifies to delete the named critical path. You can list the names of the critical paths using the Report Notest Points command with the -Paths switch. For more information on the format of the file, refer to The Path Definition File in the Scan and ATPG Process Guide. -ALL_Paths A required switch that specifies to delete all critical paths. Examples The following example deletes an incorrect notest circuit point and corrects it with a new circuit point before performing testability analysis:
set system mode dft add notest points tr_i ts_i delete notest points tr_i add notest points tr_io
Related Commands Add Notest Points Report Notest Points
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Command Dictionary Delete Output Masks
Delete Output Masks

Scope: Setup mode Usage DELete OUtput Masks primary_output | -All Description Removes the masking of the specified primary output pins. DFTAdvisor uses primary output pins as the observe points during the scan identification process. When you mask a primary output pin with the Add Output Masks command, DFTAdvisor marks that pin as an unobservable primary output during the identification process. You can set a default mask for all output and bidirectional pins using the Setup Output Masks command. You can add a hold value to a default mask with the Add Output Masks command, or remove a hold value using the Delete Output Masks command. To turn off the default masks for all output pins, you must use the Setup Output Masks command with the Off literal. Arguments primary_output A repeatable string that specifies the names of the primary output pins that you want to unmask. -All A switch that specifies to unmask all primary outputs that you previously masked by using the Add Output Masks command. Examples The following example first incorrectly chooses two of the designs primary output pins to mask. Then, the example unmasks the one primary output that was inappropriate, masks the correct primary output, and then displays the complete list of primary output pins that are currently masked from being used as observation points.
add output masks q1 qb3 -hold 1 delete output masks qb3 add output masks qb1 -hold 0 report output masks q1 hold1 qb1 hold0
Related Commands Add Output Masks Analyze Output Observe Report Output Masks Setup Output Masks
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Command Dictionary Delete Pin Constraints
Delete Pin Constraints

Scope: Setup mode Usage DELete PIn Constraints primary_input_pin | -All Description Removes the pin constraints from the specified primary input pins. The Delete Pin Constraints command deletes pin constraints that were previously added to the primary inputs with the Add Pin Constraints command. You can delete the pin constraints for specific pins or for all pins. Note This command has effects on other commands that relate to fault simulation, such as simulation-based test point selection. You can set a default pin constraint for all input and bidirectional pins using the Setup Pin Constraints command. The pin constraints set by the Setup Output Masks command can have their values overridden with the Add Pin Constraints command. You can remove an override of a default pin constraint using the Delete Pin Constraints command. To remove the default pin constraint for all input pins, you should use the Setup Pin Constraints command with the None literal. Arguments primary_input_pin A repeatable string that specifies a list of primary input pins whose pin constraints you want to delete. -All A switch that specifies to delete the pin constraints of all primary input pins.
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Command Dictionary Delete Pin Constraints
Examples The following example adds two pin constraints and then deletes one of them:
add pin constraints ph1 c0 add pin constraints ph2 c0 delete pin constraints ph1
Related Commands Add Pin Constraints Report Pin Constraints Setup Pin Constraints
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Command Dictionary Delete Pin Equivalences
Delete Pin Equivalences

Scope: Setup mode Usage DELete PIn Equivalences primary_input_pin | -All Description Removes the pin equivalence specifications for the designated primary input pins. The Delete Pin Equivalences command deletes the equivalence specifications that were previously added to the primary inputs with the Add Pin Equivalences command. You can delete pin equivalences for specific pins or for all pins. Note This command has effects on other commands that relate to fault simulation, such as simulation-based test point selection. Arguments primary_input_pin A repeatable string that specifies a list of primary input pins whose equivalence specifications you want to delete. -All A switch that specifies to delete all pin equivalence effects. Examples The following example deletes an incorrect pin equivalence specification and adds the correct one:
add pin equivalences indata2 -invert indata4 delete pin equivalences indata2 add pin equivalences indata3 -invert indata4
Related Commands Add Pin Equivalences Report Pin Equivalences
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Command Dictionary Delete Primary Inputs
Delete Primary Inputs

Scope: Setup mode Usage DELete PRimary Inputs net_pathname | primary_input_pin | -All [-Class {User | System | Full}] Description Removes the specified primary inputs from the current netlist. The Delete Primary Inputs command deletes the primary inputs that you specify from the circuit. You can delete either the user class, system class, or full classes of primary inputs. If you do not specify a class, the tool deletes the primary inputs from the user class. You can display a list of any class of primary inputs by using the Report Primary Inputs command. Arguments net_pathname A repeatable string that specifies the circuit connections that you want to delete. You can specify the class of primary inputs to delete with the -Class switch. primary_input_pin A repeatable string that specifies a list of primary input pins that you want to delete. You can specify the class of primary inputs to delete with the -Class switch. -All A switch that deletes all primary inputs. You can specify the class of primary inputs to delete with the -Class switch.
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Command Dictionary Delete Primary Inputs
-Class User | System | Full An optional switch and literal pair that specifies the class code of the designated primary input pins. The valid class code literal names are as follows: User A literal specifying that the primary inputs were added using the Add Primary Inputs command. This is the default class. System A literal specifying that the primary inputs derive from the netlist. Full A literal specifying that the primary inputs consist of both user and system classes.
Examples The following example deletes an extra added primary input from the user class of primary inputs:
add primary inputs indata2 indata4 indata6 delete primary inputs indata4 -class user
Related Commands Add Primary Inputs Report Primary Inputs Write Primary Inputs
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Command Dictionary Delete Primary Outputs
Delete Primary Outputs

Scope: Setup mode Usage DELete PRimary Outputs net_pathname | primary_output_pin | -All [-Class {User | System | Full}] Description Removes the specified primary outputs from the current netlist. The Delete Primary Outputs command deletes the primary outputs that you specify from the circuit. You can delete either the user class, system class, or full classes of primary outputs. If you do not specify a class, the tool deletes the primary outputs from the user class. You can display a list of any class of primary outputs by using the Report Primary Outputs command. Arguments net_pathname A repeatable string that specifies the circuit connections that you want to delete. You can specify the class of primary outputs to delete with the -Class switch. primary_output_pin A repeatable string that specifies a list of primary output pins that you want to delete. You can specify the class of primary outputs to delete with the -Class switch. -All A switch that deletes all primary outputs. You can specify the class of primary outputs to delete with the -Class switch. -Class User | System | Full An optional switch and literal pair that specifies the class code of the primary output pins that you specify. The valid literal names are as follows: User A literal specifying that the list of primary outputs were added using the Add Primary Outputs command. This is the default class. System A literal specifying that the list of primary outputs derive from the netlist. Full A literal specifying that the list of primary outputs consists of both the user and system class. Examples The following example deletes a primary output from the system class of primary outputs:
delete primary outputs outdata1 -class system
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Command Dictionary Delete Primary Outputs
Related Commands Add Primary Outputs Report Primary Outputs Write Primary Outputs
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Command Dictionary Delete Read Controls
Delete Read Controls

Scope: Setup mode Usage DELete REad Controls primary_input_pin | -All Description Removes the read control line off-state definitions from the specified primary input pins. The Delete Read Controls command deletes the off-state definition of the read control lines previously defined with the Add Read Controls command. You can delete the read control line definitions for specific pins or for all pins. Arguments primary_input_pin A repeatable string that specifies a list of primary input pins from which you want to delete any read control line off-state definitions. -All A switch that specifies to delete the read control line off-state definitions for all primary input pins. Examples The following example removes an incorrect read control line off-state definition, and then creates the correct off-state for that read control line:
add clocks 0 clk add read controls 0 r1 r2 delete read controls r1 add read controls 1 r1 set system mode dft
Related Commands Add Read Controls Report Read Controls
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Command Dictionary Delete Scan Chains
Delete Scan Chains

Scope: Setup Usage DELete SCan Chains chain_name | -All Description Removes the specified scan chain definitions from the scan chain list. The Delete Scan Chains command deletes scan chains previously defined with the Add Scan Chains command. You can delete the definitions of specific scan chains or of all scan chains. When you remove a scan chain definition, it is only the definition you are removing, not the scan chain itself. If you need to remove the scan chain itself, you can use the Ripup Scan Chains command. Arguments chain_name A repeatable string that specifies the names of the scan chain definitions that you want to delete. -All A switch that specifies to delete all scan chain definitions. Examples The following example defines several scan chains, adding them to the scan chain list, then deletes one of the scan chains:
add scan chains chain1 group1 indata2 outdata4 add scan chains chain2 group1 indata3 outdata5 add scan chains chain3 group1 indata4 outdata6 delete scan chains chain2
Related Commands Add Scan Chains Report Scan Chains Ripup Scan Chains
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Command Dictionary Delete Scan Groups
Delete Scan Groups

Scope: Setup mode Usage DELete SCan Groups group_name | -All Description Removes the specified scan chain group definitions from the scan chain group list. The Delete Scan Groups command deletes scan chain groups previously defined with the Add Scan Groups command. You can delete the definitions of specific scan chain groups or of all scan chain groups. When you delete a scan chain group, the tool also deletes all scan chains within the group. Arguments group_name A repeatable string that specifies the names of the scan chain group definitions that you want to delete. -All A switch that specifies to delete all the scan chain group definitions, which also automatically causes DFTAdvisor to remove all scan chain definitions. Examples The following example defines two scan chain groups, adding them to the scan chain group list, then deletes one of the scan chain groups:
add scan groups group1 scanfile1 add scan groups group2 scanfile2 delete scan groups group1
Related Commands Add Scan Groups Report Scan Groups
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Command Dictionary Delete Scan Instances
Delete Scan Instances

Scope: All modes Usage DELete SCan Instances {pathname | instance_expression [-INStance | -Control_signal | -Module]} | -All Description Removes the specified, sequential instances from the user-identified scan instance list. The Delete Scan Instances command deletes sequential instances, instances specified by control signals, or all instances within the specified module that were previously added to the scan instance list by using the Add Scan Instances command. You can delete either a specific list of instance names or all instances. You can also use this command to remove an exception status from an instance, that you added using the Add Scan Instances command, which allowed DFTAdvisor to convert the instance into a scan cell even though it violated the S4 rule. In this case, although the instance is converted back into a non-scan instance, the effects of its previous unknown state on downstream instances is not reset. User-identified scan instances result from using the Add Scan Instances or Add Scan Models commands. DFTAdvisor also selects the sequential instances by using the identification type you specify with the Setup Scan Identification command (system-identified). If you issue a Run command after removing an instance from the user-identified scan list with the Delete Scan Instances command, DFTAdvisor then has the option of including it in the system-identified scan instance list. Arguments pathname A repeatable string that specifies the pathnames of the instances or control signals (that control instances) that you want DFTAdvisor to delete from the user-identified scan instance list. The pathnames must be user-identified scan instances or control signals (that control instances), which you previously selected with the Add Scan Instances command. instance_expression A string representing a list of instances within the design. The string instance_expression is defined as:
The asterisk (*) is a wildcard that allows you to match many instances in a design. Any expression that does not contain an asterisk (*) will match exactly zero or one instance. This argument does not support pathnames to objects below the instance level of an ATPG library model. You can use a pathname expression to select several instances and the tool will then delete scan instances for all the pins on those instances; but if the expression
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Command Dictionary Delete Scan Instances
specifies a location below the instance level of an ATPG library model, the tool will issue an error message. -INStance | -Control_signal | -Module A switch that specifies whether the pathnames are instances, pins (control signals), or modules. An example Verilog module is module clkgen (clk, clk_out, ) where clkgen is the module name. You can only use the -Control_signal option in Dft mode. The default is -Instance. -All A switch that specifies to delete all instances from the user-identified scan instance list. This switch does not affect the instances in the system-identified scan instance list. Examples The following example deletes an extra sequential scan instance that was defined to be treated as a scan cell; thus, the deleted instance is no longer included in the user-identified scan instance list:
set system mode dft add scan instances i_1006 i_1007 i_1008 delete scan instances i_1007
Related Commands Add Scan Instances Report Sequential Instances
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Command Dictionary Delete Scan Models
Delete Scan Models

Scope: All modes Usage DELete SCan Models model_name | -All Description Removes the specified sequential models from the scan model list. The Delete Scan Models command deletes all instances of the sequential models that you specify. This includes removing all instances of the model_name from the user-identified scan instance list. You can delete a specific list of sequential models or all the models. There are two ways that sequential instances can be identified for scan: system and user. You can explicitly identify scan instances with either the Add Scan Instances or the Add Scan Models commands (user-identified). DFTAdvisor also selects the sequential instances by using the identification type you specify with the Setup Scan Identification command. The Delete Scan Models command does not remove instances from the system-identified scan instance list. If you issue a Run command after removing a model from the user-identified scan list with the Delete Scan Models command, DFTAdvisor then has the option of including any of the instances of that model in the system-identified scan instance list. To display the current scan model list, use the Report Scan Models command. Arguments model_name A repeatable string that specifies the model names that you want to delete from the scan model list and user-identified scan instance list. Enter the model names as they appear in the DFT library. -All A switch that specifies to delete all models from the scan model list and all instances from the user-identified scan instance list. Examples The following example deletes an extra added sequential scan model; thus, the deleted model is no longer included in the scan model list:
set system mode dft add scan models d_flip_flop1 d_flip_flop2 delete scan models d_flip_flop2
Related Commands Add Scan Instances Add Scan Models Report Scan Models
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Command Dictionary Delete Scan Partitions
Delete Scan Partitions

Scope: All modes Usage DELete SCan PArtitions {object_name... | -All} Description Deletes the user specified scan partitions. It does not delete the default scan partition, default_scan_partition. The sequential cells whose scan partitions are deleted are placed back into the default scan partition. Arguments object_name A required repeatable string that specifies the names of the scan partitions to remove. -All A required switch that specifies to remove all the user specified scan partitions. This option does not remove the default scan partition that the tool creates, default_scan_partition. Examples The following example adds three scan partitions. The scan partitions are then deleted, first partially, then completely.
add scan partition part_1 -instance umodA add scan partition part_2 -instance umodB umodC add scan partition part_3 -instance umodD delete scan partitions part_2 report scan partitions ----------------------------------------------------------------------ScanPartitionName TotalNumCells/ScannableCells Members ----------------------------------------------------------------------part_1 150/150 umodA [instance] part_3 330/250 umodD [instance] default_scan_partition 15000/0 <all_remaining_cells> ----------------------------------------------------------------------delete scan partitions -all report scan partitions ----------------------------------------------------------------------ScanPartitionName TotalNumCells/ScannableCells Members ----------------------------------------------------------------------default_scan_partition 15480/400 <all_remaining_cells> -----------------------------------------------------------------------
Related Commands Add Scan Partition Report Scan Partitions
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Command Dictionary Delete Scan Pins
Delete Scan Pins

Scope: All modes Usage DELete SCan PIns chain_name | -All Description Removes any previously-assigned scan input, output, and clock names from the specified scan chains. The Delete Scan Pins command removes user-specified names of the scan input and scan output pins of the scan chains that you previously assigned with the Add Scan Pins command. You can use the Report Scan Pins command to display all added scan input and output pin names for each scan chain. Arguments chain_name A repeatable string that specifies the names of the scan chains from which you want DFTAdvisor to remove the associated pins. -All A switch that removes all added scan pin names from all scan chains. Examples The following example removes previously-assigned scan chain input and output names for chain1:
add clocks 0 clk set system mode dft run add scan pins chain1 si so add scan pins chain2 si1 so1 delete scan pins chain1 insert test logic
Related Commands Add Scan Pins Report Scan Pins
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Command Dictionary Delete Seq_transparent Constraints
Delete Seq_transparent Constraints

Scope: Setup mode Usage DELete SEq_transparent Constraints {model_name pin_name} | -All Description Removes the pin constraints from the specified DFT library model input pins. The Delete Seq_transparent Constraints command deletes constraints that were added to clock enable pins with the Add Seq_transparent Constraints command. You can delete the constraints for all DFT library models or for specific pins of a model. Arguments model_name A string that specifies the DFT library model from whose pin_name you want to delete the constraints. pin_name A repeatable string that specifies the clock enable pin names of the model_name specified whose constraints you want to delete. -All A switch that specifies to delete the constraints of all DFT library model pins. Examples The following example adds two seq_transparent constraints and deletes one of them:
set system mode setup add seq_transparent constraints c1 gdff enable delete seq_transparent constraints gdff enable add seq_transparent constraints c1 gdff en set system mode dft setup scan identification seq_transparent
Related Commands Add Seq_transparent Constraints Report Seq_transparent Constraints
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Command Dictionary Delete Sub Chains
Delete Sub Chains

Scope: Setup mode Usage DELete SUb Chains -All | {object_name [subchain_name] [-Module | -Instance | -Library_model]} Description Removes scan subchains previously defined with the Add Sub Chains command. Use the Report Sub Chains command to display the currently defined scan subchains. Arguments -All A switch that removes all scan subchains. object_name A string that specifies either the pathname of an instance, or the name of a module or library model. If you specify an instance, you must also use the -Instance switch. If you specify a library model, you must also use the -Library_model switch. subchain_name An optional string that specifies the name of a pre-existing scan subchain to delete. If you do not specify a subchain_name, all subchains in the specified object_name are deleted. -Module An optional switch that specifies the object_name is a module. This is the default. -Instance An optional switch that specifies the object_name is an instance. -Library_model An optional switch that specifies the object_name is a library model. Examples The following example deletes the subc1 subchain from the blkA module:
add sub chains blkA subc1 si1 so1 10 mux_scan -sen_core sen1 -subclock sclk -module add sub chains blkA subc2 si2 so2 30 mux_scan -sen_core sen2 -subclock mclk -module delete sub chains blkA subc1
Related Commands Add Sub Chains Report Sub Chains
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Command Dictionary Delete Subchain Clocks
Delete Subchain Clocks

Scope: Setup mode Usage DELete SUbchain CLocks subchain_name clock_name Description Deletes subchain clocks previously defined with the Add Subchain Clocks command. Arguments subchain_name A required string that specifies the name of a subchain. clock_name A required string that specifies the name of a subchain clock. Examples The following example adds, reports, and deletes a subchain clock:
add sub chains MULTIBITSFF3 chain1 SI SO 4 mux_scan S library_model add subchain clocks chain1 0 RESET -reset add subchain clocks chain1 0 SET -set add subchain clocks 0 CK -first_cell_clock -leading_edge add subchain clocks 0 CK -last_cell_clock -leading_edge report subchain clocks chain1 // // // // // // clock name type off_state ---------- -----------RESET reset 0 SET set 0 CK first cell clock 0 CK last cell clock 0 edge -----
delete subchain clocks chain1 CK report subchain clocks chain1 // // // // clock name type off_state edge ---------- ----- --------- -----RESET reset 0 SET set 0
Related Commands Add Subchain Clocks Report Subchain Clocks
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Command Dictionary Delete Subchain Groups
Delete Subchain Groups

Scope: All modes Usage DELete Subchain Groups subchain_group_name | -All Description Removes a scan subchain group. The Delete Subchain Groups command removes subchain groups added by means of the Add Subchain Group command. To determine whether there are any current scan subchain groups, use the Report Subchain Groups command. Arguments subchain_group_name A repeatable string that specifies the names of the subchain group definitions to be deleted. -All A switch that removes all subchain group definitions. Examples The following example removes a subchain group definition:
add subchain group subchaingroup1 subchain1 subchain2 -fixed add subchain group subchaingroup2 subchain3 subchain4 -flexible report subchain groups ----------------------------------------------SubchainGroupName Type ListOfSubchains ----------------------------------------------subchaingroup1 fixed subchain1 subchain2 subchaingroup2 flexible subchain3 subchain4 delete subchain group subchaingroup1
Related Commands Add Subchain Group Add Sub Chains Delete Sub Chains Report Sub Chains Report Subchain Groups
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Command Dictionary Delete Test Points
Delete Test Points

Scope: Setup mode Usage DELete TEst Points {-All | testpoint_pin_name} [-Full | -Control | -Observe | -Lockup] [-Wrapper_chains_identified] Description Removes the specified test point definitions. If you do not specify -Control, -Observe, or -Lockup with either the testpoint_pin_name or the -All option, DFTAdvisor uses the default -Full value. The -Full means that DFTAdvisor removes all the control and observe test points and lockup cells at the specifed location(s). This command removes both user-defined and system-defined test points. You can create userdefined test points with the Add Test Points command. You can enable DFTAdvisor to automatically identify test points using a combination of the Setup Scan Identification, Setup Test_point Identification, Setup Test_point Insertion, and Run commands. Arguments -All A required switch that removes the control and/or observe test points from all locations. testpoint_pin_name A required, repeatable string that specifies a pathname to the control and/or observe test points to delete. -Full An optional switch that removes both the control and observe test points from the specified locations. This is the default. -Control An optional switch that removes the control test points from the specified locations. -Observe An optional switch that removes the observe test points from the specified locations. -Lockup An optional switch that removes the added lockup cells. -Wrapper_chains_identified An optional switch that removes the test points added automatically during the wrapper chain identification process. Such test points may be added only if the -Test_points switch is specified with the Setup Pin Constraints command. You can use the -Observe or -Control switches to filter which test points are removed. By default, all test points are removed.
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Command Dictionary Delete Test Points
Examples The following example creates the definitions for three test points (one observe and two control), then removes two of the definitions:
add cell models and2a -type and add test point /I_6_16/cp control and2a in2 add test point /I_7_16/q observe out1 add test point /I_8_16/cp control and2a in3 delete test points /I_6_16/cp /I_7_16/q
The Delete Test Points command only specifies the testpoint_pin_names of the test points, not the type. This example includes both control and observe test points and deletes them by default. Related Commands Add Test Points Report Test Logic Report Test Points Setup Pin Constraints Setup Scan Identification Setup Test_point Identification Setup Test_point Insertion
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Command Dictionary Delete Tied Signals
Delete Tied Signals

Scope: Setup mode Usage DELete TIed Signals {floating_object_name | -All} [-Class {User | System | Full}] [-Pin] Description Removes the assigned (tied) value from the specified floating nets or pins. The Delete Tied Signals command deletes the tied values that were previously assigned with the Add Tied Signals command. You can delete tied values from either user class, system class, or full classes of floating nets or pins. If you do not specify a class, the tool deletes the tied values from the user class of floating nets or pins. To display a list of any class of tied floating nets or pins, use the Report Tied Signals command. When you remove the effects of a tied signal, DFTAdvisor reassigns the default tied signal value to that object. The invocation default for tied objects is the unknown state (X), and you can change that default with the Setup Tied Signals command. Arguments floating_object_name A repeatable string that specifies the names of the tied floating nets or pins whose tied values you want to delete. The tool deletes all of the tied values associated with the floating nets or pins in the class of tied floating nets or pins which you specify with the -Class switch. If you do not specify the -Pin option, the floating_object_name is assumed to be a net name. If you specify a full net pathname, the tool deletes only the specified instance-based blackbox tied signal. If you do specify the -Pin option, the floating_object_name is assumed to be a pin name. -All A switch that deletes the tied values from all tied floating nets or pins in the class of tied floating nets or pins, which you specify with the -Class switch. This also includes all instance-based blackbox tied signals. -Class User | System | Full An optional switch and literal pair that specifies the class code of the tied floating nets or pins that you specify. The valid literal names are as follows: User A literal that specifies that the list of tied floating nets or pins were previously added by using the Add Tied Signals command. This is the default class. System A literal that specifies that the list of tied floating nets or pins are described in the netlist. Full A literal that specifies that the list of tied floating nets or pins consist of both the user and system class.
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Command Dictionary Delete Tied Signals
-Pin An optional switch that specifies that the floating_object_name argument that you provide is a floating pin name.
Examples The following example deletes the tied value from the user-class tied net vcc; thereby leaving vcc as a floating net:
add tied signals 1 vcc vdd delete tied signals vcc -class user
Related Commands Add Tied Signals Delete Black Box Report Tied Signals Setup Tied Signals
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Command Dictionary Delete Write Controls
Delete Write Controls

Scope: Setup mode Usage DELete WRite Controls primary_input_pin | -All Description Removes the RAM write control line off-state definitions from the specified primary input pins. The Delete Write Controls command deletes write control line off-state definitions previously defined with the Add Write Controls command. You can delete the write control line definitions for specific pins or for all pins. Arguments primary_input_pin A repeatable string that specifies a list of primary input pins from which you want to delete any write control line off-state definitions. -All A switch that specifies to delete the write control line off-state definitions for all primary input pins. Examples The following example deletes an incorrect write control line, and adds the correct off-state to that write control line:
add write controls 0 w1 w2 delete write controls w1 add write controls 1 w1 set system mode dft
Related Commands Add Write Controls Report Write Controls
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Command Dictionary Dofile
Dofile
Scope: All modes Usage DOFile filename [-History] Description Executes the commands contained within the specified file. The Dofile command sequentially executes the commands that are contained in a file that you specify. This command is especially useful when you must issue a series of commands. Rather than executing each command separately, you can place them into a file in their desired order, and then execute them by using the Dofile command. You can also place comment lines in the file by starting the line with a double slash (//); DFTAdvisor handles these lines as comments and ignores them. The Dofile command sends each command expression, in order, to the tool which in turn displays each command from the file before executing it. If DFTAdvisor encounters an error due to any command, the Dofile command stops and displays an error message. You can enable the Dofile command to continue regardless of errors by setting the Set Dofile Abort command to Off. Arguments filename A required string that specifies the name of the file that contains the commands you want DFTAdvisor to execute. -History An optional switch that specifies for the tool to add the commands from a dofile to the command line history list. By default, the commands in a dofile are not inserted into the history list, but the Dofile command itself is added to the list. Examples The following example executes all the commands from the command_file file:
dofile command_file
The command_file may contain any application command available. An example of a command_file is as follows:
add clocks 0 clock set system mode dft run
Related Commands History Save History Set Command Editing Set Dofile Abort
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Command Dictionary Echo
Echo
Scope: All modes Usage ECHo string [{> | >>} file_pathname] Description Issues a user-defined string to the transcript. The Echo command issues a user-defined string to the transcript or to a pathname, if you use one of the file redirection operators. Note Commands that use either the > or >> file redirection operator are first checked for correctness. Syntax errors are reported to the display prior to the commands execution. The redirection operator does not hide these errors. Arguments string A required string. The string that you want echoed to the transcript. Double quotes are required if the string contains spaces or special characters. > file_pathname An optional redirection operator and pathname pair, used at the end of the argument list, for creating or replacing the contents of file_pathname. >> file_pathname An optional redirection operator and pathname pair, used at the end of the argument list, for appending to the contents of file_pathname.
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Command Dictionary Echo
Examples The following example redirects output from several commands into a single output file, my_scan_report. The first command creates or replaces the my_scan_report file. The second and following commands append to the same file.
echo "----------- scan cells ------------" > my_scan_report report scan cells >> my_scan_report echo "----------- scan chains ----------" >> my_scan_report report scan chains >> my_scan_report
Related Commands History Report Circuit Components Report Dft Check Report DRC Rules Report Environment Report Primary Inputs Report Primary Outputs Report Scan Cells Report Scan Chains Report Scan Groups Report Scan Pins Report Sequential Instances Report Statistics Report Sub Chains Report Test Logic Report Test Points
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Command Dictionary Exit
Exit
Scope: All modes Usage EXIt [-Discard] Description Terminates the current DFTAdvisor session. The Exit command terminates DFTAdvisor and returns to the operating system. You should either save the current netlist design before exiting DFTAdvisor or specify the -Discard switch to not save the netlist. If you are operating in interactive mode (not running a dofile) and you neither saved the current netlist or used the -Discard option, DFTAdvisor displays a warning message, and you can continue the session and save the netlist before exiting. If you plan to load the scan design into Tessent FastScan, you may also want to save the ATPG setup to identify the scan chains before exiting. Arguments -Discard An optional switch that explicitly specifies to not save the current netlist and terminate the DFTAdvisor session. Examples The following example exits DFTAdvisor after performing scan chain insertion, and saving the test procedure, dofile, and new netlist for the inserted scan chains:
add clocks 1 clk1 add clocks 0 clk0 set system mode dft run insert test logic write atpg setup scan -replace write netlist scan.edif -edif exit
Related Commands Write Atpg Setup Write Netlist Write Scan Identification
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Command Dictionary Find Design Names
Find Design Names

Scope: All modes Usage FINd DEsign Names regular_expression [-LOcal | -Hier] [-Design | -NETList | -LIbrary | -All] [-INStance | -Net | -Pin [INPut | OUtput | INOut | ALLIn | ALLOut] -Cell | -Module] [{> | >>} file_pathname] Description Displays design object hierarchical names matched by an input regular expression, which may include asterisk (*) or question mark (?) wildcard characters in the pathname string. Arguments regular_expression A required, regular expression, which may include asterisk (*) or question mark (?) wildcard characters. An asterisk matches one or more characters. A question mark matches a single character. -LOcal An optional switch that matches wildcard characters within the current hierarchy level. -Hier An optional switch that matches the regular expression across hierarchy boundaries (for example, a* matches a1/b/c). This is the default. -Design An optional switch that matches only pathnames to objects at the topmost library cell level. -NETList An optional switch that matches objects from the top of the design down to the topmost library cell. -LIbrary An optional switch that matches objects within any level of library cells. -All An optional switch that specifies matches objects at all levels of the design. This is the default. -INStance An optional switch that matches only instance pathnames. This is the default. -Net An optional switch that matches only net pathnames.
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-Pin An optional switch that matches only pin pathnames (any pin direction). The following optional pin filters restrict which pins are matched: INPut Match only input pin pathnames. OUtput Match only output pin pathnames. INOut Match only bidirectional pin pathnames. ALLIn Match both input and bidirectional pin pathnames. ALLOut Match both output and bidirectional pin pathnames.
-Cell An optional switch that finds all library cell (model) names matching the specified regular expression.
-Module An optional switch that finds all netlist module names matching the specified regular expression.
> file_pathname An optional redirection operator and pathname pair, used at the end of the argument list, for creating or replacing the contents of file_pathname.
>> file_pathname An optional redirection operator and pathname pair, used at the end of the argument list, for appending to the contents of file_pathname.
Examples The following examples display object pathnames for various input wildcard expressions, given a netlist with the following instance hierarchy:
/ tiny_i U5 ret_i intreg1_reg_0 ... intreg1_reg_31 add_20 U1_0 ... U1_3 add_30 U5 ... U12 mul_18 U5 ... U868 FS U5 ... U33 mul_19 FS U5 ... U278 U5 ... U181 mul_22 U5 ... U735 FS
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Command Dictionary Find Design Names U15 ...
and assuming the U5 instances all reference the following library cell:
model LSR2BUFA(Q, QN, S, R, G, SD, RD) ( input(S, R, G, SD, RD) () output(Q) (primitive = _buf UP1 (QT, Q);) output(QN) (primitive = _buf UP2 (QNT, QN);) intern(QT_int) (instance = LSI_LSR2 UD1 (QT_int, S, R, G, SD, RD);) intern(QNT_int) (instance = LSI_LSR2N UD2 (QNT_int, S, R, G, SD, RD);) intern(QT) (instance = LSI_NOTI UD3 (QT, QT_int);) intern(QNT) (instance = LSI_NOTI UD4 (QNT, QNT_int);) )
Example 1:
SETUP> find design names /ret_i/add_2* -instance -design -hier // Note: Matched 4 names /ret_i/add_20/U1_0 /ret_i/add_20/U1_1 /ret_i/add_20/U1_2 /ret_i/add_20/U1_3
Example 2:
SETUP> find design names /ret_i/add_2* -instance -netlist -hier // Note: Matched 5 names /ret_i/add_20 /ret_i/add_20/U1_0 /ret_i/add_20/U1_1 /ret_i/add_20/U1_2 /ret_i/add_20/U1_3
Finds instance add_20 under /ret_i/, and also descends the hierarchy to find all netlist instances under /ret_i/add_20/. Example 3:
SETUP> find design names /ret_i/add_2* -inst -netlist -local // Note: Matched 1 names /ret_i/add_20
This example shows that -Local doesnt descend the hierarchy to find more matches as the previous example does. Example 4:
SETUP> find design names /ret_i/add_2* -ins -design -local // Note: Matched 0 names
There are no instances of a library cell under /ret_i/ with instance name starting with add_2.
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Example 5:
SETUP> find design names /ret_i/*_2? -ins -netlist -local // Note: Matched 2 names /ret_i/add_20 /ret_i/mul_22
Found 2 instances under /ret_i/. Note /ret_i/gt_68_2 did not match because the ? in the wildcard expression requires another character after the _2. Example 6:
SETUP> find design names */U5 -inst -design -hier // Note: Matched 7 names /tiny_i/U5 /ret_i/add_20/U5 /ret_i/mul_18/U5 /ret_i/mul_18/FS/U5 /ret_i/mul_19/U5 /ret_i/mul_19/FS/U5 /ret_i/mul_22/U5
Example 7:
SETUP> find design names ret_i/mul*/U5 -ins -des -local // Note: Matched 3 names /ret_i/mul_18/U5 /ret_i/mul_19/U5 /ret_i/mul_22/U5
Example 8:
SETUP> find design names ret_i/mul*/U5 -ins -design -hier // Note: Matched 5 names /ret_i/mul_18/U5 /ret_i/mul_18/FS/U5 /ret_i/mul_19/U5 /ret_i/mul_19/FS/U5 /ret_i/mul_22/U5
Example 9:
SETUP> find design names ret_i/mul_18/U5* -ins -library -hier // Note: Matched 5 names /ret_i/mul_18/U5 /ret_i/mul_18/U5/UD1 /ret_i/mul_18/U5/UD2
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Command Dictionary Find Design Names /ret_i/mul_18/U5/UD3 /ret_i/mul_18/U5/UD4
Example 10:
SETUP> find design names ret_i/mul*/U5/* -pin output -design -local // Note: Matched 6 names /ret_i/mul_18/U5/Q /ret_i/mul_18/U5/QN /ret_i/mul_19/U5/Q /ret_i/mul_19/U5/QN /ret_i/mul_22/U5/Q /ret_i/mul_22/U5/QN
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Command Dictionary Help
Help
Scope: All modes Usage HELp [command_name] [-MANual] Description Displays the usage syntax and system mode for the specified command. The Help command displays useful information for a selected command. You can display the usage and syntax of a command by typing Help and the command name. You can display a list of certain groups of commands by entering Help and a keyword such as Add, Delete, Save, and so on. Arguments command_name An optional string that consists of any keyword or command. You can use minimum typing for the command name. If you do not supply a command_name, the default display is a list of all the valid command names. -MANual An optional string that specifies to also display the reference manual description for the specified command. The effect is the same as if you executed the menu item, Help > On Commands > Open Reference Page, from the GUI. If you type HELp and include only the -MANual switch, the tool opens the product bookcase, giving access to all the manuals for that product group. Examples The following example displays the usage and system mode for the Report Primary Inputs command:
help report primary inputs // // // Report primary inputs usage: REPort PRimary Inputs [-Class <User|System|Full>] [-All | pin_pathname...] legal system modes: ALL
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Command Dictionary History
History
Scope: All modes Usage HIStory [list_count] [-Nonumbers] [-Reverse] [{> | >>} file_pathname] Description Displays a list of previously-executed commands. The History command is similar to the Korn shell (ksh) history command in UNIX. By default, this command displays a list of all previously-executed commands, including all arguments associated with each command, starting with the oldest. Note The HISTFILE and HISTSIZE ksh environment variables do not control the command history of the tool. The Save History command controls where the tool stores the history file. You can perform command line editing if you set the VISUAL or EDITOR ksh environment variable to either emacs, gmacs, or vi editing. Refer to the ksh(1) man page for specifics on the various editing modes. Within the tool, you can override the ksh environment variable settings by issuing the Set Command Editing command. Each command line in the history list is preceded by a leading number indicating the order in which the commands were entered. Arguments list_count An optional integer that specifies for the tool to display only the specified number (list_count) of the most recently executed commands. If no list_count is specified, the tool displays all previously-executed commands. -Nonumbers An optional string that specifies for the tool to display the history list without the leading numbers. This is useful for creating dofiles. The default displays the leading numbers. -Reverse An optional switch that specifies for the tool to display the history list starting with the most recent command rather than the oldest. > file_pathname An optional redirection operator and pathname pair, used at the end of the argument list, for creating or replacing the contents of file_pathname.
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Command Dictionary History
Examples The following command displays the history list with leading numbers, starting with the oldest command.
history 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 help hist dof instructor/fault.do set system mode atpg set fault type stuck add faults -all run report statistics report faults -class ATPG_UNTESTABLE analyze fault /I$20/en -stuck_at 1 set system mode setup set system mode atpg set fault type iddq add faults -all run report statistics history
Related Commands Echo Save History Set Command Editing
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Command Dictionary Insert Test Logic
Insert Test Logic

Scope: Dft mode Prerequisites: The Write Scan Identification command must be issued before this command is used or files generated by this command will be empty. To use the -Verilog switch, you must have defined a buffer model with the Add Cell Models command or with a cell_type attribute. Usage INSert TEst Logic [filename [-Fixed]] [-Scan {ON | OFf}] [-Test_point {ON | OFf}] [-Ram {ON | OFf}] {[-NOlimit] | [-MAx_length integer] | [-NUmber [integer]]} [-Clock {Nomerge | Merge}] [-Edge {Nomerge | Merge}] [-COnnect {ON | OFf | Tied | Loop | Buffer}] [-Output {Share | New}] [-MOdule {Norename | Rename}] [-Verilog] [-Hierarchical {OFf | ON [-Tolerance integer_percent]}] [-NEw_scan_po] [-Keep_original_net] Description Inserts the test structures that you define into the netlist to increase the designs testability. The purpose of DFTAdvisor is to perform tasks that modify the design to increase the fault coverage (testability) of the design. There are several ways that it can aid in increasing a designs fault coverage. The primary purpose of DFTAdvisor is to identify sequential cells that DFTAdvisor can replace with corresponding scan cells and then stitch together into a scan chain. In addition to scan cell replacement and stitching, DFTAdvisor can also perform two other tasks with the Insert Test Logic command that can increase the designs testability. DFTAdvisor supports the adding of test points (both system-defined and user-defined), and it supports the automatic adding of test logic. For more information on scan replacement, test points, and test logic, refer to the Scan and ATPG Process Guide. For information on test point insertion, refer to Automatically Choosing Control and Observe Points in the Scan and ATPG Process Guide. For information on handling pre-inserted scan cells, refer to Specifying Existing Scan Cells in the Scan and ATPG Process Guide. The default behavior of DFTAdvisor is to partition the scan cells over the scan chains without considering the hierarchical distribution of the sub-modules in the circuit. This is called flat partitioning and it may cause different instances of a sub-module to have a different number of scan chains. As a result, when the final scan-inserted netlist is written out, DFTAdvisor generates unique module definitions for the different instances of the same sub-module. To decrease, or prevent, the uniquification of module definitions that originate from flat scan cell partitioning, turn on the -Hierarchical switch. Hierarchical partitioning is not deployed when the filename [-Fixed] option is used. Hierarchical partitioning is recommended over flat partitioning unless the circuit has previously inserted chains and/or test points. These previously
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inserted elements can have an arbitrary distribution in the circuit and can therefore cause uniquification of modules. There could be reasons to use flat partitioning, depending on your design. For instance, flat partitioning places cells that have direct access to primary outputs at the end of the chains. This can reduce the number of scan output pins that DFTAdvisor creates. Hierarchical partitioning can cause an increased number of scan inputs and outputs for the submodules, which could be an issue for your design. If this is the case, use the -Tolerance switch. Specifying an integer percentage of tolerance allows DFTAdvisor to create chain lengths shorter or longer than their ideal length (total number of cells divided by the specified number of chains), which can reduce the number of chains per sub-module, and, thus, the interconnections between sub-modules. One possible result of using a tolerance other than 0 is a variation of the number of scan chains at the top level. The differences from the ideal length for each chain accumulate at the last chain during the insertion process. A specified high tolerance can cause the removal or the unwanted lengthening of the last chain. To see the before and after effect of the -Tolerance option, use the Report Scan Chains command. Arguments filename -Fixed An optional string and associated optional switch that specify the name of the ASCII file that lists the scan instances that you want DFTAdvisor to stitch together. This file can contain information regarding scan cell ordering along with which instances are to be in each scan chain. Note If you use this file, it must contain all instances you want stitched. If you do not specify a filename, DFTAdvisor stitches all non-scan cells that it has identified and mapped to scan cells into a scan chain using the settings of the other Insert Test Logic arguments. The -Fixed switch specifies for DFTAdvisor to stitch the scan instances in the fixed order that is given in the filename. The default scan cell ordering is based on hierarchical rules, but within a hierarchical block the scan cell ordering is random. When using the -Fixed option, it also ignores certain scan input/output mapping performed by the Add Scan Pins command. For more information, refer to Naming Scan Input and Output Ports in the Scan and ATPG Process Guide. The filename that you specify must list one instance per line and use the following format (all on one line):
instance_pathname cell_id chain_id [&sub_chain_name] [{+|-}[lockup_latch_model]]
instance_pathname A string that specifies the name of the non-scan cell that you want DFTAdvisor to put in the scan chain.
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cell_id An integer that specifies the placement of the instance_pathname in relation to other instance_pathnames. DFTAdvisor places the instance having the smallest cell_id closest to the scan chain output. All instances in the same chain must have unique cell_ids. chain_id An integer that specifies the scan chain in which you want DFTAdvisor to place the instance_pathname. DFTAdvisor places instances with the same chain_id in the same chain. &sub_chain_name An optional special character and string that specifies the name of the sub-scan chain you defined with the Add Sub Chains command. You need to specify the subchain name when more than one subchain is defined for a sub-module or a hierarchical instance. No space is allowed between the ampersand (&) and the sub_chain_name argument. {+|-}[lockup_latch_model] An optional special character and an additional optional string that specifies the location of the lockup cell. The +|- argument specifies that a lockup cell is to be added to the scan out of the current instance_pathname. No space is allowed between the +|- and the lockup_latch_model name. Note that if you define a lockup cell in this file, you must specify every location that you want to insert lockup cells. If no lockup cells are defined in this file, DFTAdvisor uses the settings in the Set Lockup Cell and Insert Test Logic commands. In such case, if you want DFTAdvisor to automatically insert lockup cells in necessary locations, you should use the -Clock/-Edge merge option(s) with the Insert Test Logic command. For more information on inserting lockup cells, refer to the Set Lockup Cell command and Merging Scan Chains with Different Shift Clocks in the Scan and ATPG Process Guide. + Specifies to use the clock used by the instance_pathname with the next lower cell_id. The next lower cell_id, refers to the a non-scan cell which will be connected to the scan out of the current instance_pathname. - Specifies to use the clock used by the instance_pathname. lockup_latch_model Specifies the name of the lockup cell model to use. The specified lockup cell must be defined by the Add Cell Models command or defined in the ATPG library using the cell_type attribute. If the lockup_latch_model is not specified, the first model in the defined latch model list is used. -Scan ON | OFf An optional switch and literal pair that specifies whether DFTAdvisor replaces the identified non-scan cells (scan candidates) with the corresponding scan cells. The valid literals are as follows: ON A literal that enables DFTAdvisor to replace the identified non-scan cells (scan candidates) with the corresponding scan cells. This is the default. OFf A literal that disables DFTAdvisor from replacing the identified non-scan cells (scan candidates) with the corresponding scan cells.
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-Test_point ON | OFf An optional switch and literal pair that specifies whether DFTAdvisor adds the identified test logic and test points into the design. The valid literals are as follows: ON A literal that enables DFTAdvisor to add the identified test logic and test points into the design. This is the default. OFf A literal that disables DFTAdvisor from adding the identified test logic and test points into the design.
-Ram ON | OFf An optional switch and literal pair that specifies whether DFTAdvisor adds the identified test logic gates that are necessary to allow the ATPG tools access to the write control lines of the RAMs. The valid literals are as follows: ON A literal that enables DFTAdvisor to add the identified test logic gates for RAM write control line access. This is the default. OFf A literal that disables DFTAdvisor from adding the identified test logic gates for RAM write control line access.
-NOlimit An optional switch specifying that the scan chain has no limit on the number of scan cells it contains. This is the default.
-MAx_length integer An optional switch and integer pair that specifies the maximum number of scan cells that DFTAdvisor can stitch into a scan chain. DFTAdvisor evenly divides the scan cells into scan chains that are smaller than the max_length integer. Final results depend upon the number of scan candidates.
-NUmber integer An optional switch and integer pair that specifies the exact number of scan chains that you want DFTAdvisor to insert. Final results depend upon the number of scan candidates. The default number of chains is 1.
-CLock Nomerge | Merge An optional switch and literal pair that specifies whether DFTAdvisor uses different clocks on the same scan chain. The two valid literals are as follows: Nomerge A literal that disables the use of different clocks on the same scan chain. This is the default. Merge A literal that enables the use of different clocks on the same scan chain.
-Edge Nomerge | Merge An optional switch and literal pair that specifies whether DFTAdvisor merges stable high chains into stable low chains. The two valid literals are as follows: Nomerge A literal that specifies to not merge stable high chains into stable low chains. This is the default.
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Merge A literal that specifies to merge stable high chains into stable low chains. -COnnect ON | OFf | Tied | Loop | Buffer An optional switch and literal pair that specifies whether DFTAdvisor stitches the scan cells together into a scan chain. The valid literals for stitching the scan chain are as follows: ON A literal that specifies for DFTAdvisor to replace the identified non-scan cells with their corresponding scan replacements and to stitch those scan cells together into a scan chain. This is the default. OFf A literal that specifies for DFTAdvisor to replace the identified non-scan cells with their corresponding scan replacements, but not stitch those scan cells together into scan chains. Tied A literal that specifies for DFTAdvisor to replace the identified non-scan cells with their corresponding scan replacements, but not stitch those scan cells together into scan chains. This option has DFTAdvisor tie the input/output scan pins to ground. Loop A literal that specifies for DFTAdvisor to replace the identified non-scan cells with their corresponding scan replacements, but not stitch those scan cells together into scan chains. This option has DFTAdvisor connect the scan_out pin to its own scan_in pin as a self-loop. Buffer A literal that specifies for DFTAdvisor to replace the identified non-scan cells with their corresponding scan replacements, but not stitch those scan cells together into scan chains. This option has DFTAdvisor connect the scan_out pin to its own scan_in pin as a self-loop with a buffer in between. -Output Share | New An optional switch and literal pair that specifies how DFTAdvisor creates scan out ports on modules. The valid literals are as follows: Share A literal specifying that DFTAdvisor may use an existing module output port on modules for scan out, if that port is directly connected to the scan out of a scan cell. This is the default. New A literal specifying that DFTAdvisor should always create a new output port for scan out. Note If you want DFTAdvisor to only create new scan output ports on the top-level module, use the -NEw_scan_po switch, instead of the -Output switch. -MOdule Norename | Rename An optional switch and literal pair that specifies how to name the modified module. The valid literals are as follows: Norename A literal specifying that DFTAdvisor should use the original module name, if it uses only one type of module modification, and that the original module is no longer used in the design. This is the default.
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Rename A literal specifying that DFTAdvisor should always rename a module if it modifies the module. -Verilog An optional switch that specifies to DFTAdvisor that the final output netlist format will be Verilog, so that DFTAdvisor knows to insert a buffer instance for any scan output pin in any module in the design hierarchy, if that pin also fans out as the modules functional output. Without this switch, DFTAdvisor uses the Verilog assign statement to generate this scan output signal from the functional output. However, some layout tools do not support the Verilog assign statement, thus the -Verilog switch is required so that DFTAdvisor will use a buffer instantiation and avoid using the assign statement. Before using this command and switch, you must have defined a buffer model with the Add Cell Models command or with a cell_type attribute. -Hierarchical {OFf | ON [-Tolerance integer_percent]} An optional switch and literal pair, with an associated optional switch and integer pair, that specify whether DFTAdvisor tries to insert the same scan chain segments into the identical sub-module instances in the design. DFTAdvisor considers the entire design hierarchy when performing the segmentation and therefore this functionality can be referred to as hierarchical scan chain segmentation. Having the same scan segments on the identical submodule instances allows them to share the same scan-inserted module definition in the scaninserted netlist which may yield a reduced netlist size. An allowable percentage variation from the ideal chain length (tolerance) helps in reaching this goal. The valid arguments are as follows: OFf A literal that specifies to not consider hierarchical scan chain segmentation. This is the invocation default. ON A literal that specifies for DFTAdvisor to perform hierarchical scan chain segmentation. The tool tries to insert the same scan chain segments into identical submodule instances in the design, so that the instances share the same scan-inserted module definition when the tool generates the scan-inserted netlist. The -Tolerance switch and integer pair can optionally be specified with this option. -Tolerance integer_percent A switch and integer pair that specifies the percentage deviation that DFTAdvisor can vary from the ideal chain length when creating the scan chains. A non-zero percentage allows DFTAdvisor to vary the chain lengths (shorter or longer), which helps in segmenting scan chains for the identical sub-modules in the design. However, this may also result in fewer than specified number of scan chains. This switch is optionally used when -Hierarchical is set to ON. integer_percent An integer percentage. The default value is 0, which causes DFTAdvisor to create chains with the ideal length.
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-NEw_scan_po An optional switch that specifies for DFTAdvisor to create new scan primary output pins even though existing functional outputs are available to use as scan outputs. The switch is a special case of the -Output switch used with New literal, as it performs new scan output port creation only on the top-level module, instead of all modules.
-Keep_original_net An optional switch that specifies for DFTAdvisor to insert a buffer in the scan path, between the last scan cell at the top-level and the top-level scan output pin, when the scan cell output has no connection to top-level but has a functional connection to other logic. The buffer insertion is done to prevent renaming the original net that the scan cell is connected to the other logic with. When this switch is not specified, DFTAdvisor renames the original net same as the primary output pin that it creates as scan output port.
Examples The following example identifies 50 percent of the scannable sequential instances during the Run command, and then uses the Insert Test Logic command to stitch them together into scan chains with a maximum length of 10 scan cells each:
add clocks 0 clock set system mode dft setup scan identification sequential atpg -percent 50 run insert test logic -scan on -max_length 10
The following example causes the insertion of three scan chains using hierarchical partitioning with a 5 percent tolerance:
insert test logic -clock merge -edge merge -number 3 -hierarchical on -tolerance 5
Related Commands Add Scan Instances Add Scan Pins Add Test Points Report Scan Chains Set Test Logic Setup Scan Identification Setup Scan Insertion Setup Test_point Identification Setup Test_point Insertion
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Command Dictionary Printenv
Printenv
Scope: All modes Usage PRIntenv Description Prints out the values of the UNIX variables in the environment. The DFTAdvisor Printenv command allows the UNIX printenv command to be available as a common DFT command, for convenience in displaying UNIX environment variables. UNIX environment variables are automatically available as variable references within DFTAdvisor. For information on how to define, reference, and report on a variables value, see the Report Variables command. Examples The following example prints out the values of the UNIX variables in the environment:
printenv
Related Commands Report Variables
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Command Dictionary Read Procfile
Read Procfile
Scope: All modes except Setup mode Usage REAd PRocfile proc_filename Description Reads the specified test procedure file. The Read Procfile command specifies for the tool to read the test procedure file. The tool merges the new procedure and timing data contained in the file with the existing data loaded from previously-read test procedure files. Information loaded with this command is used by the Write Atpg Setup command. Arguments proc_filename A required path and filename of the test procedure file to read. Examples The following example reads the test procedure file specified:
read procfile my_file.proc
Related Commands Add Scan Groups Report Procedure Report Timeplate Write Atpg Setup Write Procfile
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Command Dictionary Report Black Box
Report Black Box

Scope: All modes Usage REPort BLack Box -Instance [ins_pathname] | -Module [module_name] | -All | -Undefined [{> | >>} file_pathname] Description Displays information on blackboxes and undefined models. The Report Black Box command reports on the status of any instance- or module-based blackboxes, or undefined models that are not yet blackboxed. The report follows the following format.
MODULE: module_name (default tie value = 0|1|X|Z) SYSTEM: Inout|Output pin pin_name tied to 0|1|X|Z USER: Inout|Output pin pin_name tied to 0|1|X|Z INSTANCE: ins_name (default tie value = 0|1|X|Z) SYSTEM: Inout|Output pin pin_name tied to 0|1|X|Z USER: Inout|Output pin pin_name tied to 0|1|X|Z
For module-based blackboxes, the tool displays the string MODULE followed by the name of the module and the default tie value (0, 1, X, or Z). The tool then displays a list of module pins. For each pin, the tool displays either SYSTEM or USER followed by the direction type of the pin (Inout or Output), the name of the pin, and its tied value. SYSTEM declares that the pin is tied to the default value by the system, while USER declares that you explicitly tied the pin to the specified value. For instance-based blackboxes, the report replaces the string MODULE with INSTANCE to explicitly declare that it is an instance-based blackbox. Arguments -Instance [ins_name] A switch and optional string that specify for the tool to display information on instancebased blackboxes. If you do not supply an ins_name, DFTAdvisor displays information on all instance-based blackboxes. If you specify an instance pathname, it reports on that single, instance-based blackbox. -Module [module_name] A switch and optional string that specify for the tool to display information on modulebased blackboxes. If you do not supply a module_name, DFTAdvisor displays information on all module-based blackboxes. If you specify a module_name, it reports on that single, module-based blackbox. -All A switch that specifies for the tool to display information on all defined blackboxes and undefined models. This is the default.
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Command Dictionary Report Black Box
-Undefined A switch that specifies for the tool to display information on undefined models which have not yet been blackboxed. Use this switch to determine whether your design is complete, or is missing library models. If you intend to blackbox undefined models, this report allows you to verify that only the intended models are undefined.
Examples The following example defines module- and instance-based blackboxes, then reports on them.
add black box -module core -pin do1 0 -pin io1 1 add black box -instance core1 1 -pin do0 0 -pin io0 0 report black box -all MODULE: core (default tie value = X) SYSTEM: Output pin do0 tied to X USER: Output pin do1 tied to 0 SYSTEM: Inout pin io0 tied to X USER: Inout pin io1 tied to 1 INSTANCE: core1 (default tie value = 1) USER: Output pin do0 tied to 0 SYSTEM: Output pin do1 tied to 1 USER: Inout pin io0 tied to 0 SYSTEM: Inout pin io1 tied to 1
Related Commands Add Black Box Delete Black Box Report Tied Signals
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Command Dictionary Report Buffer Insertion
Report Buffer Insertion

Scope: All modes Usage REPort BUffer Insertion Description Displays a list of all the different scan test pins and the corresponding fanout limit. The Report Buffer Insertion command shows either the default setting (infinity) for each type of scan test pin or the new limit you set with the Add Buffer Insertion command. Examples The following example changes the fanout limit with the Add Buffer Insertion command, then reports the new setting; all the remaining settings are left at the default (infinity):
add buffer insertion 7 sen -model buf1a report buffer insertion scan_enable scan_clock test_enable test_clock scan_master_clock scan_slave_clock hold_enable 7 buf1a <infinity> <infinity> <infinity> <infinity> <infinity> <infinity>
Related Commands Add Buffer Insertion Delete Buffer Insertion
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Command Dictionary Report Cell Models
Report Cell Models

Scope: All modes Usage REPort CEll Models [-All | {-Type cell_model_type}] Description Displays a list of either all cell models or the DFT library models associated with the specified cell type. The Report Cell Models command displays the cell models that you either added with the Add Cell Models command, or described in the DFT library with the cell_type attribute. Arguments -All An optional switch that specifies to display all cell model definitions that you added with the Add Cell Models command. This is the default. -Type cell_model_type An optional switch and literal pair that specifies to display a listing of all the cell models of a particular type. The valid cell_model_types are as follows (with the minimum typing characters shown in uppercase): INV A literal that specifies a one-input inverter gate. And A literal that specifies a two-input AND gate. Buf A literal that specifies a one-input buffer gate. OR A literal that specifies a two-input OR gate. NAnd A literal that specifies a two-input NAND gate. NOr A literal that specifies a two-input NOR gate. Xor A literal that specifies an exclusive OR gate. INBuf A literal that specifies a primary input buffer gate that DFTAdvisor inserted whenever the tool added new input pins (such as the scan input or scan enable pins). OUtbuf A literal that specifies a primary output buffer gate that DFTAdvisor inserted whenever the tool added new output pins (such as the scan output pin). Mux A literal that specifies a 2-1 multiplexer. Scancell A literal that specifies a cell with four input pins (clock, data, scan in, and scan enable), clocked scan cell with four inputs (clock, data, scan clock, and scan enable), or LSSD scan cell with five inputs (clock, data, scan in, master clock, and slave clock). DFf A literal that specifies a D flip-flop with two input pins (clock and data). DLat A literal that specifies a D latch with two input pins (enable and data).
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Command Dictionary Report Cell Models
Examples The following example displays a list of all added cell models:
add clocks 0 clk set test Logic -set on -re on -clock on set system mode dft report dft check add cell models and2 -type and add cell models or2 -type or add cell models mux21h -type mux s a b add cell models nor2 -type nor report cell models insert test logic
Related Commands Add Cell Models Delete Cell Models Set Test Logic
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Command Dictionary Report Circuit Components
Report Circuit Components

Scope: All modes Usage REPort CIrcuit Components {[-INStances] {[-INDent | -Noindent] [-Level integer]}} | [-Modules] [{> | >>} file_pathname] Description Displays information about the components of the circuit as either modules or instances. Note Report Circuit Components reports only on components in the circuit; it does not report on library components. When you use the -Instances switch, the command prints out instance names, module names, and the level of hierarchy at which they exist. The default formatting is Indent. Note that the tool prints the string -top- as the name for the top-level instance. When you use the -Modules switch, the command prints out the module names and the number of instantiations of each module. Arguments -INStances [-INDent | -Noindent] [-Level integer] An optional switch with an optional switch and an optional switch and integer pair that specify to report on the module instances in the design, based on the design hierarchy. This is the invocation default. -INDent An optional switch that specifies to print the report using code-like indention. This switch works only with the -Instances switch. -Indent is the default. -Noindent An optional switch that specifies to print the report without using indention. This switch works only with the -Instances switch. -Level An optional switch and integer pair that specifies to filter the printing based on the hierarchy level specified by integer. This switch works only with the -Instances switch. integer An optional integer that specifies the hierarchy level at which you want the report to start. The report will show all instances whose level number is greater than integer; that is, levels that are at or lower in the hierarchy than integer. The default value for integer is 0, the top level. -Modules An optional switch that specifies to report on the modules, listing their names and the number of instantiations of each module in the design.
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Example 1 The following example displays a circuit component report, in indented format, of instances at and below level 0 in the hierarchy:
report circuit components -----------------------------------------------------------Output Format: InstanceName (ModuleName) [HierarchyLevel] ------------------------------------------------------------top- (m8051) [0] u10 (m3s018bo) [1] u11 (m3s019bo) [1] u5 (m3s006bo) [1] u4 (m3s005bo) [1] u3 (m3s004bo) [1] u14 (m3s025bo) [1] u13 (m3s023bo) [1] u9 (m3s015bo) [1] u4 (m3s016bo) [2] u3 (m3s016bo) [2] u2 (m3s016bo) [2] u1 (m3s016bo) [2] u12 (m3s020bo) [1] u1 (m3s014bo) [2] u7 (m3s008bo) [1] u2 (m3s039bo) [2] u1 (m3s009bo) [2] u6 (m3s007bo) [1] u2 (m3s003bo) [1] u15 (m3s028bo) [1] u8 (m3s010bo) [1] select_program_source_gt_301 (m3s010bo_DW01_cmp2_8_0) u2 (m3s013bo) [2] u1 (m3s011bo) [2] u1 (m3s001bo) [1]
[2]
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Example 2 The following example displays a circuit component report, in non-indented format, of instances at and below level 1 in the hierarchy:
report circuit components -instance -noindent -level 1 -----------------------------------------------------------Output Format: InstanceName (ModuleName) [HierarchyLevel] -----------------------------------------------------------u10 (m3s018bo) [1] u11 (m3s019bo) [1] u5 (m3s006bo) [1] u4 (m3s005bo) [1] u3 (m3s004bo) [1] u14 (m3s025bo) [1] u13 (m3s023bo) [1] u9 (m3s015bo) [1] u4 (m3s016bo) [2] u3 (m3s016bo) [2] u2 (m3s016bo) [2] u1 (m3s016bo) [2] u12 (m3s020bo) [1] u1 (m3s014bo) [2] u7 (m3s008bo) [1] u2 (m3s039bo) [2] u1 (m3s009bo) [2] u6 (m3s007bo) [1] u2 (m3s003bo) [1] u15 (m3s028bo) [1] u8 (m3s010bo) [1] select_program_source_gt_301 (m3s010bo_DW01_cmp2_8_0) [2] u2 (m3s013bo) [2] u1 (m3s011bo) [2] u1 (m3s001bo) [1]
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Command Dictionary Related Commands
Example 3 The following example displays a circuit component report of the designs modules, and the number of instantiations of each:
report circuit components -module ---------------------------------------------------Output Format: ModuleName [NumberOfinstantiations] ---------------------------------------------------m8051 [0] m3s028bo [1] m3s025bo [1] m3s023bo [1] m3s020bo [1] m3s014bo [1] m3s019bo [1] m3s018bo [1] m3s015bo [1] m3s016bo [4] m3s010bo [1] m3s010bo_DW01_cmp2_8_0 [1] m3s013bo [1] m3s011bo [1] m3s008bo [1] m3s039bo [1] m3s009bo [1] m3s007bo [1] m3s006bo [1] m3s005bo [1] m3s004bo [1] m3s003bo [1] m3s001bo [1]
Related Commands Echo
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Command Dictionary Report Clock Gating
Report Clock Gating

Scope: Setup mode Usage REPort CLock Gating [-LIbrary_model library_model_name] [-Module netlist_module_name] [-INStance pathname] [{> | >>} file_pathname] Description Reports the clock gating instances that were identified as having unconnected ports and were connected to either the scan enable signal or to a user-specified signal or, reports the unconnected ports of the specified clock gating cells only. Arguments -LIbrary_model library_model_name An optional switch and a repeatable string that specify the library model name(s) of the clock gating cell instances to be reported for unconnected ports to be connected to either the scan enable signal or the specified signals. -Module netlist_module_name An optional switch and a repeatable string that specify the netlist module name(s) of the clock gating cell instances to be reported for unconnected ports to be connected to the specified signals. -INstance pathname An optional switch and a repeatable string that specify the pathname(s) of the clock gating cell instances to be reported for unconnected ports to be connected to either the scan enable signal or the specified signals. > file_pathname An optional redirection operator and pathname pair, used at the end of the argument list, for creating or replacing the contents of file_pathname. >> file_pathname An optional redirection operator and pathname pair, used at the end of the argument list, for appending to the contents of file_pathname.
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Command Dictionary Report Clock Gating
Examples The following example connects the unconnected scan enable ports of specified clock gating instances. The first instance is connected to the sen1 pin, which drives the signal with the active state set to low. The next two instances are connected to the default scan enable signal, sen. The results of these commands are shown by the Report Clock Gating command output:
set scan enable sen setup clock gating -instance clkg1/clkg1/clkgLA -driver sen1 -active low setup clock gating -instance clkg3/clkg1/clkgLA clkg2/clkg1/clkgLA set system mode dft // Note: The following clock gating instances have unconnected ports that will be connected to a scan enable signal. ------------------------------------------------------------------------Clock Gating Unconnected Signal Instance Port Driver ------------------------------------------------------------------------clkg1/clkg1/clkgLA SE sen1 clkg2/clkg1/clkgLA SE sen clkg3/clkg1/clkgLA SE sen ------------------------------------------------------------------------....... insert test logic report clock gating -instance clkg1/clkg1/clkgLA clkg2/clkg1/clkgLA clkg3/clkg1/clkgLA ------------------------------------------------------------------------Clock Gating Unconnected Signal Instance Port Driver ------------------------------------------------------------------------clkg1/clkg1/clkgLA SE sen1 clkg2/clkg1/clkgLA SE sen clkg3/clkg1/clkgLA SE sen -------------------------------------------------------------------------
Related Topics Setup Clock Gating
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Command Dictionary Report Clock Groups
Report Clock Groups

Scope: Dft mode Usage REPort CLock Groups Description Displays a list of all clock group definitions. The Report Clock Groups command displays a list of all clock groups added with the Add Clock Groups command. Examples The following example displays a list of clock groups after they have been added to the clock list:
add clocks 1 clk1 clk2 clk3 add clocks 0 clr1 clr2 pre1 pre2 set system mode dft . . add clock groups group1 clk1 clr1 pre1 add clock groups group2 clk2 clr2 pre2 report clock groups group2: clk2 clr2 pre2 group1: clk1 clr1 pre1 all_clocks: clk3
Related Commands Add Clock Groups Delete Clock Groups
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Command Dictionary Report Clocks
Report Clocks
Scope: All modes Usage REPort CLocks [-Display {DEBug | DESign | DAta | ALl}] Description Displays a list of all clock definitions. The Report Clocks command displays a list of all clocks added with the Add Clocks command. Arguments -Display {DEBug | DESign | DAta | ALl} A switch and literal that displays the reported information graphically in the specified DFTVisualizer window(s). The choices are as follows: DEBug Debug window DESign Design window DAta Data window ALl A literal that displays the information in all of the preceding windows. See Using Tessent DFTVisualizer for more information. Examples The following example displays a list of clocks after they have been added to the clock list:
add clocks 1 clk1 add clocks 0 clk0 report clocks clk1, off_state 1 clk0, off_state 0
Related Commands Add Clocks Delete Clocks
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Command Dictionary Report Control Signals
Report Control Signals

Scope: Dft mode Usage REPort COntrol Signals {[-All] | {[pin_pathname] [-Clock] [-Set] [-Reset] [-Write] [-Read] [-Tristate_enable]} [-Verbose] [-NOSTABLE_High] [-NOSTABLE_Low] Description The Report Control Signals command displays the rules checking results for control signals consisting of clocks added with the Add Clocks command and pins identified for gating scannable memory elements with test logic. Arguments -All An optional switch that outputs all control signals to the report. Default setting. pin_pathname An optional, repeatable string that specifies the pathnames of control signals to report on. -Clock An optional switch that outputs clock control signals in the report. -Set An optional switch that reports on all set control signals. -Reset An optional switch that reports on all reset control signals. -Write An optional switch that reports on all write control signals. -Read An optional switch that reports on all read control signals. -Tristate_enable An optional switch that reports on all tristate enable signals. -Verbose An optional switch that includes all memory elements associated with each control signal in the report. -NOSTABLE_High An optional switch that disables the report on any stable-high memory elements. -NOSTABLE_Low An optional switch that disables the report on any stable-low memory elements.
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Command Dictionary Report Control Signals
Related Commands Add Clocks Delete Clocks Report Dft Check
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Command Dictionary Report Dft Check
Report Dft Check

Scope: Dft mode Usage REPort DFt Check [-All | instance_pathname] [-FUll | -Scannable | -Nonscannable | {-Defined {Scan | Nonscan} | -Identified | -Unidentified | {-RUle {S1 | S2 | S3 | S4}} | -Tristate | -RAm] [{> | >>} file_pathname] Description The Report Dft Check command generates scannability check information for all non-scan instances in the design, or within a specific hierarchical instance. The displayed or written report includes six columns of information as described here: The first column displays whether the DFT Rules Checker identified the non-scan instance as scannable or non-scannable. The second column displays whether the non-scan instance is unidentified, identified by the scan identification process, or defined as non-scannable or scannable with the Add Nonscan Instances and Add Scan Instances commands, respectively. The third column displays the clock that is associated with the non-scan instance, or displays Test-Logic to specify that test logic will be added to make the instance scannable. If the non-scan instance is identified as non-scannable, the third column displays the design rule ID number, where the non-scan instance failed the clock rules. The gate index number of the non-scannable instance is also shown, as well as the set, reset or clock primary inputs to the memory element that failed the rules checking. The fourth column displays the instance name of the non-scan instance. The fifth column displays the library model name associated with the instance. The sixth column displays Stable-high if the clock inputs of the non-scan instances are at a one-state, with respect to the clock primary inputs.
An example of the output of this command, along with additional information, is covered in Reporting Scannability Information in the Scan and ATPG Process Guide. Arguments -All An optional switch that specifies to display all non-scan instances for the entire design. This is the default. instance_pathname An optional string that specifies to report scannability information for the specified instance. If the instance pathname specifies a hierarchical instance, DFTAdvisor generates scannability information for all instances within that hierarchical block. If the instance
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pathname specifies a particular sequential instance, DFTAdvisor generates scannability information for only that instance. -Full An optional switch that specifies to display the full scannability check information for all non-scan instances. This is the default. -Scannable An optional switch that specifies to display the non-scan instances that DFTAdvisor has identified during the rules checking process to be scannable. -Nonscannable An optional switch that specifies to display the non-scan instances that DFTAdvisor has identified during the rules checking process to be non-scannable. -Defined Scan | Nonscan An optional switch and literal pair that specifies whether to display user-defined scan or non-scan instances. The valid literals are as follows: Scan A literal that specifies to display scan instances defined with the Add Scan Instances command. Nonscan A literal that specifies to display non-scan instances defined with the Add Nonscan Instances command. -Identified An optional switch that displays identified non-scan instances. -Unidentified An optional switch that displays unidentified non-scan instances. -RUle S1 | S2 | S3 | S4 An optional switch and literal that specifies which non-scannable cell violations to report. For more information on S1, S2, S3, and S4 rule violations, refer to Scanability Rules (S Rules) in the Tessent Common Resources Manual for ATPG Products. -Tristate An optional switch that displays the enable lines of tri-state gates connected to the outputs of memory elements. -RAm An optional switch that displays the RAM gates identified to be controllable through test logic insertion. > file_pathname An optional redirection operator and pathname pair, used at the end of the argument list that for creates or replaces the contents of file_pathname.
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>> file_pathname An optional redirection operator and pathname pair used at the end of the argument list to append to the contents of file_pathname.
Examples The following example displays the scannability check for all non-scan instances in the design:
add clocks 1 clk1 add clocks 0 clk0 set system mode dft report dft check SCANNABLE DEFINED-NONSCAN /CLK1 /U1 SCANNABLE IDENTIFIED /CLK1 /U2 SCANNABLE UNIDENTIFIED /CLK1 /U3 SCANNABLE DEFINED-SCAN /CLK1 /U4 SCANNABLE UNIDENTIFIED /CLK2 /U5 SCANNABLE IDENTIFIED /CLK2 /U6 NON-SCANNABLE UNIDENTIFIED S1 /U7 Clock #1: /CLK3 (11) Number of non-scannable instances fails on Number of instances found = 1 Number of instances reported = 1 FD1 FD1 FD1 FD1 FD1 FD1 FD2 (34) S1 rule = 1
Related Commands Echo Report DRC Rules Report Sequential Instances
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Command Dictionary Report DRC Rules
Report DRC Rules

Scope: All modes Usage REPort DRc Rules [-Fails_summary | -Summary | rule_id | rule_id-occurence# | -All_fails] [{> | >>} file_pathname]
C1 Usage:
REPort DRc Rules C1 [-EXcluded]

D5 Usage:
REPort DRc Rules D5 [ { [-TYpe {I0 | I1 | IX | T0 | T1 | TX | TLA}] [-NOType {I0 | I1 | IX | T0 | T1 | TX | TLA}] [-EDge_triggered | -LEvel_sensitive] } | -Summary] [{> | >>} file_pathname] Description Displays either a summary of DRC violations (fails) or violation occurrence message(s). The Report DRC Rules command displays data about design rules and DRC violations. It can display a report in one of two formats: Summary report Lists for each reported design rule, one line of data per rule, the current number of DRC violations (fails), the violation handling, and a brief description of the rule. Occurrence report Lists one or more violation occurrence messages that give details of specific DRC violations.
Table 2-4 summarizes the available information displays and the arguments you use to obtain them. Refer to the Arguments subsection for complete details about the arguments. Table 2-4. Available Information Displays and Arguments Desired Display Summary report Occurrence report Rules/Occurrences Covered Argument Design rules that resulted in violations (fails) during -Fails_summary DRC All design rules Specific rule, specific occurrence Specific rule, all occurrences All occurrences -Summary rule_id-occurence# rule_id -All_fails
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You can use the Set DRC Handling command to change the handling of the C (clock), A (RAM), D (data), P (procedure), T (trace), and E (extra) rules. For more information on the design rules, refer to the Design Rule Checking section in the Tessent Common Resources Manual for ATPG Products. Arguments -Fails_Summary A switch that specifies to display the following for each user-controllable rule that resulted in a violation (fail) during DRC:
o o o o
Rule identification (ID) Number of failures of the rule Current handling status of the rule Brief description of the rule
This is the command default. Note This switch does not display anything if there are no rule violations or the tool has not yet performed DRC. -Summary A switch that specifies to display the following for each user-controllable rule, whether or not it resulted in a violation (fail) during DRC:
o o o o
Rule identification (ID) Number of failures of the rule Current handling status of the rule Brief description of the rule
rule_id A repeatable string that specifies the identification literal (ID) of a particular design rule for which you want to display all violation occurrence messages. The design rule violations and their identification literals are divided into the following six groups: RAM, Clock, Data, Extra, Scannability, and Trace rules violation IDs. For a complete description of the RAM design rule IDs, refer to the RAM Rules section in the Tessent Common Resources Manual for ATPG Products. For a complete description of the Clock design rule IDs, refer to the Clock Rules section in the Tessent Common Resources Manual for ATPG Products. For a complete description of the Data design rule IDs, see the Scan Cell Data Rules section in the Tessent Common Resources Manual for ATPG Products.
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For a complete description of the Extra design rule IDs, refer to the Extra Rules section in the Tessent Common Resources Manual for ATPG Products. For a complete description of the Scannability design rule IDs, refer to Scanability Rules (S Rules) in the Tessent Common Resources Manual for ATPG Products. For a complete description of the Trace design rule IDs, refer to the Scan Chain Trace Rules section in the Tessent Common Resources Manual for ATPG Products.
rule_id-occurrence# A repeatable string that specifies the identification literal (ID) of a particular design rule and the violation occurrence for which you want to display the occurrence message. This argument must include the specific design rule ID (rule_id), the specific occurrence number of the violation, and the hyphen between them. For example, you can analyze the second violation occurrence of the C3 rule by specifying C3-2. The tool assigns numbers to occurrences of rule violations as it encounters them; you cannot change the number assigned to a specific occurrence.
-All_Fails A switch that specifies to display all occurrence messages for all occurrences of rule violations. The displayed information can be quite lengthy, as it is the same information you would get if you consecutively entered a report drc rules <rule_id> command for each rule that had a violation. Use this switch to output a report of all violation occurrences (most likely to a log file) for later analysis.
C1-Only Arguments
C1 A required literal that specifies reporting C1 DRC rule violations. -EXcluded An optional switch for use only with a C1 violation. Specifying this switch reports the C1 violations that have been excluded from the default C1 list because these C1 violations can be handled by the tool without causing potential mismatch.
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Command Dictionary Report DRC Rules D5-Only Arguments
-TYpe I0 | I1 | IX | T0 | T1 | TX | TLA An optional switch and repeatable literal that displays D5 occurrence messages for only the specified type(s) of non-scan sequential elements. The literal choices for the type of element are as follows (the term you will see in occurrence messages for each type is shown in parentheses): I0 If the element is at 0 at the beginning of the first capture cycle and may go to any state during capture. (INIT-0) I1 If the element is at 1 at the beginning of the first capture cycle and may go to any state during capture. (INIT-1) IX If the elements state is unknown at the beginning of the first capture cycle and may go to any state during capture. (INIT-X) T0 If the element is always at 0 during capture. (TIE-0) T1 If the element is always at 1 during capture. (TIE-1) TX If the element is always at an unknown state during capture. (TIE-X) TLA If the element is always transparent when its clock is at its off state. (TLA) Tip: Except for TLAs, you can also direct the tool to display information for only those D5 elements that are edge-triggered or level-sensitive. See the -Edge_triggered and -Level_sensitive switch descriptions for details.
-NOType I0 | I1 | IX | T0 | T1 | TX | TLA An optional switch and repeatable literal that specify not to display occurrence messages for the particular type(s) of D5 violations. See the description of the -Type switch for the meaning of the literal choices.
-EDge_triggered | -LEvel_sensitive Optional switches that specify to display D5 occurrence messages either for edge-triggered or level-sensitive elements only. The default (when neither option is specified) is to display information for both edge-triggered and level-sensitive elements.
Examples The following example changes the severity of the data rule 7 (D7) from a warning to an error, and also specifies execution of a full test generation analysis, when performing the rules checking for the clock (C) rules. Next, the example generates a display of a specific rule failure:
set drc handling d7 error atpg_analysis set system mode dft
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Command Dictionary Report DRC Rules //----------------------------------------------------------//Begin scan chain identification process, memory elements=8. //----------------------------------------------------------// Reading group test procedure file /user/design/tpf. // Simulating load/unload procedure in g1 test procedure file. // Chain = c1 successfully traced with scan_cells = 8. // Error: Flipflop /FF1 (103) has clock port set to stable high.(D7-1) // Error: Rules checking unsuccessfule, cannot exit SETUP mode. report drc rules d7-1 //Error: Flipflop /I$3
(16) has clock port set to stable high (D7-1)
Related Commands Echo Set DRC Handling
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Command Dictionary Report Environment
Report Environment
Scope: All modes Usage REPort ENvironment [{> | >>} file_pathname] Description Displays the current values of all the set commands and the default names of the scan type pins. Using the Report Environment command immediately after invocation, displays all of the default values of the set commands. Arguments > file_pathname An optional redirection operator and pathname pair, used at the end of the argument list, for creating or replacing the contents of file_pathname. >> file_pathname An optional redirection operator and pathname pair, used at the end of the argument list, for appending to the contents of file_pathname. Examples The following example reports the DFTAdvisor invocation defaults:
report environment Top Module = /designs/dft/test_design Gate Level = design Gate Report = normal Net Resolution = wire System Mode = setup Tied Signal = x Dofile Abort = on Trace Report = off Scan type = mux_scan Identification Type = sequential:on scan_sequential:off partition_scan:off full_scan:off test_point:off Identification Model = clock:original disturb:on Scan Identification = automatic Internal Full backtrack=30 cycle=16 time=100 control_coverage = 100 observe_coverage = 100 min_detection = 1 Fault Sampling = 100% Scan-in Naming = prefix:scan_in initial:1 modifier:1 suffix: Scan-out Naming = prefix:scan_out initial:1 modifier:1 suffix: Test Enable Name = test_en active = high Test Clock Name = test_clk Scan Enable Name (Core)= scan_en Scan Enable Name (Input wrapper chains)= scan_en_in Scan Enable Name (Output wrapper chains)= scan_en_out
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Command Dictionary Report Environment Scan Clock Name = scan_clk Scan Master Clock Name = scan_mclk Scan Slave Clock Name = scan_sclk Hold Enable Name = hold_en Control Input Name = test_cntl Observe Output Name = test_obs Test Logic = set:off reset:off clock:off tristate:off ram:off Screen Display = on lockup cell = off nolast
Related Commands Echo Any of the Set commands
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Command Dictionary Report Feedback Paths
Report Feedback Paths

Scope: Dft mode Prerequisites: Tool must have performed the learning process, which happens immediately after flattening a design to the simulation model. Flattening occurs when you first attempt to exit Setup mode. Usage REPort FEedback Paths [-All | loop_id#] [-Display {DEBug | DESign | DAta | ALl}] [{> | >>} file_pathname] Description Displays a textual report of the currently identified feedback paths. The Report Feedback Paths command displays any feedback paths the tool identified during the last circuit learning process. By default, the command displays all currently identified feedback paths and their identification numbers. Issuing the command with the identification numbers of specific paths of interest will limit the display to just those paths. Note Feedback paths include, by default, any duplicated gates.
Arguments -ALl An optional switch that specifies to report all currently identified feedback paths. This is the default. loop_id# An optional, repeatable, non-negative integer that specifies the identification number of a particular feedback path to report. The tool assigns the numbers consecutively, starting with 0. -Display {DEBug | DESign | DAta | ALl} A switch and literal that displays the reported information graphically in the specified DFTVisualizer window(s). The choices are as follows: DEBug Debug window DESign Design window DAta Data window ALl A literal that displays the information in all of the preceding windows. See Using Tessent DFTVisualizer for more information.
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Command Dictionary Report Feedback Paths
> file_pathname An optional redirection operator and pathname pair for creating or replacing the contents of file_pathname.
>> file_pathname An optional redirection operator and pathname pair for appending to the contents of file_pathname.
Examples The following example leaves the Setup mode (which, among other things, flattens the simulation model and performs the learning process), and displays the identification numbers of any learned feedback paths:
set system mode dft report feedback paths Loop#=0, INV PBUS ZVAL INV TIEX Loop#=1, INV PBUS ZVAL INV TIEX feedback_buffer=26, #gates_in_network=5 /I_956__I_582/ (51) /I_956__I_582/N1/ (96) /I_956__I_582/N1/ (101) /I_956__I_582/ (106) /I_956__I_582/ (26) feedback_buffer=27, #gates_in_network=5 /I_962__I_582/ (52) /I_962__I_582/N1/ (95) /I_962__I_582/N1/ (100) /I_962__I_582/ (105) /I_962__I_582/ (27)
Related Commands Report Loops
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Command Dictionary Report Flatten Rules
Report Flatten Rules

Scope: All modes Usage REPort FLatten Rules [rule_id [{occurence_id | -Verbose}]] [{> | >>} file_pathname] Description Displays either a summary of all the flattening rule violations or the data for a specific violation. The Report Flatten Rules command displays the following information for a specific violation: Rule identification number Current number of rule failures Violation handling
You can use the Set Flatten Handling command to change the handling of the net, pin, and gate flattening rules. Arguments rule_id A literal that specifies the flattening rule violation for which you want to display information. The flattening rule violations and their identification literals are divided into the following three groups: net, pin, and gate rules. Net flattening violations are described in sections FN1 through FN9 of the Tessent Common Resources Manual for ATPG Products. Pin flattening violations are described in sections FP1 through FP13 of the Tessent Common Resources Manual for ATPG Products. Gate flattening violations are described in sections FG1 through FG8 of the Tessent Common Resources Manual for ATPG Products.
occurence_id A literal that specifies the identification of the exact flattening rule violation (the occurrence) for which you want to display information. For example, you can analyze the second occurrence of the FG4 rule by specifying the rule_id and the occurence_id, FG4 2. The tool assigns the occurrences of the rules violations as it encounters them; you cannot change either the rule identification number or the ordering of the specific violations.
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Command Dictionary Report Flatten Rules
-Verbose A switch that displays the following for each flattening rule:
o o o o
Rule identification number Number of failures of each rule Current handling status of that rule Brief description of that rule
Example The following example shows the summary information of the FG3 rule:
report flatten rules fg3 // FG3: fails=2 handling=warning/noverbose
Related Commands Set Flatten Handling
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Command Dictionary Report Gates
Report Gates
Scope: All modes Prerequisites: The netlist must already have been flattened before you can use this command in either Setup or Dft mode. Netlist flattening happens when you first attempt to exit Setup mode. The next time you return to Setup mode, you can use the command. Usage REPort GAtes {gate_id# | pin_or_net_pathname | instance_name} | {-Type gate_type} Description The Report Gates command displays the netlist information for the specified design-level or primitive-level gates. You can specify the gate by its gate index number, a pathname of a pin connected to a gate, an instance name (design level only), a gate type, or a net pathname. You can specify a design cell by a pathname of a pin connected to the design cell. If you use a gate index number or gate type, the primitive-level is reported. The pin_or_net_pathname and instance_name arguments support regular expressions, which may include any number of * or ? wildcard characters embedded in the pathname string. The * character matches any sequence of characters (including none) in a name, and the ? character matches any single character. If a wildcard name is specified, the command will search for matching instance names from the top library cell level, down to the primitive gates. The format for the design level is:
instance_name cell_type input_pin_name I (data) ... output_pin_name 0 (data) ... pin_pathname... pin_pathname...
The format for the primitive level is:

instance_name (gate_ID#) gate_type input_pin_name I (data) gate_ID#-pin_pathname... ... output_pin_name O (data) gate_ID#-pin_pathname... ...
The list associated with the input and output pin names indicates the pins to which they are connected. For the primitive-level, this also includes the gate index number of the connecting gate and only includes the pin pathname if one exists at that point. There is a limitation on reporting gates at the design-level. If some circuitry inside the design cell is completely isolated from other circuitry, the command only reports the circuitry associated with the pin pathname. You can change the output of the Report Gates command by using the Set Gate Report command. Note You must flatten the netlist before issuing this command.
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Reporting on the First Input of a Gate

Report Gates provides a shortcut to display data on the gate connected to the first input of the previously reported gate. This lets you quickly and easily trace backward through circuitry. To use Report Gates in this manner, first report on a specific gate and then enter:
SETUP> b
The following example shows how to use Report Gate and B commands to trace backward through the first input of the previously reported gate.
SETUP> rep gate 26 // /u1/inst__565_ff_d_1__13 (26) // "I0" I 269// "OUT" O 268- 75SETUP> b // // // // // // // // BUF
/u1/inst__565_ff_d_1__13 (269) LA "S" I 14"R" I 145SCLK I 4-/clk D I 265-/u1/_g32/X ACLK I 2-/scan_mclk SDI I 20-/u1/inst__565_ff_d_0__dff/Q2 "OUT" O 26- 27-
SETUP> b // // /u1/inst__565_ff_d_1__13 (14) "OUT" O 269- 268TIE0
Reporting on the First Fanout of a Gate

Similar to tracing backward through circuitry, you can also use a shortcut to trace forward through the first fanout of the previously reported gate. To use Report Gates in this manner, first report on a specific gate, and then enter:
SETUP> f
The following example shows how to use Report Gate and F commands to trace forward through the first fanout of the previously reported gate.
SETUP> rep ga 269 // /u1/inst__565_ff_d_1__13 (269) LA // "S" I 14// "R" I 145// SCLK I 4-/clk // D I 265-/u1/_g32/X // ACLK I 2-/scan_mclk // SDI I 20-/u1/inst__565_ff_d_0__dff/Q2 // "OUT" O 26- 27SETUP> f // /u1/inst__565_ff_d_1__13 (26) BUF
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Command Dictionary Report Gates // "I0" // "OUT" SETUP> f // // // // // // I O 269268-
75LA
/u1/inst__565_ff_d_1__13 (268) "S" I 14"R" I 145BCLK I 1-/scan_sclk "D0" I 26"OUT" O 24- 25-
Arguments gate_id# A repeatable integer that specifies the gate identification numbers of the objects for which you want to display gate information. The value of the gate_id# argument is the unique identification number that DFTAdvisor automatically assigns to every gate within the design during the model flattening process. pin_or_net_pathname A repeatable string that specifies the pathnames of pins or nets in the design netlist. You may use wildcard characters to match multiple pin or net pathnames. For a hierarchical pathname, the display will include information describing how that pathname maps to the driving design level pin(s) and gate(s) for which data is displayed. instance_name A repeatable string that specifies the hierarchical pathname of an instance of a library cell within the design. If a valid library instance pathname is given when in primitive level, all pins on that library cell are reported. When in primitive level, instance_name may also be the pathname of a primitive instance. -Type gate_type A repeatable switch and name pair that specifies the gate types for which you want to display the gate information. The supported gate_types are listed in Table 2-5. Table 2-5. Report Gate Types gate_type BUF INV AND NAND OR NOR XOR XNOR Description buffer inverter and inverted and or inverted or exclusive-or inverted exclusive-or
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Table 2-5. Report Gate Types (cont.) gate_type DFF LA PI PO TIE0 TIE1 TIEX TIEZ TLA TSH TSL BUS Z2X WIRE MUX RAM ROM XDET ZDET Examples The following example displays the simulated values of the gate and its inputs.
SETUP> set system mode dft DFT> set gate report error_pattern DFT> set gate level primitive DFT> report gates i_1006/o // // // // /P2.13P (20) NAND A I 10-/LD.1 B I 7-/M1.1 Z O 30-/P2.2P/S
Description D flip-flop, same as _dff library primitive latch, same as _dlat library primitive primary input primary output tied low tied high tied unknown tied high impedance transparent latch tri-state driver, first input is active high enable line tri-state driver, first input is active low enable line tri-state bus Z converter gate, converts Z to X undetermined wired gate 2-way multiplexor, first line is select line random access memory read only memory X detector, gives 1 when input is X Z detector, gives 1 when input is Z
The gate report for the design level may look like the following:
// // // // /P2.13P ND2 A I /LD.1 B I /M1.1 Z O /P2.2P/S
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The next example demonstrates the use of wildcards:

ATPG> report gates /xscan_0_0_cch_scan_32x/ix15* // // // // // // // // /xscan_0_0_cch_scan_32x/ix151 NOR2XL A I /myop1<0> [1] B I /myop2[1] Y O /xscan_0_0_cch_scan_32x/sum_add_0_ix27/A0 /xscan_0_0_cch_scan_32x/ix153 NAND2X1 A I /myop1<0> [0] B I /myop2[0] Y O /xscan_0_0_cch_scan_32x/sum_add_0_ix1/A \ /xscan_0_0_cch_scan_32x/ sum_add_0_ix23/B \ /xscan_0_0_cch_scan_32x/sum_add_0_ix27/A1 /xscan_0_0_cch_scan_32x/ix155 NAND2X1 A I /myop1<0> [1] B I /myop2[1] Y O /xscan_0_0_cch_scan_32x/ix166/B0 \ /xscan_0_0_cch_scan_32x/ sum_add_0_ix27/B0 /xscan_0_0_cch_scan_32x/ix157 NAND2X1 A I /myop1<0> [3] B I /myop2[3] Y O /xscan_0_0_cch_scan_32x/ix174/B0 \ /xscan_0_0_cch_scan_32x/ sum_add_0_ix55/B0
// // // // // // // //
ATPG> rep ga /xscan_0_0_cch_scan_32x/ix159 // // // // /xscan_0_0_cch_scan_32x/ix159 NAND2X1 A I /myop1<0> [5] B I /myop2[5] Y O /xscan_0_0_cch_scan_32x/ix188/B0 \ /xscan_0_0_cch_scan_32x/ sum_add_0_ix83/B0
ATPG> set gate level primitive ATPG> report gates /xscan_0_0_cch_scan_32x/ix157 // // // // // // // // // // // // /xscan_0_0_cch_scan_32x/ix157 (43) NAND A I 7-/myop1<0> [3] B I 17-/myop2[3] Y O 60-/xscan_0_0_cch_scan_32x/ix174/B0 \ 75-/xscan_0_0_cch_scan_32x/ sum_add_0_ix55/B0 /xscan_0_0_cch_scan_32x/ix157 (43) NAND A I 7-/myop1<0> [3] B I 17-/myop2[3] Y O 60-/xscan_0_0_cch_scan_32x/ix174/B0 \ 75-/xscan_0_0_cch_scan_32x/ sum_add_0_ix55/B0 /xscan_0_0_cch_scan_32x/ix157 (43) NAND A I 7-/myop1<0> [3] B I 17-/myop2[3] Y O 60-/xscan_0_0_cch_scan_32x/ix174/B0 \ 75-/xscan_0_0_cch_scan_32x/ sum_add_0_ix55/B0
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The next example demonstrates how the output report will change if the input pathname is a hierarchical pin or net. In this case an additional line is output at the top of the report, indicating the mapping that was found:
ATPG> set gate level design ATPG> report gate /sub3/in2 // Hierarchical pin /sub3/in2 maps to /sub1/gate4/Y // /sub1/gate4 nand02 // A1 I /in1 // A0 I /sub1/gate2/Y // Y O /sub3/gate1/A1 /sub3/micro1/gate1/A1 /sub2/gate3/A1 // /sub3/gate3/A1 /sub3/micro1/gate2/A1 /sub2/gate1/A1 ATPG> report gate /w2 // Hierarchical net /w2 maps to /sub1/gate4/Y // /sub1/gate4 nand02 // A1 I /in1 // A0 I /sub1/gate2/Y // Y O /sub3/gate1/A1 /sub3/micro1/gate1/A1 /sub2/gate3/A1 // /sub3/gate3/A1 /sub3/micro1/gate2/A1 /sub2/gate1/A1
Related Commands Set Gate Level Set Gate Report
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Command Dictionary Report Loops
Report Loops
Scope: Dft mode Usage REPort LOops [-All | loop_id#] [-Display {DESign | DAta}] [{> | >>} file_pathname] Description Displays information about circuit loops. The Report Loops command displays information about currently identified loops in the circuit. For each loop, the report indicates whether the loop was broken by duplication. Loops that are not broken by duplication are shown as being broken by a constant value, which means the loop is either a coupling loop or has a single multiple fanout gate. The report also includes the pin pathname and gate type of each gate in each loop. You can write the loops report information to a file by using the commands redirection operators or the Write Loops command. Arguments -ALl An optional switch that specifies to report all the loops in the circuit. This is the default. loop_id# An optional, repeatable, positive integer that specifies the identification number of a particular loop to report. The tool assigns loop identification numbers consecutively, starting with 1. -Display {DESign | DAta} A switch and literal that displays the reported information graphically in the specified DFTVisualizer window(s). The choices are as follows: DESign Design window DAta Data window See Using Tessent DFTVisualizer for more information. > file_pathname An optional redirection operator and pathname pair for creating or replacing the contents of file_pathname. >> file_pathname An optional redirection operator and pathname pair for appending to the contents of file_pathname.
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Command Dictionary Report Loops
Examples The following example displays a list of all the loops in the circuit:
set system mode dft report loops Loop = 1: not_duplicated (coupling loop) my_design/my_minibus (SBUS) my_design/PAD (BUF) my_design/my_minibus (Z2X) Loop = 2: not_duplicated (coupling loop) ... Loop = 8: not_duplicated (single multiple fanout) my_design/al/pl/padx (BUF) my_design/al/pl/pad (BUF) my_design/pad (WIRE)
The next example displays loop 8 only:

report loops 8 Loop = 8: not_duplicated (single multiple fanout) my_design/al/pl/padx (BUF) my_design/al/pl/pad (BUF) my_design/pad (WIRE)
The next example writes the display information for loop 8 to a new file named my_loop_file:
report loops 8 > my_loop_file ... writing to file my_loop_file
Related Commands Report Feedback Paths Write Loops
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Command Dictionary Report Mapping Definition
Report Mapping Definition

Scope: Setup and DFT modes Usage REPort MApping Definition -All | {object_name [-Instance | -Module] [-Nonscan_model nonscan_model_name] [-Scan_model scan_model_name] [-Output scan_ouput_pin_name]} [-Filename filename [-Replace]] Description Reports the non-scan to scan model mapping defined in the design. The Report Mapping Definition command reports the mapping of non-scan models to scan models. You can report the scan and output mapping for an individual instance, all instances under a hierarchical instance, all instances in all occurrences of a module in the design, all occurrences of the model in the entire design, or the entire design. The report is always displayed in the transcript. You can optionally write it to a file using the -Filename switch. Arguments -All A switch that specifies to report all scan and output mapping in the entire design. object_name A string that specifies the name of the non-scan model you want to report on. You can also specify an instance, hierarchical instance, module, or scan model.
o
If this argument is the name of an instance or hierarchical instance, the -Instance switch is required, and you can optionally specify the model with the -Nonscan_model or -Scan_model switch. If this argument is the name of a module, then the -Module switch is required, and you can optionally specify the model with the -Nonscan_model or -Scan_model switch. If this argument is a scan model, then the -Output switch is required. Because you specified a scan model, you can only report the scan output pin mapping.
o
If you specify -Instance and the instance is primitive, then it reports only the named instance. If you specify -Instance and the instance is hierarchical, then it reports all instances under that instance. Optionally, you can constrain the report to matching the -Nonscan_model or (for output mapping) matching the -Scan_model.
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Command Dictionary Report Mapping Definition o
If you specify -Module, then for all occurrences of that module, it reports all instances within that module. Optionally, you can constrain the report to matching the -Nonscan_model or (for output mapping) matching the -Scan_model.
-Nonscan_model nonscan_model_name A switch and string pair that specifies the name of the non-scan model that you want to report on. This argument is only required if you specify -Instance or -Module switch and want to constrain the report to objects matching the non-scan model; otherwise, you can specify the non-scan model in the object_name argument.
-Scan_model scan_model_name A switch and string pair that specifies the name of the scan model to report on. This argument is required when you want to further constrain the report, except when you are only reporting the mapping of the scan output pin and specify the scan model in the object_name argument.
-Output [scan_ouput_pin_name] An optional switch and string pair that specifies the name of the scan output pin. You can use this to constrain the report. Specifying just the -Output switch reports all mapped scan output pins for the specified scan model, while specifying the switch with a pin name, reports the mapping for only scan models that use that pin for the scan output.
-Filename filename [-Replace] An optional switch and string that specifies that DFTAdvisor writes the scan mapping report to a file. The -Replace switch specifies that the file should be overwritten if it already exists.
Examples The following example reports the scan and output mapping for all occurrences of the fd1 nonscan model in the design:
report mapping definition fd1
The following example reports the mapping for each occurrence of the fd1 non-scan model mapped to the fd1s scan model with the scan output pin mapped to qn:
report mapping definition fd1 -scan_model fd1s -output qn
The following example reports the mapping for each occurrence of the fd1s scan model in the design:
report mapping definition fd1s -output
The following example reports the mapping for all instances under the hierarchical instance /top/counter1:
report mapping definition /top/counter1 -instance
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Command Dictionary Report Mapping Definition
The following example reports the mapping for each occurrence of the fd1s scan model with the scan output pin mapped to qn for all matching instances in the counter module and for all occurrences of that module in the design:
report mapping definition counter -module -scan_model fd1s -output qn
Related Commands Add Mapping Definition Delete Mapping Definition
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Command Dictionary Report Nofaults
Report Nofaults
Scope: All modes Usage REPort NOfaults {pathname | -All} [-Instance] [-Stuck_at {01 | 0 | 1}] [{> | >>} file_pathname] Description Displays the no-fault settings for the specified pin or instance pathnames. The Report Nofaults command displays for pin pathnames or pin names of instances the nofault settings that you previously specified with the Add Nofaults command. Arguments pathname A repeatable string that specifies the pin pathnames or the instance pathnames for which you want to display the nofault settings. If you specify an instance pathname, you must also specify the -Instance switch. -All A switch that specifies to display the nofault settings on either all pin pathnames or, if you also specify the -Instance switch, all pin names of instances. -Instance An optional switch that specifies that the pathname or -All argument indicates instance pathnames. -Stuck_at 01 | 0 | 1 An optional switch and literal pair that specifies the stuck-at nofault settings that you want to display. The valid stuck-at literals are as follows: 01 A literal that specifies to display both the stuck-at-0 and stuck-at-1 nofault settings. This is the default. 0 A literal that specifies to only display the stuck-at-0 nofault settings. 1 A literal that specifies to only display the stuck-at-1 nofault settings. > file_pathname An optional redirection operator and pathname pair, used at the end of the argument list, for creating or replacing the contents of file_pathname. >> file_pathname An optional redirection operator and pathname pair, used at the end of the argument list, for appending to the contents of file_pathname.
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Command Dictionary Report Nofaults
Examples The following example displays all pin names of the instances that have the nofault settings:
add nofaults i_1006 i_1007 i_1008 -instance report nofaults
Related Commands Add Nofaults Delete Nofaults
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Command Dictionary Report Nonscan Models
Report Nonscan Models

Scope: All modes Usage REPort NONscan Models [-Class {Full | System | User}] Description Displays the sequential non-scan model list. The Report Nonscan Models command displays sequential models that you added by using the Add Nonscan Models command, or that have the Dont_touch property in a Genie netlist. Arguments -Class Full | System | User An optional switch and literal pair that specifies the source (or class) of the sequential nonscan models that you want to display. The valid literals are as follows: Full A literal that specifies to display all the non-scan sequential models in the user and system class. This is the default. User A literal that specifies to only display the non-scan sequential models that are the result of the Add Nonscan Models command. System A literal that specifies to only display the non-scan sequential models that are a result of the Genie netlist containing the Dont_touch property. Examples The following example displays all sequential non-scan models from the non-scan model list:
set system mode dft add nonscan models d_flip_flop1 d_flip_flop2 report nonscan models
Related Commands Add Nonscan Models Delete Nonscan Models
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Command Dictionary Report Notest Points
Report Notest Points

Scope: Setup and Dft modes Usage REPort Notest Points [-Paths] [-Observe_scan_cell] Description Displays all the circuit points for which you do not want DFTAdvisor to insert controllability and observability. The Report Notest Points command displays the circuit points added using the Add Notest Points command and which therefore, DFTAdvisor cannot use for testability insertion. You can also list the critical path definitions that added notest points by using the -Paths switch, and list scan cells that are excluded from being used as observation scan cells by using the -Observe_scan_cell switch. Arguments -Paths An optional switch that displays the definitions for all currently loaded critical paths that have marked notest points. If this switch is not specified, the tool reports only the resulting notest points. -Observe_scan_cell An optional switch that specifies to list the instances that cannot be used as an observation scan cell. Examples The following example displays the list of all circuit points that DFTAdvisor cannot use for testability insertion:
set system mode dft add notest points tr_io add notest points ts_i report notest points
Related Commands Add Notest Points Delete Notest Points
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Command Dictionary Report Output Masks
Report Output Masks

Scope: All modes Usage REPort OUtput Masks Description Displays a list of the currently masked primary output pins. The Report Output Masks command displays the primary output pins that you previously masked by using the Add Output Masks command. When you mask a primary output pin, you inform DFTAdvisor to mark that pin as an invalid observation point during the scan cell identification process. DFTAdvisor uses all unmasked primary output pins as possible observation points to which the effects of all faults propagate for detection. Examples The following example masks two primary outputs and then displays the results:
add output masks q1 -hold1 add output masks qb1 -hold 0 report output masks q1 hold1 qb1 hold0
Related Commands Add Output Masks Analyze Output Observe Delete Output Masks Setup Output Masks
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Command Dictionary Report Wrapper Cells
Report Wrapper Cells

Scope: All Usage REPort WRapper Cells [-Summary | -Verbose] Arguments -Summary An optional switch. For information about this switch, see the following Description. -Verbose An optional switch. For information about this switch, see the following Description. Description Reports information about the identified wrapper cells for each I/O port subjected to wrapper cell identification. If no arguments are specified, the following information is reported for each I/O: Primary I/O port name and its direction (Input or Output). Maximum number of combinational logic levels between the I/O and the sequential cells identified for this I/O. Total number of sequential cells identified for this I/O. Wrapper cells identified. Whether this I/O was subject to the I/O Registration. If -Verbose is specified, in addition to the above information, the following is reported: Identified wrapper cell path names for each I/O that succeeded the identification or new cell for the I/Os that failed wrapper cell identification and are subject to I/O registration. Both the directly-identified and feedback-identified wrapper cells. This information is only reported if the Setup Wrapper Chains command has either the -allow_internal_feedback or -test_points option specified. Identified internal feedback cells are reported as such with the (internal feedback) notation. I/Os that failed the wrapper cell identification and the reason for the failure. Total number of internal feedback gates between the directly-identified wrapper cells and internal-feedback wrapper cells. This information is only reported if the Setup Wrapper Chains command has either the -allow_internal_feedback or -test_points switch specified. Wrapper chain type indicates whether the corresponding identified wrapper cell is part of the Input or Output wrapper chain.
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Clocks controlling both the identified wrapper cells and wrapper cells to be added. If -Summary is specified, the following information is reported: Total number of primary inputs. Total number of primary outputs. Total number of identified wrapper cells. Total number of added wrapper cells. Total number of design gates between the newly added wrapper cells and the logic that would have terminated the forward/backward tracing from each PI/PO during wrapper cells identification. Total number of design gates between all PI/POs for which the wrapper cells identification has succeeded, and the corresponding identified wrapper cells. Example 1 The following example shows the output generated when the Report Wrapper Cells command is executed with the -Verbose switch and neither the -allow_internal_feedback or -test_points switch is specified for the Setup Wrapper Chains command.
report wrapper cells -Verbose
--------------------------------------------------------------------------------------------------------Primary I/O Max Logic # Wrapper Cells Wrapper Wrapper Clock New Reason For Port Level Identified Cells Chain Registration Failed [1/32] [256/256] Identified Type Cell Added Identification --------------------------------------------------------------------------------------------------------in2 (I) 1 2 flop3 Input clk No -flop4 Input clk in1 (I) 0 2 flop1 Input clk No -flop2 Input clk in3 (I) 0 0 new cell Input clk Yes Max Logic Level in4 (I) 0 0 new cell Input clk Yes Combin. Logic Only in5 (I) 0 0 new cell Input clk Yes Max Logic Level in6 (I) 0 0 new cell Input clk Yes Combin. Logic Only out1 (O) 0 0 new cell Output test_clk Yes Input Wrapper Cell out2 (O) 0 0 new cell Output test_clk Yes Combin. Logic Only ---------------------------------------------------------------------------------------------------------
Example 2 The following example shows the output generated when the Report Wrapper Cells command is executed with the -Verbose switch when the -test_points option switch is specified for the Setup Wrapper Chains command.
--------------------------------------------------------------------------------------------------------Primary I/O Max Logic #Wrapper Cells #Internal Wrapper Wrapper Clock New Port Level (Direct/Internal-Feedback)Feedback Cells Chain Regist [32/32] Identified [256/256] Gates Identified Type Cell Added --------------------------------------------------------------------------------------------------------o[1] (O) 2 3 d7 Output clk No d8 Output clk d9 Output clk o[2] (O) 0 1 d9 Output clk No i[3] (I) 3 3/3 4 d2 Input clk No d3 Input clk d10 Input clk i[2] (I) 2 1/2 2 d1 Input clk No ---------------------------------------------------------------------------------------------------------
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Example 3 The following example shows the output generated when the Report Wrapper Cells command is executed without the -Verbose switch when the -test_points option switch is specified for the Setup Wrapper Chains command.
report wrapper cells
-----------------------------------------------------------------Primary I/O Max Logic # Wrapper Cells New Port Level Identified Registration [32/32] [256/256] Cell Added -----------------------------------------------------------------o[1] (O) 2 3 No o[2] (O) 0 1 No i[3] (I) 3 3 No i[2] (I) 2 1 No ------------------------------------------------------------------
Example 4 The following example shows the output generated when the Report Wrapper Cells command is executed with the -Verbose switch when the -allow_internal_feedback option switch is specified for the Setup Wrapper Chains command.
Primary I/O Port Max Logic #Wrapper Cells Internal Wrapper Wrapper Clock New Reason Level (Dir/Int-Feedback) Feedback Cells Chain Registr. Failed [32/32] Identified[256/256]Gates Identified Type Cell Added Ident. --------------------------------------------------------------------------------------------------------o[1] (O) 0 1 d2 Output clk No -i[2] (I) 2 1/2 2 d3 Input clk No -d2(int feedb) Output clk d4(int feedb) Output clk i[1] (I) 1 1/1 1 d1 Input clk No -d2(int feedb) Output clk ---------------------------------------------------------------------------------------------------------
Related Commands Setup Registered IO Setup Scan Identification Setup Wrapper Chains
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Command Dictionary Report Pin Constraints
Report Pin Constraints

Scope: All modes Usage REPort PIn Constraints [-All | primary_input_pin] [-Display {DEBug | DESign | DAta | ALl}] Description Displays the pin constraints of the primary inputs. The Report Pin Constraints command displays the pin constraints that you previously added to the primary inputs with the Add Pin Constraints command. You can change the constant value constraints of the primary inputs by using the Add Pin Constraints or Setup Pin Constraints commands. Note The information this command reports has effects on other commands that relate to fault simulation, such as simulation-based test point selection. Arguments -All An optional switch that specifies to display the current constraints for all primary input pins. This is the default. primary_input_pin An optional repeatable string that specifies a list of primary input pins whose constraints you want to display. -Display {DEBug | DESign | DAta | ALl} A switch and literal that displays the reported information graphically in the specified DFTVisualizer window(s). The choices are as follows: DEBug Debug window DESign Design window DAta Data window ALl A literal that displays the information in all of the preceding windows. See Using Tessent DFTVisualizer for more information. Examples The following example displays the cycle behavior constraints of all primary inputs.
add pin constraints ph1 c0 add pin constraints ph2 c1 report pin constraints -all
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Command Dictionary Report Pin Constraints
Related Commands Add Pin Constraints Delete Pin Constraints Setup Pin Constraints Setup Scan Identification
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Command Dictionary Report Pin Equivalences
Report Pin Equivalences

Scope: All modes Usage REPort PIn Equivalences Description Displays the pin equivalences of the primary inputs. The Report Pin Equivalences command displays a list of primary inputs, which you previously restricted to be at equivalent or complementary values, by using the Add Pin Equivalences command. Note The information this command reports has effects on other commands that relate to fault simulation, such as simulation-based test point selection. Examples The following example displays all pin equivalences that have been added to the primary inputs:
add pin equivalences indata2 indata4 add pin equivalences indata3 -invert indata5 report pin equivalences
Related Commands Add Pin Equivalences Delete Pin Equivalences
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Command Dictionary Report Primary Inputs
Report Primary Inputs

Scope: All modes Usage REPort PRimary Inputs [-All | primary_input_pin] [{> | >>} file_pathname] Description Displays the specified primary inputs. The Report Primary Inputs command displays a list of either all the primary inputs of a circuit or a specific list of primary inputs that you specify. Arguments -All An optional switch that specifies to display all the primary inputs. This is the default. primary_input_pin An optional repeatable string that specifies a list of primary input pins that you want to display. > file_pathname An optional redirection operator and pathname pair, used at the end of the argument list, for creating or replacing the contents of file_pathname. >> file_pathname An optional redirection operator and pathname pair, used at the end of the argument list, for appending to the contents of file_pathname. Examples The following example displays all of the primary inputs:
report primary inputs -all SYSTEM: SYSTEM: /clk /datain
Note The label system means that these are primary inputs that DFTAdvisor automatically recognizes because they were in the netlist. Because there is no Add Primary Inputs command in DFTAdvisor as there is in Tessent FastScan, all primary inputs are of the system-defined class. Related Commands Echo Write Primary Inputs
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Command Dictionary Report Primary Outputs
Report Primary Outputs

Scope: All modes Usage REPort PRimary Outputs [-All | primary_output_pin] [{> | >>} file_pathname] Description Displays the specified primary outputs. The Report Primary Outputs command displays a list of either all the primary outputs of a circuit or a specific list of primary outputs that you specify. Arguments -All An optional switch that specifies to display all the primary outputs. This is the default. primary_output_pin An optional repeatable string that specifies a list of primary output pins that you want to display. > file_pathname An optional redirection operator and pathname pair, used at the end of the argument list, for creating or replacing the contents of file_pathname. >> file_pathname An optional redirection operator and pathname pair, used at the end of the argument list, for appending to the contents of file_pathname. Examples The following example displays all of the primary outputs:
report primary outputs -all SYSTEM: SYSTEM: /dataout /dataout1
Note The label system means that these are primary outputs that DFTAdvisor automatically recognizes because they were in the netlist. Because there is no Add Primary Outputs command in DFTAdvisor as there is in Tessent FastScan, all primary outputs are of the system-defined class. Related Commands Echo Write Primary Outputs
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Command Dictionary Report Procedure
Report Procedure
Scope: All modes except Setup mode Usage REPort PRocedure {procedure_name [group_name]} | -All [{> | >>} file_pathname] Description Displays the specified procedure. The Report Procedure command displays all procedures or the specified procedure. Arguments procedure_name A string that specifies which procedure to display. group_name An optional string that specifies a particular scan group from which to display the specified procedure. -All A switch that specifies for the tool to display all procedures. This is the default. > file_pathname An optional redirection operator and pathname pair, used at the end of the argument list, for creating or replacing the contents of file_pathname. >> file_pathname An optional redirection operator and pathname pair, used at the end of the argument list, for appending to the contents of file_pathname. Related Commands Add Scan Groups Read Procfile Report Timeplate Write Procfile
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Command Dictionary Report Read Controls
Report Read Controls

Scope: All modes Usage REPort REad Controls Description Displays all of the currently defined read control lines. The Report Read Controls command displays all the read control lines that you previously specified by using the Add Read Controls command. The display also includes the corresponding off-state with each read control line. Examples The following example displays a list of the current read control lines:
add read controls 0 r1 r3 add read controls 1 r2 r4 report read controls
Related Commands Add Read Controls Delete Read Controls
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Command Dictionary Report Scan Cells
Report Scan Cells

Scope: Dft mode Usage REPort SCan CElls [-All | chain_name] [-SHift_register_flops] [-Filename filename [-Replace]] [-Display {DEBug | DESign | DAta}] [{> | >>} file_pathname] Description Displays a report or writes a file on the scan cells that reside in the specified scan chains. The Report Scan Cells command provides a report on the scan cells within specific scan chains. The following information is provided in the report for each scan cell: Chain cell index number (where 0 is the scan cell closest to the scan-out pin). When the scan cell is a sub-chain, the CellNo column specifies a range from the first to the last cell in the sub-chain separated by a hyphen. Name of the scan chain in which the scan cell resides. Scan group in which the scan chain resides (dummy is the default group name, if reporting scan cells on inserted scan chains). Instance name of the scan cell. Library model name of the scan cell (if -Filename is not specified). Scan output port name of the scan cell (if -Filename is not specified). Global clock for each scan cell (if -Filename is not specified). When the scan cell is a sub-chain, the Clock column contains the clock for the first cell in the sub-chain and the clock for the last cell in the sub-chain. Polarity of the global clock, whether the clock is leading or trailing edge (if -Filename is not specified).When the scan cell is a sub-chain, the Clock Polarity column contains the polarity of the first clock in the Clock column and the polarity of the second clock in the Clock column. Associated lockup cells for each clock domains transition and active-high to active-low edge domains transition when automatic insertion of lockup cells is enabled (if -Filename is not specified).
If you issue the command without specifying any arguments, then DFTAdvisor displays a report on the scan cells for all scan cells in existing scan chains, and also scan cells from the inserted scan chains. If you issue the command with the -Filename switch, then DFTAdvisor writes the scan cells to a file in the format that can be read by the Insert Test Logic command. The format of the written file is different than the format of the viewed report. You can optionally edit the scan cell order in the file before reading the file with the Insert Test Logic command.
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Arguments -All | chain_name An optional switch or repeatable string. The -All switch specifies to display the scan cells for all scan chains. This is the default. The repeatable string specifies the scan chains whose scan cells you want to display. -SHift_register_flops An optional switch that specifies to print only the shift register flip-flops that are stitched into scan chains. -Filename filename [-Replace] An optional switch and string that specifies that DFTAdvisor writes the list of scan cells to a file. The format of the written file is different than the format of the viewed report. The -Replace switch specifies that the file should be overwritten if it already exists. -Display {DEBug | DESign | DAta} A switch and literal that displays the reported information graphically in the specified DFTVisualizer window(s). The choices are as follows: DEBug Debug window DESign Design window DAta Data window See Using Tessent DFTVisualizer for more information. > file_pathname An optional redirection operator and pathname pair, used at the end of the argument list, for creating or replacing the contents of file_pathname. >> file_pathname An optional redirection operator and pathname pair, used at the end of the argument list, for appending to the contents of file_pathname.
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Example 1 The following example displays a list of all scan cells in the DFT system mode:
add scan groups group1 scanfile add scan chains chain1 group1 indata2 outdata4 set system mode dft report scan cells
-------------------------------------------------------------------------------Chain Group Clock CellNo Name Name Pathname CellName ScanOut Clock Polarity -------------------------------------------------------------------------------0 chain1 group1 /MQ_I400 sffr Q clk2 (+) 1 chain1 group1 /FH_I400 sffr QB clk2 (+) 2 chain1 group1 /FQ_I10 sffr QB clk2 (+) chain1 group1 /lckup1 latch Q clk1 (-) 3 chain1 group1 /RP_I10 sffr Q clk1 (+) 4 chain1 group1 /IS_I10 sffr Q clk1 (+) 5 chain1 group1 /CZ_I400 sffr QB clk1 (+) --------------------------------------------------------------------------------
The first column displays the chain cell index number, where 0-0 is the scan cell closest to the scan-out pin. The second column displays the chain name where the scan cell resides. The third column displays the group name where the scan cell resides. The fourth column displays the hierarchical path of the scan cell. The fifth column displays the library model name for the scan cell. The sixth column displays the scan out port of the scan cell. The seventh column displays the clock for the scan cell. The eighth column displays the polarity of the clock of the scan cell.
Example 2 The following example adds the new column ShiftRegID/CellNo to the report when it identifies a shift register in the netlist. This column contains a tool-assigned number for the shift register ID and a cell number that indicates the order in which the flip-flops are originally connected in the shift register structures. The column contains -/- for those cells that are not part of a shift register.
report scan cells
-------------------------------------------------------------------------------Chain Group ShiftReg Clock CellNo Name Name Pathname ID/CellNo CellName ScanOut Clock Polarity -------------------------------------------------------------------------------0 chain1 dummy /ud5 -/sff Q clk (+) 1 chain1 dummy /ud6 -/sff Q clk (+) 2 chain1 dummy /ud4 1/4 dff Q clk (+) 3 chain1 dummy /ud3 1/3 dff Q clk (+) 4 chain1 dummy /ud2 1/2 dff Q clk (+) 5 chain1 dummy /ud1 1/1 sff QB clk (+) --------------------------------------------------------------------------------
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Example 3 The following example uses the -shift_register_flops switch to print only the shift register flops in the report:
report scan cells -shift_register_flops
-------------------------------------------------------------------------------Chain Group ShiftReg Clock CellNo Name Name Pathname ID/CellNo CellName ScanOut Clock Polarity -------------------------------------------------------------------------------2 chain1 dummy /ud4 1/4 dff Q clk (+) 3 chain1 dummy /ud3 1/3 dff Q clk (+) 4 chain1 dummy /ud2 1/2 dff Q clk (+) 5 chain1 dummy /ud1 1/1 sff QB clk (+) --------------------------------------------------------------------------------
Example 4 The following example shows the additional output that is reported when sub-chains are encountered. Specifically, the starting and ending cell in a sub-chain are listed as a range value in the CellNo column, the clock for the first and last cell in the sub-chain are listed in the Clock column, and the polarity of each clock is listed in the Clock Polarity column.
-------------------------------------------------------------------------------Chain Group Clock CellNo Name Name Pathname CellName ScanOut Clock Polarity -------------------------------------------------------------------------------0 chain1 grp1 /usf2 SCIFTD11S10 SO sysCLK (+) 1 chain1 grp1 /usf1 SCIFTD11S10 SO sysCLK (+) 0-3 chain2 grp1 /um1 &subchain1 SO sysCLK,sysCLK (+,+) 4-7 chain2 grp1 /uB1/um1 &subchain1 SO sysCLK,sysCLK (+,+) 8-9 chain2 grp1 /uC1 &subchain2 so sysCLK,sysCLK (+,+) 10 chain2 grp1 /uff2 SCIFTD11S10 SO sysCLK (+) 11 chain2 grp1 /uB1/uff2 SCIFTD11S10 SO sysCLK (+) 0-3 chain3 grp1 /um2 &subchain1 SO MYTCLK,MYTCLK (+,+) 4-7 chain3 grp1 /uB2/um2 &subchain1 SO MYTCLK,MYTCLK (+,+) 8-11 chain3 grp1 /uB2/um1 &subchain1 SO MYTCLK,MYTCLK (+,+) 12-15 chain3 grp1 /uB1/um2 &subchain1 SO MYTCLK,MYTCLK (+,+) 16-17 chain3 grp1 /uC2 &subchain2 so MYTCLK,MYTCLK (+,+) 18 chain3 grp1 /uff1 SCIFTD11S10 SO MYTCLK (+) 19 chain3 grp1 /uB1/uff1 SCIFTD11S10 SO MYTCLK (+) 20 chain3 grp1 /uB2/uff1 SCIFTD11S10 SO MYTCLK (+) 21 chain3 grp1 /uB2/uff2 SCIFTD11S10 SO MYTCLK (+) ---------------------------------------------------------------------------------
Related Commands Add Scan Chains Add Scan Groups Report Shift Registers
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Command Dictionary Report Scan Chains
Report Scan Chains

Scope: All modes Usage REPort SCan CHains [{> | >>} file_pathname] Description Displays a report on all the current scan chains. The Report Scan Chains command provides the following information in a report for each scan chain: Name of the scan chain Name of the scan chain group Scan chain input and output pins Length of the scan chain
Arguments > file_pathname An optional redirection operator and pathname pair, used at the end of the argument list, for creating or replacing the contents of file_pathname. >> file_pathname An optional redirection operator and pathname pair, used at the end of the argument list, for appending to the contents of file_pathname. Examples The following example displays a report of all the scan chains:
add scan groups group1 scanfile add scan chains chain1 group1 indata2 outdata4 add scan chains chain2 group1 indata3 outdata5 report scan chains
Related Commands Add Scan Chains Delete Scan Chains Echo
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Command Dictionary Report Scan Enable
Report Scan Enable

Scope: DFT Usage REPort SCan Enable [{> | >>} file_pathname] Description Reports on scan_enable signals and associated scan chains. The following details are reported for each scan enable signal: Primary input port (top-level scan enable port) Internal connection node (internal instance pin designated as the scan enable signal driver) Associated scan chain(s)
Arguments > file_pathname An optional redirection operator and pathname pair, used at the end of the argument list, for creating or replacing the contents of file_pathname. >> file_pathname An optional redirection operator and pathname pair, used at the end of the argument list, for appending to the contents of file_pathname. Examples The following example reports the scan_enable details for each of four scan chains.
// command: report scan enable
-------------------------------------------------------Primary Input Internal Connection Node Scan Chain -------------------------------------------------------/scan_en -c3 c4 ------------------------------------------------------------/SEN /I_IOPADS/I_SEN/I0/X c1 c2 -------------------------------------------------------------
Related Commands Set Scan Enable Set Scan_enable Sharing
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Command Dictionary Report Scan Groups
Report Scan Groups

Scope: All modes Usage REPort SCan Groups [{> | >>} file_pathname] Description Displays a report on all the current scan chain groups. The Report Scan Groups command provides the following information in a report for each scan chain group: Name of the scan chain group Number of scan chains within the scan chain group Number of shifts Name of the test procedure file, which contains the information for controlling the scan chains in the reported scan chain group
Arguments > file_pathname An optional redirection operator and pathname pair, used at the end of the argument list, for creating or replacing the contents of file_pathname. >> file_pathname An optional redirection operator and pathname pair, used at the end of the argument list, for appending to the contents of file_pathname. Examples The following example displays a report of all the scan groups:
add scan groups group1 scanfile add scan groups group2 scanfile1 report scan groups
Related Commands Add Scan Groups Delete Scan Groups Echo
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Command Dictionary Report Scan Models
Report Scan Models

Scope: All modes Usage REPort SCan Models Description Displays the sequential scan models currently in the scan model list. The Report Scan Models command displays sequential models which you previously added to the scan model list by using the Add Scan Models command. Examples The following example displays all the sequential scan models from the scan model list:
set system mode dft add scan models d_flip_flop1 d_flip_flop2 report scan models
Related Commands Add Scan Models Delete Scan Models
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Command Dictionary Report Scan Partitions
Report Scan Partitions

Scope: All modes Usage REPort SCan PArtitions {object_name... | -Default | -All} [-Expand] [{> | >>} file_pathname] Description Reports the scan partitions. The user specified scan partitions are reported in the same order they are specified with the Add Scan Partition command. If -expand option is specified, the pathnames of all the sequential instances placed into the scan partitions are reported. Otherwise, the scan partitions are reported in the same format they are defined. Arguments object_name A required repeatable string that specifies the name(s) of the scan partition to report. -Default A required switch that specifies to report the default scan partition. -All A required switch that specifies to report all scan partitions, including the user specified scan partitions and the default scan partition. -Expand An optional switch that specifies to display the pathnames of all the sequential instances placed into the scan partitions. Without this switch, DFTAdvisor reports the scan partitions in the exact format they are declared with the Add Scan Partition command. If the instances are added to the partition by their container module instance, for example, the sequential instances are not reported unless this option is used. > file_pathname An optional redirection operator and pathname pair, used at the end of the argument list, for creating or replacing the contents of file_pathname. >> file_pathname An optional redirection operator and pathname pair, used at the end of the argument list, for appending to the contents of file_pathname. Examples The following example adds two scan partitions. The first partition, partA, is added by using exact pathnames of the sequential instances and by the container module name; the second
235
Command Dictionary Report Scan Partitions
partition, partB, is added by the container module instance of the sequential instances. The scan partitions are then reported twice, with and without the expand switch.
add sub chain D subch1 si so 5 mux_scan se -subclock clk add nonscan instances /umodA/udff1 add scan partition partA -instance udff1 umodA/udff1 umodB/udff1 -module modD add scan partition partB -instance umodC -number 3 report scan partitions -expand ----------------------------------------------------ScanPartitionName Members ----------------------------------------------------partA udff1 umodA/udff1 umodB/udff1 umodD/subch1 (subchain) umodE/umodD/subch1 (subchain) partB umodC/umodX/udff1 umodC/umodX/udff2 umodC/udff1 umodC/udff2 default_scan_partition udff2 umodA/udff2 umodB/udff2 -----------------------------------------------------
Note that the subchain cells are not reported, rather, the entire subchain is reported with its container module instance. Also, the sequential instance /umodA/udff1 is still reported as part of the scan partition, partA, even though it is declared as a nonscan instance.
report scan partitions ----------------------------------------------------------------------ScanPartitionName TotalNumCells/ScannableCells Members ----------------------------------------------------------------------partA 13/12 udff1 [instance] umodA/udff1 [instance] umodB/udff1 [instance] modD [module] partB 4/4 umodC [instance] default_scan_partition 3/3 <all_remaining_cells> -----------------------------------------------------------------------
An extra column is printed, TotalNumCells/ScannableCells, when the -expand switch is not specified. The subchain cells are counted based on the length specified with the Add Sub Chain command. The sequential instances that have S1/S2 scannability rule failure or that are defined nonscan are not included in the ScannableCells section of this column. Related Commands Add Scan Partition Delete Scan Partitions
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Command Dictionary Report Scan Pins
Report Scan Pins

Scope: All modes Usage REPort SCan PIns [{> | >>} file_pathname] Description Displays all previously assigned scan input, output, and clock names. The Report Scan Pins command displays the user-specific names that you have added to the scan input and scan output pins of the scan chains. Arguments > file_pathname An optional redirection operator and pathname pair, used at the end of the argument list, for creating or replacing the contents of file_pathname. >> file_pathname An optional redirection operator and pathname pair, used at the end of the argument list, for appending to the contents of file_pathname. Examples The following example displays all scan input and scan output names for the scan chains and then inserts the scan chains.
add clocks 0 clk set system mode dft run add scan pins chain1 si so add scan pins chain2 si1 so1 report scan pins insert test logicinsert test logic
Related Commands Add Scan Pins Delete Scan Pins Echo
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Command Dictionary Report Seq_transparent Constraints
Report Seq_transparent Constraints

Scope: All modes Usage REPort SEq_transparent Constraints Description Displays the seq_transparent constraints. The Report Seq_transparent Constraints command displays the constraints that you added to the DFT library model clock enable pins with the Add Seq_transparent Constraints command. You can change the constant value constraints of the pins by using the Add Seq_transparent Constraints command. Examples The following example displays all the seq_transparent constraints.
report seq_transparent constraints
Related Commands Add Seq_transparent Constraints Delete Seq_transparent Constraints Setup Scan Identification
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Command Dictionary Report Sequential Instances
Report Sequential Instances

Scope: All modes Usage REPort SEquential Instances [-SCannable] [-NONscannable] [-DEFINED_Scan] [-DEFINED_Nonscan] [-Subchain] [-IDentified] [-Unidentified] [-STitched] [-Polarity {+ | -}] [-CLock clockname ] [-CHain chainname ] [-Library_model modelname ] [-INstance object_pathname ... | -Module object_name ] [-NOHeader] [-NOFooter] [-NOVerbose] [-Format format_code ] [-DRIVEN_SEN_info] [{> | >>} file_pathname] [-DRIVEN_SCAN_pin_cells] Description The Report Sequential Instances command reports information and testability data for the sequential instances in the design. You can display the sequential instances in the design using various filtering options. When you specify multiple filters, the command reports only the sequential instances that satisfy every filtering condition. If no filters are specified, the command reports all sequential instances in the design. You can also control the output of the command, such as printing header and footer information, and formatting the output columns. The total number of reported instances is contained in the footer of the report. Arguments -SCannable An optional switch that reports the sequential instances that can be placed into scan chains. -NONscannable An optional switch that reports the sequential instances that cannot be placed into scan chains. The scannability condition of a sequential instance is determined by the DRC rule checker. -DEFINED_Scan An optional switch that reports the sequential instances you define as scannable. -DEFINED_Nonscan An optional switch that reports the sequential instances you define as non-scannable. -Subchain An optional switch that reports the sequential instances contained in user-defined subchains. Note that all the cells under the parent module of a subchain are marked as subchain cells. Therefore, there may be cells marked as subchain cells even though they are not physically on the specified subchains.
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-IDentified An optional switch that reports the sequential instances identified as scannable by DFTAdvisor. This is only valid after executing a Run command.
-UNidentified An optional switch that reports sequential instances not identified as scannable by DFTAdvisor.
-STitched An optional switch that reports the sequential instances already placed in scan chains. Such instances that cannot hold the scannable or non-scannable conditions.
-Polarity + | An optional switch and a sign character that reports the sequential instances clocked by stable_low (+) or stable_high (-) clocks.
-INstance object_pathname An optional switch and repeatable string that reports the sequential instances that reside under specified instances.
-Module object_name An optional switch and repeatable string that reports the sequential instances that reside under specified modules.
-NOHeader An optional switch that disables reporting of the header information in the output. -NOFooter An optional switch that disables reporting of the footer information in the output. The footer information includes the total number of reported instances.
-NOVerbose An optional switch that reports the body of the report output, which is all the information except the header and the footer.
-Format format_code An optional switch and repeatable string that specifies which information columns to include in the report. When this switch is used, the specified columns are reported in the specified order. Use the format codes described in Table 2-6 to specify columns. Table 2-6. Output Format Codes Format_code PN MN Column Pathname Description Pathname of the sequential instance.
Module Name Library module name of the sequential instance.
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Table 2-6. Output Format Codes Format_code GI Column Gate ID Description Flattened netlist gate ID of the sequential instance. Available only in DFT mode when the flattened netlist is not freed in the process (before test logic insertion). By default, this column is not included in the output. Name of the primary input pin that clocks the sequential instance. If this pin is unidentified, Unknown or Test-logic displays. Test-logic is reported if you issue the Set Test Logic -clock ON reset ON command and DRC determines that test logic is needed for the sequential element to be scannable.
CN
Clock Name
CP TY
Clock Polarity Clock polarity information for the sequential instance. Type Sequential instance type: Unknown (if in SETUP mode) Scannable Pos-scannable Non-scannable Ignored Trans-latch Constant chain name or DFT (after test logic insertion) If the sequential instance is part of a scan chain, the chain name is listed. If the sequential instance is either a test logic control/observe point or a lockup cell inserted by DFTAdvisor, DFT is listed. Sequential instance status: None (before scan identification process) Unidentified (before scan identification process) Identified (after scan identification process) Defined-scan Defined-nonscan Defined-nonscan [Driven-SEN] (scan-enable pin is functionally driven) Subchain scan cell number (after test logic insertion)
ST
Status
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-DRIVEN_SEN_info An optional switch that reports sequential instances with functionally-driven scan enable pins. The scan enable pin is considered functionally driven if the driving pin is a PI pin or an output pin of a library instance that is not an inverter or buffer. The driver and driven pins can be at different levels of hierarchy where the buffers and inverters between them are transparent to the tool. When functionally-driven sequential instances are found, they are added to the non-scan instance list and a warning message displays. This switch also writes out a dofile (delete_nonscan_instances_for_driven_sen.dofile) that can be used to remove the functionally-driven sequential instances from the non-scan cell list and include them back into scan insertion. This also preserves the original connection to the driving scan enable signal for these sequential instances. Alternately, if the reported global scan enable pin (driving pin) is common to all reported sequential instances, you can define it as the global scan enable pin with the Set Scan Enable command in a new DFTAdvisor session. Once defined, it will be used as the scan enable signal during scan insertion.
> file_pathname An optional redirection operator and pathname pair used at the end of the argument list to create or replace the contents of a specified file with command output.
>> file_pathname An optional redirection operator and pathname pair used at the end of the argument list to append command output to the contents of a specified file.
-DRIVEN_SCAN_pin_cells An optional switch that reports sequential instances with functionally-driven scan input pins. The scan input pin is considered to be functionally driven if the driving pin is a PI pin or an output pin of a library instance that is not an inverter or buffer. The driver and driven pins can be at different levels of hierarchy where the buffers and inverters between them are transparent to the tool. The sequential instances with functionally-driven scan input pins are still considered as scan candidates by default, unlike the sequential instances with functionally-driven scan enable pins. DFTAdvisor reports the existence of functionally-driven sequential instances to the user when it switches to DFT mode. This provides you with the option of examining instances with this switch and including them in the list of previously inserted scan chains via the Add Scan Chains or Add Sub Chains commands; otherwise, the tool disconnects the original connections to the scan input pins and stitches them in new scan chains along with the other scan candidates.
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Example The following example identifies sequential instances with functionally driven scan enable pins, and restores the sequential instances to the scannable cell list with the original scan enable connections preserved. The following command sets DFT mode, runs DRC and returns a warning message when driven scan enable pins are found.
set system mode dft
// // // // // // // // // // Warning: The design includes scan cells whose scan enable pins are driven. 1) These scan cells have been added to the non-scan cell list by the tool 2) You can use the Report Sequential Instances command to examine them 3) If a pre-routed global scan enable is used, you can define it using the 'Setup Scan Insertion' command to have these cells re-evaluated. 4) You can also use the Delete Nonscan Instances command to preserve the original scan enable pin driver without specifying a global scan enable pin and a re-evaluation.
The following command reports all sequential instance types.

report sequential instances
----------------------------------------------------------------------Model Clock Clock PathName Name Name Polarity Type Status -----------------------------------------------------------------------udff4 sff clk (+) Scannable Defined-nonscan [Driven-SEN] uA/udff3 sff clk (+) Scannable Defined-nonscan [Driven-SEN] uA/udff1 sff clk (+) Scannable Defined-nonscan [Driven-SEN] uA/udff2 sff clk (+) Scannable Unidentified ------------------------------------------------------------------------Number of instances: 4
The following command reports on the sequential instances with driven scan enable pins.
report sequential instances -driven_sen_info
-------------------------------------------------------------------------------Model Clock Clock Sen SenDriver PathName Name Name Polarity Type Status Pinname PinPathname -------------------------------------------------------------------------------udff4 sff clk (+) Scannable Defined-nonscan SE /sen uA/udff3 sff clk (+) Scannable Defined-nonscan SE /sen uA/udff1 sff clk (+) Scannable Defined-nonscan SE /uA/ux/Y -------------------------------------------------------------------------------Number of instances: 3 // Note: A dofile named 'delete_nonscan_instances_for_driven_sen.dofile' // is written out in the current directory.
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The following command executes the dofile created by the previous example and deletes the instances from the non-scan cell list.
dofile delete_nonscan_instances_for_driven_sen.dofile
// // // command: delete nonscan instances udff4 command: delete nonscan instances uA/udff3 command: delete nonscan instances uA/udff1
The following command runs the scan identification process as specified by the Setup Scan Identification command.
run
// // // Number of targeted sequential instances = 4 Performing scan identification ... Total sequential instances identified = 4
The following command reports on all sequential instances.

report sequential instances
-----------------------------------------------------------------------Model Clock Clock PathName Name Name Polarity Type Status -----------------------------------------------------------------------udff4 sff clk (+) Scannable Identified [Driven-SEN] uA/udff3 sff clk (+) Scannable Identified [Driven-SEN] uA/udff1 sff clk (+) Scannable Identified [Driven-SEN] uA/udff2 sff clk (+) Scannable Identified -----------------------------------------------------------------------Number of instances: 4
The following commands insert test logic and report on the inserted sequential instances stitched into scan chains.
insert test logic report sequential instances
---------------------------------------------------Model Clock Clock PathName Name Name Polarity Type Status ---------------------------------------------------udff4 sff clk (+) chain1 0 uA/udff3 sff clk (+) chain1 1 uA/udff1 sff clk (+) chain1 2 uA/udff2 sff clk (+) chain1 3 ---------------------------------------------------Number of instances: 4
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Related Commands Add Nonscan Instances Delete Nonscan Instances Echo Insert Test Logic Report Circuit Components Report Dft Check Report Scan Cells Run Set Scan Enable Set System Mode
245
Command Dictionary Report Shift Registers
Report Shift Registers

Scope: DFT mode Usage REPort SHift Registers [-Verbose | -Summary] Description Reports the identified shift registers in the design after switching to DFT mode. The tool tries to preserve the original connections inside the identified shift registers during stitching. Therefore, this command may report the shift registers in the design differently, before and after the execution of the Insert Test Logic command. For each identified shift register, this command reports the following information: Length Hierarchical path where the shift register flip-flops reside First and last flip-flop instance name unless the -verbose switch is specified in which case all flip-flops in the shift registers are reported
Arguments -Verbose An optional switch that reports all of the flip-flops identified in the shift registers. -Summary An optional switch that reports a summary text without printing the flip-flops identified in the shift registers. Example 1 The following example shows the output when neither switch is specified:
report shift registers -------------------------------------------------------------------Hierarchical SequentialCell Clock Library Id Length Path InstanceName Edge & Name ModelName -------------------------------------------------------------------[1] 4 / ud1 + clk dff ... ud4 + clk dff // Number of sequential elements in design: 6 // Number of shift register flops recorded for scan insertion: 4 // => 66.67% of all sequential elements in design // Number of shift registers recorded for scan insertion: 1 // Longest shift register has 4 flops. // Shortest shift register has 4 flops. // Potential number of nonscan flops to be converted to scan cells: 1 // Potential number of scan cells to be converted to nonscan flops: 0
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Command Dictionary Report Shift Registers
Example 2 The following example shows the output when the -verbose switch is specified:
report shift registers -verbose -------------------------------------------------------------------Hierarchical SequentialCell Clock Library Id Length Path InstanceName Edge & Name ModelName -------------------------------------------------------------------[1] 4 / ud1 + clk dff ud2 + clk dff ud3 + clk dff ud4 + clk dff // Number of sequential elements in design: 6 // Number of shift register flops recorded for scan insertion: 4 // => 66.67% of all sequential elements in design // Number of shift registers recorded for scan insertion: 1 // Longest shift register has 4 flops. // Shortest shift register has 4 flops. // Potential number of nonscan flops to be converted to scan cells: 1 // Potential number of scan cells to be converted to nonscan flops: 0
Example 3 The following example shows the output when the -summary switch is specified:
report shift registers -summary // // // // // // // // Number of sequential elements in design: 6 Number of shift register flops recorded for scan insertion: 4 => 66.67% of all sequential elements in design Number of shift registers recorded for scan insertion: 1 Longest shift register has 4 flops. Shortest shift register has 4 flops. Potential number of nonscan flops to be converted to scan cells: 1 Potential number of scan cells to be converted to nonscan flops: 0
Related Topics Setup Shift_register Identification
247
Command Dictionary Report Statistics
Report Statistics
Scope: All modes Usage REPort STAtistics [{> | >>} file_pathname] Description Displays a detailed report of the designs statistics. The Report Statistics command displays a detailed statistics report to the screen. The report includes the following information when in Setup and Dft modes: Total number of sequential instances Number of defined non-scan instances Number of non-scan instances identified by the DRC Number of defined scan instances Number of scan instances identified by the DRC Number of identified scan instances Number of scannable instances with test logic Number of pre-existing scan chains The total numbers for the following:
o
Total patterns simulated in the preceding fault simulation process. This subgroup may additionally contain total numbers for the following internal patterns sets: basic scan patterns Clock_po patterns Ram_sequential patterns Clock_sequential patterns
o o
Total patterns currently in the test pattern set Total CPU time
If a pattern type has no patterns, the report does not display the count for that type. If all patterns are basic patterns, it will not display any count. And, it counts clock_sequential patterns that are also clock_po only as clock_sequential patterns. Arguments > file_pathname An optional redirection operator and pathname pair, used at the end of the argument list, for creating or replacing the contents of file_pathname.
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Command Dictionary Report Statistics
Examples The following example displays the statistics report after performing the scan identification process in Dft mode:
add clocks 0 clock set system mode dft run report statistics Total number of sequential instances Number of defined nonscan instances Number of nonscan instances identified by drc Number of defined scan instances Number of scan instances identified by drc Number of identified scan instances Number of scannable instances Number of scannable instances with test logic =40 =5 (12.50%) =5 (12.50%) =5 (12.50%) =5 (12.50%) =5 (12.50%) =10 =5
Related Commands Echo
249
Command Dictionary Report Sub Chains
Report Sub Chains

Scope: All modes Usage REPort SUb Chains [{> | >>} file_pathname] Description Displays a report on the scan subchains. The Report Sub Chains command transcripts the scan subchain definition(s), which includes the scan type, module or instance pathname, name of the subchain, defined length of the subchain, scan input of the subchain, and the scan output of the subchain. For mux-scan, the report includes the scan enable of the subchain. For clocked-scan, the report includes the scan clock. For LSSD, the report includes the scan master clock and the scan slave clock. Arguments > file_pathname An optional redirection operator and pathname pair, used at the end of the argument list, for creating or replacing the contents of file_pathname. >> file_pathname An optional redirection operator and pathname pair, used at the end of the argument list, for appending to the contents of file_pathname. Examples The following example generates a report for a scan subchain:
add sub chains /instA subch1 /si1 /so1 10 mux_scan -sen_core sen -instance report sub chains mux_scan: instA subc1 10 si1 so1 sen
Related Commands Add Sub Chains Delete Sub Chains Echo
250
Command Dictionary Report Subchain Clocks
Report Subchain Clocks

Scope: All modes Usage REport SUbchain CLocks subchain_name Description Reports on subchain clocks defined with the Add Subchain Clocks command. Arguments subchain_name A required string that specifies the name of a subchain. Examples
add sub chains MULTIBITSFF3 chain1 SI SO 4 mux_scan S library_model add subchain clocks chain1 0 RESET -reset add subchain clocks chain1 0 SET -set add subchain clocks 0 CK -first_cell_clock -leading_edge add subchain clocks 0 CK -last_cell_clock -leading_edge report subchain clocks chain1 // // // // // // clock name type off_state ---------- -----------RESET reset 0 SET set 0 CK first cell clock 0 CK last cell clock 0 edge -----
delete subchain clocks chain1 CK report subchain clocks chain1 // // // // clock name type off_state edge ---------- ----- --------- -----RESET reset 0 SET set 0
Related Commands Add Subchain Clocks Delete Subchain Clocks
251
Command Dictionary Report Subchain Groups
Report Subchain Groups

Scope: All modes Usage REPort Subchain Groups Description Displays a report on the subchain groups. The Report Subchain Groups command transcripts the subchain group definitions used in Add Subchain Group command. The definitions include the name of the subchain group, the list of subchains, and the type of the subchain group. Examples The following example illustrates the usage and the output format of the Report Subchain Groups command.
add subchain group subchaingroup1 subchain1 subchain2 -fixed add subchain group subchaingroup2 subchain3 subchain4 -flexible report subchain groups ----------------------------------------------SubchainGroupName Type ListOfSubchains ----------------------------------------------subchaingroup1 fixed subchain1 subchain2 subchaingroup2 flexible subchain3 subchain4
Related Commands Add Subchain Group Add Sub Chains Delete Sub Chains Delete Subchain Groups Report Sub Chains
252
Command Dictionary Report Test Logic
Report Test Logic

Scope: All modes Prerequisites: Test logic or test points must be added with the Insert Test Logic command. Usage REPort TEst Logic [-Instance | -Module | -Summary | -Location] [{> | >>} file_pathname] Description Displays the test logic that DFTAdvisor added during the scan insertion process. The Report Test Logic command displays information about the test logic that DFTAdvisor added during the scan insertion process as a result of the Set Test Logic and Add Test Points commands. Arguments -Instance An optional switch that displays the list of instance pathnames and the corresponding DFT library model that DFTAdvisor inserted as test logic and test points. This option also includes a summary of the number of each instance-based DFT library model that DFTAdvisor inserted. This is the default. -Module An optional switch that displays the list of module names, the list of instance pathnames, and the corresponding DFT library models that DFTAdvisor inserted as test logic and test points. This option also includes a summary of the number of each module-based DFT library model that DFTAdvisor inserted. -Summary An optional switch that displays a summary that contains the number of each module and instance-based DFT library model that DFTAdvisor inserted. -Location An optional switch that displays the pin pathname where DFTAdvisor inserted test logic and identifies whether it was a result of the test logic settings or test points that you specified. > file_pathname An optional redirection operator and pathname pair, used at the end of the argument list, for creating or replacing the contents of file_pathname. >> file_pathname An optional redirection operator and pathname pair, used at the end of the argument list, for appending to the contents of file_pathname.
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Command Dictionary Report Test Logic
Examples The following example uses both test logic and test points. The report displays the locations where DFTAdvisor inserted the test logic as a result of both the Add Test Point command and the Set Test Logic command:
add cell models and2a -type and add cell models inv1a -type inv add cell models mux1a -type mux s a b add test point /I_6_16/cp control and2a control_input set test logic -set on -reset on set system mode dft run insert test logic report test logic -location /I_6_16/reset (test points) /I_7_16/set (scan cell)
Related Commands Add Test Points Delete Test Points Echo Report Test Points
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Command Dictionary Report Test Points
Report Test Points

Scope: All modes Usage REPort TEst Points [-Full | -Control | -Observe | -Lockup] [-Wrapper_chains_identified] [{> | >>} file_pathname] [-Wrapper_chains_identified] Description Displays both user-defined and system-defined test points. You can create user-defined test points with the Add Test Points command. You can enable DFTAdvisor to automatically identify test points using a combination of the Setup Scan Identification, Setup Test_point Identification, Setup Test_point Insertion, and Run commands. However, DFTAdvisor does not actually generate the test point circuitry until you issue the Insert Test Logic command. The report marks the system-defined test points with [Selected] prior to the test point information. Arguments -Full An optional switch that displays all of the information available on both control and observe test points for both the user-defined and the system-defined test points. This is the default. -Control An optional switch that displays all the test point definitions (both user- and system-defined) that are for the purpose of enabling better test coverage in design areas where, previously, DFTAdvisor could not force certain state values. -Observe An optional switch that displays all the test point definitions (both user- and system-defined) that are for the purpose of enabling better test coverage by allowing the tester access to certain fault effects. -Lockup An optional switch that displays all test points (both user- and system-defined) with added lockup cells. -Wrapper_chain_identified An optional switch that reports the test points automatically added during the wrapper cell identification process. Such test points may be added only if the -Test_points switch is specified with the Setup Pin Constraints command. The -Control or -Observe switches can be used along with this switch to display either control or observe test points of this type. By default, all the test points are reported.
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Command Dictionary Report Test Points
Examples The following example creates one user-defined control point and one user-defined observe point and then reports their definitions:
add test points /I_7_16/q Observe observe_output add cell models and2a -type and add cell models sdff1a -type sdff clk data add test points /I_6_16/reset control and2a tp_clk -new_scan_cell sdff1a insert test logic report test points Control: /I_6_16/reset Control and2a tp_clk -New_scan_cell sdff1a // (internal scan) ctlff1 Observe: /I_7_16/q Observe observe_output
The control point report columns consist of the control point pathname, the library model name used for the control point, the top-level clock pin specified for the control point scan cell, the library model name used for the scan cell, the type of scan chain the test point inserted into, and the instance pathname for the scan cell inserted. The last two columns are not printed if the command is issued before the Insert Test Logic command. The observe point report columns consists of the observe point pathname and the primary output pin created for the observe point. Related Commands Add Test Points Delete Test Points Echo Insert Test Logic Report Test Logic Run Setup Pin Constraints Setup Scan Identification Setup Test_point Identification Setup Test_point Insertion
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Command Dictionary Report Testability Analysis
Report Testability Analysis

Scope: Dft mode Prerequisites: You must first issue the Analyze Testability command to calculate the values on which to report. Usage REPort TEstability Analysis [pathname] [-Controllability | -OBservability] [{-Number integer} | {-Percent integer} | {-OVer integer}] Description Displays the results of the Analyze Testability command. The Report Testability Analysis command displays a columnar list of either the controllability or observability values for each pin in the flattened design. The -Controllability and -Observability switches determine the column definitions. The Analyze Testability command calculates the controllability and observability values for each gate in the flattened design. If the designs fault coverage in Tessent FastScan is lower than you desire, you can re-invoke DFTAdvisor to perform the testability analysis, which allows you access to the controllability and observability values. You can then generate test points (either manually or automatically) based on the results of the testability analysis to help increase the designs fault coverage. If you are going to manually investigate the results of the testability analysis and insert userdefined test points, you need to use the Add Test Points command. If you are going to have DFTAdvisor automatically identify (system-defined) test points, you need to use a combination of the Setup Scan Identification, Setup Test_point Identification, and Run commands. Tip: For more information, see Setting Up for Test Point Insertion in the Scan and ATPG Process Guide. Arguments pathname An optional string that specifies the instance name whose pins for which you want DFTAdvisor to display the controllability or observability values. The default is all pins for all instances. -Controllability An optional switch that specifies for DFTAdvisor to only display the pin controllability values. This is the default. The controllability report displays the following information in columnar format:
o o
The controllability value for the low logic state The controllability value for the high logic state
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Command Dictionary Report Testability Analysis o o o
The primitive gate type The gate identification number The pathname to the gate
If DFTAdvisor cannot control the inputs of a gate, the report displays NC (non-controllable) for the corresponding logic state. -OBservability An optional switch that specifies for DFTAdvisor to only display the pin observability values. The observability report displays the following information in columnar format:
o o o o
The observability value The primitive gate type The gate identification number The pathname to the gate
If DFTAdvisor cannot observe the outputs of a gate at any observation point, the report displays NO (non-observable). -Number integer An optional switch and integer pair that specifies the maximum number of pins whose values you want to display. If you specify the -Number switch, you must provide the associated integer. -Percent integer An optional switch and integer pair that specifies the percentage of the total number of available design pins whose values you want to display. You determine the total number of available design pins by whether you specify or do not specify the instance pathname argument. If you specify the -Percent switch, you must provide the associated integer. -OVer integer An optional switch and integer pair that specifies the minimum controllability or observability values whose pins you want to display. If you specify the -Over switch, you must provide the associated integer. Examples The following example displays the controllability values of five percent of all the pins in the design.
set system mode dft setup scan identification none analyze testability -scoap_only setup test_point identification -control 1 run
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Command Dictionary Report Testability Analysis // // // // Performing test_point identification ... Number of control points to be identified = 1 Number of observe points to be identified = 0 1: CV1=16458417 gate_index=3805 INV /CNTR/U783/ZN
report testability analysis -controllability -percent 5 NC 0 100 0 NC 1 BUF INV BUF 25 27 39 /I_6_16 /I_7_14 /I_8_21
The report displays the controllability value for the low logic state (where NC means noncontrollable), the controllability value for the high logic state, the primitive gate type, the gate identification number, and the pathname to the gate. Related Commands Analyze Testability
259
Command Dictionary Report Tied Signals
Report Tied Signals

Scope: All modes Usage REPort TIed Signals [-Class {Full | User | System}] [{> | >>} file_pathname] Description Displays a list of the tied floating signals and pins. The Report Tied Signals command displays either the user class, system class, or full classes of tied floating signals and pins. If you do not specify a class, the command displays all the tied floating signals and pins. Arguments -Class Full | User | System An optional switch and literal pair that specifies the source (or class) of the tied floating signals or pins which you want to display. The valid literals are as follows: Full A literal that specifies to display all the tied floating signals or pins in the user and system class. This is the default. User A literal that specifies to only display the tied floating signals or pins that you created by using the Add Tied Signals command. This includes all instance-based blackbox tied signals. System A literal that specifies to only display the tied floating signals or pins described in the netlist. > file_pathname An optional redirection operator and pathname pair, used at the end of the argument list, for creating or replacing the contents of file_pathname. >> file_pathname An optional redirection operator and pathname pair, used at the end of the argument list, for appending to the contents of file_pathname. Examples The following example will display the tied signals from the user class.
add tied signals 1 vcc vdd report tied signals -class user
Related Commands Add Tied Signals Delete Tied Signals Report Black Box Setup Tied Signals
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Command Dictionary Report Timeplate
Report Timeplate
Scope: All modes except Setup mode Usage REPort TImeplate timeplate_name | -All [{> | >>} file_pathname] Description Displays the specified timeplate. The Report Timeplate command displays all timeplates or the specified timeplate. Arguments timeplate_name A string that specifies which timeplate to display. -All A switch that specifies for the tool to display all timeplates. This is the default. > file_pathname An optional redirection operator and pathname pair, used at the end of the argument list, for creating or replacing the contents of file_pathname. >> file_pathname An optional redirection operator and pathname pair, used at the end of the argument list, for appending to the contents of file_pathname. Related Commands Add Scan Groups Read Procfile Report Procedure Write Procfile
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Command Dictionary Report Variables
Report Variables
Scope: All modes Usage REPort VAriables Description Displays user-defined variables and values. The Report Variables command displays the list of user-defined variables and their corresponding values. This list does not include environment variables defined in the parent shell environment. Variables are defined, referenced, and reported on in the following manner: 1. Defining Use the following syntax to create and set a variables value. Define variables from the tools command line, throughout a dofile, or from a startup file.
$variable = value
2. Referencing To refer to a variable causes its value to be substituted into a command. Multiple variable references are allowed per tool command. You must define variables before they are referenced.
${variable}
If a variable is not meant to be concatenated with any other strings, then use the $variable-name construct as in the following example:
insert test logic -max_length $MAX_SCAN_LEN -scan on
Variables are not expanded if there has been no definition. This condition behaves like any other syntax error that may be present on the command line or within a dofile. 3. Reporting Use the Report Variables command to display user-defined variables and values.
REPort VAriables
Examples The following example defines four variables, refers to them within tool commands, and displays a list of all variables:
... set system mode dft $design_base_file = scan $design_base_dir = /$USER/dft_scan_designs $max_scan_len = 100 $revision = 1.42 run insert test logic write netlist -verilog ${design_base_dir}/${design_base_file}.v report variables
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Command Dictionary Report Variables design_base_dir /$USER/dft_scan_designs design_base_file scan revision 1.42 max_scan_len 100
Note As $USER is defined in the parent shell environment, it is available for use within the tool and in other variable definitions. The next example invokes DFTAdvisor with a parameterized dofile: A UNIX script file can contain the variable settings:
#!/bin/csh setenv MY_DESIGN m8051 setenv NUM_SCAN_CHAINS 8 dftadvisor -verilog ${MY_DESIGN}.v -library atpg.lib -dofile scan.do
And the scan.do file can reference the variables:

echo "... processing $MY_DESIGN " analyze control signals -auto_fix set test logic -reset on -set on set system mode dft setup scan identification full_scan run echo "... insert $NUM_SCAN_CHAINS scan chains" insert test logic -number $NUM_SCAN_CHAINS report scan chains > reports/${MY_DESIGN}.chain.report report test logic -summary > reports/${MY_DESIGN}.testlogic.report write netlist netlists/${MY_DESIGN}_scan.v -verilog -rep write atpg setup scripts/${MY_DESIGN} -rep exit
Related Commands Printenv
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Command Dictionary Report Write Controls
Report Write Controls

Scope: All modes Usage REPort WRite Controls Description Displays the currently defined write control lines and their off-states. The Report Write Controls command displays the write control lines, with corresponding offstates, that you previously added by using the Add Write Controls command. Examples The following example adds four write control lines and then displays a list of the control line definitions:
add write controls 0 w1 w3 add write controls 1 w2 w4 report write controls
Related Commands Add Write Controls Delete Write Controls
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Command Dictionary Reset State
Reset State
Scope: All modes Usage RESet STate Description Removes all instances from both the scan identification and test point identification lists that DFTAdvisor identified during a run. The Reset State command removes scan instances or test points identified with the Run command. If, however, you have stitched the scan chain or inserted test points, this command has no effect on these. Examples The following example performs a full scan identification process, then removes the identified scan instances and performs a 75 percent ATPG scan identification process:
set system mode dft setup scan identification full_scan run report sequential instances . . . reset state setup scan identification sequential atpg -percent 75 run report sequential instances . . .
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Command Dictionary Ripup Scan Chains
Ripup Scan Chains

Scope: Dft mode Usage RIPup SCan Chains {-All | chain_name} [-Output] [-Keep_scancell [Off | Tied | Loop | Buffer]] [-Model model_name] Description Removes the specified scan chains from the design. The Ripup Scan Chains command removes scan chains that DFTAdvisor placed during the scan insertion process. You can remove (rip up) either all the scan chains or individual scan chains. You can also rip up the scan chain output pin. If you only want to remove a scan chain definition that you previously created with the Add Scan Chains command, use the Delete Scan Chains command. This command removes any inserted lockup cell under the following conditions: a.) The latch is an instance of a cell library model previously defined as a DLAT model. b.) After chain removal, the instance has only one connected port and that port was declared as the clock/enable port. Note that lockup cell insertion is optional. Normally, you would not allow lockup cell insertion during the DFTAdvisor session(s) before layout. lockup cell insertion should be activated during the DFTAdvisor session after placement. Note If the design contains test logic in addition to scan circuitry, this command only removes the scan circuitry, not the test logic. Arguments -All A switch that specifies to remove all scan chains. chain_name A repeatable string that specifies the names of the scan chains that you want to remove. -Output An optional switch that specifies that the existing scan chain output pins are to be ripped up together with the scan chains. -Keep_scancell [Off | Tied | Loop | Buffer] An optional switch and literal pair that specifies to remove the connection between the scan input/output ports of each scan cell. The connections of all other ports are not altered and the scan cells are not mapped to their non-scan models. If this switch is not specified, the default
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Command Dictionary Ripup Scan Chains
is to remove the connections of all test ports and map the scan cells back to their original non-scan model. Off DFTAdvisor disconnects the scan_out pin and scan_in pin and leaves them dangling. This is the default. Tied DFTAdvisor disconnects the scan_out pin and scan_in pin and ties them to ground. Loop DFTAdvisor disconnects the scan_out pin and scan_in pin and connects them to each other as a self-loop for each scan cell. Buffer DFTAdvisor disconnects the scan_out pin and scan_in pin and connects them to each other as a self-loop with a buffer in between for each scan cell. -Model model_name An optional switch and string pair that specifies the name of a buffer in the ATPG library for DFTAdvisor to insert in the self-loop. This option is only valid if you specify the -Keep_scancell Buffer. You must first identify the buffer with either the Add Cell Models command or with the cell_type library attribute. If you do not specify the -Model switch, by default, DFTAdvisor uses the first buffer model in the buffer cell model listsee the Report Cell Models command. Examples The following example illustrates usage of the Ripup Scan Chains command.
add clocks 0 clock add scan groups group1 scan.testproc add scan chains chain1 group1 scan_in1 scan_out1 set system mode dft report scan chains ripup scan chains -all
Related Commands Add Scan Chains Report Scan Chains
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Command Dictionary Run
Run
Scope: Dft mode Usage RUN Description Runs the scan or test point identification process. The Run command performs the scan or test point identification process in Dft mode depending on the identification type you set with the Setup Scan Identification command. The Run command performs the scan identification process, as indicated by the Setup Scan Identification command (if the identification type is set to -Sequential), and the test point identification process as indicated by the Setup Test_point Identification command. During the identification run, DFTAdvisor displays progress messages. The first number indicates the number of instances currently identified for scan (added to the scan candidate list). During the controllability phase, the second number indicates the estimated percentage of toggle coverage. During the observability phase, this number indicates the estimated observability coverage of stuck-at faults. For example, if you set the identification type to sequential, the tool may display the following for the controllability phase:
// Sequential instances identified = 238 (Controllability = 97.31%)
Examples The following example runs a scan identification process:

set system mode dft setup scan identification sequential atpg run report sequential instances
Related Commands Setup Scan Identification Setup Test_point Identification
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Command Dictionary Save History
Save History
Scope: All modes Usage SAVe HIstory filename [-Replace] Description Saves the command line history file to the specified file. The Save History command saves the list of previously executed commands in the file that you specify. You can then execute the file using the Dofile command. Arguments filename A required string that specifies the name of the file in which the tool saves the command line history list. -Replace An optional switch that specifies for the tool to overwrite the contents of filename, if a file by that name already exists. Examples The following example displays the current history list, then saves it in a file called my_history, which already exists.
history -nonumbers add clocks 0 clock set system mode dft setup scan identification sequential atpg -percent 50 run setup scan insertion -seb MY_SEN insert test logic -nolimit report scan chains ripup scan chains -all set system mode setup set system mode dft reset state setup scan identification sequential atpg -percent 50 run insert test logic -max_length 100 report scan chains history -nonumbers save history my_history -replace
Related Commands Dofile History Set Command Editing
269
Command Dictionary Set Bidi Gating
Set Bidi Gating

Scope: Setup mode Usage SET BIdi Gating [OFf | ON | Scan] [-Control {SEn | TEn}] [-Direction {Input | Output}] [-Top {ALl | primary_bidi_pin...}] [-Force_gating] Description Specifies how bidirectional (bidi) pins are controlled during scan chain shifting to prevent potential bus contention or to ensure an on/off state during testing. When enabled, test logic is inserted for bidi pins as necessary to control the enable signal and/or the input/output direction as specified. By default, when the enable signal of a bidi pin is directly controlled by a primary input, by TIE0, or by TIE1, no gating is necessary and a force statement for the primary input is added to the load_unload procedure in the new procedure file. This behavior can be overridden by using the -Force_gating switch. You can also specify which enable signal (TEN or SEN) enables bidi pins. Arguments OFf | ON | Scan Required literal that specifies whether to insert test logic to control the enable lines of bidi pins during scan chain shifting. For more information on scan chain shifting, see Enabling Test Logic Insertion in the Scan and ATPG Process Guide. Literal options include: OFf no test logic is inserted to control bidi pins. Default setting. ON test logic is inserted as necessary to control bidi pins. Scan inserts test logic on the scan I/O bidi pins to control the direction of the bidi pin for scan shifting and ensure the success of scan chain tracing. Scan output bidi pins are gated to be in output mode while all other bidi pins are gated to be in input mode (Z state on the tester). -Control SEn | TEn An optional switch and literal pair that specifies the enable signal used to control bidi pins. Options include: SEn scan_enable signal. Default setting. TEn test_enable signal. -Direction Input | Output An optional switch and literal pair that specifies the direction of the bidi pins specified by the -Top switch. Options include: Input bidi pins are gated so they are in input mode. Default setting. Output bidi pins are gated so they are in output mode.
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Command Dictionary Set Bidi Gating
-Top ALl | primary_bidi_pin... An optional switch and literal or repeatable string pair that specifies which bidi pins are controlled with the specified enable signal. Options include: ALl all bidi pins. Default setting. primary_bidi_pin a specified primary bidi pin. Test logic is inserted to ensure that these bidi pins are controlled as specified.
-Force_gating An optional switch that adds test logic to the enable lines of bidirectional pins that are directly controlled by primary inputs, by TIE1, or by TIE0. When the enable line is directly controlled by a primary input, DFTAdvisor adds the force statement for this primary input to the load_unload procedure in the procedure file.
Example 1 The following example uses the Set Bidi Gating command to insert test logic to control all bidi pins used for scan I/O via the SEN signal, and reports the gated bidi pin.
add clocks 0 clk setup scan identification full_scan set tristate gating on set bidi gating scan add scan pins c1 bidi_in1/X blkB1/blkA/utri2/A -top io out1 set system mode dft report dft check -full ------------------------------------------------------------------------Bidi Primitive Control Control Tri-state State Direction Gating ID Signal Driver ------------------------------------------------------------------------/bidi_in1 OFF IN YES 20 SEN /or2/Y /blkB1/blkA/utri3 OFF -YES 15 SEN /udff0/Q /blkB1/blkA/utri2 ON -YES 17 SEN /or2/Y /blkB1/blkA/utri1 OFF -YES 16 SEN /or2/Y -------------------------------------------------------------------------
Example 2 The following example uses the force_gating switch to insert gating logic controlled by the TEN control signal on the enable line of /uio1 and reports the gated tri-state devices. /uio1 is a bidirectional device driving primary inout port dinout[1]; its enable signal is directly controlled by the primary input /io_control1.
set bidi gating on -control ten -direction input -top dinout[1] -force_gating report dft check -tri
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Command Dictionary Set Bidi Gating ----------------------------------------------------------------------Bidi Primitive Control Control Tri-state State Direction Gating ID Signal Driver ----------------------------------------------------------------------/uioM OFF IN YES 84 TEN /udff20/QB /uio3 ON OUT YES 77 SEN /io_control /uio2 OFF IN NO 76 SEN /io_control /uio1 OFF IN YES 75 TEN /io_control1 /uio0 OFF IN NO 73 SEN /io_control -----------------------------------------------------------------------
Related Commands Report Dft Check Report Test Logic Report Control Signals Set Test Logic Set Tristate Gating
272
Command Dictionary Set Capture Clock
Set Capture Clock

Scope: All modes Usage SET CApture Clock primary_input_pin [-Atpg] Description Specifies the capture clock name for random pattern simulation. The Set Capture Clock command specifies the name of the capture clock that the tool uses during random pattern simulation. You can specify the name of either a specific pin or a clock procedure in a test procedure file that identifies the pin. In either case, the pin must be a currently defined clock pin. Also, the capture clock that you specify cannot have a pin constraint. If you do not specify a capture clock with this command, DFTAdvisor sets the capture clock to none. If there is no capture clock and there is only one clock in the circuit that is not a set or reset line, DFTAdvisor sets that clock as the capture clock during rules checking and displays a warning message that identifies the capture clock. You can use the Report Environment command to list the capture clock and the Report Clocks command to identify the current list of clocks. Arguments primary_input_pin A string that specifies the name of the primary input pin that you want to assign as the capture clock. clock_procedure_name A string that specifies the name of the clock procedure in the test procedure file that identifies the primary input pin that you want to assign as the capture clock. -Atpg An optional switch that specifies for the tool to use the capture clock for all scan patterns it creates during the ATPG process, and places in the internal pattern set. Examples The following example specifies a capture clock:
add clocks 1 clock1 set capture clock clock1 set system mode dft
Related Commands Add Clocks Delete Clocks Report Clocks Report Environment
273
Command Dictionary Set Command Editing
Set Command Editing

Scope: All modes Usage SET COmmand Editing -Off | -Vi | -Emacs | -Gmacs Description Sets the command line editing mode. Upon invocation, the command line editing mode is set to emacs, regardless of any VISUAL or EDITOR environment variables. When you issue this command, the tool changes the editing mode without affecting your UNIX environment variables or settings. You can also turn off command line editing. Arguments -Off | -Vi | -Emacs | -Gmacs A required switch that specifies the command line editing mode. -Off Turns command line editing off. -Vi Sets vi as the command line editing mode. -Emacs Sets emacs as the command line editing mode. -Gmacs Sets gmacs as the command line editing mode. Examples The following example sets the command line editing mode to vi within the tool:
set command editing -vi
Related Commands History Save History
274
Command Dictionary Set Contention Check
Set Contention Check

Scope: All modes Usage SET COntention Check OFf | {ON [-ATpg] [-Start frame#]} [-Bus | -Port | -ALl] Description Specifies whether DFTAdvisor checks the gate types that you determine for contention. The Set Contention Check command specifies whether contention checking is on and the conditions under which the tool performs the checks. When contention checking is on, DFTAdvisor checks for contention during the ATPG-based identification run. Contention checking is set to On upon invocation of the tool. Arguments OFf | ON A literal that specifies whether the tool should perform contention checking, during simulation, without propagating captured data effects. The invocation default behavior is On. -ATpg An optional switch that specifies for DFTAdvisor to use deterministic fault simulation when identifying non-scan cells. -Start frame# An optional switch and integer pair that specifies the number of timeframes after design initialization when DFTAdvisor begins the contention check. The default is time frame 0. Due to sequential initialization, the initial states on a bus may be unknown, and possible contention may be unavoidable. Thus, this switch allows you to begin the contention checking after the design has initialized. -Bus An optional switch that specifies for DFTAdvisor to perform contention checking tri-state driver buses. This is the default. Tri-state logic allows several bus drivers to time share a bus. However, if the circuit enables two bus drivers of opposite logic to drive the bus, physical damage can happen. This switch allows the tool to identify these conditions and notify you of their existence. -Port An optional switch that specifies for DFTAdvisor to perform contention checking for multiple-port flip-flops and latches. The tool identifies any multiple-port latch or flip-flop that has more than one clock, set, or reset input active (or at X).
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Command Dictionary Set Contention Check
-ALl An optional switch that specifies for DFTAdvisor to perform contention checking for both tri-state driver buses and multiple-port flip-flops and latches.
Examples The following example performs contention checking on both multiple-port sequential gates and tri-state buses, stops the simulation if any bus contention occurs, and displays an error message that will indicate the gate on which the contention occurred:
set system mode dft set contention check on -all run
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Command Dictionary Set Display
Set Display
Scope: All modes Usage SET DIsplay display_name Description Sets the DISPLAY environment variable from the tools command line. The Set Display command sets the DISPLAY environment variable to display_name without exiting the currently running application. If you invoke the tool in command line mode (the default), then the DISPLAY variable is not required in order to use most commands successfully. Note This command effects the DISPLAY setting within the currently running application only. When you exit the tool, the setting in the invocation shell will be what it was when you invoked the tool. Arguments display_name A required string that specifies a valid display setting for the machine on which the tool is running. Examples The following example sets the DISPLAY variable. The example also uses the System command to pass a UNIX echo $DISPLAY command to the shell in order to check the variables setting.
system echo $DISPLAY set display my_workstation:0.0 system echo $DISPLAY my_workstation:0.0
Related Commands System
277
Command Dictionary Set Dofile Abort
Set Dofile Abort

Scope: All modes Usage SET DOfile Abort ON | OFf | Exit Description Lets you specify that the tool complete processing of all commands in a dofile regardless of an error detection. By default, if an error occurs during the execution of a dofile, processing stops, and the line number of the error in the dofile is reported. The Set Dofile Abort command lets you turn this functionality off so that the tool continues to process all commands in the dofile. Arguments ON A required literal that halts execution of a dofile upon detection of an error. This is the default upon invocation of the tool. OFf A required literal that forces dofile processing to complete all commands in a dofile regardless of error detection. Exit A required literal that directs the tool to exit if it detects an error while executing a dofile. Use this setting to prevent a batch job from hanging at the application prompt when an error occurs in a dofile. Examples The following example sets the Set Dofile Abort command off to ensure that all commands in test1.dofile are executed.
set system mode dft set dofile abort off dofile test1.dofile
Related Commands Dofile
278
Command Dictionary Set DRC Handling
Set DRC Handling

Scope: Setup and Dft modes Usage SET DRc Handling rule_id [Error | Warning | NOTe | Ignore] [NOVerbose | Verbose] [NOAtpg_analysis | Atpg_analysis] [-Mode {Sequential | Combinational}] [-Cross_clock_domain] Description The Set DRC Handling command specifies how design rule violations are handled for RAM, Clock, Data, Extra, Procedure file, and Trace rules. You can specify that the violation messages for these checks be either error, warning, note, or ignore. Note The Set DRC Handling command does not support the scannability (S) rules except for the S3 and S5 rules. Unlike the other DRC rules, setting the handling type to Error does not turn on the transcript verbosity for the S3 rule. The verbosity can only be turned on via the optional literal verbose. The Set DRC Handling command does not support any (F )rules. Use the Set Flatten Handling command to specify how design rule violations are handled for (F) rules. Each design rule has an associated occurrence message and summary message. The tool displays the occurrence message only for either error conditions or if you specify the Verbose option for that rule. The tool displays the rule identification number in all rules violation messages. The Atpg_analysis option provides full test generation analysis when performing rules checking for some clock (C) rules, for some data (D) rules, and for some extra (E) rules. For example, if you specify Atpg_analysis for clock rule C1 and the tool simulates a clock input to be X, the rule violation occurs when it is possible for the test generator to create a test pattern while that clock input is on, all defined clocks are set off, and constrained pins are set to their constrained state. Note When you specify Atpg_analysis, the tool requires some additional CPU time and memory to perform the full test generation analysis. (The Atpg_analysis option is enabled by default for rules C1, E4, E10, E11 and E13; you can disable it for these rules by specifying the Noatpg_analysis option.) Arguments rule_id A required literal that specifies a design rule.
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The design rule violations and their identification literals are divided into the following seven groups: RAM, Clock, Data, Extra, Procedure, Scannability, and Trace rules violation IDs. For a complete description of the RAM design rule IDs, refer to the RAM Rules section in the Tessent Common Resources Manual for ATPG Products. For a complete description of the Clock design rule IDs, refer to the Clock Rules section in the Tessent Common Resources Manual for ATPG Products. For a complete description of the Data design rule IDs, see the Scan Cell Data Rules section in the Tessent Common Resources Manual for ATPG Products. For a complete description of the Extra design rule IDs, refer to the Extra Rules section in the Tessent Common Resources Manual for ATPG Products. For a complete description of the Procedure design rule IDs, refer to the Procedure Rules section in the Tessent Common Resources Manual for ATPG Products. The violation handling for Procedure rules can only be set to ignore or error. For a complete description of the Scannability design rule IDs, refer to Scanability Rules (S Rules) in the Tessent Common Resources Manual for ATPG Products. For a complete description of the Trace design rule IDs, refer to the Scan Chain Trace Rules section in the Tessent Common Resources Manual for ATPG Products.
Error
An optional literal that both displays the error occurrence message and immediately terminates the rules checking. Warning An optional literal that displays a warning summary message to indicate the number of times the rule was violated. If you also specify the Verbose option, the tool also displays the occurrence message for each occurrence of the rules violation. NOTe An optional literal that displays a summary message to indicate how many times the rule was violated. If you also specify the Verbose option, the tool also displays the occurrence message for each occurrence of the rules violation. Ignore An optional literal that disables the display of any messages when the specified rule is violated. The tool must still check some rules and they must pass to allow certain functions to be performed later. NOVerbose An optional literal that displays the occurrence message only once for the rules violation. This is the default.
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Verbose An optional literal that displays the occurrence message for each violation of a design rules. NOAtpg_analysis An optional literal that disables full test generation analysis when performing rules checking. This is the default.
Atpg_analysis An optional literal that enables full test generation analysis when performing rules checking for clock rules (like C1, C3, C4, and C5), some D rules (like D6 and D9), and some E rules (like E4, E5, E8, E10, E11, and E12). Note To use the constraint values during the D6 rule analysis, you need to use the Atpg_analysis option.
-Mode {Combinational | Sequential} An optional switch and literal for the E10 rule. The Combination option is the default upon invocation of DFTAdvisor. It performs bus contention mutual-exclusivity checking. This checking differs from rule E4 in that it does not check for this condition during test procedures. The Sequential option considers the inputs to a single level of sequential cells behaving as staging latches in the enable lines of tri-state drivers. All of the latches found in a back trace must share the same clock. There must also be only a single clocked data port on each cell, and both set and reset inputs must be tied (not pin constrained) to the inactive state. This check ensures that there is no connectivity from the cells in the input cone of the sequential cells and enables of the tri-state devices except through the sequential cells.
-Cross_clock_domain A switch that specifies to report violations during C6 analysis when the data path of a flipflop is driven by a different top-level clock signal than the clock that is driving the clock port.
Examples The following example specifies rule checking E4 to be an error:

add scan groups group1 scanfile add scan chains chain1 group1 indata2 outdata4 add clocks 1 clock1 add clocks 0 clock2 set drc handling e4 error set system mode dft
Related Commands Report DRC Rules Set Flatten Handling
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Command Dictionary Set Fault Sampling
Set Fault Sampling

Scope: All modes Usage SET FAult Sampling percentage Description The Set Fault Sampling command specifies the fault sampling percentage used for scan identification. By default, all faults (100 percent) in the internally generated fault list for scan identification are used. Fault sampling allows you to use a fraction of the total faults and decrease processing time for large circuits. Once a percentage is specified, a sample is randomly selected. Arguments percentage A required positive integer from 1 to 100 that specifies the fault sampling percentage that you want DFTAdvisor to use for scan identification. The invocation default is 100 percent. Examples The following example performs scan identification with only 50 percent of the internally generated fault list.
add clocks 0 clock set system mode dft set fault sampling 50 run report sequential instances
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Command Dictionary Set File Compression
Set File Compression

Scope: All modes Usage SET FIle Compression [ON | OFf] Description Controls whether the tools read and write files with .Z or .gz extensions as compressed files (the default). Files that contain large pattern sets consume a very large amount of disk space. Fault lists and the design data itself also take up a lot of disk space. To conserve this space, the tools normally store files in one of two compressed formats when you provide a filename with the appropriate extension, as follows: .Z specifies to compress the file using the UNIX compress command. .gz specifies to compress the file using the GNU gzip command. You can control the type of GNU compression with the Set Gzip Options command.
When compressed file handling is enabled and you provide a filename with either of the above extensions, a tool will automatically decompress (for reading) or compress (for writing) the specified file. The Set File Compression command allows you to turn off the tools normal compressed file handling functionality. This is useful in rare cases where files have either of the compressed file extensions, but should not be saved or read as compressed files. Arguments ON An optional literal that enables compressed file handling. This is the default. OFf An optional literal that disables compressed file handling. When set to off, the tools process .Z or .gz files without using compression. Examples Suppose the file testpat.ascii.gz is not a compressed file. The following example disables compressed file handling so the tool will read testpat.ascii.gz as a normal file rather than as a compressed file:
set file compression off
The next example re-enables compressed file handling, then saves the file fault.pat in GNU format:
set file compression on write netlist verilog.scan.gz -verilog
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Command Dictionary Set File Compression
Related Commands Set Gzip Options
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Command Dictionary Set Flatten Handling
Set Flatten Handling

Scope: All modes Usage SET FLatten Handling rule_id [Error | Warning | NOTe | Ignore] [Verbose | NOVerbose] Description Specifies how DFTAdvisor globally handles flattening violations. The Set Flatten Handling command specifies the handling of the messages for net flattening, pin flattening, and gate flattening. You can specify that the violation messages for these checks be either error, warning, note, or ignored. Each rules violation has an associated occurrence message and summary message. The tool displays the occurrence message for error conditions, or if you specify the Verbose option for that rule. The tool displays the rule identification number in all rules violation messages. Arguments rule_id A required literal that specifies the identification of the exact flattening rule violations whose message handling you want to change. The flattening rule violations and their identification literals divide into the following three groups: net, pin, and gate rules. Net flattening violations are described in sections FN1 through FN9 of the Tessent Common Resources Manual for ATPG Products. Pin flattening violations are described in sections FP1 through FP13 of the Tessent Common Resources Manual for ATPG Products. Gate flattening violations are described in sections FG1 through FG8 of the Tessent Common Resources Manual for ATPG Products.
Error An optional literal that specifies for the tool to both display the error occurrence message and immediately terminate the rules checking.
Warning An optional literal that specifies for the tool to display the warning summary message indicating the number of times the rule was violated. If you also specify the Verbose option, the tool also displays the occurrence message for each occurrence of the rules violation.
NOTe An optional literal that specifies for the tool to display the summary message indicating the number of times the rule was violated. If you also specify the Verbose option, the tool also displays the occurrence message for each occurrence of the rules violation.
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Command Dictionary Set Flatten Handling
Ignore An optional literal that specifies for the tool to not display any message for the rules violations. The tool must still check some rules and they must pass to allow certain functions to be performed later.
NOVerbose An optional literal that specifies for the tool to only display the occurrence message once for the rules violation and to give a summary of the number of violations. This is the default.
Verbose An optional literal that specifies for the tool to display the occurrence message for each occurrence of the rules violation.
Example The following example changes the handling of the FG7 flattening rule to warning and specifies that each occurrence should be listed:
set flatten handling fg7 warning verbose
Related Commands Report Flatten Rules Set DRC Handling
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Command Dictionary Set Gate Level
Set Gate Level

Scope: All modes Usage SET GAte Level Primitive | Design | Low_design Description Specifies the hierarchical level of gate reporting and displaying. The Set Gate Level command specifies the hierarchical gate level at which the tool reports. Once you set the gate level, the tool processes all subsequent report and display commands using the new gate level. Whenever you issue a command that invalidates the flattened model, the tool also invalidates the hierarchical gate display structure. You can rebuild the hierarchical gate structure by creating a new, flattened model. To do so, enter and exit the Setup mode. Arguments Primitive A literal that specifies to display gate information at the built-in primitive gate level. Design A literal that specifies to display gate information at the design library hierarchical gate level. These are the top level cells of the design library instantiated in your design. This is the default upon invocation of the tool. Low_design A literal that specifies to display gate information at the pseudo-hierarchical gate level. A pseudo-hierarchical gate is a cluster gate that contains primitive gates and is at the lowest hierarchy level in the design library. These gates only differ from design-level gates if the library contains macro cells. Examples The following example sets the gate report level so that simulated values of the gate and its inputs are shown (assuming a rules checking error occurred when exiting the Setup system mode):
add clocks 0 clock set system mode dft set gate level primitive set gate report error_pattern report gates i_1006/o
Related Commands Report Gates Set Gate Report
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Command Dictionary Set Gate Report
Set Gate Report

Scope: All modes Usage SET GAte REport {Normal | Trace | Error_pattern | {PATtern_index pattern_index [-Internal | -External]} | {Parallel_pattern pattern_number} | Fault_status | Test_data | TIe_value | Constrain_value | {Drc_pattern {{Test_setup [{{-Cycle | -Time} n1} [n2 | End]]} | Load_unload | SHIft | SKew_load | SHADOW_Control | Master_observe | SHADOW_Observe | STate_stability} [-All | time]} [-False_paths {ON | OFf}] Description The Set Gate Report command customizes the gate report produced by the the Report Gates command. By default the gate report contains netlist information. This command allows you to add test pattern and simulation information to the gate report. Note When you exit the Setup system mode, the trace and any rules-checking error pattern results are unavailable to this command. Arguments Normal A literal that specifies only default information is in the gate report. Trace A literal that adds the simulated values of the gates for shift patterns to the gate report. Use the Trace option to determine why a scan chain was not properly sensitized during the shift procedure. Error_pattern A literal that adds the inputs and simulated values of the gates for patterns with audit error to the gate report. PATtern_index pattern_index [-Internal | -External] A literal, integer, and optional switch triplet that specifies the pattern to use when displaying the value of a gate. The pattern_index must be a non-negative integer. Depending on whether the tool is set up for primitive or design level gate reporting, you may see additional information as follows (use the Report Environment command to check the current gate level): Primitive level (Set Gate Level Primitive): If a reported sequential element is part of a scan cell, and the value captured by the element is not what is observed/unloaded from the scan cell for that particular pattern, the display shows Unobs next to the captured value and explanatory text is included indicating which element is observed for that scan cell and that pattern. Unobs and
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extra explanatory text is displayed, for example, if you report on the slave latch within an LSSD scan cell and the test procedure file includes a master_observe procedure (the slave is not observed when a master_observe procedure exists). Note When reporting gates at the primitive level, the tool displays captured/unload values only for the outputs of DFF and LA primitives, both scan and non-scan. Captured/unload values are not reported for transparent latches (TLAs). Design level (Set Gate Level Design): If the sequential element reported is a scan cell and an output value resulting from capture does not correspond to what is observed/unloaded from the scan cell for that particular pattern, the display shows Unobs next to the captured value. Explanatory text is not displayed for these Unobs values. For examples of captured/unload displays for different scan cells and reporting levels (primitive or design), see the Examples section. If, after setting the gate report with this option, you alter the tool environment (for example by issuing a Set Clock_off Simulation or Set Split Capture_cycle command), be sure to reissue the set gate report command. This will cause the tool to re-simulate the patterns, ensuring the values reported for a gate are up to date with the latest tool settings. -Internal An optional switch that specifies an internal pattern set. This is the default. -External An optional switch that specifies an external pattern set. Parallel_pattern pattern_number Note Use this option only if another command directs you to use it; for example, the Analyze Bus command might transcript a message that explicitly says to use set gate report parallel_pattern 0. If you use this option, be sure Report Gates is the first command you enter after simulation; bogus simulation values may be reported if you enter any other tool command after simulation, but before you report gates. You should use the Pattern_index argument to specify a pattern for the Report Gates command to use when displaying the value of a gate. A literal and integer pair that specifies the pattern number from the last simulation pass that you want the Report Gates command to use when displaying the value of a gate. For 32-bit invocations, the pattern_number must be an integer between 0 and 31. For 64-bit invocations, the pattern_number must be an integer between 0 and 63. With Set Clock_off Simulation on, Set Split Capture_cycle on, and the Set Gate Report command set with the Parallel_pattern option, the gate report displays three values. The first is the result of the analysis for clock_off simulation. The second is the value at the leading
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edge of the clock. Finally, the third is the trailing edge of the clock (for split capture_cycle analysis). When reporting a sequential element (scan or nonscan), the command also displays in a pair of brackets ([ ]) at each output of the element, the value that resulted from capture. If set up for primitive level gate reporting (Set Gate Level Primitive), the tool displays captured values only for the outputs of DFF and LA primitives. Captured values are not reported for transparent latches (TLAs). Fault_status A literal that specifies fault detection status of both SA-0 and SA-1 of all gates. If a schematic is currently displayed in the DFTVisualizer Debug window and you change the gate report data (by issuing the Set Gate Report command), all fault sites are annotated with fault detection status. The format of the fault status data is as follows: <sa0-status:sa1-status> where sa0-status and sa1-status are one of the following: DS Detected by simulation DI Detected by implication PU Possible detect untestable PT Possible detect testable AU Atpg untestable UC Undetected uncontrolled UO Undetected unobserved UU Untestable unused BL Untestable blocked TI Untestable tied RE Untestable redundant F Recognized fault site, but no fault has been added yet N Site is nofaulted; either due to internal faults being on or off depending on where the fault site is), or because a user has nofaulted it with the Add Nofaults command. - Nothing known about this pin; used for pins created by the flattening process or pins that are not fault sites (for example, the pins of an unnamed internal instance of a library cell). The DFTVisualizer command, Report Display Instances, reports the fault detection status in the transcript.
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Test_data A literal that specifies previously-calculated control and observe values. You must specify the Test_data option prior to running design rules checking to make test data available. This option is primarily for logic BIST purposes (when inserting control and observation points). It is typically used with the Analyze Control Signals and Analyze Output Observe commands. The data for each pin of a reported gate consists of three integers indicating how many times the pin was controllable to 0, how many times it was controllable to 1, and how many times it was observable during the preceding analysis. The data is displayed in the following format: (# of times controlled to 0-# of times controlled to 1, # of times observed) Note When the Test_data option is in effect, the Report Environment command shows BIST data as the current gate report setting.
TIe_value A literal that adds the simulated values that result from all natural tied gates and learned constant value non-scan cells to the gate report.
Constrain_value A literal that adds the simulated values that result from all natural tied gates, learned constant value non-scan cells, constrained pins, and constrained cells to the gate report. The Report Gates command displays three values which are separated by a slash (/). These values are the gate constrained value (0, 1, X, or Z), the gate forbidden values (-, 0, 1, Z, or any combination of 01Z), and the fault blockage status (- or B, where B indicates all fault effects of this gate are blocked).
Drc_pattern procedure_name [-All | time] Two literals and an optional time triplet that specifies the name of the procedure and the time in the test procedure file that the Report Gates command uses to display a gatessimulated value. The valid options for use with Drc_pattern are as follows: procedure_name A literal that specifies a procedure in the test procedure file for the Report Gates command to use when displaying the value of a gate. The valid literals for the procedure_name option are as follows: Test_setup A literal that specifies the use of the test_setup procedure. In the test procedure file, this procedure sets non-scan elements to the state you desire for the load_unload procedure. The tool uses the entire test_setup procedure unless you restrict the report to a certain portion using the -Cycle or -Time switch. In order to conserve screen width, time values are listed vertically in Test_setup gate reports.
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-Cycle | -Time n1 A switch and integer pair that specifies to use the part of the test_setup procedure that begins either at a particular cycle or at a particular time. The following describes each of the arguments in more detail: -Cycle A switch that indicates n1 is a cycle number and specifies to start the report at cycle n1. -Time A switch that indicates n1 is a time and specifies to start the report at time n1. The time units are based on the timescale defined in the test procedure file, which by default is 1 nanosecond. n1 An integer that specifies a cycle or time at which to start reporting. When used with the -Time switch, n1 specifies a time.When used with the -Cycle switch, n1 specifies a cycle. The tool numbers cycles beginning with 0; so, for example, to specify the second cycle, you would use -cycle 1. n2 An optional integer that specifies to report from cycle (or time) n1 to cycle (or time) n2 and stop reporting. End An optional literal that specifies to report from cycle (or time) n1 to the end of the test_setup procedure. Note When using the -Cycle or -Time switch, if you do not include either the n2 or End argument, gate reports will show data for only the n1 cycle (or time). Load_unload this required procedure describes how to load and unload data in the scan chains. SHIft this required procedure describes how to shift data one position down the scan chain. SKew_load this optional procedure describes how to propagate the output value of the preceding scan cell into the master memory element of the current cell (without changing the slave) for all scan cells. SHADOW_Control this optional procedure describes how to load the contents of a scan cell into the associated shadow. Master_observe this procedure describes how to place the contents of a master into the output of its scan cell. SHADOW_Observe this optional procedure describes how to place the contents of a shadow into the output of its scan cell. -All An optional switch that specifies to use all times in the test procedure file. This is the default. time An optional positive integer greater than 0 that specifies a time in the test procedure file.
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-False_paths [ON | Off] An optional switch and literal pair that enables or disables the reporting of false path information for the Report Gates command and the DFTVisualizer Debug window. The two -False_paths options are as follows. ON False path information is reported by the Report Gates command and displayed in the Debug window. This option is only effective during non-Setup mode. When you enable this switch, any subsequent issuance of the Report Gates command can include one or more of the following false path-related keywords: Fr: Indicates the launch/start point of a false path. To: Indicates the capture/end point of a false path. Th: Indicates points along a false path. In: Indicates points along the intersection of multiple false paths. Ef: Indicates points in a false path effect cone. : Indicates points that are not part of any false path. OFf False path information is not reported by the Report Gates command. Because the -false_paths argument does not reset the previously-specified gate report option, you can use this argument in conjunction with other Set Gate Report settings.
Example 1 The following example sets the gate report so that simulated values of the gate and its inputs are shown (assuming a rules checking error occurred when exiting the setup system mode):
set gate report trace set system mode dft report gates I_1006/O
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Example 2 The following example illustrates how to use the Report Gate command to trace the transition of the pattern along the false paths. In this example, false path and an internal pattern simulation values are reported.
ATPG> set gate report false_paths on ATPG> set gate report pattern_index 1 ATPG> report gates /ix21/UD1 ATPG> rep gat /ix21/UD1 // /ix21/UD1 (36) DFF Functional Specification for New ATPG Kernel Rev. 0.1 Page: 8 Date Modified: 1/20/09 9:49 PM // "S" I (0-0)(--) 6// "R" I (0-1)(--) 20// "C0" I (1-0)(--) 10// "D0" I (1-1)(To) 32// "OUT" O (1-1 [0])(In/Ef) 9// MASTER cell_id=2 chain=chain1 group=grp1 invert_data=FFFT ATPG> f // /ix21/UD1 (9) BUF // "I0" I (1-1)(Fr/Ef) 36// "OUT" O (1-1)(In) 18- 19ATPG> f // /ix21 (18) BUF // "I0" I (1-1)(In) 9// Q O (1-1)(To) 28-/fdgd/A 29-/ix19/A ATPG> f // /fdgd (28) NAND // A I (1-1)(To) 18-/ix21/Q // B I (1-0)(--) 1-/s // Z O (0-1)(Ef) 37-/y[2] ATPG> f // /y[2] (37) PO // "I0" I (0-1)(Ef) 28-/fdgd/Z // y[2] O (0-1)(Ef)
Related Commands Report Gates Set Gate Level
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Command Dictionary Set Gzip Options
Set Gzip Options

Scope: All modes Usage SET GZip Options [-Path gzip_path] [-Fast | -Best | -integer] Description Specifies GNU gzip options to use with the GNU gzip command. The Set Gzip Options command specifies GNU gzip options the tool will use when compressing or decompressing files using the GNU gzip command. When file compression handling is enabled (as described under the Set File Compression command), the tool uses GNU gzip when processing files have a .gz extension. Arguments -Path gzip_path An optional literal that specifies the full path gzip_path to a gzip executable file. You need to provide this pathname only if gzip is not in your normal UNIX search path. If you have specified a pathname with this option, you can restore the default behavior of using your UNIX path to find gzip by issuing the command with the -Path gzip option. The following switches all control the speed of compression: -Fast An optional switch that specifies to use the fastest compression method, which yields the least compression, and corresponds to the gzip -1 option. This is the default. -Best An optional switch that specifies to use the slowest compression method, which yields the most compression. This corresponds to the gzip -9 option. The default compression is -6. -digit An optional switch that specifies an integer from 1 to 9 that the tool passes to gzip to control the rate of compression. You obtain the least amount of compression with -1, the greatest amount of compression with -9. Examples The following example ensures file compression is enabled, sets gzip compression to the fastest method, then saves a file using the .gz file naming extension in order to activate gzip file compression handling:
set file compression on set gzip options -fast write netlist verilog.scan.gz -verilog
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Command Dictionary Set Gzip Options
Related Commands Set File Compression
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Command Dictionary Set Identification Model
Set Identification Model

Scope: Setup mode Usage SET IDentification Model [-Clock {Original | None | Extra}] [-Disturb {ON | OFf}] Description Specifies the simulation model that DFTAdvisor uses to imitate the scan operation during the scan identification process. The Set Identification Model command specifies a simulation model needed to imitate scan operation during scan identification, before real scan chains are inserted. In normal scan operation, after DFTAdvisor loads values into the scan cells, a scan memory element should not change its scan-in value until the loaded value is used. To achieve this scan cell stability, all the clocks of a scan cell should be at their off-state. However, because the implementation of scan chains is not done yet, DFTAdvisor does not yet know its ability to control all the clocks. Therefore, the Set Identification Model command allows you three -Clock options, along with the -Disturb argument, to specify how DFTAdvisor is to handle scan operation during the scan identification process. The scan identification process is performed with the Run command and this is the time when DFTAdvisor selects the non-scan cells that are to be replaced with the corresponding scan cell. If you want to display the current settings for the scan identification model, you can use the Report Environment command. During the scan identification process, DFTAdvisor automatically decides which non-scan cells require extra logic to fix their clock behavior. When DFTAdvisor performs the scan identification, it processes each non-scan cell separately. By default, the scan identification model specifies for DFTAdvisor to use the -Clock Original option for non-scan cells that do not require the extra logic to control its clocks, and the -Clock Extra option for the non-scan cells that do require the extra logic for clock controllability. Arguments -Clock Original | None | Extra An optional switch and literal pair that determines the effect of the clocks on scan memory elements values. The three -Clock options are as follows: Original A literal specifying that scan memory elements operate as their current clock configuration. This is the default for non-scan cells that DFTAdvisor determines do not require extra logic for controllability of that non-scan cells clocks. If you specify this option, then DFTAdvisor does not add any extra logic, and uses the original clock configuration for each non-scan cell on a global design-wide basis. None A literal specifying that after scan loading, scan memory elements can hold their value for one time frame, regardless of their clock values.
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Command Dictionary Set Identification Model
Extra A literal specifying that external controllable clocks replace the original clocks so that the scan cells are capable of holding their scan values right after scan loading. This option is the default for non-scan cells that DFTAdvisor determines do require extra logic for controllability of that non-scan cells clocks. If you specify this option, then DFTAdvisor adds extra logic to every non-scan cell on a global design-wide basis. -Disturb ON | OFf An optional switch and literal pair that determines the effect of scan loading on non-scan memory elements. The two -Disturb options are as follows. ON A literal specifying that the value of the non-scan memory elements can be disturbed by scan loading operations. This is the default. If the disturb option is on, DFTAdvisor sets the states of non-scan memory elements to the unknown (X) state after the scan loading operation. OFf A literal specifying that the value of non-scan memory elements cannot be disturbed by scan loading. When the disturb option is off, the states of the non-scan memory elements are the same as before the scan loading operation. Examples The following example forces DFTAdvisor to add extra primary input pins to replace the original clocks on a global design-wide basis:
set identification model -clock extra set system mode dft setup scan identification full_scan run
Related Commands Report Environment
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Command Dictionary Set Internal Fault
Set Internal Fault

Scope: Setup mode Usage SET INternal Fault ON | OFf Description Specifies whether the tool allows faults within or on the boundary of library models. The Set Internal Fault command specifies whether the tool will allow faults on internal nodes of library models or only on the library model boundary. The default upon invocation of the tool is to allow faults on the internal nodes of library models. Arguments ON A literal that specifies to allow faults on the internal nodes of library models. This is the default upon invocation of the tool. OFf A literal that specifies to allow faults only on the boundary of the library models. Examples The following example invokes the scan identification process such that DFTAdvisor does not take into consideration any internal faults when in calculating the efficiency percentage:
set internal fault off set system mode dft setup scan identification full_scan run
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Command Dictionary Set Internal Name
Set Internal Name

Scope: Setup mode Usage SET INternal Name OFf | ON Description Specifies whether to delete or keep pin names of library internal pins containing no-fault attributes. The Set Internal Name command specifies whether to keep internal library pins with no-fault attributes. Normally, you should delete these names for memory and performance reasons. The default operation (OFF) upon invocation of DFTAdvisor is to delete these names. Arguments OFf A literal that deletes the lowest level pin names if they have the nofault attribute. This is the default upon invocation of DFTAdvisor. ON A literal that keeps the lowest level pin names, even if they have the nofault attribute. Example The following example deletes pin names with the nofault attribute.
set internal name off
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Command Dictionary Set Io Insertion
Set Io Insertion
Scope: All modes Prerequisites: Input and output buffers must be defined in either the ATPG library or with the Add Cell Models command. Usage SET IO Insertion ON | OFf | {[TEn] [Ram] [SEn] [TClks] [SIns] [SOuts] [Control] [OBserve] [-Model model_name]} Description Specifies whether to insert I/O buffers. The Set IO Insertion command specifies whether DFTAdvisor should insert I/O buffers automatically during scan insertion. By having automatic I/O buffer insertion turned off (the default), you can perform scan insertion at the block level, or insert the I/O buffers manually after inserting scan at the design level. If you defined I/O buffers in the ATPG library or used the Add Cell Models command to define them, when you set this command to ON, DFTAdvisor will automatically insert the I/O buffers during scan insertion. You can specify which test control signals should have I/O buffers added. You can specify one or more of the test signal literal arguments. The specified signals can be internal signals (output port of a library cell) or new pins generated by DFTAdvisor. The Set IO Insertion command is additive. This means that each time you issue the command, it adds any new options to those already defined. Arguments ON | OFf A required literal that specifies whether to insert I/O buffers for all test signals. If you are not turning On or Off all test signals, you must specify at least one of the test signal arguments. If you want to remove any existing I/O buffer signals from the list of signals to buffer, you turn off I/O buffer insertion (Set IO Insertion off). The default upon invocation is off. TEn A literal that specifies to buffer the test_enable pin. Ram A literal that specifies to buffer the ram_write_control and ram_read_control pins. SEn A literal that specifies to buffer the scan_enable pin(s). TClks A literal that specifies to buffer all test clock pins, including clock, set, and reset.
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Command Dictionary Set Io Insertion
SIns A literal that specifies to buffer all scan_in pins of inserted scan chains. SOuts A literal that specifies to buffer all scan_out pins of inserted scan chains. No buffer is inserted unless a buffer has been defined with the -Type outbuf option of the Add Cell Models command, or if you have used the -Model switch, and specified a buffer as part of this command.
Control A literal that specifies to buffer all test point control pins, if no scan cell is requested with the Setup Test_point Insertion command.
OBserve A literal that specifies to buffer all test point observe pins, if no scan cell is requested with the Setup Test_point Insertion command.
-Model model_name An optional switch and string pair that specifies the name of a buffer in the ATPG library for DFTAdvisor to insert on the test pins. You must first identify the buffer with either the Add Cell Models command or with the cell_type library attribute. The specified model should be the OUTBUF type for scan outputs and the INBUF type for all scan inputs and test signals. If you do not use the -Model switch, by default, DFTAdvisor uses the first buffer model in the buffer cell model list (which you can see with the Report Cell Models command).
Examples The following example shows how to enable the adding of I/O buffers automatically to all test control signals:
set io insertion on
To enable the adding of I/O buffers to only the scan in, scan out, control, and observe signals, enter:
set io insertion sins souts control observe
Related Commands Add Buffer Insertion Add Cell Models
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Command Dictionary Set Latch Handling
Set Latch Handling

Scope: Setup mode Usage SET LAtch Handling None | Scan Description Specifies whether the tool considers non-transparent latches for scan insertion while test logic is turned on. The Set Latch Handling command specifies whether the tool can consider non-transparent latches as candidates for scan insertion. If you determine that the tool is to consider nontransparent latches as candidates for scan insertion, you must turn on the appropriate Set Test Logic command settings before DFTAdvisor performs the rules checking process. If you use the Set DRC Handling command to set the D6 rule to error or warning, D6 checks the non-scannable latches for transparency. By default, if they are not transparent and you turned test logic insertion on, DFTAdvisor does not consider the non-transparent latches for scan insertion. However, if you use the Scan argument with the Set Latch Handling command, DFTAdvisor will consider the non-transparent latches for scan insertion. If you use the Set DRC Handling command to ignore the D6 rule, then rules checking does not check the non-scannable latches for transparency and DFTAdvisor will automatically consider all non-scannable latches, whose test logic you turned on, for scan insertion. Arguments None A literal that specifies to give no consideration to non-transparent latches for scan insertion. This is the default upon invocation of DFTAdvisor. Scan A literal that specifies to consider non-transparent latches for scan insertion when test logic is turned on. Related Commands Set DRC Handling Set Test Logic
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Command Dictionary Set Lockup Cell
Set Lockup Cell

Scope: All modes Prerequisites: Lockup cell model(s) must be specified with the Add Cell Models command and an inverter model must be specified with the Add Cell Models command or cell_type model attribute. Usage SET LOckup Cell {OFf | ON} [-First_clock | -SEcond_clock] [-Type {DLat | DFf}] [-CApture_edge_at_scan_chain_input {LE | TE | ANY}] [-CHange_edge_at_scan_chain_output {LE | TE | ANY | OFF} [{ALL | WRApper}]] Description The Set Lockup Cell command enables the automatic insertion of lockup cells. You can insert the lockup cells at the beginning/end of each scan chain or between all scan cells in different clock/edge domains. The lockup cells are inserted only on the scan path and do not interfere with the functional operation of the design. Lockup cells are inserted at each transition of the different clock domains and at the transition of active-high to active-low edge domains. The edge domain of a scan cell is determined by the combined effect of the following parameters: The off-state value of the feeding top-level clock, which is defined by the Add Clocks command. The overall inversions along the clock path, from the clock pin of the scan cell to the top level clock pin. The inversions on the clock path within the scan cell library model, which is defined by using the clock input attribute statement and/or _inv primitives in the library model definition.
Lockup cell and inverter models must be defined in the DFT library before they can be used in lockup cell insertion. Also, a lockup cell model of type DLAT or DFF must be specified using the Add Cell Models command. You must use the -Active switch to specify the overall signal inversion on the enable pin of the latch (or the clock pin of the flip-flop) inside the library model. DFTAdvisor does not examine or simulate the implementation of the lockup model to determine if it is an active high or active low cell. In the following example, the overall inversion on the enable pin is active high. For more information, see the Add Cell Models command.
model lockup (D, CLK, Q, QB) ( cell_type = DFF CLK D; input (D) () input (CLK) (clock = fall_edge;) intern(CLKn) (primitive = _inv (CLK, CLKn);) output(Q, QB) (primitive = _dff(, , CLKn, D, Q, QB);) )
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If a cell order file is used with the Insert Test Logic command, lockup cells are inserted only at the locations specified in the cell order file. If you are using a DLAT model as a lockup cell, you must specify the model type using the Add Cell Model command. If you are using a DFF model as a lockup cell, you must specify the model type using the Set Lockup Cell command because it is the only way to specify the type of library model to use for lockup cells. Using the Set Lockup Cell command also turns on the reporting of those locations that require lockup cells in theory but are not covered in the the cell order file. If no lockup cell location is specified in the cell order file, the tool inserts lockup cells automatically at the required locations. For more information, see the Insert Test Logic command. Table 2-7 illustrates how DFTAdvisor inserts lockup cells at different clock/edge domains. Table 2-7. Lockup Cell(s) Used Between Different Clock/Edge Transitions Clock/Edge Transition c1+ --> c2+ c1+ --> c2+ c1+ --> c2+ c1- --> c2c1- --> c2c1+ --> c2c1- --> c2+ Lockup Cell Models Defined lat+ latlat+, latlat+ latlat+, latlat+, latLockup Cell Inserted c1+ --> (lat+ + inv) --> c2+ c1+ --> (lat-) --> c2+ c1+ --> (lat-) --> c2+ c1- --> (lat+) --> c2c1- --> (lat- + inv) --> c2c1+ --> (lat-) --> c2c1- --> c2+ (no lockup)
The first column lists a clock/edge transition where an active high-clock 1 to an active-low clock 2 is shown as c1+ --> c2-. The second column lists the lockup cell models defined in the DFT library where lat+ is an active-high model and lat- is an active-low model. The third column lists the transitions after lockup cell insertion where the lockup cell inserted is listed in the parenthesis. A lockup cell labeled as (lat+ + inv) in the table indicates that a lockup model is inserted in the scan path and an inverter is inserted on the clock line of the lockup cell to provide a half cycle delay. In Table 2-7, it is assumed that the clock signal is tapped from the clock input of the leading flop. The inverter is used when an active low model is needed but not defined. DFTAdvisor can also insert lockup cells at the non-transition locations in a chain, namely, at the beginning and at the end of the chain. The -Capture_edge_at_scan_chain_input switch provides the ability to control the time when the first cell of the scan chain captures a value. To guarantee a capture edge (specified with LE or TE argument) at the first cell in chain, DFTAdvisor inserts a lockup cell before the first cell in the chain (closer to the scan chain input) if the first cell has the opposite capture edge. If the ANY argument is specified, DFTAdvisor always inserts a lockup cell at the beginning of the chain with the opposite capture edge of the first cell. The tool uses the clock signal of the first cell with the opposite clock edge when a DLAT model is used and with the same clock edge when a DFF model is used for a lockup cell. Note that the capture
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and the change edges for a DLAT model are the opposite, whereas for a DFF model, they are the same. For example, for an active high DLAT model, the capture edge is trailing (TE) and the change edge is leading (LE). Similarly, for a leading edge DFF model, the capture and change edges are both leading (LE). The Change_edge_at_scan_chain_output switch provides the ability to control the change time at the output of the last scan cell in the chain. To guarantee a change edge (specified with LE or TE argument) at the last cell in chain, DFTAdvisor inserts a lockup cell after the last cell in the chain (closer to the scan chain output) if the last cell has the opposite change edge. If the ANY argument is specified, DFTAdvisor always inserts a lockup cell at the end of the chain with the opposite change edge of the last cell. The tool uses the clock signal of the last cell with the opposite clock edge regardless of the latch model being used (DLAT or DFF) for a lockup cell. Lockup cells are inserted based on the change edge of the source cell clock and the capture edge of the destination clock. For a lockup cell that will be inserted at the beginning of a scan chain, the source cell does not exist and therefore the capture edge of the destination cell (first cell in chain) is specified. Similarly, for lockup cell that will be inserted at the end of a scan chain, the destination cell does not exist and the change edge of the source cell (last cell in chain) is specified. The lockup cells between two cells within the scan chain are inserted automatically by DFTAdvisor since both source and destination cells are available. For more information on change edge and capture edge, refer to Lockups Between Decompressor and Scan Chain Inputs in the Tessent TestKompress Users Guide. For more information on inserting lockup cells, refer to Merging Chains with Different Shift Clocks in the Scan and ATPG Process Guide. Arguments OFf | ON A required literal that determines whether lockup cells are inserted. By default, lockup cells are inserted. -First_clock | -SEcond_clock An optional switch that determines which clock signal the lockup cells use. Options include: -First_clock clock signal is tapped from the clock input of the scan cell closer to the scan chain input. By default, the first clock is used. -SEcond_clock clock signal is tapped from the clock input of the scan cell closer to the scan chain output. -Type {DLat | DFf} Optional switch and literal pair that specifies the type of model used for a lockup cell. Options include: DLat Specifies D latch with two input pins (enable and data). DFf Specifies a D flip-flop with two input pins (clock and data).
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-CApture_edge_at_scan_chain_input {LE | TE | ANY} Optional switch and literal pair that determines whether a lockup cell is inserted between the first scan cell and the scan input pin of scan chains. This switch allows you to control the capture edge used by the first scan cell. Options include: LE lockup cell is inserted to ensure that the first scan cell captures data on the leading edge. TE lockup cell is inserted to ensure that the first scan cell captures data on the trailing edge. ANY lockup cell is inserted independently from the capture edge of the first scan cell. If a DFF model is to be used as a lockup cell, the clock signal obtained from the first scan cell in chain is inverted before connecting it to the clock input of the lockup cell. If a DLAT model is used, on the other hand, the clock signal is not inverted.
-CHange_edge_at_scan_chain_output {LE | TE | ANY | OFF} Optional switch and literal that determines whether a lockup cell is inserted between the last scan cell and the output pin of scan chains. This switch allows you to control the capture edge used by the last scan cell. Options include: LE lockup cell is inserted to ensure that the last scan cell can update its output on the leading edge. TE lockup cell is inserted to ensure that the last scan cell can update its output on the trailing edge. ANY lockup cell is inserted independently from the change edge of the last scan cell. OFF lockup cells are not inserted at the end of any chains (wrapper or core). The clock signal obtained from the last scan cell in chain is always inverted before connecting it to the clock input of the lockup cell whether a DFF model or a DLAT model is used.
{ALL | WRApper} Optional switch that specifies the insertion of lockup cells at the end of all chains or of only wrapper chains. ALL a lockup cell is inserted at the end of all chains. WRApper a lockup cell is inserted at the end of all wrapper chains.
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Example 1 The following example defines two different groups of clocks, specifies a flop model and inverter model to use for lockup cells, enables lockup cell insertion, and performs the insertions. The -Clock Merge option combines the scan cells associated with each of the specified clock groups into a scan chain when the test logic is inserted.
add clocks 0 clk1 clk2 clk3 add clocks 1 clk4 clk5 clk6 add clock groups group1 clk1 clk2 clk3 add clock groups group2 clk4 clk5 clk6 add cell model dff04 -type dff clk data add cell model inv -type inv set lockup cell on -type dff run insert test logic -scan on -clock merge
In this example, DFTAdvisor creates two scan chains, one for each clock group and inserts lockup cells between the clock domains that are in the same clock group. Example 2 The following example defines a latch model and inverter model to use for lockup cells, turns on the insertion of lockup cells to ensure that the first scan cell captures data on the leading edge, and inserts the test logic.
add cell model dlat1a -type dlat enable data add cell model inv -type inv set lockup cell on -capture_edge_at_scan_chain_input LE -type dlat run insert test logic -scan on
Example 3 The following example inserts lockup cells at the end of all wrapper chains with ANY capture edge and at the end of core chains with a LE capture edge. The following commands must be executed in the order shown because the effect of the switches is cumulative. Note that the second command overrides the capture edge constraint for wrapper chains only which leaves the LE capture constraint to apply to core chains only.
Set Lockup Cells on change_edge_at_scan_chain_output le all Set Lockup Cells on change_edge_at_scan_chain_output any wrapper
Related Commands Add Cell Models Add Clock Groups Add Test Points Delete Test Points Insert Test Logic Report Test Points
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Command Dictionary Set Logfile Handling
Set Logfile Handling

Scope: All modes Usage SET LOgfile Handling {[filename] [-Replace | -Append]} Description Specifies for DFTAdvisor to direct the transcript information to a file. The Set Logfile Handling command causes DFTAdvisor to write the transcript information, which includes the commands and the corresponding output (if any), into the file you specify. You can execute the Set Logfile Handling command at any time within DFTA, and you can also execute it multiple times. In the logfile, all commands that DFTAdvisor executes are preceded with the command keyword. You can easily search for the commands you executed, and then you can generate a separate dofile containing those commands which you can re-run within DFTAdvisor. When you set the logfile handling, DFTAdvisor still writes the same information to the session transcript window in addition to the logfile. However, you can disable the writing of the information to the transcript window with the Set Screen Display command. If you want DFTAdvisor to stop writing to a logfile, issue the Set Logfile Handling command with no options, which closes the appropriate files. Arguments filename An optional string that specifies the name of the file where you want DFTAdvisor to write the transcript output. This string can be a full pathname or a leafname. If you only specify a leafname, the tool creates the file in the directory from which you invoked the tool. -Replace An optional switch that forces DFTAdvisor to overwrite the file, if a file by that name already exists. -Append An optional switch that causes DFTAdvisor to begin writing the transcript at the end of the specified file. Examples The following example specifies for DFTAdvisor to write a logfile and to disable the writing of the transcript:
set logfile handling /user/designs/setup_logfile set screen display off add clocks 0 clk add clocks 1 pre clr report clocks
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Command Dictionary Set Logfile Handling
The following information shows what the logfile contains after running the preceding set of commands:
// command: set scr d off // command: add clocks 0 clk // command: add clocks 1 pre clr // command: report clocks PRE, off_state 1 CLR, off_state 1 CLK, off_state 0
Related Commands Set Screen Display
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Command Dictionary Set Net Resolution
Set Net Resolution

Scope: Setup mode Usage SET NEt Resolution Wire | And | Or Description Specifies the behavior of multi-driver nets. The Set Net Resolution command specifies the behavior of non tri-state multi-driver nets. The default upon invocation of the tool is Wire, which requires all inputs be at the same value to achieve a value. If possible, you should specify the And or Or option; otherwise, some loss of test coverage results. Arguments Wire A literal that specifies for the tool to use unknown behavior for non tri-state multi-driver nets. This requires all inputs to be at the same value to achieve a value other than X. This is the default upon invocation of the tool. And A literal that specifies for the tool to use wired-AND behavior. Or A literal that specifies for the tool to use wired-OR behavior. Examples The following example specifies that the behavior of non tri-state multi-driver nets is wiredAND during the scan identification process.
set net resolution and add clocks 0 clock set system mode dft run report sequential instances
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Command Dictionary Set Nonscan Handling
Set Nonscan Handling

Scope: Setup modes Usage SET NOnscan Handling {Check | Nocheck} Description Specifies whether to check the non-scan instances for scannability. The Set Nonscan Handling command specifies whether the added non-scan instances are checked for scannability. Nonscan instances are defined by the Add Nonscan Instances command, Add Nonscan Models command, or the non-scan models due to no scan equivalents. These non-scan instances are not checked because the instances cannot be selected for scan insertion. You can enable checking on non-scan instances by using this command with the Check option. Arguments Check | Nocheck A required literal that specifies whether to check the non-scan instances for scannability. The default upon invocation is Nocheck. Examples The following example shows how to check all added non-scan instances:
set nonscan handling Check
Related Commands Add Nonscan Instances Add Nonscan Models Set DRC Handling
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Command Dictionary Set Scan Enable
Set Scan Enable

Scope: Setup and DFT modes Prerequisites: mux-DFF scan type Usage SET Scan Enable [scan_enable_pin_pathname [-isolate]] [primary_input] [-Active {High | Low}] [-Chain chain_name... | -Wrapper_chain [chain_name... | -INput | -OUTput] | -Partition partition_name...] [-Clock clock_pin] Description Assigns scan_enable signals to specific scan chains. Scan chains can be specified by either name, wrapper chain type, scan partition, or clock domain. If no scan chains are specified, the specified scan_enable signal is assigned to all scan chains. The Set Scan Enable command uses either the default scan enable signal names or allows you to assign a new scan enable signal name to all or to just the specified scan chains using the scan_enable_pin_pathname argument. Table 2-8 shows the default names for three types of scan enable signals used in DFTAdvisor. Table 2-8. Default Scan Enable Signal Names Default Name scan_en scan_en_in scan_en_out Description Scan enable for mux-DFF type (core scan cells) Scan enable for mux-DFF type (input wrapper cells) Scan enable for mux-DFF type (output wrapper cells)
DFTAdvisor creates three types of scan enable signals: one for core scan cells, one for input wrapper cells, and one for output wrapper cells. You can override the default base names for each scan enable signal type using one of the following commands:
Set Scan Enable <scan_enable_pin_pathname> Set Scan Eanble <scan_enable_pin_pathname> -Wrapper_chain -Input Set Scan Enable <scan_enable_pin_pathname> -Wrapper_chain -Output
The Set Scan Enable command can be issued in a sequence to either refine the scan enable signals assignments or overwrite the previous assignments (see the example section for this command). In general, the following rules are applied to determine how signal assignments are affected by subsequent commands: The most recent command that assigns a scan_enable signal takes precedence. If the most recent command operates on a disjoint set of scan chains, then the previous scan enable signal assignments remain intact.
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If the most recent command operates on previously specified scan chains, then previous scan_enable signal assignments are overwritten.
Arguments scan_enable_pin_pathname [-Isolate] An optional string that specifies a pin pathname for the scan_enable signal driver. The specified pin can be either a top-level scan enable port or an internal instance pin (connection node). If an internal instance pin is specified, it must trace back to a primary input via a simple path (only inverters or buffers) or the primary_input argument. -Isolate Isolates new fanouts of the specified scan enable signal. Each new fanout connection is gated by an AND or NOR gate and controlled by the global test enable signal. This switch is applicable to a scan enable signal driven by a top-level port or a top-level internal instance pin only. If no scan_enable signal driver is specified, the default scan enable name is used: scan_en, scan_en_in, scan_en_out. primary_input An optional string that specifies a top-level scan_enable port. This argument supplies a primary input/top-level port for an internal instance pin specified by the scan_enable_pin_pathname argument. The specified top-level port is used when generating the ATPG dofile and test procedure files. If the specified top-level port does not exist, it is created. The specified top-level port must be a primary input port. -Active {High | Low} An optional switch and literal pair that specifies whether the scan_enable signal is active low or high. -CHain chain_name An optional switch and a repeatable string that identifies individual scan chains to assign the specified scan_enable signal to. -Wrapper_chain [chain_name | -INPut | -OUTput] An optional switch and a repeatable string or literal pair that identifies the wrapper chains to assign a specified scan_enable signal to. Options include: chain_name... Specifies one or more wrapper chain names. -INPut Specifies all input wrapper chains when two-domain distribution is used. -OUTput Specifies all output wrapper chains when two-domain distribution is used. The -Input | -Output options should be used if the specified scan enable signal will be associated with either all input wrapper chains or all output wrapper chains, respectively. When the -Wrapper_chain switch is issued without arguments, the specified scan enable signal is assigned to all wrapper chains when one-domain distribution is used. Wrapper chain creation must be enabled. For more information on distribution modes and creating wrapper chains, see the Setup Pin Constraints command.
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This switch, along with either the -Input or -Output option, can be used in conjunction with the -Clock switch. In this case, the specified scan enable signal is assigned only to the wrapper chains that belong to both the specified type of wrapper chains and the specified clock domain. -Partition partition_name An optional switch and repeatable string pair that specifies names of scan partitions added using the Add Scan Partition command. Use this option to assign a specified scan_enable signal to the scan chains created within one or more partitions. This option can be used in conjunction with the -Clock switch. In this case, the specified scan enable signal is assigned only to the scan chains that belong to both the specified scan partition and the specified clock domain. -Clock clock_pin An optional switch and string pair that associates the specified scan enable signal with the specified clock (clock domain). Clock_pin can be either an existing top level port (primary input pin) or an existing internal pin pathname. This switch can be used in conjunction with either the -Wrapper_chain or -Partition option, in which case a unique scan enable signal is generated just for the scan chains that belong to both the specified wrapper chain type or partition and the specified clock domain. This switch is ignored when it is used in conjunction with the -Chain option. An error message is issued when this switch is specified with either the -Clock Merge or the filename -Fixed option of the Insert Test Logic command. This switch can be used in conjunction with the -Edge Merge option of the Insert Test Logic command. Example 1 Assuming two-domain distribution of the identified wrapper cells, the following example uses a sequence of Set Scan Enable commands to make all input wrapper chains controllable via the insen1 signal, and all output wrapper chains controllable via the outsen1 signal. All of the commands operate on disjoint sets of scan chains; therefore, each command affects different scan chains and does not override scan_enable assignments made by the previous command.
Set Scan Enable insen1 -wrapper_chain -input Set Scan Enable outsen1 -wrapper_chain -output
Example 2 The following example defines two scan partitions: partA and partB. A single scan chain is inserted by default for partA and two scan chains are inserted for partB. Two scan chains are
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inserted for the remaining cells in the default scan partition, as specified by the -number argument of the Insert Test Logic command.
Set System Mode dft Add Scan Partition partA -instance udff1 umodA/udff2 umodB/udff3 // 1 chain Add Scan Partition partB -instance umodC -number 2 // 2 chains Set Scan Enable sen Set Scan Enable senPartA -partition partA Set Scan Enable senPartB -partition partB Insert Test Logic -number 2 // 2 chains inserted for the default partition
The first Set Scan Enable command makes all scan chains controllable via the sen scan enable signal. The second Set Scan Enable command refines the first command and makes scan chains of partA controllable via the senPartA scan enable signal. The third Set Scan Enable command further refines the first command and makes scan chains of partB controllable via the senPartB scan enable signal. The second command operates on a set of scan chains that is entirely within the set specified in the first command; therefore, the scan chains that are in both sets will get the most recent assignment. The third command operates on a set of scan chains that is disjoint from the set in the second command but is entirely contained within the first set; therefore, the scan chains that are in both the first and the third sets get the most recent assignment. Example 3 The following example defines two scan partitions: partA and partB. The first Set Scan Enable command makes all scan chains controllable via the sen scan enable signal. The second Set Scan Enable command specifies an internal pin, /modX/i_sen/x, associated with the primary input, senPartA, as a driver of the scan enable signal controlling all scan chains of partA. The third Set Scan Enable command specifies an internal pin, /modY/i_sen/x, associated with the primary input, senPartB, as driver of the scan enable signal controlling all scan chains of partB.
Add Clock 0 /clkInput Set System Mode dft Add Scan Partition partA -instance udff1 umodA/udff2 umodB/udff3 // 1 chain Add Scan Partition partB -instance umodC -number 2 // 2 chains Set Scan Enable sen Set Scan Enable /modX/i_sen/x senPartA -partition partA Set Scan Enable /modY/i_sen/x senPartB -partition partB Set Scan Enable senClk -clock clkInput Insert Test Logic -number 2 // 2 chains inserted for the default partition
The last Set Scan Enable command specifies that all scan chains in the clkInput clock domain are controllable by the senClk scan enable signal. The second and the third Set Scan Enable commands overwrite the assignments of the first Set Scan Enable command affecting chains that are in partA and partB. Since the second and the third Set Scan Enable commands operate on disjoint sets, they do not affect previous assignments.
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The fourth command will overwrite some of the assignments of the second and the third commands for scan chains that are in partA and partB and also in the clkInput clock domain. If it is desirable to restrict the clock domain's assignments to a specific partition, the -Partition and -Clock options should be issued in conjunction in the same Set Scan Enable call as shown in Example 4. Example 4 In this example, two scan partitions are defined: partA and partB. This example uses a Set Scan_enable Sharing command to make all scan chains within each scan partition controllable via a unique scan enable signal partSenN where N is a unique number for each partition. Next, the Set Scan Enable command specifies to assign a unique scan enable signal, clkSen, to only the scan chains inside the partB scan partition that are also in the clock1 clock domain. The second call operates on a set of scan chains that is the same as the set of scan chains in the first call; therefore, certain previous assignments that are subject to the most recent assignment are overwritten.
Add Clock 0 clk1 Set System Mode dft Add Scan Partition partA -instance udff1 umodA/udff2 umodB/udff3 // 1 chain Add Scan Partition partB -instance umodC -number 2 // 2 chains Set Scan_enable Sharing -Prefix partSen -Scan_partition Set Scan Enable clkSen -Partiton partB -Clock clock1
Related Commands Add Scan Partition Report Scan Enable Set Scan_enable Sharing Setup Pin Constraints Setup Scan Insertion
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Command Dictionary Set Scan_enable Sharing
Set Scan_enable Sharing

Scope: Setup and DFT modes Prerequisites: mux-DFF scan type Usage SET SCan_enable Sharing [-Prefix base_name] [-Active {High | Low}] {[-Max_number_of_chains integer] [-Input_wrapper_chain | -Output_wrapper_chain | -Scan_partition] [-Clock_domain]} Description Divides all scan chains into specified groups and assigns a unique scan_ enable signal to each group. Scan chains can be grouped by: Specifying a maximum number of chains in each group, by wrapper chain types, by scan partitions, or by clock domains. Specifying a maximum number of chains within groups there were created by wrapper chain types, by scan partitions, or by clock domains. Clock domains within groups created by wrapper chain types or by scan partitions.
The Set Scan_enable Sharing command can be issued in a sequence to either refine the scan enable signals assignments or overwrite the previous assignments (see the example section for this command). In general, the following rules are applied to determine how signal assignments are affected by subsequent commands: The most recent command that assigns a scan_enable signal takes precedence. If the most recent command operates on a disjoint set of scan chains, then the previous scan enable signal assignments remain intact. If the most recent command operates on previously specified scan chains, then previous scan_enable signal assignments are overwritten.
Arguments -Prefix base_name An optional switch and string pair that specifies a base name (prefix) used in combination with sequential numbers to automatically generate unique top-level scan_enable signals (base_nameN) for specified groups of scan chains. If this option is not specified, an appropriate default scan enable name (scan_en, scan_en_in, scan_en_out) is used as the base name (prefix). -Active {High | Low} An optional switch and literal pair that specifies whether the scan_enable signal is active low or high.
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-Max_number_of_chains integer A required switch and integer or literal pair that divides scan chains into groups. Options include: integer Groups chains by a specified integer, where each group cannot have more than the integer number of scan chains. A unique scan_enable signal is then generated and assigned to each group.
-Input_wrapper_chain | -Output_wrapper_chain Optional switches specifying to generate a unique scan enable signal for either all input wrapper chains or all output wrapper chains. When the switches are used in conjunction with the -Max_number_of_chains option, the number specified by integer is applied only to the specified type of wrapper chains. The generated scan enable signals are treated as SEN_IN or SEN_OUT type, respectively. -Input_wrapper_chain Used to specify grouping for input wrapper chains. When this switch is used in conjunction with the the Max_number_of_chains switch, the number specified by integer is applied to only input wrapper chains. Only valid when input wrapper chains are defined. For more information, see the Setup Pin Constraints command. -Output_wrapper_chain Used to specify grouping for output wrapper chains. When this switch is used in conjunction with the the -Max_number_of_chains switch, the number specified by integer is applied to only output wrapper chains. Only valid when output wrapper chains are defined. For more information, see the Setup Pin Constraints command. These switches can be used in conjunction with the -Clock_domain switch.
-Scan_partition An optional switch that specifies groupings for each scan partition added using the Add Scan Partition command. With this switch, a unique scan enable signal is generated for every scan partition (that is, for scan chains within each partition). When this switch is used in conjunction with the -Max_number_of_chains switch, the number specified by integer is applied to each scan partition. This switch can be used in conjunction with the -Clock_domain switch.
-Clock_domain An optional switch that specifies to generate a unique scan enable signal for each clock domain. When this switch is used in conjunction with the -Max_number_of_chains switch, the number specified by integer is applied to each clock domain. This switch can be used in conjunction with either the -Input_wrapper_chain or -Output_wrapper_chain option; in this case a unique scan enable signal is generated only for each clock domain within the input or output wrapper chains. This switch cannot be used in conjunction with the -Clock Merge or the filename -Fixed switches of the Insert Test Logic command; in this case an error message is issued.
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This switch can be used in conjunction with the -Edge Merge switch of the Insert Test Logic command. Example 1 The following example uses a sequence of Set Scan_enable Sharing commands to make every group of 3 input wrapper chains controllable via a unique scan_enable signal, insenN, and every group of 5 output wrapper chains controllable via a unique scan enable_signal, outsenN.
Set Scan_enable Sharing -Prefix insen -Max_number_of_chains 3 -Input_wrapper_chain Set Scan_enable Sharing -Prefix outsen -Max_number_of_chains 5 -Output_wrapper_chain
The second command operates on a set of scan chains that is disjoint from the set of scan chains operated on by in the first command, so the previous assignments remain intact. Example 2 The following example defines 3 scan partitions: spar1, spar2, spar3. Two scan chains are created for spar1, 6 scan chains for spar2, and 3 scan chains for spar3. Two scan chains are created in the default scan partition for the remaining cells, as specified by the -number argument of the Insert Test Logic command.
add scan partition spar1 -ins a2/e* -verbose // 2 chains: chain1, chain2 add scan partition spar2 -ins a1/b2 a1/b1/e2 -max_length 2 -verbose // 6 chains: chain3, chain4, chain5, chain6, chain7, chain8 add scan partition spar3 -mod C -number 3 -verbose // 3 chains: chain9, chain10, chain11 set scan_enable sharing -prefix SENPAR -scan_partition insert test logic -number 2 // 2 chains for the default partition: chain12, chain13 report scan enable
--------------------------------------------------------------------------// command: report scan enable --------------------------------------------------------------------------Primary Input Internal Connection Node Scan Chain --------------------------------------------------------------------------/SENPAR1 -chain12 chain13 --------------------------------------------------------------------------/SENPAR2 -chain1 chain2 --------------------------------------------------------------------------/SENPAR3 -chain3 chain4 chain5 chain6 chain7 chain8 --------------------------------------------------------------------------/SENPAR4 -chain9 chain10 chain11 ---------------------------------------------------------------------------
A unique scan_enable signal, SENPARN, is generated and assigned to all core scan chains.
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Example 3 The following example uses a sequence of Set Scan_enable Sharing commands to make every group of three input wrapper chains controllable via a unique scan enable signal insenN, where N is a unique number for each group, and every group of five output wrapper chains controllable via a unique scan enable signal outsenN, where N is a unique number of each group.
Set Scan_enable Sharing -Prefix insen -Max_number_of_chains 3 -Input_wrapper_chain Set Scan_enable Sharing -Prefix outsen -Max_number_of_chains 5 -Output_wrapper_chain
The second command operates on a set of scan chains that is disjoint from the set of scan chains in the first command; therefore, the previous assignments are not affected by the subsequent assignments. Example 4 In this example, two scan partitions are defined: partA and partB. This example uses a Set Scan_enable Sharing command to make all scan chains within each scan partition controllable via a unique scan enable signal partSenN, where N is a unique number for each partition. Next, the Set Scan Enable command specifies to assign a unique scan enable signal, clkSen, to only the scan chains inside the partB scan partition that are also in the clock1 clock domain. The Set Scan Enable command operates on a set of scan chains that is the same as the set of scan chains in the Set Scan_enable Sharing command; therefore, certain previous assignments that are subject to the most recent assignment are overwritten.
Add Clock 0 clk1 Set System Mode dft Add Scan Partition partA -instance udff1 umodA/udff2 umodB/udff3 // 1 chain Add Scan Partition partB -instance umodC -number 2 // 2 chains Set Scan_enable Sharing -Prefix partSen -Scan_partition Set Scan Enable clkSen -Partition partB -Clock clock1
Related Commands Add Scan Partition Report Scan Enable Set Scan Enable Setup Pin Constraints Setup Scan Insertion
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Command Dictionary Set Scan Type
Set Scan Type

Scope: Setup mode Usage SET SCan Type {Mux_scan | Lssd | Clocked_scan} Description Specifies the scan style design. The Set Scan Type command specifies the scan style of a design which the scan insertion will create. If this command is not used, then during the scan insertion process, DFTAdvisor will use the mux-DFF scan style. Arguments Mux_scan A literal that specifies for DFTAdvisor to insert mux-DFF type scan elements during the scan insertion process. This is the default behavior upon invocation. Lssd A literal that specifies for DFTAdvisor to insert LSSD type scan elements during the scan insertion process. Clocked_scan A literal that specifies for DFTAdvisor to insert clocked-signal type scan elements during the scan insertion process. Examples The following example uses a mux-DFF scan type design during scan insertion:
set scan type mux_scan add clocks 0 clock set system mode dft setup scan identification sequential atpg -percent 50 run insert test logic -max_length 10
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Command Dictionary Set Screen Display
Set Screen Display

Scope: All modes Usage SET SCreen Display ON | OFf Description Specifies whether DFTAdvisor writes the transcript to the session window. If you create a logfile with the Set Logfile Handling command, you may want to disable DFTAdvisor from writing the same information to the session transcript window. Arguments ON A literal that specifies to enable the tool to write the session information to the transcript window. This is the default behavior upon invocation. OFf A literal that specifies to disable the tool from writing any of the session information to the transcript window, including error messages. Examples The following example shows how to use the logfile functionality to capture the transcript in a file and then disable DFTAdvisor from writing to the display:
set logfile handling /user/design/setup_file set screen display off
Related Commands Report Environment Set Logfile Handling
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Command Dictionary Set Sensitization Checking
Set Sensitization Checking

Scope: All modes Usage SET SEnsitization Checking OFf | ON Description Specifies whether DRC checking attempts to verify a suspected C3 rules violation. The Set Sensitization Checking command specifies whether the DRC verifies that the path from the source and sink of a suspected C3 violation exists when the source and sink clocks are on and all other clocks are off. If sensitization checking is on and the paths associated with the violation meet these conditions, the DRC reports the C3 violation. Arguments OFf A literal that disables the C3 DRC sensitization check. This is the default behavior upon invocation. ON A literal that enables the C3 DRC sensitization check. Related Commands Set DRC Handling
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Command Dictionary Set Shadow Check
Set Shadow Check

Scope: All modes. Usage SET SHadow Check OFf | ON Description Specifies whether DFTAdvisor will identify sequential elements as shadow elements when tracing existing scan chains. You can use the Set Shadow Check command to disable the checking and avoid corresponding error messages. This will prevent identification of any non-scan sequential element as a shadow element. Arguments OFf A literal that disables shadow checking. ON A literal that enables shadow checking. This is the initial state upon invocation of DFTAdvisor. Examples The following example disables shadow checking.
set shadow check off
Related Commands Set DRC Handling Report Environment
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Command Dictionary Set Stability Check
Set Stability Check

Scope: Setup mode, before design rule checking Usage SET STability Check All_shift Description Specifies how the tool checks the effect of applying the shift procedure on non-scan cells. When non-scan state elements control scan chain operation, DFTAdvisor needs to understand the values of these elements in order to perform scan chain tracing. For example, a control register in a test controller, such as a JTAG TAP, needs to be checked to see that the TAP register holds state during the shift procedure. Or, for a design containing BIST, a shift counter -- composed of non-scan elements -- controls the scan chain shifting. This counter counts from zero to a predetermined number and then resets to zero. This predetermined number is related to the number of shifts applied by the load_unload procedure. By default, DFTAdvisor only simulates one shift of the scan chain, which does not provide enough information about the non-scan elements and how they control scan shifting. Therefore, you should specify this command with the All_shift option to simulate all applications of the shift procedure or rules checking will not succeed. Arguments All_shift A literal that enables the tool to perform the most detailed level of checking. The shift procedure is simulated for as many applications as the load_unload procedure calls for. When you specify this option, it can significantly increase your run time. This option should be used with BIST. Examples The following example shows how to enable the detail checking which simulates the shift procedure more than once.
set stability check all_shift
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Command Dictionary Set System Mode
Set System Mode

Scope: All modes Usage SET SYstem Mode Setup | Dft Description Specifies the next system mode for the tool to enter. The Set System Mode command directs DFTAdvisor to a specific system mode, which includes scan insertion (Dft) or the default system mode of Setup. When switching from the Setup mode to the Scan Insertion system mode, DFTAdvisor builds a flat, gate-level simulation model. After the initial building of the flat, gate-level simulation model, if you return to Setup mode, issue any of the following commands and then switch to Dft mode; or DFTAdvisor builds a new simulation model: Add Nofaults Add Tied Signals Delete Nofaults Delete Tied Signals Set Internal Fault Set Internal Name Setup Tied Signals
Arguments Setup A literal that specifies for the tool to enter the Setup system mode. Dft A literal that specifies for the tool to enter the Scan Insertion system mode. Examples The following example will change the system mode so you can perform a scan identification run.
add tied signals 1 vcc add tied signals 0 vss add clocks 0 clock set system mode dft run report sequential instances
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Command Dictionary Set Test Logic
Set Test Logic

Scope: Setup mode Usage SET TEst Logic {-Set {ON | OFf} | -REset {ON | OFf} | -Clock {ON | OFf} | -RAm {ON | OFf} | -C6 {ON | OFf}} Description Inserts test logic to control the set, reset, clock, enable, or write control signals to make them scannable when scan chains are inserted. Before inserting scan chains, you must specify the cell models with the Add Cell Models command. You can use the Report Dft Check command to display the signals where test logic can be inserted to make the signals controllable. By default, no test logic is inserted on control signals. You can use the Report Environment command to display the current test logic settings. If all enable signals of a bus are driven purely by combinational logic, no additional test logic is needed to prevent contention due to scan shifting. Arguments -Set ON | OFf A switch and literal pair that enables the insertion of test logic to make set signals controllable. The default setting is off. -REset ON | OFf A switch and literal pair that enables the insertion of test logic to make set signals controllable. The default setting is off. -Clock ON | OFf A switch and literal pair that enables the insertion of test logic to make clock signals controllable. The default setting is off. -RAm ON | OFf A switch and literal pair that enables the insertion of test logic to make read and write signals controllable. The default setting is off. This option does not affect the set and reset signals of the RAM. You should use the edge_trigger attribute in the library definition of the RAM to specify inserting test logic to control these signals. For more information, see the Attributes of RAM/ROM Primitives section of the Tessent Common Resources Manual for ATPG Products. -C6 {ON | OFf} A switch and literal pair that, when enabled, instructs DFTAdvisor to add hardware to fix identified C6 violations. DFTAdvisor fixes a C6 violation by inserting a multiplexer into the data path that feeds the flip-flop generating the violation. The test mode input of the multiplexer is driven by a nearby scan flip-flop. When a top-level clock feeds the data input
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Command Dictionary Set Test Logic
of many flip-flops (which results in multiple C6 violations), the multiplexer is inserted at the highest possible level of hierarchy. The driving scan cells are selected to be in the same clock domain as the flip-flops generating the C6 violations. This setting is off by default. Note This option cannot be used when the Set Drc Handling -Conservative switch is enabled. Example The following example checks the set and clock signals of uncontrollable memory elements and makes them controllable with the addition of test logic:
add clocks 0 clk set test logic -set on -clock on set system mode dft report dft check add cell models and2 -type and add cell models or2 -type or add cell models mux21h -type mux s a b add cell models nor2 -type nor report cell models insert test logic
Related Commands Add Cell Models Delete Cell Models Report Cell Models Set Latch Handling
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Command Dictionary Set Trace Report
Set Trace Report

Scope: All modes Usage SET TRace Report OFf | ON Description Specifies whether the tool displays gates in the scan chain trace. The Set Trace Report command controls whether the tool displays all of the gates in the scan chain trace during rules checking. Arguments OFf A literal that specifies for the tool to not display gates in the scan chain trace. This is the default behavior upon invocation. ON A literal that specifies for the tool to display gates in the scan chain trace during rules checking. Examples The following example displays the gates in the scan chain trace during rules checking:
add clocks 0 clock add scan groups group1 scanfile add scan chains chain1 group1 indata2 outdata4 set trace report on set system mode dft
Related Commands Add Scan Chains Report Scan Chains
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Command Dictionary Set Transient Detection
Set Transient Detection

Scope: All modes Usage SET TRansient Detection OFf | {ON [-Verbose | -NOVerbose]} Description Specifies whether the tool detects all zero width events on the clock lines of state elements. The Set Transient Detection command sets the simulator to detect all zero width events on the clock lines of state elements. If the zero width event causes a change of state in the state element, then the tool sets that state element to X. If Off is specified, DRC simulation treats all events on state elements as valid. Because the simulator is a zero-delay simulator, it is possible for DRC to simulate zero width, monostable circuits with ideal behavior which is rarely matched in silicon. The resulting zero width output pulse from the monostable circuit is also treated as a valid clocking event for other state elements. Arguments OFf A literal that specifies for the tool to set transient detection off. ON A literal that specifies for the tool to set transient detection on. This is the invocation default. -Verbose An optional switch that specifies the tool to display a message identifying each time a state element is set to X due to transient detection. This is the invocation default and is only valid when transient detection is enabled. -NOVerbose An optional switch that specifies the tool not to display a message identifying each time a state element is set to X due to transient detection. This switch is only valid when transient detection is enabled. Example To remove the verbose messages during DRC checking, enter:
set transient detection on -noverbose
Related Commands Report Environment
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Command Dictionary Set Tristate Gating
Set Tristate Gating

Scope: Setup mode Usage SET TRistate Gating { OFf | ON | Busdrivers | Scan | primary_input_or_output... | Decoded} [-Control {SEn | TEn}] [-Force_gating] Description Specifies how tri-state devices are controlled during scan chain shifting. The Set Tristate Gating command ensures tri-state devices are controlled to either prevent bus contention or be turned on during testing. If the necessary test logic already exists, none is inserted. When enabled, test logic is inserted that controls tri-state devices as follows: Multiple tri-state gates driving nets (bus net) One gate is turned on and the rest are turned off during testing. Single tri-state gates driving nets (primary net or an internal net) All single tristate gates are turned on for testing.
You can also specify which signal (SEN or TEN) controls the enable lines of tri-state devices. By default, when the enable signal of a tri-state device is directly controlled by a primary input, by TIE0, or by TIE1, no gating is necessary and a force statement for the primary input is added to the load_unload procedure in the new procedure file. This behavior can be overridden by using the -Force_gating switch. Arguments {OFf | ON | Busdrivers | Scan | primary_input_or _output... | Decoded} Required literal or repeatable string that specifies which tri-state devices to control during scan shifting. The default setting is off. Options include: OFf no test logic is inserted to control tri-state devices. Default setting. ON test logic is inserted when necessary to control all tri-state devices. Busdrivers test logic is inserted to control tri-state devices driving bus nets. Scan test logic is inserted to control tri-state devices used as scan inputs/outputs. primary_input_or_output specifies a primary input or output pin. Test logic is inserted to control the tri-state devices driving the specified primary output pin(s) or driven by the specified primary input pin(s). Decoded test logic is inserted to control tri-state devices with the TEN signal to ensure test logic structures are valid only in test mode.
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Command Dictionary Set Tristate Gating
-Control SEn | TEn An optional switch and literal pair that specifies the enable signal used to control tri-state devices. Literal options include: SEn Specifies the scan_enable signal. Default setting. TEn Specifies the test_enable signal.
-Force_gating An optional switch that adds test logic to the enable lines of tri-states devices when these lines are directly controlled by primary inputs, or by TIE1, or by TIE0. When the enable line is directly controlled by a primary input, DFTAdvisor adds the force statement for this primary input to the load_unload procedure in the procedure file.
Example 1 The following example uses the Set Tristate Gating command to insert test logic and make all tri-state devices driving bus nets controllable via the SEN signal; it then reports the gated tri-state devices.
add clocks 0 clk setup scan identification full_scan set tristate gating on set bidi gating scan add scan pins c1 bidi_in1/X blkB1/blkA/utri2/A -top io out1 set system mode dft report dft check -tristate ------------------------------------------------------------------------Bidi Primitive Control Control Tri-state State Direction Gating ID Signal Driver ------------------------------------------------------------------------/bidi_in1 OFF IN YES 20 SEN /or2/Y /blkB1/blkA/utri3 OFF -YES 15 SEN /udff0/Q /blkB1/blkA/utri2 ON -YES 17 SEN /or2/Y /blkB1/blkA/utri1 OFF -YES 16 SEN /or2/Y -------------------------------------------------------------------------
Example 2 The following example uses the force_gating switch to insert test logic controlled by the SEN control signal on the enable line of /tpin_2. /tpin_2 is a tristate device driving primary output out4; its enable signal is directly controlled by the primary input /io_control1.
set tristate gating out4 -force_gating report dft check -tri
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Command Dictionary Set Tristate Gating ---------------------------------------------------------------------Bidi Primitive Control Control Tri-state State Direction Gating ID Signal Driver ---------------------------------------------------------------------/tpin_1 ON -NO 44 SEN /io_control /tpin_2 ON -YES 43 SEN /io_control1 /bidi_1 ON OUT NO 45 SEN /io_control /bidi_2 ON OUT NO 46 SEN /io_control /bidi_3 ON OUT NO 41 SEN /io_control ----------------------------------------------------------------------
Related Commands Report Dft Check Report Test Logic Report Control Signals Set Bidi Gating Set Test Logic
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Command Dictionary Setup Clock Gating
Setup Clock Gating

Scope: Setup mode Usage SETup CLock Gating [-LIbrary_model library_model_name] [-Module netlist_module_name] [-INStance pathname] [-Port_to_connect port_name [-INVert]] [-Driver pin_pathname [-Active {High | Low}]] Description Specifies clock gating cells whose unconnected scan enable ports need to be connected to either the scan enable signal or a specified signal (pin). DFTAdvisor does one of the following: Automatically checks if the scan enable port of each recognized clock gating instance is unconnected and, if unconnected, connects it to either the scan enable signal or the signal specified by the -Driver pin_pathname argument. This occurs when none of the following switches is specified: -Library_model, -Module, -Instance, or Port_to_connect. Automatically checks if the specified port of each specified instance is unconnected and, if unconnected, connects it to either the scan enable signal or the signal specified by the -Driver pin_pathname argument.
-LIbrary_model library_model_name An optional switch and a repeatable string that specify the library model name(s) of the clock gating cell instances whose unconnected port is to be connected to either the scan enable signal or to the specified signal.
-Module netlist_module_name An optional switch and a repeatable string that specify the netlist module name(s) of the clock gating cell instances whose unconnected port is to be connected to the specified signal. This option requires both the -Port_to_connect and -Driver options to be specified as well. DFTAdvisor only attempts to connect the specified port of the specified clock gating cell if it determines the port is really unconnected.
-INstance pathname A optional switch and a repeatable string that specify the pathname(s) of the clock gating cell instances whose unconnected port is to be connected to either the scan enable signal or to the specified signal.
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Command Dictionary Setup Clock Gating
-Port_to_connect port_name [-INVert] An optional switch and a string pair that specifies the unconnected port of the clock gating cell to be connected to either the scan enable signal or to the specified signal. This option must be specified when the -Module switch is specified. -INVert By default, the expected input value for the unconnected port is set to 1 during the shift cycle. This switch specifies that the expected input value is set to 0 during the shift cycle.
-Driver pin_pathname [-Active {High | Low}] An optional switch and literal pair that specifies the pin pathname for the signal driver that the unconnected port is to be connected to. The specified pin_pathname can be either a toplevel port or an internal pin instance. When this option is not specified, DFTAdvisor assumes the unconnected ports are to be connected to the scan enable signal. This option must be specified when the -Module switch is specified. -Active An optional switch that indicates whether the specified signal is active Low or High. By default, DFTAdvisor assumes the active state is High, unless it is an existing global signal whose active state is known.
Examples The following example connects the unconnected scan enable ports of specified clock gating instances. The first instance is connected to the sen1 pin which drives the signal with the active state set to low. The next two instances are connected to the default scan enable signal, sen. The results of these commands are shown by the Report Clock Gating command output:
set scan enable sen setup clock gating -instance clkg1/clkg1/clkgLA -driver sen1 -active low setup clock gating -instance clkg3/clkg1/clkgLA clkg2/clkg1/clkgLA set system mode dft // Note: The following clock gating instances have unconnected ports that will be connected to a scan enable signal. ------------------------------------------------------------------------Clock Gating Unconnected Signal Instance Port Driver ------------------------------------------------------------------------clkg1/clkg1/clkgLA SE sen1 clkg2/clkg1/clkgLA SE sen clkg3/clkg1/clkgLA SE sen ------------------------------------------------------------------------....... insert test logic
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Command Dictionary Setup Clock Gating report clock gating -instance clkg1/clkg1/clkgLA clkg2/clkg1/clkgLA clkg3/clkg1/clkgLA ------------------------------------------------------------------------Clock Gating Unconnected Signal Instance Port Driver ------------------------------------------------------------------------clkg1/clkg1/clkgLA SE sen1 clkg2/clkg1/clkgLA SE sen clkg3/clkg1/clkgLA SE sen -------------------------------------------------------------------------
Related Topics Report Clock Gating
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Command Dictionary Setup EDT
Setup EDT
Scope: All modes Usage SETup EDt -Location {External | Internal} Description The Setup EDT command identifies a design that uses the internal flow and enables the Write ATPG Setup command to write out EDT-specific commands for the internal flow to the ATPG setup files. Arguments -Location Internal | External A required switch and literal pair that specifies whether the location of the EDT logic is internal or external to an existing chip. The default is the external flow. Note Tessent TestKompress supports two flows for inserting compression hardware into a netlist: an internal flow and an external flow. For more information on these flows, refer to the Tessent TestKompress Users Guide. Examples The following example writes out EDT-specific commands for an internal flow to the ATPG setup files.
setup edt -location internal write atpg setup scan -edt
Related Commands Write Atpg Setup
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Command Dictionary Setup Naming
Setup Naming
Scope: All modes Usage SETup NAming [{-Net prefix_name} | {-INStance {[Tristate | Xbound | Lockup | CONTROL_Flop | CONTROL_Point | OBSERVE_Flop|OBSERVE_Point|IN_register|OUt_register] prefix_name}} {-Scan_chain prefix_name} | {-INPut_wrapper_chain prefix_name} | {-Output_wrapper_chain prefix_name}] Description Explicitly defines the default names for nets and instances, and reports current or modified settings. The Setup Naming command serves two purposes. You can use it to change the default prefix that DFTAdvisor uses to name certain types of added test logic, and you can change the default the tool uses to name nets. If you invoke the command without an argument, it automatically reports on the current settings for all prefixes. If you make any changes, it reports the modified settings. Table 2-9 shows the invocation defaults for particular logic instance types: Table 2-9. Instance Type Prefix Defaults Object Type Tri-state control X bounding lockup cells Control point flip-flop Control point logic Observe point flip-flop Observe point logic Input partition flip-flop Output partition flip-flop Other logic Arguments -Net prefix_name An optional switch and string pair that specifies the prefix_name you want as the default prefix for naming nets. The invocation default prefix is net. Default Prefix Name tcntl xbnd lckup ctlff ctlpt obsff obspt inreg outreg uu Instance Literal Tristate Xbound Lockup CONTROL_Flop CONTROL_Point OBSERVE_Flop OBSERVE_Point IN_register OUt_register
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-INStance [Tristate | Xbound | Lockup | CONTROL_Flop | CONTROL_Point | OBSERVE_Flop | OBSERVE_Point] prefix_name An optional switch, with an optional, repeatable literal and string pair, that specifies the prefix_name you want as the default prefix for the object type specified by the literal. If you do not specify an object type literal, prefix_name applies to all added test logic not covered by one of the object type literals. The default prefix for this other logic is uu. Tristate An optional literal that specifies to apply the prefix_name as the default for the logic object type tri-state control. The default prefix is tcntl. Xbound An optional literal that specifies to apply the prefix_name as the default for the logic object type X bound control. The default prefix is xbnd. Lockup An optional literal that specifies to apply the prefix_name as the default for the logic object type lockup cell. The default prefix is lckup. CONTROL_Flop An optional literal that specifies to apply the prefix_name as the default for the logic object type control-point flip-flop. The default prefix is ctlff. CONTROL_Point An optional literal that specifies to apply the prefix_name as the default for the logic object type control-point logic. The default prefix is ctlpt. OBSERVE_Flop An optional literal that specifies to apply the prefix_name as the default for the logic object type observe-point flip-flop. The default prefix is obsff. OBSERVE_Point An optional literal that specifies to apply the prefix_name as the default for the logic object type observe-point logic. The default prefix is obspt. IN_register An optional literal that specifies to apply the prefix_name as the default for the logic object type input partition flip-flop. The default prefix is inreg. OUt_register An optional literal that specifies to apply the prefix_name as the default for the logic object type output partition flip-flop. The default prefix is outreg.
-Scan_chain prefix_name An optional switch and string pair that specifies a new default prefix for naming scan chains of any scan chain type. At invocation, the default value for prefix_name is chain.
-INPut_wrapper_chain prefix_name An optional switch and string pair that specifies a new default prefix for naming input wrapper chains. At invocation, the default value for prefix_name is chain.
-Output_wrapper_chain prefix_name An optional switch and string pair that specifies a new default prefix for naming output wrapper chains. At invocation, the default value for prefix_name is chain.
Example 1 The following example resets the default prefix name for tri-state control logic to tric and for lockup cells to lockl:
setup naming -instance tristate tric lockup lockl
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DFTAdvisor will change the prefix names and issue the following report:
// // // // // // // // // // // // Setup naming prefixes: nets : net tristates : tric xbounding : xbnd lockup cells : lockl observe flops : obsff observe points : obspt control flops : ctlff control points : ctlpt input registers : inreg output registers : outreg other instances : uu
Example 2 The following example overrides the default scan chain name assignments for all three scan chain types and applies the new default prefixes to the newly created chains of each type.
setup naming -scan_chain coreChain setup naming -input_wrapper_chain inputWrapper setup naming -output_wrapper_chain outputWrapper ... report scan chains Input wrapper chains: ------------------------------------------------------------------------chain = inputWrapper1 group = group1 input = /scan_in1 output = /out1 length = 3 scan_enable = /se_in clock = /clk chain = inputWrapper2 group = group1 input = /scan_in2 output = /scan_out1 length = 3 scan_enable = /se_in clock = /clk chain = inputWrapper3 group = group1 input = /scan_in3 output = /scan_out2 length = 2 scan_enable = /se_in clock = /clk Output wrapper chains: ------------------------------------------------------------------------chain = outputWrapper1 group = group1 input = /scan_in4 output = /out2 length = 1 scan_enable = /se_out clock = /test_clk Default scan partition chains: ------------------------------------------------------------------------chain = coreChain1 group = group1 input = /scan_in5 output = /scan_out3 length = 1 scan_enable = /scan_en clock = /clk
Related Commands Insert Test Logic Set Test Logic Report Scan Chains Setup Registered IO
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Command Dictionary Setup Output Masks
Setup Output Masks

Scope: Setup mode Usage SETup OUtput Masks OFf | {ON [-Bidi_exclude] [-Lbist_exclude] [-Exclude primary_output_pin]} Description Sets the default mask for all output and bidirectional pins. The Setup Output Masks command masks all the output and bidirectional pins specified. This default mask is present on the output pin, unless overridden by the Add Output Masks command. DFTAdvisor uses primary output pins as the observe points during the scan and test point identification process. When you mask a primary output pin, you inform DFTAdvisor to mark that pin as an invalid observation point during the scan and test point identification process. You can exclude bidirectional pins, LBISTArchitect scan output pins, and any specified pins. You use the Off literal to remove all default masks defined with this command. You can add a hold value to a default mask with the Add Output Masks command, or remove a hold value using the Delete Output Masks command. You can also use the Add Output Masks command to add a mask to any of the output pins excluded with the Setup Output Masks command. Arguments OFf | ON A required string that specifies to set or remove the current default mask setting for all primary output pins. When turning masking on, you can exclude pins from the mask. The tool invocation default setting is no masks. -Bidi_exclude An optional switch that specifies to exclude bidirectional pins from the mask setting. -Lbist_exclude An optional switch that specifies to exclude LBISTArchitect scan output pins from the mask setting. -Exclude primary_output_pin An optional switch and repeatable string that specifies to exclude the specified primary output pins from the mask setting.
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Command Dictionary Setup Output Masks
Examples The following example defines the default mask for all but the LBISTArchitect scan output pins, then adds two additional pin masks with a hold value of 1:
setup output masks on -lbist_exclude add output masks out1 out2 -hold 1
Related Commands Add Output Masks Delete Output Masks Report Output Masks
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Command Dictionary Setup Pin Constraints
Setup Pin Constraints

Scope: Setup mode Usage SETup PIn Constraints None | {{C0 | C1 | CZ | CX} [-Bidi_exclude] [-Lbist_exclude] [-Exclude primary_input_pin]} Description Sets the default pin constraint value for all input and bidirectional pins. The Setup Pin Constraints command constrains all input and bidirectional pins to the specified default value. This default value is present on the input pin, unless overridden by the Add Pin Constraints command. You can exclude bidirectional pins, LBISTArchitect-related control and data pins, and any specified pin. You use the None literal to remove all default settings defined with this command. Arguments None A required string that specifies to remove all the current default constraints for all primary input and bidirectional pins. You must specify this literal or one of the C literals. This is the tool invocation default. C0 | C1 | CZ | CX A literal that specifies the default constant value constraint for the primary_input pins, except for any pins excluded by the specified exclude options. You must specify one of these literals or the None literal. The constraint choices are as follows: C0 A literal that specifies application of the constant 0 to the chosen primary input pins. C1 A literal that specifies application of the constant 1 to the chosen primary input pins. CZ A literal that specifies application of the constant Z (high-impedance) to the chosen primary input pins. CX A literal that specifies application of the constant X (unknown) to the chosen primary input pins. -Bidi_exclude An optional switch that specifies to exclude bidirectional pins from the setup setting. -Lbist_exclude An optional switch that specifies to exclude LBISTArchitect-related input pins from the setup setting. These pins include clocks, RAM/ROM read signals, RAM/ROM write signals, sets, resets, and known scan inputs.
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Command Dictionary Setup Pin Constraints
-Exclude primary_input_pin An optional switch and repeatable string that specifies to exclude the specified primary input pins from the setup setting.
Examples The following example defines the default pin constraints for all but the LBISTArchitect related control and data pins, then adds two additional pin constraints that override the default:
setup pin constraints c0 -lbist_exclude add pin constraints kgmt c1 add pin constraints ckgmt c1
Related Commands Add Pin Constraints Add Seq_transparent Constraints Analyze Input Control Delete Pin Constraints Report Pin Constraints
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Command Dictionary Setup Registered IO
Setup Registered IO
Scope: All modes Prerequisites: A scan model must be defined with the Add Cell Models command before using this command. Usage SETup REgistered IO {[-Exclude pin_names] | [-INClude pin_names...]} [-INPUT_Model model_name] [-OUTPUT_Model model_name] [-INPUT_Clock pin_pathname] [-OUTPUT_Clock pin_pathname] [-REG_Floating] [-REG_Comb_feedthrough] [-REG_Seq_feedthrough] Description Turns on the automatic registration of the primary I/O pins of the design. The registered cells are also placed into scan chains. The user-defined clocks and scan-related I/O pins are automatically excluded from registration. The specified I/O pins are registered with scan cells defined through the Add Cell Models command, and the inserted scan cells can be included in the same scan chains along with the existing cells of the design. To place the input and output registration cells in separate scan chains, the Setup Wrapper Chains command can be used in conjunction with this command to specify different number of chains and scan enable pins for the input and output registration cells. The input registration cells and the input wrapper cells are then placed in the same scan chains. Similarly, the output registration cells and the output wrapper cells are placed in the same scan chains. By default, I/Os that are designated as scan-in/scan-out pins or are driving/driven by scanin/scan-out pins are not registered unless they are explicitly added to the -Include list of this command. During I/O registration, DFTAdvisor will report scan-in/scan-out related I/Os that are not explicitly listed with the -Include switch as not being registered. The -Include switch cannot be used in conjunction with the -Exclude switch. You can specify that specific clocks are used for the registration cells by using the -Input_clock and -Output_clock switches. If clocks are not specified, the clocks of adjacent cells in the chain or new test clock signals will be used for the registration cells. By default, unconnected I/Os are not registered. You can specify that unconnected I/Os should be registered by doing one of the following: Specify the -REG_floating switch for this command. Specify the unconnected I/Os in the -Include list of this command.
By default, combinational feed-throughs are not registered. You can specify that combinational feed-throughs should be registered by doing one of the following: Specify the -REG_Comb_feedthrough switch for this command.
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Specify the PI/POs of the combinational feed-throughs in the -Include list of this command.
Be default, sequential feed-throughs are not registered. You can specify that sequential feedthroughs should be registered by doing one of the following: Specify the -REG_Seq_feedthrough switch for this command. Specify the PI/POs of the sequential feed-throughs in the -Include list of this command. Note This feature does not address the stitching of multiple cores, but rather the insertion of wrapper chains in a single core. Arguments -Exclude pin_names An optional switch and repeatable string that specifies primary I/O pins to exclude from registration. Note that clock and scan-related pins are automatically excluded. This switch cannot be used with the -Include switch. -Include pin_names An optional switch and repeatable string that specifies which primary I/O pins to register. Clock and scan-related pins are automatically excluded from registration. This switch cannot be used with the -Exclude switch. -Input_model model_name An optional switch and string pair that uses model_name cells for registering primary inputs. You must first define model_name with the Add Cell Models command. -Output_model model_name An optional switch and string pair that uses model_name cells for registering primary outputs You must first define model_name with the Add Cell Models command. -Input_clock pin_pathname An optional switch and string pair that specifies to use pin_pathname clock to control registration cells inserted for input pins. The specified pin pathname should either be a primary input or a top-level instance output pin. If this switch is not specified, DFTAdvisor uses the clock of the neighboring cell in the input wrapper chain (when wrapper chains are inserted) or a test clock (when neighboring cell does not exist). -Output_clock pin_pathname An optional switch and string pair that specifies to use the pin_pathname clock to control registration cells inserted for output pins. The specified pin pathname should either be a primary input or a top-level instance output pin. If this switch is not specified, DFTAdvisor uses the clock of the neighboring cell in the output wrapper chain (when wrapper chains are inserted) or a test clock (when neighboring cell does not exist).
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-REG_Floating An optional switch that specifies to register unconnected I/Os. By default, unconnected I/Os are not registered.
-REG_Comb_feedthrough An optional switch that specifies to register combinational feed-throughs. A combinational feed-through is a path between a PI and PO that is either through combinational logic only or no logic at all. By default, combinational feed-throughs are not registered. Note: A multi fan-out PI is considered a combinational feed-through only when all of its fan-outs are combinational feed-throughs.
-REG_Seq_feedthrough An optional switch that specifies to register sequential feed-throughs. A sequential feedthrough is a path between PI and PO that has only one sequential cell and contains no combinational logic other than buffers and inverters. By default, sequential defaults are not registered. Note: A multi fan-out PI is considered a sequential feed-through only when all of its fan-outs are sequential feed-throughs.
Examples The following example illustrates how scan-based I/O registration can be used along with wrapper chains:
add cell model FDSQ -type scancell CLK D setup wrapper chains -exclude in1 in2 out1 out2 -input_number 1 -output_number 1 setup registered IO -include in1 in2 out1 out2 set system mode dft run report wrapper cells insert test logic
In this example, DFTAdvisor identifies the input and output wrapper cells upon issuing the Run command. Four I/O pins are excluded from identification by the Setup Wrapper Chains command and explicitly included for I/O registration by the Setup Registered IO command. The input registration cells are placed into the input wrapper chains and output registration cells are placed into the output wrapper chains. For more information, see the Setup Wrapper Chains command. Note that this registration allows inserting registration cells along with the identified wrapper cells. The scan cell used for registration can be modeled in many ways as long as it has the same input and output pins as a scan cell. The following figure shows a scan cell that is used as a control and observe point. When used as an observe point, it can capture data by means of the feedback
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connection. Also, note that the input registration cell uses the input wrapper chain scan enable signal, whereas the output registration cell uses the output wrapper chain scan enable signal.
Related Commands Add Cell Models Related Commands Setup Naming Setup Wrapper Chains
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Command Dictionary Setup Scan Identification
Setup Scan Identification

Scope: All modes Usage SETup SCan Identification {Full_scan | {Clock_sequential [-Depth integer]} | {SEQ_transparent [-Reconvergence {ON | OFf}]} | {Wrapper_chains [-Input_threshold {integer | Nolimit}] [-Output_threshold {integer | Nolimit}]} | [-Internal |-External filename] [-COntrollability integer] [-Observability integer] [-Backtrack integer] [-CYcle integer] [-Time integer] [-Min_detection floating_point]} | {AUtomatic [{-Percent integer} | {-Number integer}] {SCoap [-Percent integer | -Number integer]} | {STructure [-Percent integer | -Number integer] [-Loop {ON | OFf}] [-Self_loop {integer | Nolimit}] [-Depth {integer | Nolimit}]}} | None} [-MAx_length integer | -NUmber integer]
Description Specifies the scan identification methodology and amount of scan to consider during the identification run. Full Scan Arguments Full_scan A required literal that enables full scan for scan identification. Full scan is the fastest identification method, converting all scannable sequential elements to scan. You can use Tessent FastScan for ATPG on full scan designs. This is the default upon invocation of the tool. For more information on full scan, refer to Understanding Full Scan in the Scan and ATPG Process Guide. Clock Sequential Arguments Clock_sequential A required literal that enables clock sequential techniques for scan identification. This method selects scannable cells by cutting sequential loops and limiting sequential depth based on the -Depth switch. For more information on clock sequential scan, refer to Tessent FastScan Handling of Non-Scan Cells in the Scan and ATPG Process Guide. -Depth integer An optional switch and integer pair that specifies the maximum sequential depth on any sequential path. The maximum depth is 255. The default depth is 16.
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Sequential Transparent Arguments SEQ_transparent A required literal that enables the sequential transparency identification method for scan. Note that this technique is useful for data path circuits. Scan cells are selected such that all sequential loops, including self loops, are cut. For more information on sequential transparent scan, refer to Tessent FastScan Handling of Non-Scan Cells in the Scan and ATPG Process Guide. -Reconvergence {ON | OFf} An optional switch and literal pair that removes sequential reconvergent paths by selecting a scannable instance on the sequential path for scan. The default is ON. Wrapper Chain Arguments Wrapper_chains A required literal that enables wrapper chains for controllability and observability of wrapper cells. You can also set threshold limits to control the overhead sometimes associated with wrapper cell identification. For example, overhead extremes may occur when DFTAdvisor identifies a large number of wrapper cells for a given uncontrollable primary input or unobservable primary output. By setting the wrapper cell threshold limit for primary inputs (-Input_threshold switch) and primary outputs (-Output_threshold switch), you maintain control over the trade-off of whether to scan these wrapper cells or, instead, insert a controllability/observability scan cell. When DFTAdvisor reaches the specified threshold for a given primary input or primary output, it terminates the wrapper chain identification process on that primary input or primary output and unmarks any wrapper cell identified for that pin. For more information on wrapper chains, refer to Understanding Wrapper Chains in the Scan and ATPG Process Guide. -Input_threshold {integer | Nolimit} An optional switch and integer or literal pair that specifies the maximum number of wrapper cells for any given uncontrollable input. The default is nolimit. -Output_threshold {integer | Nolimit} An optional switch and integer or literal pair that specifies the maximum number of wrapper cells for any given unobservable output. The default is nolimit. Sequential Using ATPG Arguments -Internal An optional switch that bases scan identification on the internally-generated fault list. This is the default.
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-External filename An optional switch and string pair that specifies a fault file to base scan identification. The file must contain the user-defined fault list for identifying critical flip-flops that you want to convert to scan flip-flops.
-COntrollability integer An optional switch and integer pair that specifies the percentage of controllability test coverage. DFTAdvisor continues the scan identification process until it either reaches the specified test coverage or no productive scan candidates are available. The default upon invocation of DFTAdvisor is 100 percent.
-Observability integer An optional switch and integer pair that specifies the percentage of observability test coverage. DFTAdvisor continues the scan identification process until it either reaches the specified test coverage or no productive scan candidates are available. The default upon invocation of DFTAdvisor is 100 percent.
-Backtrack integer An optional switch and integer pair that specifies the number of conflicts DFTAdvisor encounters before aborting the target fault. The default upon invocation of DFTAdvisor is 30 conflicts.
-CYcle integer An optional switch and integer pair that specifies the number of test cycles DFTAdvisor encounters before aborting the target fault. The default upon invocation of DFTAdvisor is 16 test cycles.
-Time integer An optional switch and integer pair that specifies the CPU time in seconds that DFTAdvisor uses before aborting the target fault. The default upon invocation of DFTAdvisor is 100 seconds of CPU time.
-Min_detection floating_point An optional switch and floating point pair that specifies the minimum percentage of test coverage that a scan cell must provide. If a scan cell does not detect at least the specified minimum percentage of faults, DFTAdvisor does not select the cell for scan. The default upon invocation of DFTAdvisor is 0.01 percent.
Sequential Using Automatic Arguments AUtomatic An optional literal that enables the automatic technique for partial scan selection. This method selects scan cells using a combination of several scan selection techniques. The goal is to select the minimum set of best scan candidates needed to achieve high fault coverage.
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{-Percent integer} | {-Number integer} An optional switch and integer pair that specifies the maximum percentage of scan based on the total number of sequential elements in the design or absolute number of sequential instances that you want to identify as scan. By default, automatic scan selection analyzes the circuit and attempts to identify the minimum amount of scan needed to achieve high fault coverage. However, if a limit is set using either of those two switches, DFTAdvisor attempts to select the best scan cells within the limit. During the first scan selection and ATPG iteration, you should use the default to allow the tool to determine the amount of scan needed. Then, based on the ATPG results and how they compare to the required test coverage criteria, you can specify the exact amount of scan to select. The amount of scan selected in the first (default) ATPG iteration can be used as a reference point for determining how much more or less scan to select in subsequent iterations (such as what limit to specify).
Sequential Using SCOAP Arguments SEQUential A required literal that enables partial scan for scan identification. Partial sequential scan results in a subset of scannable sequential elements being converted to scan. Partial scan requires that you specify the SCOAP algorithm and how many scan elements to identify. SCoap An optional literal that enables the SCOAP-based technique for partial scan selection. SCOAP-based selection is typically faster than ATPG-based selection, and produces an optimal set of scan candidates. {-Percent integer} | {-Number integer} An optional switch and integer pair that specifies the percentage of scan based on the total number of sequential elements in the design or absolute number of sequential instances that you want to treat as scan instances. By default, the number of scan cells the tool selects is 50 percent. Sequential Using Structure Arguments SEQUential A required literal that enables partial scan for scan identification. Partial sequential scan results in a subset of scannable sequential elements being converted to scan. Partial scan requires that you specify the Structure algorithm and how many scan elements to identify. For more information on partial scan, refer to Understanding Partial Scan in the Scan and ATPG Process Guide. STructure An optional literal that enables structure-based scan selection techniques. These techniques include loop breaking, self-loop breaking, and limiting the designs sequential depth.
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{-Percent integer} | {-Number integer} An optional switch and integer pair that specifies the maximum percentage of scan based on the total number of sequential elements in the design or absolute number of sequential instances that you want to identify as scan. By default, the number of scan cells the tool can select is 100 percent (which means that there is no limit). When specifying the percentage, you are providing DFTAdvisor an absolute maximum percentage of scan cells it can choose. Often, it will choose less than you specify if it can do so and still meet the other criteria of selection.
-Loop {ON | OFf} An optional switch and literal pair that cuts global loops by inserting scan instances. The default is ON.
-Self_loop {integer | Nolimit} An optional switch and integer or literal pair that specifies the maximum number of consecutive self-loops allowed to remain on any sequential path. The default is 8.
-Depth {integer | Nolimit} An optional switch and integer or literal pair that specifies the maximum sequential depth allowed to remain on any sequential path. The default is 16.
No Scan Identification Argument None A literal that disables scan identification. Use this option in combination with the Add Test Points or Setup Test_point Identification command to insert test points (and not scan) in your design. If you want to insert both test points and scan, you should always do the scan identification before the test point identification to ensure an optimal test point selection. For more information on test points, refer to Understanding Test Points in the Scan and ATPG Process Guide. General Arguments -MAx_length integer | -NUmber integer Two optional, mutually-exclusive switch and integer pairs that specify one of the following: -MAx_length integer Specifies the maximum number of scan cells that DFTAdvisor can stitch into a scan chain. DFTAdvisor evenly divides the scan cells into scan chains that are smaller than the max_length integer. Final results depend upon the number of scan candidates. -NUmber integer Specifies the exact number of scan chains that you want DFTAdvisor to insert. Final results depend upon the number of scan candidates. The default number of chains is 1.
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Examples The following example sets up for full scan:

setup scan identification full_scan run
The following example sets up for a test point only run:

setup scan identification none setup test_point identification -control 10 -observe 5 run
Related Commands Add Test Points Report Sequential Instances Run Setup Pin Constraints Setup Test_point Identification Write Scan Identification
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Command Dictionary Setup Scan Insertion
Setup Scan Insertion

Scope: Setup Usage SETup SCan INsertion [-TEn pathname] [-TClk pathname] [-SClk pathname] [-SMclk pathname] [-SSclk pathname] [-SET pathname] [-RESet pathname] [-Write pathname] [-REAd pathname] [-Muxed | -Disabled | -Gated] [-Active {High | Low}] Description Specifies the pin parameters used by the Insert Test Logic command. Additional pin parameters are specified with Set Scan Enable, Set Bidi Gating, and Set Tristate Gating commands. DFTAdvisor uses the write control and read control pins when inserting test logic for RAMs. DRC verifies whether the RAMs can be held off when the write control pin is off. No test logic is inserted in RAMs that can be held off. If the new scan design is intended for Tessent FastScan/Tessent TestKompress, and the write clock input of the RAM is not controllable, it is multiplexed out by a new write clock. The selector to the mux is the test enable pin. You can use instance pin pathnames to define the test enable and clock pin names. The instance pathnames must trace back through a simple path (inverters or buffers only) to a primary input/output of the design, or you must manually develop the test procedure file and the dofile before running ATPG. Arguments -TEn pathname An optional switch and string pair that specifies a name for the test enable pin. By default, the test enable pin is named test_en. Use the -Active switch to specify whether the test enable pin is active low or active high. -TClk pathname An optional switch and string pair that specifies a pathname for the test clock pin for all scan types. If no test clock pin exists, one is created using the specified name. By default, the new test clock pin is named test_clk. If no test clock pin is specified, an existing clock pin from the design is used. Eligible clock pins must be defined with the Add Clocks command and capable of capturing data in a sequential cell without test logic in the clock path. The clock pin is selected at random. If no clock pins are found, a new one is created and named test_clk. If an internal pin is specified as the test clock pin, it is traced back to a predefined scan clock. If a predefined scan clock is found, the off-state value is used for test logic insertion. This tracing can only be performed along a single path that consists of only straight wire, inverters, and buffers.
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Use the -Active switch to specify whether the test clock pin is active high or low. This value is used to verify the off-state value on the scan clock found by tracing back from a specified internal pin. -SClk pathname An optional switch and string pair that specifies a pathname for the clock pin in clock-scan type scan. A scan clock pin is only created for the scan clock port in the dual-port type mux scan. By default, the new scan clock pin is named scan_clk. -SMclk pathname An optional switch and string pair that specifies a pathname for the scan master clock pin in LSSD type scan. By default, the scan master clock pin is named scan_mclk. -SSclk pathname An optional switch and string pair that specifies a pathname for the scan slave clock pin in LSSD type scan. By default, the scan slave clock pin is named scan_sclk. -SET pathname An optional switch and string pair that specifies a pathname for the set pin used for the flipflop or latch when inserting test logic. By default, the set pin is named scan_set. Use the -Active switch to specify whether the set pin is active high or low. -RESet pathname An optional switch and string pair that specifies a pathname for the reset pin used for the flip-flop or latch when inserting test logic. By default, the set pin is named scan_reset. Use the -Active switch to specify whether the reset pin is active high or low. -Write pathname An optional switch and string pair that specifies a pathname for the write control pin used for RAM when inserting test logic. By default, the write control pin is named write_clk. -REAd pathname An optional switch and string pair that specifies a pathname for the read control pin used for RAM when inserting test logic. By default, the read control pin is named read_clk. -Muxed | -Disabled | -Gated An optional switch that determines how the specified set, reset, write control, or read control lines are gated. These options can only be used with -Set, -Reset, -Write, and -Read switches specified in the same command. Options include: -Muxed Multiplexes all set and reset pins with the original signal. Only set and reset pins defined as clocks are affected. Default setting. -Disabled Uses an AND gate with the test enable signal to disable the set and reset inputs of flip-flops and the SEN type scan enable signal to disable the write and read clocks.
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-Gated Uses either the set and reset pins defined as clocks or the write and read clocks to disable the set and reset inputs of flip-flops. -Active High | Low An optional switch and literal pair that determines whether the scan clock activates the specified test enable, set, or reset pins on high or low. Within a single command, you can only use the -Active switch once. The -Active switch applies to any of the following pins specified in the command: -Ten, -Tclk, -Set, and -Reset. By default, all these signals are active on high. Example 1 The following example renames the test enable pin name to test_en_L, connects it to an internal node, and makes it active low during the scan insertion process.
add clocks 0 clock set system mode dft run setup scan insertion -ten modxyz/nand02/test_en_L -active low insert test logic -number 8
Example 2 The following example shows how to set different controls with successive Setup Scan Insertion commands.
setup scan insertion -ten TEST_MODE -active high setup scan insertion -reset RESET_L -active low setup scan insertion -write ATPG_WRT_INH -read ATPG_READ_INH setup scan insertion -set ATPG_SET -disabled
Related Commands Insert Test Logic Related Commands Report Scan Pins Set Bidi Gating Set Scan Enable Set Scan_enable Sharing Set Tristate Gating
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Command Dictionary Setup Scan Pins
Setup Scan Pins

Scope: All modes Usage SETup SCan Pins {Input | Output} [-INDexed | -Bused] [-Prefix base_name] [-INItial index#] [-Modifier incr_index#] [-Suffix suffix_name] Description Changes the scan-in or scan-out pin naming parameters to index or bus format. The Setup Scan Pins command specifies the index or bus naming conventions for scan-in or scan-out pins. The Report Environment command displays the names and values that DFTAdvisor uses for scan-in and scan-out pins when inserting scan chains. Once you have inserted scan chains, you can use the Report Scan Chains command to display the chosen index or bus naming convention for the scan-in pins and/or scan-out pins. Indexed names are in the form:
base_name + index# + suffix_name
Bused names are in the form:

base_name + [index#]
Arguments Input A literal specifying that DFTAdvisor apply the index or bus format on the scan-in pins. Output A literal specifying that DFTAdvisor apply the index or bus format on the scan-out pins. -INDexed An optional switch specifying that DFTAdvisor apply the index format to the scan-in or scan-out pin names. This is the default. -Bused An optional switch specifying that DFTAdvisor apply the bus format to the scan-in or scanout pin names. -Prefix base_name An optional switch and string pair that specifies the root name of the scan-in or scan-out pin. The default name is scan_in. -INItial index# An optional switch and integer pair that specifies the initial index value of the scan-in or scan-out pin name. The default value is 1.
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Command Dictionary Setup Scan Pins
-Modifier incr_index# An optional switch and integer pair that specifies the incremental value that to add to the index# when creating additional names with the same base_name. The default is 1.
-Suffix suffix_name An optional switch and string pair that specifies the name that you want to place after the index#. DFTAdvisor only uses this for indexed naming. The default is null.
Examples The following example configures scan insertion to use bus names for the scan-in pins and scanout pins, with the index number starting at 5 and incrementing by 2 for scan-in pins, and the index number starting at 4 and incrementing by 2 for scan-out pins:
add clocks 0 clock set system mode dft run setup scan pins input -bused -prefix scin -initial 5 -modifier 2 setup scan pins output -bused -prefix scout -initial 4 -modifier 2 insert test logic -number 7
Related Commands Insert Test Logic
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Command Dictionary Setup Shift_register Identification
Setup Shift_register Identification

Scope: Setup mode Usage SETup SHift_register Identification ON | OFF Description Enables/disables shift register identification. The default is ON. For more information about automatic identification of shift registers, see Automatic Recognition of Existing Shift Registers in the Scan and ATPG Process Guide. Arguments ON A required literal that enables shift registration identification. This is the default. OFf A required literal that disables shift registration identification. Example The following example disables automatic shift register identification.
setup shift_register identification off
Related Topics Report Scan Cells Report Shift Registers
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Command Dictionary Setup Test_point Identification
Setup Test_point Identification

Scope: Setup and Dft modes Prerequisites: If you only want test points (and not scan) identified, use the Setup Scan Identification commands None option. Usage SETup TEst_point IDentification [-COntrol integer] [-OBserve integer [-Primary_outputs [-EXClude pins]]] [-Verbose | -NOVerbose] [-Internal | {-External filename}] Description Specifies the number of control and observe test points that DFTAdvisor flags during the identification run. Test points allow you to gain access into the design to aid in detecting the undetectable faults, which increases the designs fault coverage. Test points may translate into additional input or output pins or scan cells at the chip level. Control test points allow you to gain access to the inputs of a gate (or multiple gates) where faults are undetectable. Usually the reason these faults are undetectable is because the ATPG tool cannot simultaneously force the correct combination of values onto the inputs. By creating a test point at that location, you give the ATPG tool direct control over the input values of that gate, which then gives the tool the ability to force (control) the necessary combination of input values to detect the previously undetectable faults. Observe test points allow you to gain access to the outputs of a gate (or multiple gates) where faults are undetectable. With observability problems, usually the reason these faults are undetectable is because the effects of this fault never propagate to a primary output or other observation point. A fault cannot be detected unless one or more primary outputs shows the fault effect. By creating a test point at that location, you allow direct access to the fault effect, which changes the fault from an unobservable (undetected) fault to a detected fault. Once you enable DFTAdvisor to identify the optimum test point locations (with the Setup Scan Identification command) and set the number of each type of test point that DFTAdvisor is to locate (with the Setup Test_point Identification command), you need to enter Dft mode (with the Set System Mode command). After successfully entering Dft mode, you perform the test point analysis, based on the SCOAP pin selection technique, with the Run command. While performing the analysis, DFTAdvisor lists the test point locations that it identifies. Tip: See Analyzing the Design for Controllability and Observability of Gates in the Scan and ATPG Process Guide.
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Arguments -COntrol integer An optional switch and integer pair that specifies how many test points you want DFTAdvisor to identify to aid in increasing the controllability of the design. The default upon invocation of DFTAdvisor for identifying test points for controllability is 0. -OBserve integer [-Primary_outputs [-EXClude pins]] An optional switch and integer pair that specifies how many test points you want DFTAdvisor to identify to aid in increasing the observability of the design. The default upon invocation of DFTAdvisor for identifying test points for observability is 0. -Primary_outputs An optional switch that specifies to add an observe point to primary outputs. The implementation of this option depends on the settings in the Setup Test_point Insertion command. -EXClude pins An optional switch and repeatable string that excludes the specified primary output pins from use as observe points. -Verbose | -NOVerbose An optional switch that specifies the amount of information that DFTAdvisor displays during test point generation. -Internal | {-External filename} An optional switch or switch and string that specifies which faults to use when performing SCOAP-based test point selection. -Internal A switch that specifies to consider all faults. This is the default. -External filename A switch and string that specifies to use only those faults listed in the specified faults list file for evaluating the benefit of a test point. Detected, redundant, and unused fault found in the file are ignored. Any other faults previously loaded are discarded. Typically, this fault list file is saved after running ATPG. This file only needs to be set once, and it is used by all SCOAP test point selection methods until it is changed (with -Internal or -External).
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Examples The following example shows the flow of having DFTAdvisor automatically identify and insert two test points for controllability:
set system mode dft setup scan identification none setup test_point identification -control 2 run // // // Performing test_point identification ... Number of control points to be identified = 2 Number of observe points to be identified = 0
insert test logic -test_point on report test points Control [Selected]: /CNTR/U783/ZN Control [Selected]: /ADDR/U23/D1 or2a or2a test_cntl1 test_cntl2
Related Commands Add Cell Models Add Test Points Insert Test Logic Report Test Points Setup Scan Identification Setup Scan Insertion
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Command Dictionary Setup Test_point Insertion
Setup Test_point Insertion

Scope: All modes Prerequisites: You must identify model_name, and the models for use with the -New_scan_cell option, with the Add Cell Models command before using the -Model or -New_scan_cell switch. Usage
Control Point Usage
SETup TEst_point INsertion [-Control [{pin_pathname -None} | -New_scan_cell | {-Model model_name}]] [-REconvergence {OFf | ON}] [-CShare integer]
Observe Point Usage
SETup TEst_point INsertion [-Observe [{pin_pathname -None} | {observe_enable -Existing_scan_cell} | -New_scan_cell | {-Model model_name}]] [-REconvergence {OFf | ON}] [-OShare integer] Description Specifies how DFTAdvisor configures the inputs for the control test points and the outputs for the observe test points. The Setup Test_point Insertion command modifies how the Insert Test Logic command inserts test points. By default, the Insert Test Logic command creates a primary input for the control test points named test_cntrl and a primary output for the observe test points named test_obs. You can change these default names with the pin_pathname argument. When you specify that you want new scan cells inserted for test points (-Model or New_scan_cell switch), DFTAdvisor inserts these new scan cells locally on the module where the test point resides. If you specify that you want an XOR tree, DFTAdvisor analyzes the list of new observe points and groups them based on hierarchical information. The tool then inserts the resulting observe scan cell in the module where the XOR tree emerges. Each of the new scan cells is fitted into nearby existing scan chains that do not exceed the chain length limit. The clock for each new scan cell is the same as the clock of the scan cell it feeds in the chain. If DFTAdvisor cannot find a nearby chain, it drops the test point. If you want DFTAdvisor to automatically identify test points, you can use the Setup Scan Identification command in combination with the Setup Test_point Identification and Run commands. After DFTAdvisor identifies the optimum test points, you then insert those test points with the Insert Test Logic command. Arguments -Control An optional switch that specifies how to configure the inputs for control test points.
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If you use the -None switch (the default) in combination with this switch, DFTAdvisor does not use a scan cell, instead controlling the test point it inserts with the pin specified by the prefix name, pin_pathname, as shown in Figure 2-3. Figure 2-3. Control Point Example for -None and -Model
If you use the -Model switch in combination with the -Control switch, DFTAdvisor controls the test point by adding an additional scan cell, defined by model_name, when the test logic is synthesized (Figure 2-3). Each of the new scan cells is fitted into a nearby existing scan chain that does not exceed the chain length limit. The clock for each new scan cell is the same as the scan cell it feeds in the chain. If DFTAdvisor cannot find a nearby chain, it drops the control point. If you use the -New_scan_cell switch in combination with the -Control switch, DFTAdvisor controls the test point by adding an additional scan cell when the test logic is synthesized (Figure 2-4). The new scan cell is fitted into a nearby existing scan chain that does not exceed the chain length limit. DFTAdvisor chooses the new cell to be edge-compatible with the existing scan cells in the chain. The clock for each new scan cell is the same as the scan cell it feeds in the chain. If DFTAdvisor cannot find a nearby chain, it drops the control point.
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Figure 2-4. Control Point Example for -New_scan_cell
-Observe An optional switch that specifies how to configure the outputs for observe test points. If you use the -None switch (the default) in combination with this switch, DFTAdvisor controls the test point it inserts with the pin specified by the prefix name, pin_pathname, as shown in Figure 2-5. Figure 2-5. Observe Point Example for -None and -Model
If you use the -Model switch in combination with the -Observe switch, DFTAdvisor controls the test point by adding an additional scan cell when the test logic is synthesized, as shown in Figure 2-5. Each of the new scan cells is fitted into a nearby existing scan chain
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that does not exceed the chain length limit. The clock for each new scan cell is the same as the scan cell it feeds in the chain. If DFTAdvisor cannot find a nearby chain, it drops the observe point. If you use the -New_scan_cell switch in combination with -Observe, it behaves much the same as when using -Model, except DFTAdvisor will choose the new cell to be edgecompatible with the existing scan cells in the target scan chain when the test logic is synthesized (Figure 2-6). This matching of the rising/falling edge attribute will prevent D7 type DRC violations. Each of the new scan cells is fitted into nearby existing scan chains that do not exceed the chain length limit. The clock for each new scan cell is the same as the scan cell it feeds in the chain. If DFTAdvisor cannot find a nearby chain, it drops the observe point. Figure 2-6. Observe Point Example with -New_scan_cell
If you use the -Existing_scan_cell switch in combination with the -Observe switch, DFTAdvisor controls the test point by adding multiplexing to an existing nearby scan cell when the test logic is synthesized, as shown in Figure 2-7. The observe_enable specifies the name of the observe enable signal that controls the input to the scan cell.
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Figure 2-7. Observe Point Example with -Existing_scan_cell
pin_pathname -None An optional string and switch pair that specifies for DFTAdvisor to only insert the test point without inserting an additional scan cell, as shown in Figure 2-3 and Figure 2-5. This is the default.
-Existing_scan_cell observe_enable An optional switch and string pair that specifies for DFTAdvisor to use nearby scan cells for observation points, as shown in Figure 2-7. The observe point is propagated to a nearby scan cell and multiplexed with the functional path D input of the cell. In this case, you must specify the data_in parameter in the scan_definition section of the model for all scan cells used in the design. This option is only valid with the -Observe switch. observe_enable The observe_enable specifies the name of the observe enable signal that controls the input to the scan cell.
-New_scan_cell An optional switch that specifies for DFTAdvisor to determine the rising/falling edge of scan cells in use in the nearby target scan chain, and to use an edgecompatible scan cell model for the new scan cell. See Figure 2-4 and Figure 2-6. You must identify the type of the scan cell models with the Add Cell Models command or have the type assigned in the library models before using this switch. -Model modelname An optional switch and string pair that specifies for DFTAdvisor to insert a cell along with the test point, as shown in Figure 2-3 and Figure 2-5. The specified model must be of type SCANCELL. You must identify the type of the modelname with the Add Cell Models command or have the type assigned in the library model before using this switch.
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-REconvergence {OFf | ON} An optional switch and literal pair that enables the sharing of test points based on reconvergence analysis. DFTAdvisor performs reconvergence analysis to determine which test points can share the same pin and scan cell. If the backward cones of observe points or the forward cones of control points intersect, the test points are not shared. When this option is On, the amount of sharing is limited, which guarantees that no fault masking can occur due to sharing (often a negligible phenomenon). The sharing is also influenced by the existence of scan chains inside of modules when new scan cells are used for testpoints. In this case, a nearby scan chain may be used for the new scan cell created by the shared tree of test points. The default is Off.
-CShare integer An optional switch and integer pair that specifies the maximum number of control points that can share a primary input or a single scan cell. When you issue the Setup Test_point Insertion command, the default maximum number of control points that DFTAdvisor will allow to share a single scan cell or primary input is 16. Not all control points can share a single scan cell. If you enable the -Reconvergence option and the forward trace of any two control points intersect, they must use separate scan cells. This may result in less than the maximum number of control points sharing any given scan cell.
-OShare integer An optional switch and integer pair that specifies the maximum number of observe points you want DFTAdvisor to share with a primary output or a single scan cell. When you issue the Setup Test_point Insertion command, the default maximum number of observe points that DFTAdvisor will allow to share a single scan cell or primary output is 16. Not all observe points can share a single scan cell. If you enable the -Reconvergence option and the backward trace of any two observe points intersect, they must use separate scan cells. This may result in less than the maximum number of observe points sharing any given scan cell.
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Examples The following example shows the flow of having DFTAdvisor automatically identify and insert two test points for controllability:
set system mode dft setup scan identification none setup test_point identification -control 2 run // // // // // Performing test_point identification ... Number of control points to be identified = 2 Number of observe points to be identified = 0 1: CV1=16458424 gate_index=3805 INV /CNTR/U783/ZN 2: CV1=16458417 gate_index=1058 BUF /ADDR/U23/D1
add cell models dffslp -type scancell CK D SDI SE add cell models or2a -type Or add cell models and2a -type and setup test_point insertion -control test_cntrl1 -model dffslp insert test logic -test_point on report test points Control [Selected]: /CNTR/U783/ZN Control [Selected]: /ADDR/U23/D1 and2a or2a test_cntl1 test_cntl1
Related Commands Add Cell Models Insert Test Logic Setup Scan Identification Setup Test_point Identification
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Command Dictionary Setup Tied Signals
Setup Tied Signals

Scope: Setup mode Usage SETup TIed Signals 0 | 1 | X | Z Description Changes the default value for floating pins and floating nets that do not have assigned values. The Setup Tied Signals command specifies the default value that the tool ties to all floating nets and floating pins that are not specified with the Add Tied Signals command. Upon invocation of the tool, if you do not assign a specific value, the tool assumes the default value is unknown. If the model is already flattened and then you use this command, you must delete and recreate the flattened model. Arguments 0 A literal that specifies to tie the floating nets or pins to logic 0 (low to ground). 1 A literal that specifies to tie the floating nets or pins to logic 1 (high to voltage source). X A literal that specifies to tie the floating nets or pins to unknown. Z A literal that specifies to tie the floating nets or pins to high-impedance. Examples The following example ties floating net vcc to logic 1 and ties the remaining unspecified floating nets and pins to logic 0, then performs a scan identification run.
setup tied signals 0 add tied signals 1 vcc set system mode dft run
Related Commands Add Tied Signals Delete Tied Signals Report Tied Signals
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Command Dictionary Setup Wrapper Chains
Setup Wrapper Chains

Scope: Setup mode Prerequisites: At-speed test cells must be specified with the Add Cell Models command or cell_type model attribute. Usage SETup WRapper Chains [-EXClude pin_names] [{-INPUT_NUMber integer} | {-INPUT_MAX_length integer}] [{-OUTPUT_NUMber integer} | {-OUTPUT_MAX_length integer}] [-INPUT_Flops_reached {integer | Nolimit}] [-OUTPUT_Flops_reached {integer | Nolimit}] [-INPUT_Gates_level integer] [-OUTPUT_Gates_level integer] [{-No_internal_feedback | -Allow_internal_feedback | -Test_points}] [-IO_registration {ON | OFf}] [-AT_SPEED_TEST_FLOP_Insertion {ON | OFf}] [-AT_SPEED_TEST_FLOP_Model modelname] Description Specifies wrapper chains for scan insertion as follows: Setup Pin Constraints CX -Lbist_exclude Setup Output Masks On -Lbist_exclude Set Scan Type mux_scan Setup Scan Identification Wrapper_chains Note In the 2009_2 release and all subsequent releases, the Setup Wrapper Chains command performs both wrapper chain and core chain insertion in a single run. This is a change in behavior from previous releases and is not backward-compatible. Wrapper cells are sequential elements used as input/output registration cells (cells only accessible via combinational logic from primary inputs or primary outputs). Depending on the specified switches, wrapper cells are identified and distributed to scan chains in either one-domain or two domains. Wrapper cell distribution is determined by the switches: -Input_number, -Input_max_length, Output_number, or -Output_max_length. If any of these switches are specified, two-domain distribution is used. If none are specified, one-domain distribution is used. One-domain distribution Wrapper cells are distributed to scan chains as specified by the -number, -max_length, and -nolimit arguments of the Insert Test Logic command.
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The SEN type scan_enable signal is used for both one-domain wrapper chains and core chains. Two-domain distribution Input and output wrapper cells are distributed separately to input wrapper chains and output wrapper chains. When two-domain distribution is enabled, the -Number, -Max_length, and -Nolimit arguments of the Insert Test Logic command are ignored and separate, dedicated scan enable signals are used; SEN_IN type for input, SEN_OUT type for output, and SEN for core chains.
You can modify the scan enable signals with the Set Scan_enable Sharing command and the Set Scan Enable command. If you specify to insert both an at-speed test flip-flop at the beginning of each wrapper chain (-AT_SPEED_TEST_FLOP_Insertion option) and a lockup cell at the end of each wrapper chain (Set Lockup Cells commands argument (-CApture_edge_at_scan_chain_input option), the order of stitching is: scan input, lockup cell, at-speed test flip-flop, and first wrapper chain cell. Inserted at-speed flip-flops are reported as part of the wrapper chain by the Report Scan Cells command. You can specify how wrapper cells are identified with the -No_internal_feedback, -Allow_internal_feedback, and -Test_points switches. By default, DFTAdvisor identifies the wrapper cells by structurally tracing forward from the primary inputs until the first level of memory cells is reached and then, traces backward from the primary outputs until the last level of memory cells is reached. Figure 2-8 illustrates the default tracing where the traced logic and identified wrapper cells are shown in bold. Figure 2-8. I/O Identification Default Tracing Mode
To control all the inputs of the combinational logic traced from the primary inputs, use the Allow_internal_feedback switch. Figure 2-9 shows the gate inputs with feedback connections marked as a and b. Tracing backward from these inputs identifies one additional cell from the second level of memory cells to include in the input wrapper chains.
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Figure 2-9. All Input Logic Tracing
Depending on the circuit topology, tracing such internal feedback may include an impractical number of core cells (not first or last level memory cells). In that case, you can control the feedback inputs on the logic gates by means of control points. In the above circuit, only the gate input b requires a control point because gate input a is controlled from its driver gate which is an identified input wrapper cell. In a multiple-phase testing of wrapper cells and core cells (i.e. hierarchical at-speed testing at a higher level of the design), the gate output marked as c cannot be observed when the testing of core cells is active and the testing of input wrapper cells is inactive. In that case, an observe point may be necessary at the gate output c. The automatic insertion of such control and observe points can be specified using the -Test_points switch. Upon issuing the Run command, the test point locations are identified along with the wrapper cell candidates. The identified test points are scheduled for insertion automatically. At this point, you can examine and modify the scheduled test points with the following commands: Report Test Points, Add Test Points, and Delete Test Points. The actual insertion of the test points occurs later when the Insert Test Logic command is issued. Figure 2-10 highlights the logic DFTAdvisor adds as the control and observe points. DFTAdvisor uses SEN_OUT type scan enable for the control points and SEN_IN type scan enable for the observe points, where possible. Figure 2-10. Control and Observe Point Insertion
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Arguments -Exclude pin_names An optional switch and a repeatable string that specifies the primary input/output pins to exclude from the wrapper cell identification process. The system clock pins (set, reset, clock, etc.) and test-related pins such as scan I/O, scan enable and test enable pins are excluded from the identification process automatically. -INPUT_NUMber integer An optional switch and an integer pair that enables two-domain distribution and specifies the number of scan chains for input wrapper cells. The default value for the number of input wrapper chains is 1. -INPUT_MAX_length integer An optional switch and an integer pair that enables two-domain distribution and specifies the maximum length of scan chains for input wrapper cells. The default value for the maximum length of the input wrapper chains is unlimited. -OUTPUT_NUMber integer An optional switch and an integer pair that enables two-domain distribution and specifies the number of scan chains for output wrapper cells. The default value for the number of output wrapper chains is 1. -OUTPUT_MAX_length integer An optional switch and an integer pair that enables two-domain distribution and specifies the maximum length of scan chains for output wrapper cells. The default value for the maximum length of the output wrapper chains is unlimited. -INPUT_Flops_reached {integer | Nolimit} An optional switch and integer or literal pair that specifies the maximum number of sequential elements allowed to be reached during the forward tracing from a primary input. Default is 256. -OUTPUT_Flops_reached {integer | Nolimit} An optional switch and integer or literal pair that specifies the maximum number of sequential elements to be reached during the backward tracing from a primary output. Default is 256. -INPUT_Gates_level integer An optional switch and integer pair that specifies the maximum number of levels of combinational gates to be traversed during the forward tracing from a primary input until the first sequential element is reached. Default is 32. -OUTPUT_Gates_level integer An optional switch and integer pair that specifies the maximum number of levels of combinational gates to be traversed during the backward tracing from a primary output until the first sequential element is reached. Default is 32.
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{-No_internal_feedback | -Allow_internal_feedback | -Test_points} An optional switch that specifies the identification mode for input wrapper cells. Options include: -No_internal_feedback Identifies the first level of registration cells by forward tracing from the primary inputs. This is the default mode. -Allow_internal_feedback Identifies additional cells with outputs fed back into the combinational logic between the primary inputs and the first level of registration cells. -Test_points switch Inserts control and observe points at the feedback connections instead of identifying additional cells from these feedback connections.
-IO_registration {ON | OFf} An optional switch and literal pair that specifies whether to automatically use the current I/O registration mechanism to add wrapper cells for the primary inputs and outputs that fail wrapper cell identification. Wrapper cell identification will fail in the following cases:
o o
If tracing limits are exceeded during wrapper cell identification for an I/O. If you have specified the identified sequential cell to be a non-scan instance or if DRC has marked it as a non-scan instance. If the identified sequential cell is part of an existing scan chain. If a blackbox is encountered during the wrapper cell identification for an I/O. If no sequential cells were identified during wrapper cell identification for an I/O. If the currently identified sequential cell is already identified as a wrapper cell for an I/O of the opposite direction.
o o o o
Options include: ON A new wrapper cell is inserted for each failed primary input and output. OFF A wrapper cell is not automatically inserted for each failed primary input and output. This is the default. -AT_SPEED_TEST_FLOP_Insertion {ON | OFf} An optional switch and literal pair that specifies whether to automatically insert an at-speed test flip-flop at the beginning of each wrapper chain. Default is On. If a preferred model is not specified with the -AT_SPEED_TEST_FLOP_Model switch, DFTAdvisor uses the first DFF model declared by the Add Cell Models command; -AT_SPEED_TEST_FLOP_Model modelname An optional switch and literal pair that specifies the DFF model to use for an at-speed test flip-flop when more than one DFF model is declared via the Add Cell Models command.
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Examples The following example excludes the primary I/O pins a and b from wrapper cell identification; sets up four input wrapper scan chains and eight output wrapper scan chains; sets sen1 and sen2 for the scan enable pin names of the input and output wrapper chains and reports the sequential cells identified per I/O pin.
add cell model LATX -type dlat G D add cell model INVX -type inv setup wrapper chains -input_num 4 -output_num 8 -exclude a b set scan enable sen1 -wrapper_chain -input set scan enable sen2 -wrapper_chain -output set system mode dft run report wrapper cells insert test logic -clock merge -edge merge
Related Commands Add Test Points Delete Test Points Related Commands Report Test Points Run Set Lockup Cell Setup Output Masks Setup Registered IO Setup Scan Identification Set Scan Enable Set Scan_enable Sharing Write Netlist
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Command Dictionary System
System
Scope: All modes Usage SYStem os_command Description Passes the specified command to the operating system for execution. The System command executes one operating system command without exiting the currently running application. Arguments os_command A required string that specifies any legal operating system command. Examples The following example performs a scan identification run, then displays the current working directory without exiting DFTAdvisor:
set system mode dft run system pwd
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Command Dictionary Write Atpg Setup
Write Atpg Setup

Scope: Dft mode Prerequisites: Scan chains must be inserted. Usage WRIte ATpg Setup basename [-Replace] [-Procfile] [-NO_merge] [-Edt] [-All_internal_clocks] Description The Write Atpg Setup command writes a test procedure file and the dofile file for the existing scan chains. You can use these files to identify the scan chains when loading the scan design into Tessent FastScan. By default, the test procedure and the dofile for newly inserted scan chains are merged with those for existing scan chains. The order of the commands in the test procedure file determine the different levels of test procedure file information produced by this command. If you execute Write ATPG Setup without first using the Read Procfile command, a test procedure file that contains default timeplates and the procedures needed for ATPG setup (for example, shift, load_unload, and test_setup) are created. If you run Read Procfile and load a test procedure file that contains timeplate definitions, non-scan procedure definitions (capture, ram_sequential, and others), and empty or template scan procedures, and then execute the Write Atpg Setup command, a more complete test procedure file is created. Note If the test procedure file loaded with the Read Procfile command contains scan procedures (for example, shift and load_unload), they are replaced by ones generated with the Write Atpg Setup command based on test logic inserted during the current session. DFTAdvisor issues a W14 warning each time it replaces a procedure. However, it uses timeplates specified in the original procedure file for the newly-generated procedures. The only exceptions are for the test_setup procedure. Instead of being replaced, the events created by the Write Atpg Setup command are appended to the end of the test_setup procedure. Arguments basename A required string that specifies the root name for the test procedure and dofile. The files produced are basename.testproc and basename.dofile. -Replace An optional switch that replaces the contents of a file that already exists. By default, files are not replaced.
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-Procfile An optional switch that creates the test procedure file. By default, a test procedure file is created.
-No_merge An optional switch that prevents merging the test procedure and the dofile of the newly inserted scan chains with those of the existing scan chains. By default, the test procedures and dofiles are merged.
-Edt An optional switch that writes EDT-specific commands to the ATPG setup files. For more information, see the Setup EDT command.
-All_internal_clocks An optional switch that specifies to write all internally defined clocks to the timeplate, to the ATPG dofile, and to the shift procedure.
Example 1 The following example writes the test procedure, the dofile, and the new netlist for the inserted scan chains to the specified filenames:
add clocks 1 clk1 add clocks 0 clk0 set system mode dft run insert test logic write atpg setup scan -replace write netlist scan.v -verilog
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Example 2 The following example uses the write atpg setup -all_internal_clocks switch on a design with a single internal clock (output net is pll/out1) and a single top-level clock (clk1) to specify to write out the internally defined clock as shown in the following generated test procedure file.
... procedure shift = scan_group grp1 ; timeplate gen_tp1 ; // cycle 1 starts at time 0 cycle = force_sci ; measure_sco ; pulse clk1 ; pulse pll/out1 ; //internal PLL output net is pulsed during scan chain shifting end; end; procedure load_unload = scan_group grp1 ; timeplate gen_tp1 ; // cycle 1 starts at time 0 cycle = force clk1 0 ; force pll/out1 0 ; //internal PLL output initialized at start of scan unload sequence force scan_en 1 ; end ; apply shift 4; end;
Related Commands Insert Test Logic Read Procfile Setup EDT Write Netlist Write Procfile
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Command Dictionary Write Formal_verification Setup
Write Formal_verification Setup

Scope: Dft mode Usage WRIte FOrmal_verification Setup constraint_filename [-Replace] Description Writes a constraints driver file for the formal verification tool, FormalPro. You can use the constraints file with FormalPro to verify that any DFTAdvisor additions have not functionally changed the design. The output file describes the DFTAdvisor changes that FormalPro needs to ignore when comparing against the non-scan (reference) design. The constraints file will contain the following constraints: Force all scan inputs to 1 Ignore all scan outputs (including scan-outs shared with primary output pins) Force scan enables to be in functional mode Constrain test_en, lbist_en, and test_obs to their inactive states
When you enable observe point sharing and sink the tree into a new scan cell, FormalPro automatically ignores the extra registers (observe point registers) found in the modified design. You can perform formal verification after any DFTAdvisor step. FormalPro always compares the original non-scan design to the current output of DFTAdvisor. Arguments constraint_filename A required string that specifies the name of the file to which DFTAdvisor writes the formal verification constraints file. -Replace An optional switch that specifies for DFTAdvisor to replace the contents of the file, constraint_filename, if the file already exists.
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Command Dictionary Write Formal_verification Setup
Examples The following example writes out a constraints file named scan.constraints and also includes a shell script to invoke FormalPro: //scan dofile //perform scan analysis and test logic synthesis
write netlist m8051_scan.v -replace write formal_verification setup scan.constraints -replace exit -d
#shell script to run FormalPro

<Path_to_FormalPro_Tree>/bin/formalpro -a -verilog m8051_core.v \ -b -verilog m8051_scan.v -common -lib lcbg10p_atpg.lib \ -constraintfile scan.constraints -overwrite
Related Commands Write Netlist
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Command Dictionary Write Loops
Write Loops
Scope: Dft mode Usage WRIte LOops filename [-Replace] Description Writes a list of all loops to the specified file. The Write Loops command writes all loops in a circuit to a file. For each loop, the report indicates whether the loop was broken by duplication. Loops that are not broken by duplication are shown as being broken by a constant value, which means the loop is either a coupling loop, or has a single multiple fanout gate. The report also includes the pin pathname and gate type of each gate in each loop. You can display the loops report information to the transcript by using the Report Loops command. Arguments filename A required string that specifies the name of the file to which DFTAdvisor writes the loop report information. -Replace An optional switch that specifies for DFTAdvisor to replace the contents of the file, if the file already exists. Examples The following example writes a list of all loops to a file:
set system mode dft write loops loop.info -replace
Related Commands Report Loops
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Command Dictionary Write Netlist
Write Netlist
Scope: All modes Usage WRIte NEtlist filename [-Replace] [-User_setup] [-Split_bus] [{-BLock module_name... {-FUll | -CHildren} -FIle block_filename}] [-PREserve_assign] Description Writes the current design to a Verilog netlist. Depending on the process, the current design is either the one used to invoke DFTAdvisor or the one created by the scan insertion process. This command can be used to write out: A complete design netlist to a specified file. A netlist for particular modules and all of their children to a specified file. A netlist for the children of particular modules to a specified file.
Arguments filename A required string that specifies a pathname for the Verilog netlist. -Replace An optional switch that overwrites the contents of the specified file if it already exists. -User_setup An optional switch that writes the design netlist based on the state of the current design, with respect to Add Black Box and Delete Black Box commands. -Split_bus An optional switch that writes out mapped buses as individual pins in the port mapping. By default, all pins are listed together. For example: By default, bus pins are written as follows:
ex_mod ex_inst (.ex_bport (a[3:0]), ...
If the -Split_bus switch is used, bus pins are written as follows:

ex_mod ex_inst (.ex_bport ({a[3], a[2], a[1], a[0]}), ...
-Block module_name... An optional switch and a repeatable string that specifies the names of the modules whose netlists are redirected to a separate file. Module definitions redirected to the separate file are not written out to the file specified by the filename argument. The output content is determined by the specification of the -Full | -Children switch. The output is written to the file specified by the -File switch and block_filename string pair.
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If -Block is used, the -Full | -Children and -File switches are required as shown. Neither of these required switches can be used without -Block.
[{-BLock module_name... {-FUll | -CHildren} -File block_filename}]
-FUll | -CHildren A switch that specifies, for each module_name string, whether the netlist for the moduless complete hierarchy (module_name) is redirected to a separate file or only its children modules are redirected. This switch is required when -Block is specified; it is invalid when -Block is not specified.
-FIle block_filename A switch and string that specifies the file to which the separate netlists are written. This switch is required when -Block is specified; it is invalid when -Block is not specified.
-PREserve_assign An optional switch that specifies not to replace assign statements in the incoming netlist with supply statements when writing out the netlist. Nets defined with the supply statement in the incoming netlist are written out unchanged (using supply) but none of the original assign statements are modified. By default, nets assigned to a constant 0 or 1 via an assign statement are replaced with supply nets. This option is useful if you are using a layout tool that does not recognize supply0 and supply1 nets when identifying nets that are part of the power grid as part of an automatic flow.
Example 1 The following example adds scan and writes out a Verilog netlist named verilog.scan.
add clocks 0 clock set system mode dft setup scan identification sequential atpg -percent 50 run insert test logic -max_length 10 write netlist verilog.scan
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Example 2 The following example writes out the A module and its sub-blocks to one file and writes the remaining netlist to the main output file.
add clock 0 clk set scan enable /uA/ubuf/Y set system mode dft run insert test logic report scan chains write netlist results/c_scan.v -block A -full -file results/blockA.v
Given the following input:

module C (clk); input clk; dff udff (.CLK(clk)); endmodule module A (clk, sen); input clk, sen; buf02 ubuf(.A(sen), .Y()); C uC (.clk(clk)); endmodule module top (clk, sen); input clk, sen; A uA (.clk(clk), .sen(sen)); endmodule
The following output is written to results/blockA.v. The remainder of the output is written to results/c_scan.v.
module C ( clk , scan_in1 , scan_out1 , sen ); input clk , scan_in1 , sen ; output scan_out1 ; sff udff (.D () , .SI ( scan_in1 ) , .SE ( sen ) , .CLK ( clk ) , .Q ( scan_out1 )); endmodule module A ( clk , sen , scan_in1 , scan_out1 ); input clk , sen , scan_in1 ; output scan_out1 ; wire Y ; buf02 ubuf (.A ( sen ) , .Y ( Y )); C uC (.clk ( clk ) , .scan_in1 ( scan_in1 ) , .scan_out1 ( scan_out1 ) , .sen ( Y )); endmodule
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Example 3 This example writes out the child hierarchy of the specified A module; the remaining netlist including module A is written to the main netlist.
add clock 0 clk set scan enable /uA/ubuf/Y set system mode dft run insert test logic report scan chains write netlist results/c_scan.v -block A -children -file results/blockA.v
Given the same input as shown in the previous example, the following output is written to results/blockA.v. The remainder of the output is written to results/c_scan.v:
module C ( clk , scan_in1 , scan_out1 , sen ); input clk , scan_in1 , sen ; output scan_out1 ; udff (.D () , .SI ( scan_in1 ) , .SE ( sen ) , .CLK ( clk ) , .Q ( scan_out1 )); endmodule sff
Related Commands Write Atpg Setup Add Black Box Delete Black Box
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Command Dictionary Write Primary Inputs
Write Primary Inputs

Scope: All modes Usage WRIte PRimary Inputs filename [-Replace] [-All | primary_input_pin] Description Writes primary inputs to the specified file. The Write Primary Inputs command writes a list of either all the primary inputs of a circuit or a specific list of primary inputs that you specify into a file where it can be reviewed. This command is identical to the Report Primary Inputs command except the data is written into a file. Arguments filename A required string that specifies the name of the file to which DFTAdvisor writes the primary inputs. -Replace An optional switch that specifies for DFTAdvisor to replace the contents of the file, if the file already exists. -All An optional switch that specifies to write all the primary inputs to the file. This is the default. primary_input_pin An optional repeatable string that specifies a list of primary input pins that you want to write to the file. Examples The following example writes all primary inputs to a file:
write primary inputs inputfile
Related Commands Report Primary Inputs
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Command Dictionary Write Primary Outputs
Write Primary Outputs

Scope: All modes Usage WRIte PRimary Outputs filename [-Replace] [-All | primary_output_pin] Description Writes primary outputs to the specified file. The Write Primary Outputs command writes a list of either all the primary outputs of a circuit or a specific list of primary outputs that you specify into a file where it can be reviewed. This command is identical to the Report Primary Outputs command except the data is written into a file. Arguments filename A required string that specifies the name of the file to which DFTAdvisor writes the primary outputs. -Replace An optional switch that specifies for DFTAdvisor to replace the contents of the file, if the file already exists. -All An optional switch that specifies to write all the primary outputs to the file. This is the default. primary_input_pin An optional repeatable string that specifies a list of primary output pins that you want to write to the file. Examples The following example writes all primary outputs to a file:
write primary outputs outputfile
Related Commands Report Primary Outputs
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Command Dictionary Write Procfile
Write Procfile
Scope: DFT mode Usage WRIte PRocfile proc_filename [-Replace] [-Full] Description Writes existing procedure and timing data to the named test procedure file. The Write Procfile command writes out existing procedure and timing data to the named test procedure file. Arguments proc_filename A required string that specifies the name of the file to which you want to write existing procedure and timing data. -Replace An optional switch that replaces the contents of the file if the proc_filename already exists. -Full An optional switch that causes the tool to parse the ATPG pattern list (if any) and create all needed non-scan procedures before writing the procedure file data. Note The -Full option can cause the Write Procfile command to take more time if there are a large number of ATPG-generated patterns in the internal pattern list. Examples The following example writes the existing procedure and timing data to the specified file:
write procfile myprocfile.proc
Related Commands Add Scan Groups Read Procfile Report Procedure Report Timeplate
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Command Dictionary Write Scan Identification
Write Scan Identification

Scope: All modes Usage WRIte SCan Identification filename [-Replace] [-Full | -Identified | -Defined] [-DOfile | -Backannotation] Description Writes a list of the scan instances that DFTAdvisor has identified or you have defined as scan cells. The Write Scan Identification command writes scan cell instances that either DFTAdvisor identified during the identification process or that you defined by using the Add Scan Instances or Add Scan Models commands. The Write Scan Identification command lists the scan instances in descending order, with the first instance being the most critical scan instance. If you are identifying scan sequential, the Write Scan Identification command displays the sequential loops that DFTAdvisor cuts after you perform the identification process with the Run command. If you are identifying partition scan, the Write Scan Identification command displays the partition cells that DFTAdvisor flagged during the identification process performed with the Run command. If you issue the command without specifying -Backannotation or -Dofile options, the command writes out both identified and defined scan instances. You must issue this command before executing the Insert Test Logic command or the files generated by Insert Test Logic will be empty. Arguments filename A required string that specifies the name of the file to which DFTAdvisor writes the scan instances. -Replace An optional switch that specifies for DFTAdvisor to replace the contents of the file, if the file already exists. -Full | -Identified | -Defined An optional switch that specifies at what level to write the file. The -Full option specifies to write both identified and defined scan instances. This is the default. The -Identified option specifies to write only scan instances that DFTAdvisor identified during the identification process. The -Defined option specifies to only write scan instances that you defined by using the Add Scan Instances or Add Scan Models commands.
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Command Dictionary Write Scan Identification
-DOfile | -Backannotation An optional switch that specifies to write the scan instances in dofile or back annotation format. In dofile format the file is written as a list of lines that can be executed by the Dofile command. For example:
add scan instances instance_pathname
Examples The following example writes all scan instances to a file after performing a full scan identification run:
set system mode dft setup scan identification full_scan run write scan identification scanfile -identified
The following is an example of the files contents:

Type Instance ------------------------------------defined /I_1_16 identified /I_1_16 identified /I_6_16 identified /I_8_16
Related Commands Report Sequential Instances
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Command Dictionary Write Scan Order
Write Scan Order

Scope: All modes Usage WRIte SCan Order [-Scandef | -Def] filename [-Replace] [-No_segmentation] [-Keep_short_segments] Description Creates the DEF file specified by the filename argument. After scan chain insertion, the Write Scan Order command creates a DEF representation of the scan chains in a design. You can generate either the entire netlist or only the scan definition part of the netlist in the DEF file. Note Each shift register is written into a separate ORDERED section of the DEF file.
The Add Scan Pins command affects the scan definitions in the DEF file. If you specify existing/non-existing scan I/O with this command, the specified names are used in the scan chain START and STOP point definitions. When DFTAdvisor successfully traces through a subchain, the cells that comprise the subchain are written to the ORDERED section of the generated scan DEF file by default. DFTAdvisor tries to avoid having any subchain cells at scan chain boundaries during scan chain stitching in order to prevent the cells comprising the subchain from being written to the START and STOP sections. If there is not a scan cell available that is not part of a subchain, DFTAdvisor inserts lockup cells at the boundaries of the scan chains. This default behavior can be overridden when adding subchains with the Add Sub Chains command by using the Allow_reordering switch. In this case, cells comprising such subchains are considered to be floating cells and can be written to the START and STOP sections. Arguments -Scandef | -Def An optional switch that determines the type of DEF file output. Options include: -Scandef scan chain definitions only. Default setting. -Def entire flattened netlist. This file can be quite large. filename A required string that specifies the name of the DEF file. -Replace An optional switch that replaces the specified file, filename, if it exists.
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-No_segmentation An optional switch that disables the segmentation of scan chains in the DEF file. By default, scan chains with different clocks/edges are segmented into separate chains. If you disable the segmentation of scan chains, cells of scan chains with different clock/edge domains are written out into a single ORDERED list and the PARTITION and MAXBITS information is not written out for these scan chains in the DEF file. This prevents the reordering of scan flip-flops along the scan chains and across the scan chains.
-Keep_short_segments An optional switch that specifies that scan chains that contain only one or two scan cells and contain no lockup latches are written to the scan DEF file and are not commented out; by default, scan chains of this type are written to the scan DEF file and are commented out.
Example 1 Assume the following in this example: 1. The design has two sub-modules, subA and subB, each having three D-type flip-flops. 2. All flip-flops in the design will be included in a single scan chain at the top level. 3. The flip-flops in subA and in subB are clocked with clockA and clockB, respectively. 4. The user turns on lockup cell insertion between clock domains in a chain. 5. The user specifies internal scan input/output pins using the Add Scan Pins command; pad/buf1/Z and pad/buf2/A are the scan input and output pins, respectively. The following command generates the default scan DEF file with a segmented scan chain as shown.
write scan order -scandef deffile VERSION 5.7 ; DIVIDERCHAR "/" ; BUSBITCHARS "[]" ; DESIGN top ; SCANCHAINS 2 ; - chain1_sub0 + START pad/buf1 Z + FLOATING subA/flop1 ( IN SI ) ( OUT QN ) subA/flop2 ( IN SI ) ( OUT QN ) subA/flop3 ( IN SI ) ( OUT QN ) + STOP subA/lockup D # Partition for clock clockA (pos-edge) + PARTITION partition_1 MAXBITS 3 ;
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Command Dictionary Write Scan Order - chain1_sub1 + START subB/flop1 QN + FLOATING subB/flop2 ( IN SI ) ( OUT QN ) subB/flop3 ( IN SI ) ( OUT QN ) + STOP pad/buf2 A # Partition for clock clockB (neg-edge) + PARTITION partition_2 MAXBITS 2 ; END SCANCHAINS END DESIGN
Example 2 Assume the following in this example: 1. The design has two sub-modules, subA and subB, each having three D-type flip-flops. 2. All flip-flops in the design will be included in a single scan chain at the top level. 3. The flip-flops in subA and the flip-flops in subB are clocked with clockA and clockB, respectively. The following command generates an unsegmented scan DEF file as follows.
write scan order -scandef deffile -no_segmentation VERSION 5.7 ; DIVIDERCHAR "/" ; BUSBITCHARS "[]" ; DESIGN top ; SCANCHAINS 1 ; - chain1 + START PIN scan_in1 + FLOATING subA/flop1 ( IN SI ) subA/flop2 ( IN SI ) subA/flop3 ( IN SI ) subB/flop1 ( IN SI ) subB/flop2 ( IN SI ) subB/flop3 ( IN SI ) + STOP PIN scan_out1 ; END SCANCHAINS END DESIGN
( ( ( ( ( (
OUT OUT OUT OUT OUT OUT
QN QN QN QN QN QN
) ) ) ) ) )
397
Example 3 This example illustrates the information reported with the Report Scan Cells command and written to the scanDEF file.
report scan cells
--------------------------------------------------------------------------------Chain Group ShiftReg Library Clock Clock CellNo Name Name Pathname ID/CellNo ModelName ScanOut Pinname Polarity --------------------------------------------------------------------------------0 chain1 dummy /ud5 -/sff QB clk1 (+) 1 chain1 dummy /ud4 1/4 dff QB clk1 (+) 2 chain1 dummy /ud3 1/3 dff Q clk1 (+) 3 chain1 dummy /ud2 1/2 dff Q clk1 (+) 4 chain1 dummy /ud1 1/1 sff Q clk1 (+) 5 chain1 dummy /ud10 3/2 dff Q clk1 (+) 6 chain1 dummy /ud9 3/1 sff Q clk1 (+) 7 chain1 dummy /ud8 -/sff QB clk1 (+) 0 chain2 dummy /ud11 -/sff Q clk1 (+) 1 chain2 dummy /ud7 2/2 dff QB clk1 (+) 2 chain2 dummy /ud6 2/1 sff Q clk1 (+) 3 chain2 dummy /ud12 -/sff Q clk1 (+) 4 chain2 dummy /ud13 -/sff Q clk1 (+) 5 chain2 dummy /ud14 -/sff Q clk1 (+) 6 chain2 dummy /ud15 -/sff Q clk1 (+) ---------------------------------------------------------------------------------
The tool identifies three shift registers as shown in the following output generated by the Report Shift Registers command.
report shift registers -verb ----------------------------------------------------------------Hierarchical SequentialCell Clock Library Id Length Path InstanceName Edge & Name ModelName ----------------------------------------------------------------[1] 4 / ud1 + clk1 sff ud2 + clk1 dff ud3 + clk1 dff ud4 + clk1 dff [2] 2 / ud6 + clk1 sff ud7 + clk1 dff [3] 2 / ud9 + clk1 sff
Given this input, the following command generates the scan DEF file that follows.
write scan order results/scandef -replace
Note Regular flip-flops and shift register flip-flops within the same domain are separated by FLOATING and ORDERED segments, respectively. Each shift register is written out in a separate ORDERED list.
398
Command Dictionary Write Scan Order # # #
DESC: Generated by DFTAdvisor at Thu Apr 15 15:54:34 2010
VERSION 5.7 ; DIVIDERCHAR "/" ; BUSBITCHARS "[]" ; DESIGN A ; UNITS DISTANCE MICRONS 1000 ; SCANCHAINS 2 ; - chain1_sub0 + START ud8 QB + ORDERED ud9 ( IN SI ) ( OUT Q ) ud10 ( IN D ) ( OUT Q ) + ORDERED ud1 ( IN SI ) ( OUT Q ) ud2 ( IN D ) ( OUT Q ) ud3 ( IN D ) ( OUT Q ) ud4 ( IN D ) ( OUT QB ) + STOP ud5 SI # Partition for core chain in clock clk1 (pos-edge) domain + PARTITION partition_1 MAXBITS 6 ;
- chain2_sub0 + START ud15 Q + FLOATING ud14 ( IN SI ) ( OUT Q ) ud13 ( IN SI ) ( OUT Q ) ud12 ( IN SI ) ( OUT Q ) + ORDERED ud6 ( IN SI ) ( OUT Q ) ud7 ( IN D ) ( OUT QB ) + STOP ud11 SI # Partition for core chain in clock clk1 (pos-edge) domain + PARTITION partition_1 MAXBITS 5 ;
END SCANCHAINS END DESIGN
Similarly, given the same input, the following command generates the scan DEF file that follows:
write scan order no_segmentation scan.def
399
Note In the following output: 1. sub1 and sub2 are instances of library cell libsubchmodel which contains a subchain of length 2. The scan DEF includes this length in the BITS field. For regular cells of length 1, the BITS field is not printed. 2. All flip-flops are written out in one ORDERED list because chain1 contains cells in different clock edge domains.
VERSION 5.7 ; DIVIDERCHAR "/" ; BUSBITCHARS "[]" ; DESIGN A ; UNITS DISTANCE MICRONS 1000 ; SCANCHAINS 1 ; - chain1 + START u5 Q + ORDERED u1 ( IN SI ) ( OUT Q ) u2 ( IN D ) ( OUT Q ) u3 ( IN D ) ( OUT Q ) u4 ( IN D ) ( OUT Q ) u6 ( IN SI ) ( OUT Q ) u7 ( IN D ) ( OUT Q ) u8 ( IN SI ) ( OUT Q ) u9 ( IN D ) ( OUT Q ) u10 ( IN D ) ( OUT Q ) u11 ( IN SI ) ( OUT Q ) u12 ( IN D ) ( OUT Q ) u13 ( IN SI ) ( OUT Q ) u14 ( IN D ) ( OUT Q ) u15 ( IN SI ) ( OUT Q ) lckup1 ( IN D ) ( OUT Q ) sub1 ( IN sci1 ) ( OUT sco1 ) ( BITS 2 ) + STOP sub2 sci2 ; END SCANCHAINS
400
Example 4 This example illustrates the information reported with the Report Scan Cells command and written to the scanDEF file when traceable subchains are present in the design.
report scan cells
--------------------------------------------------------------------------------Chain Group Clock CellNo Name Name Pathname CellName ScanOut Clock Polarity --------------------------------------------------------------------------------chain1 dummy /lckup1 latch Q clk2 (-) 0 chain1 (schi2) dummy /uB/f3 sff Q clk2 (+) 1 chain1 (schi2) dummy /uB/f2 sff Q clk2 (+) 2 chain1 (schi2) dummy /uB/f1 sff Q clk2 (+) chain1 dummy /lckup2 latch Q clk2 (+) 0 chain2 (schc1) dummy /uWA/uA/f21 sff Q clk (+) 1 chain2 dummy /ud sff Q clk (+) 2 chain2 dummy /us sff Q clk (+) 0 chain3 (scho1) dummy /uWA/uA/f31 sff Q clk (+) chain4 dummy /lckup3 latch Q clk (-) 0 chain4 (schi1) dummy /uWA/uA/f3 sff Q clk (+) 1 chain4 (schi1) dummy /uWA/uA/bb/f2 sff Q clk (+) 2 chain4 (schi1) dummy /uWA/uA/f1 sff Q clk (+) chain4 dummy /lckup4 latch Q clk (+)
write scan order # # # DESC: Generated by DFTAdvisor at Wed Mar 17 10:50:58 2010
VERSION 5.7 ; DIVIDERCHAR "/" ; BUSBITCHARS "[]" ; DESIGN top ; UNITS DISTANCE MICRONS 1000 ; SCANCHAINS 1 ; - chain1_sub0 + START lckup2 Q + FLOATING uB/f1 ( IN SI ) ( OUT Q ) uB/f2 ( IN SI ) ( OUT Q ) uB/f3 ( IN SI ) ( OUT Q ) + STOP lckup1 D # Partition for core chain in clock clk2 (pos-edge) domain + PARTITION partition_1 MAXBITS 3 ;
- chain2_sub0 + START us Q + FLOATING ud ( IN SI ) ( OUT Q ) + STOP uWA/uA/f21 SI # Partition for core chain in clock clk (pos-edge) domain + PARTITION partition_2 MAXBITS 1 ;
401
Command Dictionary Write Scan Order # The following chain segment with only 1 or 2 scan cells has been # commented out for compatibility with the layout tools. #- chain3_sub0 # + START uWA/uA/f31 SI # + STOP uWA/uA/f31 Q ; - chain4_sub0 + START lckup4 Q + FLOATING uWA/mux ( IN A1 ) ( OUT Y ) ( BITS 0 ) uWA/uA/f1 ( IN SI ) ( OUT Q ) uWA/uA/bb/f2 ( IN SI ) ( OUT Q ) uWA/uA/f3 ( IN SI ) ( OUT Q ) + STOP lckup3 D # Partition for core chain in clock clk (pos-edge) domain + PARTITION partition_2 MAXBITS 3 ;
END SCANCHAINS END DESIGN
Example 5 Note This example is a modification of Example 4. In this example, the Set Bidi Gating command assigns the attribute hard_macro to the module blackBox. An instance of this module, uWA/uA/bb, is written to the scanDEF file unexpanded and the number of scan cells on its scan path appears in the BITS statement. Additionally, the -no_reordering switch was used with the Add Sub Chains command when defining subchains; therefore, the flip-flops contained within the subchains are written to the ORDERED sections.
set attribute blackBox -name hard_macro -value true # # # DESC: Generated by DFTAdvisor at Fri Mar 26 17:48:50 2010
VERSION 5.7 ; DIVIDERCHAR "/" ; BUSBITCHARS "[]" ; DESIGN top ; UNITS DISTANCE MICRONS 1000 ; SCANCHAINS 1 ; - chain1_sub0 + START lckup2 Q + ORDERED uB/f1 ( IN SI ) ( OUT Q ) uB/f2 ( IN SI ) ( OUT Q ) uB/f3 ( IN SI ) ( OUT Q ) + STOP lckup1 D
402
Command Dictionary Write Scan Order # Partition for core chain in clock clk2 (pos-edge) domain + PARTITION partition_1 MAXBITS 3 ;
- chain2_sub0 + START us Q + FLOATING ud ( IN SI ) ( OUT Q ) + STOP uWA/uA/f21 SI # Partition for core chain in clock clk (pos-edge) domain + PARTITION partition_2 MAXBITS 1 ;
# # ## #
The following chain segment with only 1 or 2 scan cells has been commented out for compatibility with the layout tools. chain3_sub0 + START uWA/uA/f31 SI + STOP uWA/uA/f31 Q ;
- chain4_sub0 + START lckup4 Q + ORDERED uWA/mux ( IN A1 ) uWA/uA/f1 ( IN SI uWA/uA/bb ( IN si uWA/uA/f3 ( IN SI + STOP lckup3 D
( ) ) )
OUT Y ( OUT ( OUT ( OUT
) ( BITS 0 ) Q ) so ) ( BITS 1 ) Q )
# Partition for core chain in clock clk (pos-edge) domain + PARTITION partition_2 MAXBITS 3 ; END SCANCHAINS END DESIGN
Related Commands Add Scan Pins Add Sub Chains
403
Command Dictionary Write Subchain Setup
Write Subchain Setup

Scope: Dft mode Usage WRIte Subchain Setup filename -Replace Description Writes the appropriate Add Sub Chains commands to a file so that DFTAdvisor can understand the pre-existing scan subchains at the top-level of this module. The Write Subchain Setup command is useful if you are performing a block-by-block test synthesis at the lower design level. By using this command to specify for DFTAdvisor to write the subchain setup information at the lower-level and then reading in the setup file as part of the scan subchain setup, you can avoid having to define the pre-existing scan subchain at the higher design level with the Add Sub Chains command. Arguments filename A required string that specifies the name of the file to which DFTAdvisor writes the scan subchain setup information. For information on this file format, refer to the Insert Test Logic command. -Replace An optional switch that specifies for DFTAdvisor to replace the contents of the file, if the file already exists. Examples The following example writes the scan chain setup information for this module so that you can later use the module1.setup file at the top-level to define the pre-existing scan subchain:
insert test logic write subchain setup /user/designs/module1.setup
The following example shows the contents of the module1.setup file:

add sub chains /user/designs/sub1 subc1 scan_in1 scan_out1 7 mux_scan scan_en
Related Commands Add Sub Chains Insert Test Logic Report Sub Chains
404
Chapter 3 Shell Commands

The DFTAdvisor shell commands are described in this chapter.
Shell Command Summary

Table 3-1 contains a summary of the shell commands available in DFTAdvisor. Table 3-1. Command Summary Command dftadvisor stil2mgc Description Invokes DFTAdvisor in either a graphical or commandline session. Translates STIL Test Procedure (STP) files into Tessent FastScan, FlexTest, and DFTAdvisor dofiles and test procedure files.
405
Shell Commands dftadvisor
dftadvisor
Prerequisites: Verilog netlist and cell library containing descriptions of the cells used in the design. Usage dftadvisor {design_name... {-LIBrary {filename...}} [-INCDIR include_directory...] [-INSENsitive | -SENsitive] [-LOg filename [-Replace]] [-TOp module_name] [-Dofile dofile_name [-HIstory]] [-LICense retry_limit] [-32 | -64]} | [-Load_warnings] [-TCL] | [-HElp | -USAGE | -MANUAL | -VERSion] [-LIBRARY_ARRAY_DELIMITER {square | angle}] Description Invokes DFTAdvisor in a command-line session. To invoke DFT, enter the required arguments on the shell command line. The design and library load and DFTAdvisor invokes in Setup mode. Arguments design_name... A required, repeatable string that specifies the pathname to a Verilog netlist. -LIBrary filename A required switch and repeatable string pair that specifies the files containing the ATPG library descriptions for all cell models in design_name. UNIX/Linux wildcard characters may be used to specify multiple library files. This argument is not required if all primitives are fully defined in your netlist. -INCDIR include_directory... An optional switch and repeatable string pair that specifies the directories to search for files included in a Verilog design with the include compiler directive. The specified directories must be either a pathname relative to the current (tool invocation) directory or an absolute pathname. Directories are searched in the order they are specified. DFTAdvisor uses the first occurrence of a specified file and ignores others with the same name. DFTAdvisor searches for include files in the following order of precedence: a. Absolute pathnames specified by include directives in the Verilog design b. Directories specified with the -Incdir invocation switch c. Directory where the calling file is located d. Directory the tool was invoked from (current directory) -INSENsitive | -SENsitive Optional switch that specifies whether pin, instance, and net pathnames are case-sensitive. By default, only object names are treated as case-sensitive.
406
-LOg filename An optional switch and string pair that determines whether a session log file is saved to a specified file. By default, session information is only sent to the terminal display.
-Replace An optional switch that enables DFTAdvisor to overwrite an existing logfile with the same name.
-TOp model_name An optional switch and string pair that specifies the name of the top-level model in the netlist. By default, the first top-level module is assumed to be the top module.
-Dofile dofile_name An optional switch and string pair that specifies the name of a dofile to execute upon invocation.
-HIstory An optional switch that adds commands from a dofile to the command line history list. By default, the commands in a dofile are not inserted into the history list, but the dofile command itself is added to the list.
-LICense retry_limit An optional switch and integer pair that specifies how long DFTAdvisor should check for an available license before exiting the invocation process. This switch is only valid for batch mode. If no license is available, DFTAdvisor checks for a license every minute until the specified retry_limit is reached. If the retry_limit equals 0 (zero), DFTAdvisor continues checking for a license until one is obtained. By default, the invocation process exits when no license is available.
-32 | -64 An optional switch that invokes the 32-bit or 64-bit version of the software. The default is 64-bit. If the platform does not support the specified version, the tool gives a warning message and ignores the switch.
-LOAd_warnings An optional switch that reports any warnings and notes returned while loading the netlist and library. By default, only a summary message for most warnings and notes is reported.
-TCL An optional switch that invokes the tool in Tcl scripting mode. See Using the Tcl Scripting Interface in the Tessent Common Resources Manual for ATPG Products for complete information.
-HElp An optional switch that displays the version and usage syntax for DFTAdvisor. No other arguments can be specified with this switch.
407
-USAGE An optional switch that displays a message that contains the DFTAdvisor invocation switches, with no descriptions.
-MANUAL An optional switch that displays the DFT documentation set in an HTML browser. -VERSion An optional switch that displays the version of the DFTAdvisor software currently available. No other arguments can be specified with this switch.
-LIBRARY_ARRAY_DELIMITER {square | angle} An optional switch that sets the default array delimiter for library parsing to either square brackets [] or angle brackets <>. The default is [].
Examples The following example invokes DFTAdvisor on a netlist named design1.v. This design contains library parts that are specified in a file called mitsu_lib10. A session log is saved to a file named design1_scan.log that is overwritten if it already exists.
<Tessent_Tree_Path>/bin/dftadvisor design1.v -library mitsu_lib10 \ -log design1_scan.log -replace
408
Shell Commands stil2mgc
stil2mgc
Prerequisites: STIL test procedure file. Usage stil2mgc {-STil stil_filename [-TPf tpf_filename] [-DOfile dofile_name] [-FLex_dofile dofile_name] [-ALias Min | All] [-CApture NOne | Single | NAmed] [-LOgfile logfile_name [-REplace]]} | {-Version | -Help | -Usage} Description The stil2mgc utility translates STIL test procedure files into Tessent FastScan, FlexTest, and DFTAdvisor dofiles and test procedure files. The stil2mgc utility produces: Dofiles that define clocks, scan chains, scan groups, and pin constraints Test procedure files that define a timeplate and the test_setup, load_unload, and shift scan procedures.
The tool translates STIL signal groups used in timeplates or procedures into alias statements in the test procedure file. It also produces a test procedure file timeplate definition for each WaveformTable in the STIL file, exactly matching the timing specified in the STIL file. Any procedure or macro whose name matches a Mentor Graphics procedure type (load_unload, master_observe, and so on) is translated into that Mentor Graphics procedure. Also, any procedure or macro in the STIL file that has capture in its name is translated into a named capture procedure if the -Capture named switch is used. Any other macro whose name does not match Mentor Graphics names is translated into an unused sub-procedure. Arguments -STil stil_filename A required switch and string pair that specifies the name of the input STIL test procedure file. -TPf tpf_filename An optional switch and string pair that specifies a name for the translated test procedure file. By default, the translated file assumes the name of the STIL test procedure with .proc appended. -DOfile dofile_name An optional switch and string pair that specifies a name for the generated dofile. By default, the dofile assumes the name of the STIL test procedure with .dof appended. -FLex_dofile dofile_name An optional switch and string pair that generates an additional dofile for the FlexTest tool.
409
Shell Commands stil2mgc
-ALias Min | -ALl An optional switch that specifies how alias statements are applied during conversion. Options include: -ALias Min Produces the minimum required alias statements in the MGC procedure file. Default. -ALl Produces alias statements for all signal groups found in the STIL test procedure file.
-CApture {NOne | Single | NAmed} An optional switch and literal pair that determines how named capture procedures are applied in the MGC procedure file. Options include: NOne Produces no capture procedures. Default. Single Produces a single unnamed capture procedure. NAmed Produces a named capture procedure for each capture Macro found in the STIL test procedure file.
-LOgfile logfile_name An optional switch and string pair that specifies the name of the file to write all session information.
-REplace An optional switch that enables stil2mgc to overwrite an existing logfile with the same name.
-Version An optional switch that displays the version of the stil2mgc utility. -Help An optional switch that displays the stil2mgc switches and a brief description of each. -Usage An optional switch that displays the usage syntax for the stil2mgc command. -MANual An optional switch that displays the DFT documentation in an HTML browser.
Examples The following example executes the stil2mgc utilty on design.stp.

stil2mgc -stil design.stp -tpf new_design.tpf -dofile new_dofile.do
410
Appendix A Using Tessent DFTVisualizer

Tessent DFTVisualizer (hereafter know as DFTVisualizer) is a graphical debugging and analysis schematic viewing tool you can use with DFTAdvisor. Tip: For complete DFTVisualizer documentation, see Getting Started with DFTVisualizer in the Tessent Common Resources Manual for ATPG Products. Table A-1 lists the DFTVisualizer-related DFTAdvisor commands available for your use. Table A-1. DFTVisualizer-Related Commands Command Add Browser Data Add Display Data Add Display Instances Description Adds data columns to the Browser window of DFTVisualizer. Adds data columns to the Data window of DFTVisualizer. Displays instances in DFTVisualizer and enables you to trace visually through the design using the Debug or Design window. Generates a netlist of the portion of the design involved with the specified rule violation number. Closes the DFTVisualizer window. Removes data columns from the Browser window of DFTVisualizer. Removes a data column from the Data window of DFTVisualizer. Removes the specified design instances from a DFTVisualizer display window. Reads a DFTVisualizer preferences file and sets current preferences as described in the file. Applies a different color to instances in the Debug window. Opens the DFTVisualizer main window. Lists netlist information for specified instances displayed in the Debug window.
Analyze Drc Violation Close Visualizer Delete Browser Data Delete Display Data Delete Display Instances Load Visualizer Preferences Mark Open Visualizer Report Display Instances
411
Using Tessent DFTVisualizer
Table A-1. DFTVisualizer-Related Commands Command Save Visualizer Dofile Save Window Select Object Set Visualizer Preferences Unmark Write Visualizer Preferences Description Writes a dofile containing commands needed to recreate current instance and data displays. Saves a screen capture of a DFTVisualizer window. Selects the specified objects in the Debug and/or Design window. Controls a subset of DFTVisualizer preferences for the Debug, and Design, Browser, and Data windows. Removes color highlighting and/or marking from instances in the Debug window. Writes the current DFTVisualizer preference settings to a file.
412
Appendix B Getting Help

There are several ways to get help when setting up and using Tessent software tools. Depending on your need, help is available from documentation, online command help, and Mentor Graphics Support.
Documentation
A comprehensive set of reference manuals, user guides, and release notes is available in two formats: HTML for searching and viewing online PDF for printing
The documentation is available from each software tool and online at:
http://supportnet.mentor.com
For more information on setting up and using Tessent documentation, see the Using Tessent Documentation chapter in the Managing Mentor Graphics Tessent Software manual.
Mentor Graphics Support

Mentor Graphics software support includes software enhancements, access to comprehensive online services with SupportNet, and the optional On-Site Mentoring service. For details, see:
http://supportnet.mentor.com/about/
If you have questions about a software release, you can log in to SupportNet and search thousands of technical solutions, view documentation, or open a Service Request online at:
http://supportnet.mentor.com
If your site is under current support and you do not have a SupportNet login, you can register for SupportNet by filling out the short form at:
http://supportnet.mentor.com/user/register.cfm
All customer support contact information can be found on our web site at:
http://supportnet.mentor.com/contacts/supportcenters/index.cfm
413
Getting Help Mentor Graphics Support
414
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Index
B
B command, 202 Delete Black Box, 108 Delete Buffer Insertion, 109 Delete Cell Models, 111 Delete Clock Groups, 113 Delete Clocks, 114 Delete Mapping Definition, 115 Delete Nofaults, 118 Delete Nonscan Instances, 120 Delete Nonscan Models, 122 Delete Notest Points, 124 Delete Output Masks, 126 Delete Pin Constraints, 127 Delete Pin Equivalences, 129 Delete Primary Inputs, 130 Delete Primary Outputs, 132 Delete Read Controls, 134 Delete Scan Chains, 135 Delete Scan Groups, 136 Delete Scan Instances, 137 Delete Scan Models, 139 Delete Scan Partitions, 140 Delete Scan Pins, 141 Delete Seq_transparent Constraints, 142 Delete Sub Chains, 143, 144, 251 Delete Subchain Groups, 145 Delete Test Points, 146 Delete Tied Signals, 148 Delete Write Controls, 150 Dofile, 151 Echo, 152 Exit, 154 F, 202 Find Design Names, 155 Help, 160 History, 161 Insert Test Logic, 163 Printenv, 170 Read Procfile, 171 Report Black Box, 172 Report Buffer Insertion, 174
415
C
Command Dictionary, 15 Commands Add Black Box, 28 Add Buffer Insertion, 30 Add Cell Models, 32 Add Clock Groups, 35 Add Clocks, 37 Add Mapping Definition, 40 Add Nofaults, 43 Add Nonscan Instances, 46 Add Nonscan Models, 48 Add Notest Points, 49 Add Output Masks, 51 Add Pin Constraints, 53 Add Pin Equivalences, 55 Add Primary Inputs, 57 Add Primary Outputs, 59 Add Read Controls, 60 Add Scan Chains, 61 Add Scan Group, 63 Add Scan Instances, 64 Add Scan Models, 66 Add Scan Partition, 68 Add Scan Pins, 72 Add Seq_transparent Constraints, 77 Add Sub Chains, 79, 84 Add Subchain group, 87 Add Test Points, 90 Add Tied Signals, 94 Add Write Controls, 96 Alias, 97 Analyze Control Signals, 100 Analyze Input Control, 103 Analyze Output Observe, 104 Analyze Testability, 105 B, 202
Report Cell Models, 175 Report Circuit Components, 177 Report Clock Groups, 183 Report Clocks, 184 Report Control Signals, 185 Report Dft Check, 187 Report Drc Rules, 190 Report Environment, 195 Report Feedback Paths, 197 Report Flatten Rules, 199 Report Gates, 201 Report Loops, 207 Report Mapping Definition, 209 Report Nofaults, 212 Report Nonscan Models, 214 Report Notest Points, 215 Report Output Masks, 216 Report Pin Constraints, 220 Report Pin Equivalences, 222 Report Primary Inputs, 223 Report Primary Outputs, 224 Report Procedure, 225 Report Read Controls, 226 Report Scan Cells, 227 Report Scan Chains, 231 Report Scan Groups, 233 Report Scan Models, 234 Report Scan Partitions, 235 Report Scan Pins, 237 Report Seq_transparent Constraints, 238 Report Sequential Instances, 239 Report Statistics, 248 Report Sub Chains, 250 Report Subchain Groups, 252 Report Test Logic, 253 Report Test Points, 255 Report Testability Analysis, 257 Report Tied Signals, 260 Report Timeplate, 261 Report Variables, 262 Report Wrapper Cells, 219 Report Write Controls, 264 Reset State, 265 Ripup Scan Chains, 266 Run, 268 Save History, 269 Set Bidi Gating, 270 Set Capture Clock, 273 Set Command Editing, 274 Set Contention Check, 275 Set Dofile Abort, 278 Set Drc Handling, 279 Set Fault Sampling, 282, 338 Set File Compression, 283 Set Flatten Handling, 285 Set Gzip Options, 295 Set Identification Model, 297 Set Internal Fault, 299 Set Io Insertion, 301 Set Latch Handling, 303 Set Lockup Latch, 304 Set Logfile Handling, 309 Set Net Resolution, 311 Set Nonscan Handling, 312 Set Scan Type, 322 Set Screen Display, 323 Set Sensitization Checking, 324 Set Shadow Checking, 325 Set Stability Check, 326 Set System Mode, 327 Set Test Logic, 328 Set Trace Report, 330 Set Transient Detection, 331 Set Tristate Gating, 332 Setup Naming, 339 Setup Output Masks, 342 Setup Pin Constraints, 344 Setup Registered Io, 346 Setup Scan Identification, 350 Setup Scan Insertion, 356 Setup Scan Pins, 359 Setup Test_point Identification, 362 Setup Test_point Insertion, 365 Setup Tied Signals, 372 Stil2mgc, 409 System, 379 Write Atpg Setup, 380 Write Formal_verification Setup, 383 Write Loops, 385 Write Netlist, 386
416
Write Primary Inputs, 390 Write Primary Outputs, 391 Write Procfile, 392 Write Scan Identification, 393 Write Scan Order, 395 Write Subchain Setup, 404
D
DFTAdvisor Inputs, 11 Outputs, 11
F
F command, 202
I
Inputs, 11 to DFTAdvisor, 11
N
Non-scan initialization values, 63
O
Outputs to DFTAdvisor, 11
R
Reporting report gate format, 201
S
stil2mgc script, 409
T
TIE0, scannable, 46 TIE1, scannable, 46
417
418
Third-Party Information
This section provides information on open source and third-party software that may be included in Tessent software products.
This software application may include GTK 2.6.1 third-party software and may be subject to the following copyright(s) and/or use terms: Copyright (c) 1998, 1999, 2000 Thai Open Source Software Center Ltd and Clark Cooper Copyright (c) 2001, 2002 Expat maintainers. Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Copyright (c) 1998, 1999 Henry Spencer. All rights reserved. Development of this software was funded, in part, by Cray Research Inc., UUNET Communications Services Inc., Sun Microsystems Inc., and Scriptics Corporation, none of whom are responsible for the results. The author thanks all of them. Redistribution and use in source and binary forms -- with or without modification -- are permitted for any purpose, provided that redistributions in source form retain this entire copyright notice and indicate the origin and nature of any modifications. I'd appreciate being given credit for this package in the documentation of software which uses it, but that is not a requirement. THIS SOFTWARE IS PROVIDED `ÀS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL HENRY SPENCER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
wxWindows adopted the code out of Tcl 8.4.5. Portions of regc_locale.c and re_syntax.n were developed by Tcl developers other than Henry Spencer; these files bear the Tcl copyright and license notice:
This software is copyrighted by the Regents of the University of California, Sun Microsystems, Inc., Scriptics Corporation, ActiveState Corporation and other parties. The following terms apply to all files associated with the software unless explicitly disclaimed in individual files. The authors hereby grant permission to use, copy, modify, distribute, and license this software and its documentation for any purpose, provided that existing copyright notices are retained in all copies and that this notice is included verbatim in any distributions. No written agreement, license, or royalty fee is required for any of the authorized uses. Modifications to this software may be copyrighted by their authors and need not follow the licensing terms described here, provided that the new terms are clearly indicated on the first page of each file where they apply. IN NO EVENT SHALL THE AUTHORS OR DISTRIBUTORS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OF THIS SOFTWARE, ITS DOCUMENTATION, OR ANY DERIVATIVES THEREOF, EVEN IF THE AUTHORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE AUTHORS AND DISTRIBUTORS SPECIFICALLY DISCLAIM ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, AND THE AUTHORS AND DISTRIBUTORS HAVE NO OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. GOVERNMENT USE: If you are acquiring this software on behalf of the U.S. government, the Government shall have only "Restricted Rights" in the software and related documentation as defined in the Federal Acquisition Regulations (FARs) in Clause 52.227.19 (c) (2). If you are acquiring the software on behalf of the Department of Defense, the software shall be classified as "Commercial Computer Software" and the Government shall have only "Restricted Rights" as defined in Clause 252.227-7013 (c) (1) of DFARs. Notwithstanding the foregoing, the authors grant the U.S. Government and others acting in its behalf permission to use and distribute the software in accordance with the terms specified in this license. The wxWindows license applies to further modifications to regcustom.h and regc_locale.c.
License for Scintilla and SciTE Copyright 1998-2003 by Neil Hodgson <neilh@scintilla.org> All Rights Reserved Permission to use, copy, modify, and distribute this software and its documentation for any purpose and without fee is hereby granted, provided that the above copyright notice appear in all copies and that both that copyright notice and this permission notice appear in supporting documentation. NEIL HODGSON DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL NEIL HODGSON BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
Copyright (c) 1988-1997 Sam Leffler Copyright (c) 1991-1997 Silicon Graphics, Inc. Permission to use, copy, modify, distribute, and sell this software and its documentation for any purpose is hereby granted without fee, provided that (i) the above copyright notices and this permission notice appear in all copies of the software and related documentation, and (ii) the names of Sam Leffler and Silicon Graphics may not be used in any advertising or publicity relating to the software without the specific, prior written permission of Sam Leffler and Silicon Graphics.
THE SOFTWARE IS PROVIDED "AS-IS" AND WITHOUT WARRANTY OF ANY KIND, EXPRESS, IMPLIED OR OTHERWISE, INCLUDING WITHOUT LIMITATION, ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL SAM LEFFLER OR SILICON GRAPHICS BE LIABLE FOR ANY SPECIAL, INCIDENTAL, INDIRECT OR CONSEQUENTIAL DAMAGES OF ANY KIND, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER OR NOT ADVISED OF THE POSSIBILITY OF DAMAGE, AND ON ANY THEORY OF LIABILITY, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
(C) 1995-2004 Jean-loup Gailly and Mark Adler This software is provided 'as-is', without any express or implied warranty. In no event will the authors be held liable for any damages arising from the use of this software. Permission is granted to anyone to use this software for any purpose, including commercial applications, and to alter it and redistribute it freely, subject to the following restrictions: 1. The origin of this software must not be misrepresented; you must not claim that you wrote the original software. If you use this software in a product, an acknowledgment in the product documentation would be appreciated but is not required. Altered source versions must be plainly marked as such, and must not be misrepresented as being the original software. This notice may not be removed or altered from any source distribution. Mark Adler madler@alumni.caltech.edu
2. 3.
Jean-loup Gailly jloup@gzip.org
If you use the zlib library in a product, we would appreciate *not* receiving lengthy legal documents to sign. The sources are provided for free but without warranty of any kind. The library has been entirely written by Jean-loup Gailly and Mark Adler; it does not include third-party code. If you redistribute modified sources, we would appreciate that you include in the file ChangeLog history information documenting your changes. Please read the FAQ for more information on the distribution of modified source versions.
This software application may include GTK 2.6.1 third-party software and may be subject to the following copyrights. wxWindows Library Licence, Version 3 Copyright (C) 1998 Julian Smart, Robert Roebling [, ...] Everyone is permitted to copy and distribute verbatim copies of this licence document, but changing it is not allowed. WXWINDOWS LIBRARY LICENCE TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION This library is free software; you can redistribute it and/or modify it under the terms of the GNU Library General Public Licence as published by the Free Software Foundation; either version 2 of the Licence, or (at your option) any later version. This library is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Library General Public Licence for more details.
You should have received a copy of the GNU Library General Public Licence along with this software, usually in a file named COPYING.LIB. If not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. EXCEPTION NOTICE 1. As a special exception, the copyright holders of this library give permission for additional uses of the text contained in this release of the library as licenced under the wxWindows Library Licence, applying either version 3 of the Licence, or (at your option) any later version of the Licence as published by the copyright holders of version 3 of the Licence document. The exception is that you may use, copy, link, modify and distribute under the user's own terms, binary object code versions of works based on the Library. If you copy code from files distributed under the terms of the GNU General Public Licence or the GNU Library General Public Licence into a copy of this library, as this licence permits, the exception does not apply to the code that you add in this way. To avoid misleading anyone as to the status of such modified files, you must delete this exception notice from such code and/or adjust the licensing conditions notice accordingly. If you write modifications of your own for this library, it is your choice whether to permit this exception to apply to your modifications. If you do not wish that, you must delete the exception notice from such code and/or adjust the licensing conditions notice accordingly.
2. 3.
4.
This software application may include GTK+ third-party software, portions of which may be subject to the GNU Library General Public License. You can view the complete license at: http://www.gnu.org/copyleft/library.html, or find the file at your_Mentor_Graphics_documentation_directory/legal/. To obtain a copy of the GTK+ source code, send a request to request_sourcecode@mentor.com. This offer may be accepted for three years from the date Mentor Graphics Corporation first distributed the GTK+ source code. This software application may include freestdf third-party software that may be subject to the following copyright(s): 2004 Nelson Ingersoll <njall@users.sourceforge.net> 2004-2005 Mike Frysinger vapier@gmail.com. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. Neither the name of the FREESTDF nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
This software application may include LEF/DEF third-party software, which is distributed under the terms of the Mentor Graphics End User License Agreement. You can view the complete license in the Mentor Graphics End User License Agreement in this document. To obtain a copy of the LEF/DEF source code, or to obtain a copy of changes made to the source code, if any, send a request to request_sourcecode@mentor.com. LEF/DEF software distributed under the License is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for the specific language governing rights and limitations under the License.
This software application may include zlib version 1.1.4 third-party software. Zlib version 1.1.4 is distributed under the terms of the zlib/libpng license and is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the license for the specific language governing rights and limitations under the license. You can view a copy of the license at: your_Mentor_Graphics_documentation_directory/legal//zlib_libpng.pdf. Zlib version 1.1.4 may be subject to the following copyrights: 1995-2005 Jean-loup Gailly and Mark Adler This software is provided 'as-is', without any express or implied warranty. In no event will the authors be held liable for any damages arising from the use of this software. Permission is granted to anyone to use this software for any purpose, including commercial applications, and to alter it and redistribute it freely, subject to the following restrictions: 1. The origin of this software must not be misrepresented; you must not claim that you wrote the original software. If you use this software in a product, an acknowledgment in the product documentation would be appreciated but is not required. Altered source versions must be plainly marked as such, and must not be misrepresented as being the original software. This notice may not be removed or altered from any source distribution.
2. 3.
Jean-loup Gailly jloup@gzip.org Mark Adler madler@alumni.caltech.edu
This software application may include wxglade version 0.6.3 third-party software, which is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. This software application may include TKtreectrl version 2.2.7 third-party software, which is distributed on an AS IS basis, WITHOUT WARRANTY OF ANY KIND, either express or implied TKtreectrl version 2.2.7 may be subject to the following copyrights: This software is copyrighted by Tim Baker and other parties. The following terms apply to all files associated with the software unless explicitly disclaimed in individual files. The authors hereby grant permission to use, copy, modify, distribute, and license this software and its documentation for any purpose, provided that existing copyright notices are retained in all copies and that this notice is included verbatim in any distributions. No written agreement, license, or royalty fee is required for any of the authorized uses. Modifications to this software may be copyrighted by their authors and need not follow the licensing terms described here, provided that the new terms are clearly indicated on the first page of each file where they apply. IN NO EVENT SHALL THE AUTHORS OR DISTRIBUTORS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OF THIS SOFTWARE, ITS DOCUMENTATION, OR ANY DERIVATIVES THEREOF, EVEN IF THE AUTHORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
THE AUTHORS AND DISTRIBUTORS SPECIFICALLY DISCLAIM ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. THIS SOFTWARE IS PROVIDED ON AN AS IS BASIS, AND THE AUTHORS AND DISTRIBUTORS HAVE NO OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
This software application may include tkcon version 2.4 third-party software, which is distributed on an AS IS basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.
This software application may include MiniSat version 1.14 third-party software, which is distributed on an AS IS basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. This software application may include tcllib inifile version 1.0 third-party software, which is distributed on an AS IS basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. tcllib inifile v1.0 may be subject to the following copyrights: 2003 Aaron Faupell afaupell@users.sourceforge.net All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. Neither the name of the organization nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
This software application may include Boost version 1.39.0 third-party software. Boost version 1.39.0 is distributed under the terms of the Boost Software License version 1.0 and is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the license for the specific language governing rights and limitations under the license. You can view a copy of the license at: <path to legal directory>/legal/ boost_1.0.pdf. Portions of this software may be subject to the Boost Artistic License. You can view a copy of the Boost Artistic License at: <path to legal directory>/legal/boost_artistic_2000.pdf. Boost version 1.39.0 may be subject to the following copyrights: 2002-2003, Trustees of Indiana University. 2000-2001, University of Notre Dame. All rights reserved. Indiana University has the exclusive rights to license this product under the following license. Software License, Version 1.0
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * All redistributions of source code must retain the above copyright notice, the list of authors in the original source code, this list of conditions and the disclaimer listed in this license; * All redistributions in binary form must reproduce the above copyright notice, this list of conditions and the disclaimer listed in this license in the documentation and/or other materials provided with the distribution; * Any documentation included with all redistributions must include the following acknowledgement: "This product includes software developed at the University of Notre Dame and the Pervasive Technology Labs at Indiana University. For technical information contact Andrew Lumsdaine at the Pervasive Technology Labs at Indiana University. For administrative and license questions contact the Advanced Research and Technology Institute at 351 West 10th Street. Indianapolis, Indiana 46202, phone 317-278-4100, fax 317-274-5902." Alternatively, this acknowledgement may appear in the software itself, and wherever such third-party acknowledgments normally appear. * The name Indiana University, the University of Notre Dame or "Caramel" shall not be used to endorse or promote products derived from this software without prior written permission from Indiana University. For written permission, please contact Indiana University Advanced Research & Technology Institute. * Products derived from this software may not be called "Caramel", nor may Indiana University, the University of Notre Dame or "Caramel" appear in their name, without prior written permission of Indiana University Advanced Research & Technology Institute. Indiana University provides no reassurances that the source code provided does not infringe the patent or any other intellectual property rights of any other entity. Indiana University disclaims any liability to any recipient for claims brought by any other entity based on infringement of intellectual property rights or otherwise. LICENSEE UNDERSTANDS THAT SOFTWARE IS PROVIDED "AS IS" FOR WHICH NO WARRANTIES AS TO CAPABILITIES OR ACCURACY ARE MADE. INDIANA UNIVERSITY GIVES NO WARRANTIES AND MAKES NO REPRESENTATION THAT SOFTWARE IS FREE OF INFRINGEMENT OF THIRD PARTY PATENT, COPYRIGHT, OR OTHER PROPRIETARY RIGHTS. INDIANA UNIVERSITY MAKES NO WARRANTIES THAT SOFTWARE IS FREE FROM "BUGS", "VIRUSES", "TROJAN HORSES", "TRAP DOORS", "WORMS", OR OTHER HARMFUL CODE. LICENSEE ASSUMES THE ENTIRE RISK AS TO THE PERFORMANCE OF SOFTWARE AND/OR ASSOCIATED MATERIALS, AND TO THE PERFORMANCE AND VALIDITY OF INFORMATION GENERATED USING SOFTWARE. 2001-2003 William E. Kempf Permission to use, copy, modify, distribute and sell this software and its documentation for any purpose is hereby granted without fee, provided that the above copyright notice appear in all copies and that both that copyright notice and this permission notice appear in supporting documentation. William E. Kempf makes no representations about the suitability of this software for any purpose. It is provided "as is" without express or implied warranty. 1994, 2002 Hewlett-Packard Company Permission to use, copy, modify, distribute and sell this software and its documentation for any purpose is hereby granted without fee, provided that the above copyright notice appear in all copies and that both that copyright notice and this permission notice appear in supporting documentation. Hewlett-Packard Company makes no representations about the suitability of this software for any purpose. It is provided "as is" without express or implied warranty. 1996, 1997, 1998, 1999 Silicon Graphics Computer Systems, Inc. Permission to use, copy, modify, distribute and sell this software and its documentation for any purpose is hereby granted without fee, provided that the above copyright notice appear in all copies and that both that copyright notice and this permission notice appear in supporting documentation. Silicon Graphics makes no representations about the suitability of this software for any purpose. It is provided "as is" without express or implied warranty. The Loki Library
2001 by Andrei Alexandrescu This code accompanies the book: Alexandrescu, Andrei. "Modern C++ Design: Generic Programming and Design Patterns Applied". 2001. Addison-Wesley Permission to use, copy, modify, distribute and sell this software for any purpose is hereby granted without fee, provided that the above copyright notice appear in all copies and that both that copyright notice and this permission notice appear in supporting documentation. The author or Addison-Welsey Longman make no representations about the suitability of this software for any purpose. It is provided "as is" without express or implied warranty. 2002-2003 David Moore, William E. Kempf Permission to use, copy, modify, distribute and sell this software and its documentation for any purpose is hereby granted without fee, provided that the above copyright notice appear in all copies and that both that copyright notice and this permission notice appear in supporting documentation. William E. Kempf makes no representations about the suitability of this software for any purpose. It is provided "as is" without express or implied warranty. 2001 Ronald Garcia Permission to use, copy, modify, distribute and sell this software and its documentation for any purpose is hereby granted without fee, provided that the above copyright notice appears in all copies and that both that copyright notice and this permission notice appear in supporting documentation. Ronald Garcia makes no representations about the suitability of this software for any purpose. It is provided "as is" without express or implied warranty. 2001 Jeremy Siek Permission to use, copy, modify, distribute and sell this software and its documentation for any purpose is hereby granted without fee, provided that the above copyright notice appears in all copies and that both that copyright notice and this permission notice appear in supporting documentation. Silicon Graphics makes no representations about the suitability of this software for any purpose. It is provided "as is" without express or implied warranty. 2002 CrystalClear Software, Inc. Permission to use, copy, modify, distribute and sell this software and its documentation for any purpose is hereby granted without fee, provided that the above copyright notice appear in all copies and that both that copyright notice and this permission notice appear in supporting documentation. CrystalClear Software makes no representations about the suitability of this software for any purpose. It is provided "as is" without express or implied warranty.
1998, 2002-2006 Kiyoshi Matsui <kmatsui@t3.rim.or.jp> All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE AUTHOR `ÀS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2000 Jeremy Siek, Lie-Quan Lee, and Andrew Lumsdaine Permission to use, copy, modify, distribute and sell this software and its documentation for any purpose is hereby granted without fee, provided that the above copyright notice appears in all copies and that both that copyright notice and this permission notice appear in supporting documentation. We make no representations about the suitability of this software for any purpose. It is provided "as is" without express or implied warranty. 2005 JongSoo Park Permission to use, copy, modify, distribute and sell this software and its documentation for any purpose is hereby granted without fee, provided that the above copyright notice appears in all copies and that both that copyright notice and this permission notice appear in supporting documentation. Jeremy Siek makes no representations about the suitability of this software for any purpose. It is provided "as is" without express or implied warranty. 2006 Michael Drexl Permission to use, copy, modify, and distribute this software and its documentation for any purpose is hereby granted without fee, provided that the above copyright notice appears in all copies and that both that copyright notice and this permission notice appear in supporting documentation. Michael Drexl makes no representations about the suitability of this software for any purpose. It is provided "as is" without express or implied warranty. 1991 Massachusetts Institute of Technology Permission to use, copy, modify, distribute, and sell this software and its documentation for any purpose is hereby granted without fee, provided that the above copyright notice appear in all copies and that both that copyright notice and this permission notice appear in supporting documentation, and that the name of M.I.T. not be used in advertising or publicity pertaining to distribution of the software without specific, written prior permission. M.I.T. makes no representations about the suitability of this software for any purpose. It is provided "as is" without express or implied warranty. 2001, 2002 Indiana University 2000, 2001 University of Notre Dame du Lac 2000 Jeremy Siek, Lie-Quan Lee, Andrew Lumsdaine 1996-1999 Silicon Graphics Computer Systems, Inc. 1994 Hewlett-Packard Company This product includes software developed at the University of Notre Dame and the Pervasive Technology Labs at Indiana University. For technical information contact Andrew Lumsdaine at the Pervasive Technology Labs at Indiana University. For administrative and license questions contact the Advanced Research and Technology Institute at 351 West 10th Street. Indianapolis, Indiana 46202, phone 317-278-4100, fax 317-274-5902. Some concepts based on versions from the MTL draft manual and Boost Graph and Property Map documentation, the SGI Standard Template Library documentation and the Hewlett-Packard STL, under the following license: Permission to use, copy, modify, distribute and sell this software and its documentation for any purpose is hereby granted without fee, provided that the above copyright notice appears in all copies and that both that copyright notice and this permission notice appear in supporting documentation. Silicon Graphics makes no representations about the suitability of this software for any purpose. It is provided "as is" without express or implied warranty.
Fri Aug 15 16:29:47 EDT 1997 Harwell-Boeing File I/O in C V. 1.0 National Institute of Standards and Technology, MD. K.A. Remington NOTICE Permission to use, copy, modify, and distribute this software and its documentation for any purpose and without fee is hereby granted provided that the above copyright notice appear in all copies and that both the copyright notice and this permission notice appear in supporting documentation. Neither the Author nor the Institution (National Institute of Standards and Technology) make any representations about the suitability of this software for any purpose. This software is provided "as is" without expressed or implied warranty. This software application may include RTreeTemplate third-party software, which is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. This software application may include C++/Tcl version 1.1.3 third-party software, which is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. This software application may include Swig version 1.3.40 third-party software, which is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. Swig version 1.3.40may be subject to the following copyrights: 1995-1998 The University of Utah and the Regents of the University of California All Rights Reserved Permission is hereby granted, without written agreement and without license or royalty fees, to use, copy, modify, and distribute this software and its documentation for any purpose, provided that (1) The above copyright notice and the following two paragraphs appear in all copies of the source code and (2) redistributions including binaries reproduces these notices in the supporting documentation. Substantial modifications to this software may be copyrighted by their authors and need not follow the licensing terms described here, provided that the new terms are clearly indicated in all files where they apply. IN NO EVENT SHALL THE AUTHOR, THE UNIVERSITY OF CALIFORNIA, THE UNIVERSITY OF UTAH OR DISTRIBUTORS OF THIS SOFTWARE BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE AUTHORS OR ANY OF THE ABOVE PARTIES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE AUTHOR, THE UNIVERSITY OF CALIFORNIA, AND THE UNIVERSITY OF UTAH SPECIFICALLY DISCLAIM ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS ON AN "AS IS" BASIS, AND THE AUTHORS AND DISTRIBUTORS HAVE NO OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. This software includes contributions that are 1998-2005 University of Chicago. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. Neither the name of the University of Chicago nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE UNIVERSITY OF CHICAGO AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE UNIVERSITY OF CHICAGO OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. This software includes contributions that are 2005-2006 Arizona Board of Regents (University of Arizona). All Rights Reserved Permission is hereby granted, without written agreement and without license or royalty fees, to use, copy, modify, and distribute this software and its documentation for any purpose, provided that (1) The above copyright notice and the following two paragraphs appear in all copies of the source code and (2) redistributions including binaries reproduces these notices in the supporting documentation. Substantial modifications to this software may be copyrighted by their authors and need not follow the licensing terms described here, provided that the new terms are clearly indicated in all files where they apply. THIS SOFTWARE IS PROVIDED BY THE UNIVERSITY OF ARIZONA AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE UNIVERSITY OF ARIZONA OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
This software application may include zlib version 1.1.3 third-party software. Zlib version 1.1.3 is distributed under the terms of the zlib license and is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the license for the specific language governing rights and limitations under the license. You can view a copy of the license at: your_Mentor_Graphics_documentation_directory/legal/zlib_libpng.pdf. Zlib version 1.1.3 may be subject to the following copyrights: 1997 Christian Michelsen Research AS, Advanced Computing, Fantoftvegen 38, 5036 BERGEN, Norway http://www.cmr.no Permission to use, copy, modify, distribute and sell this software and its documentation for any purpose is hereby granted without fee, provided that the above copyright notice appear in all copies and that both that copyright notice and this permission notice appear in supporting documentation. Christian Michelsen Research AS makes no representations about the suitability of this software for any purpose. It is provided "as is" without express or implied warranty.
This software application may include Perl 5.8.0 third-party software. Perl 5.8.0 is distributed under the terms of the GNU General Public License version 2.0 and is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the license for the specific language governing rights and limitations under the license. You can view a copy of the license at: your_Mentor_Graphics_documentation_directory/legal/gnu_gpl_2.0.pdf. To obtain a copy of Perl 5.8.0 source code, send a request to request_sourcecode@mentor.com. This offer shall only be available for three years from the date Mentor Graphics Corporation first distributed Perl 5.8.0. Perl 5.8.0 may be subject to the following copyrights: 1989, 1993, 1994 The Regents of the University of California. All rights reserved.
This code is derived from software contributed to Berkeley by Guido van Rossum. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. 2. 3. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS `ÀS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1998-2000 Gisle Aas. 1995-1996 Neil Winton. 1991-1992 RSA Data Security, Inc. This code is derived from Neil Winton's MD5-1.7 Perl module, which in turn is derived from the reference implementation in RFC 1321 which comes with this message: 1991-2, RSA Data Security, Inc. Created 1991. All rights reserved. License to copy and use this software is granted provided that it is identified as the "RSA Data Security, Inc. MD5 Message-Digest Algorithm" in all material mentioning or referencing this software or this function. License is also granted to make and use derivative works provided that such works are identified as "derived from the RSA Data Security, Inc. MD5 Message-Digest Algorithm" in all material mentioning or referencing the derived work. RSA Data Security, Inc. makes no representations concerning either the merchantability of this software or the suitability of this software for any particular purpose. It is provided "as is" without express or implied warranty of any kind. These notices must be retained in any copies of any part of this documentation and/or software.
This software application may include Tcl 8.4.11 third-party software, which is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. Tcl 8.4.11 may be subject to the following copyright: Regents of the University of California, Sun Microsystems, Inc., Scriptics Corporation, ActiveState Corporation and other parties. The following terms apply to all files associated with the software unless explicitly disclaimed in individual files. The authors hereby grant permission to use, copy, modify, distribute, and license this software and its documentation for any purpose, provided that existing copyright notices are retained in all copies and that this notice is included verbatim in any distributions. No written agreement, license, or royalty fee is required for any of the authorized uses. Modifications to this software may be copyrighted by their authors and need not follow the licensing terms described here, provided that the new terms are clearly indicated on the first page of each file where they apply.
IN NO EVENT SHALL THE AUTHORS OR DISTRIBUTORS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OF THIS SOFTWARE, ITS DOCUMENTATION, OR ANY DERIVATIVES THEREOF, EVEN IF THE AUTHORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE AUTHORS AND DISTRIBUTORS SPECIFICALLY DISCLAIM ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, AND THE AUTHORS AND DISTRIBUTORS HAVE NO OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. GOVERNMENT USE: If you are acquiring this software on behalf of the U.S. government, the Government shall have only "Restricted Rights" in the software and related documentation as defined in the Federal Acquisition Regulations (FARs) in Clause 52.227.19 (c) (2). If you are acquiring the software on behalf of the Department of Defense, the software shall be classified as "Commercial Computer Software" and the Government shall have only "Restricted Rights" as defined in Clause 252.227-7013 (c) (1) of DFARs. Notwithstanding the foregoing, the authors grant the U.S. Government and others acting in its behalf permission to use and distribute the software in accordance with the terms specified in this license.
This software application may include Tk 8.4.11 third-party software, which is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. Tk 8.4.11 may be subject to the following copyright: Regents of the University of California, Sun Microsystems, Inc., Scriptics Corporation, ActiveState Corporation and other parties. The following terms apply to all files associated with the software unless explicitly disclaimed in individual files. The authors hereby grant permission to use, copy, modify, distribute, and license this software and its documentation for any purpose, provided that existing copyright notices are retained in all copies and that this notice is included verbatim in any distributions. No written agreement, license, or royalty fee is required for any of the authorized uses. Modifications to this software may be copyrighted by their authors and need not follow the licensing terms described here, provided that the new terms are clearly indicated on the first page of each file where they apply. IN NO EVENT SHALL THE AUTHORS OR DISTRIBUTORS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OF THIS SOFTWARE, ITS DOCUMENTATION, OR ANY DERIVATIVES THEREOF, EVEN IF THE AUTHORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE AUTHORS AND DISTRIBUTORS SPECIFICALLY DISCLAIM ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, AND THE AUTHORS AND DISTRIBUTORS HAVE NO OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. GOVERNMENT USE: If you are acquiring this software on behalf of the U.S. government, the Government shall have only "Restricted Rights" in the software and related documentation as defined in the Federal Acquisition Regulations (FARs) in Clause 52.227.19 (c) (2). If you are acquiring the software on behalf of the Department of Defense, the software shall be classified as "Commercial Computer Software" and the Government shall have only "Restricted Rights" as defined in Clause 252.227-7013 (c) (1) of DFARs. Notwithstanding the foregoing, the authors grant the U.S. Government and others acting in its behalf permission to use and distribute the software in accordance with the terms specified in this license.
This software application may include itcl 3.2.1 third-party software, which is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. itcl 3.2.1 may be subject to the following copyrights: 1993-1996 Lucent Technologies
Permission to use, copy, modify, and distribute this software and its documentation for any purpose and without fee is hereby granted, provided that the above copyright notice appear in all copies and that both that the copyright notice and warranty disclaimer appear in supporting documentation, and that the names of Lucent Technologies any of their entities not be used in advertising or publicity pertaining to distribution of the software without specific, written prior permission. Lucent Technologies disclaims all warranties with regard to this software, including all implied warranties of merchantability and fitness. In no event shall Lucent be liable for any special, indirect or consequential damages or any damages whatsoever resulting from loss of use, data or profits, whether in an action of contract, negligence or other tortuous action, arising out of or in connection with the use or performance of this software. Lucent Technologies, Inc., and other parties. The following terms apply to all files associated with the software unless explicitly disclaimed in individual files. The authors hereby grant permission to use, copy, modify, distribute, and license this software and its documentation for any purpose, provided that existing copyright notices are retained in all copies and that this notice is included verbatim in any distributions. No written agreement, license, or royalty fee is required for any of the authorized uses. Modifications to this software may be copyrighted by their authors and need not follow the licensing terms described here, provided that the new terms are clearly indicated on the first page of each file where they apply. IN NO EVENT SHALL THE AUTHORS OR DISTRIBUTORS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OF THIS SOFTWARE, ITS DOCUMENTATION, OR ANY DERIVATIVES THEREOF, EVEN IF THE AUTHORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE AUTHORS AND DISTRIBUTORS SPECIFICALLY DISCLAIM ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, AND THE AUTHORS AND DISTRIBUTORS HAVE NO OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. GOVERNMENT USE: If you are acquiring this software on behalf of the U.S. government, the Government shall have only "Restricted Rights" in the software and related documentation as defined in the Federal Acquisition Regulations (FARs) in Clause 52.227.19 (c) (2). If you are acquiring the software on behalf of the Department of Defense, the software shall be classified as "Commercial Computer Software" and the Government shall have only "Restricted Rights" as defined in Clause 252.227-7013 (c) (1) of DFARs. Notwithstanding the foregoing, the authors grant the U.S. Government and others acting in its behalf permission to use and distribute the software in accordance with the terms specified in this license. 1993 AT&T Bell Laboratories Permission to use, copy, modify, and distribute this software and its documentation for any purpose and without fee is hereby granted, provided that the above copyright notice appear in all copies and that both that the copyright notice and warranty disclaimer appear in supporting documentation, and that the names of AT&T Bell Laboratories any of their entities not be used in advertising or publicity pertaining to distribution of the software without specific, written prior permission. AT&T disclaims all warranties with regard to this software, including all implied warranties of merchantability and fitness. In no event shall AT&T be liable for any special, indirect or consequential damages or any damages whatsoever resulting from loss of use, data or profits, whether in an action of contract, negligence or other tortuous action, arising out of or in connection with the use or performance of this software.
This software application may include iwidgets 4.0.1third-party software, which is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. iwidgets 4.0.1 may be subject to the following copyrights: 1997 DSC Technologies Corporation Permission to use, copy, modify, distribute and license this software and its documentation for any purpose, and without fee or written agreement with DSC, is hereby granted, provided that the above copyright notice appears in all copies and that both the copyright notice and warranty disclaimer below appear in supporting documentation, and that the names of
DSC Technologies Corporation or DSC Communications Corporation not be used in advertising or publicity pertaining to the software without specific, written prior permission. DSC DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, AND NON-INFRINGEMENT. THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, AND THE AUTHORS AND DISTRIBUTORS HAVE NO OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. IN NO EVENT SHALL DSC BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTUOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. RESTRICTED RIGHTS: Use, duplication or disclosure by the government is subject to the restrictions as set forth in subparagraph (c) (1) (ii) of the Rights in Technical Data and Computer Software Clause as DFARS 252.227-7013 and FAR 52.227-19. 1995 1999 DSC Technologies Corporation Permission to use, copy, modify, distribute and license this software and its documentation for any purpose, and without fee or written agreement with DSC, is hereby granted, provided that the above copyright notice appears in all copies and that both the copyright notice and warranty disclaimer below appear in supporting documentation, and that the names of DSC Technologies Corporation or DSC Communications Corporation not be used in advertising or publicity pertaining to the software without specific, written prior permission. DSC DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, AND NON- INFRINGEMENT. THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, AND THE AUTHORS AND DISTRIBUTORS HAVE NO OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. IN NO EVENT SHALL DSC BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTUOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
1996 Lucent Technologies Permission to use, copy, modify, and distribute this software and its documentation for any purpose and without fee is hereby granted, provided that the above copyright notice appear in all copies and that both that the copyright notice and warranty disclaimer appear in supporting documentation, and that the names of Lucent Technologies any of their entities not be used in advertising or publicity pertaining to distribution of the software without specific, written prior permission. Lucent Technologies disclaims all warranties with regard to this software, including all implied warranties of merchantability and fitness. In no event shall Lucent Technologies be liable for any special, indirect or consequential damages or any damages whatsoever resulting from loss of use, data or profits, whether in an action of contract, negligence or other tortuous action, arising out of or in connection with the use or performance of this software.
1994, 1995 by the Lawrence Berkeley Laboratory. Redistribution and use in source and binary forms, with or without modification, are permitted provided that: 1. 2. 3. source code distributions retain the above copyright notice and this paragraph in its entirety, distributions including binary code include the above copyright notice and this paragraph in its entirety in the documentation or other materials provided with the distribution, and all advertising materials mentioning features or use of this software display the following acknowledgement:
This product includes software developed by the University of California, Lawrence Berkeley Laboratory and its contributors.
Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED `ÀS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
This software application may include Tcllib version 1.10 third-party software, which is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. Tcllib version 1.10 may be subject to the following copyrights: 1988,1991 Rechenzentrum der Ruhr-Universitaet Bochum [german hyphen patterns] 1993,1994,1999 Bernd Raichle/DANTE e.V. [macros, adaption for TeX 2] IMPORTANT NOTICE: This program can be redistributed and/or modified under the terms of the LaTeX Project Public License Distributed from CTAN archives in directory macros/latex/base/lppl.txt; either version 1 of the License, or any later version. 1998, 2001 Claudio Beccari This program can be redistributed and/or modified under the terms of the LaTeX Project Public License Distributed from CTAN archives in directory macros/latex/base/lppl.txt; either version 1 of the License, or any later version. 2004 Salvatore Sanfilippo <antirez@invece.org>. All rights reserved. Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, provided that the above copyright notice(s) and this permission notice appear in all copies of the Software and that both the above copyright notice(s) and this permission notice appear in supporting documentation. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT OF THIRD PARTY RIGHTS. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR HOLDERS INCLUDED IN THIS NOTICE BE LIABLE FOR ANY CLAIM, OR ANY SPECIAL INDIRECT OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. Except as contained in this notice, the name of a copyright holder shall not be used in advertising or otherwise to promote the sale, use or other dealings in this Software without prior written authorization of the copyright holder.
1990-2, RSA Data Security, Inc. All rights reserved. License to copy and use this software is granted provided that it is identified as the "RSA Data Security, Inc. MD4 Message-Digest Algorithm" in all material mentioning or referencing this software or this function. License is also granted to make and use derivative works provided that such works are identified as "derived from the RSA Data Security, Inc. MD4 Message-Digest Algorithm" in all material mentioning or referencing the derived work. RSA Data Security, Inc. makes no representations concerning either the merchantability of this software or the suitability of this software for any particular purpose. It is provided "as is" without express or implied warranty of any kind.
These notices must be retained in any copies of any part of this documentation and/or software. 2001, 2002 Allan Saddi <allan@saddi.com> All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. 2. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS `ÀS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
This software application may include strawberry-perl 5.10.0.6 third-party software. strawberry-perl 5.10.0.6is distributed under the terms of the GNU General Public License version 2.0 and is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the license for the specific language governing rights and limitations under the license. You can view a copy of the license at: your_Mentor_Graphics_documentation_directory/legal/gnu_gpl_2.0.pdf. Portions of this software may be subject to the GNU Library General Public License v2. You can view a copy of the GNU Library General Public License v2 at: your_Mentor_Graphics_documentation_directory/legal/ gnu_library_gpl_2.0.pdf. Portions of this software may be subject to the GNU Lesser General Public License v2.1. You can view a copy of the GNU Lesser General Public License v2.1 at: your_Mentor_Graphics_documentation_directory/legal/ gnu_lgpl_2.1.pdf. Portions of this software may be subject to the Apach License, version 2.0. You can view a copy of the Apache 2.0 license at: your_Mentor_Graphics_documentation_directory/legal/ Apache_2.0.pdf. Portions of this software may be subject to the Artistic License. You can view a copy of the Apache 2.0 license at: your_Mentor_Graphics_documentation_directory/legal/ perl_artistic_2.0.pdf. Portions of this software may be subject to the Unicode Terms of Use. You can view a copy of the Unicode Terms of Use at: your_Mentor_Graphics_documentation_directory/legal/ unicode_term_of_use.pdf. To obtain a copy of the strawberry-perl 5.10.0.6 source code, send a request to request_sourcecode@mentor.com. This offer shall only be available for three years from the date Mentor Graphics Corporation first distributed strawberry-perl 5.10.0.6. strawberry-perl 5.10.0.6 may be subject to the following copyrights: 1982, 1986, 1987, 1989, 1992, 1993, 1994, 1996 The Regents of the University of California. All rights reserved. This code is derived from software contributed to Berkeley by Guido van Rossum. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
1. 2. 3.
Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS `ÀS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1994, Hewlett-Packard Company Permission to use, copy, modify, distribute and sell this software and its documentation for any purpose is hereby granted without fee, provided that the above copyright notice appear in all copies and that both that copyright notice and this permission notice appear in supporting documentation. Hewlett-Packard Company makes no representations about the suitability of this software for any purpose. It is provided "as is" without express or implied warranty.
1996,1997, Silicon Graphics Computer Systems, Inc. Permission to use, copy, modify, distribute and sell this software and its documentation for any purpose is hereby granted without fee, provided that the above copyright notice appear in all copies and that both that copyright notice and this permission notice appear in supporting documentation. Silicon Graphics makes no representations about the suitability of this software for any purpose. It is provided "as is" without express or implied warranty.
1995-2005 Jean-loup Gailly and Mark Adler This software is provided 'as-is', without any express or implied warranty. In no event will the authors be held liable for any damages arising from the use of this software. Permission is granted to anyone to use this software for any purpose, including commercial applications, and to alter it and redistribute it freely, subject to the following restrictions: 1. The origin of this software must not be misrepresented; you must not claim that you wrote the original software. If you use this software in a product, an acknowledgment in the product documentation would be appreciated but is not required. Altered source versions must be plainly marked as such, and must not be misrepresented as being the original software. This notice may not be removed or altered from any source distribution. Mark Adler madler@alumni.caltech.edu
2. 3.
Jean-loup Gailly jloup@gzip.org
1991-2005 Unicode, Inc. All rights reserved.
Distributed under the Terms of Use in L<http://www.unicode.org/copyright.html>. 1991-2, RSA Data Security, Inc. Created 1991. All rights reserved. License to copy and use this software is granted provided that it is identified as the "RSA Data Security, Inc. MD5 Message-Digest Algorithm" in all material mentioning or referencing this software or this function. License is also granted to make and use derivative works provided that such works are identified as "derived from the RSA Data Security, Inc. MD5 Message-Digest Algorithm" in all material mentioning or referencing the derived work. RSA Data Security, Inc. makes no representations concerning either the merchantability of this software or the suitability of this software for any particular purpose. It is provided "as is" without express or implied warranty of any kind. These notices must be retained in any copies of any part of this documentation and/or software.
This software application may include libftd2xx 0.4.16 third-party software. Portions of libftd2xx 0.4.16 are distributed under the terms of the GNU Lesser General Public License v2.1 and are distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the license for the specific language governing rights and limitations under the license. You can view a copy of the license at: your_Mentor_Graphics_documentation_directory/legal/gnu_lgpl_2.1.pdf. To obtain a copy of the libftd2xx 0.4.16 source code, send a request to request_sourcecode@mentor.com. This offer shall only be available for three years from the date Mentor Graphics Corporation first distributed libftd2xx 0.4.16. The files usb.h.in and/or usb.h are licensed under the BSD license: 2000-2003 Johannes Erdfelt johannes@erdfelt.com All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. 2. 3. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. The name of the author may not be used to endorse or promote products derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE AUTHOR `ÀS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. This software application may include gzip version 1.3.12 third-party software. gzip version 1.3.12 is distributed under the terms of the GNU General Public License version 2.0 and is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the license for the specific language governing rights and limitations under the license. You can view a copy of the license at: your_Mentor_Graphics_documentation_directory/legal/gnu_gpl_2.0.pdf. Portions of this software may be subject to the GNU Free Documentation License version 1.2. You can view a copy of the GNU Free Documentation License version 1.2 at: your_Mentor_Graphics_documentation_directory/legal/gnu_free_doc_1.2.pdf. To obtain a copy of the gzip version 1.3.12 source code, send a request to request_sourcecode@mentor.com. This offer shall only be available for three years from the date Mentor Graphics Corporation first distributed gzip version 1.3.12. This software application may include libusb version 0.1.12 third-party software. libusb version 0.1.12 is distributed under the terms of the GNU Lesser General Public License version 2.1and is distributed on an "AS IS" basis, WITHOUT
WARRANTY OF ANY KIND, either express or implied. See the license for the specific language governing rights and limitations under the license. You can view a copy of the license at: your_Mentor_Graphics_documentation_directory/legal/gnu_lgpl_2.1.pdf. To obtain a copy of the libusb version 0.1.12 source code, send a request to request_sourcecode@mentor.com. This offer shall only be available for three years from the date Mentor Graphics Corporation first distributed libusb version 0.1.12. libusb version 0.1.12 may be subject to the following copyrights: 2000-2003 Johannes Erdfelt <johannes@erdfelt.com> All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 4. 5. 6. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. The name of the author may not be used to endorse or promote products derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE AUTHOR `ÀS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
End-User License Agreement

The latest version of the End-User License Agreement is available on-line at: www.mentor.com/eula IMPORTANT INFORMATION USE OF ALL SOFTWARE IS SUBJECT TO LICENSE RESTRICTIONS. CAREFULLY READ THIS LICENSE AGREEMENT BEFORE USING THE PRODUCTS. USE OF SOFTWARE INDICATES CUSTOMERS COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH IN THIS AGREEMENT. ANY ADDITIONAL OR DIFFERENT PURCHASE ORDER TERMS AND CONDITIONS SHALL NOT APPLY.
END-USER LICENSE AGREEMENT (Agreement) This is a legal agreement concerning the use of Software (as defined in Section 2) and hardware (collectively Products) between the company acquiring the Products (Customer), and the Mentor Graphics entity that issued the corresponding quotation or, if no quotation was issued, the applicable local Mentor Graphics entity (Mentor Graphics). Except for license agreements related to the subject matter of this license agreement which are physically signed by Customer and an authorized representative of Mentor Graphics, this Agreement and the applicable quotation contain the parties' entire understanding relating to the subject matter and supersede all prior or contemporaneous agreements. If Customer does not agree to these terms and conditions, promptly return or, in the case of Software received electronically, certify destruction of Software and all accompanying items within five days after receipt of Software and receive a full refund of any license fee paid.
1. ORDERS, FEES AND PAYMENT. 1.1. To the extent Customer (or if agreed by Mentor Graphics, Customers appointed third party buying agent) places and Mentor Graphics accepts purchase orders pursuant to this Agreement (Order(s)), each Order will constitute a contract between Customer and Mentor Graphics, which shall be governed solely and exclusively by the terms and conditions of this Agreement, any applicable addenda and the applicable quotation, whether or not these documents are referenced on the Order. Any additional or conflicting terms and conditions appearing on an Order will not be effective unless agreed in writing by an authorized representative of Customer and Mentor Graphics. 1.2. Amounts invoiced will be paid, in the currency specified on the applicable invoice, within 30 days from the date of such invoice. Any past due invoices will be subject to the imposition of interest charges in the amount of one and one-half percent per month or the applicable legal rate currently in effect, whichever is lower. Prices do not include freight, insurance, customs duties, taxes or other similar charges, which Mentor Graphics will state separately in the applicable invoice(s). Unless timely provided with a valid certificate of exemption or other evidence that items are not taxable, Mentor Graphics will invoice Customer for all applicable taxes including, but not limited to, VAT, GST, sales tax and service tax. Customer will make all payments free and clear of, and without reduction for, any withholding or other taxes; any such taxes imposed on payments by Customer hereunder will be Customers sole responsibility. If Customer appoints a third party to place purchase orders and/or make payments on Customers behalf, Customer shall be liable for payment under Orders placed by such third party in the event of default. 1.3. All Products are delivered FCA factory (Incoterms 2000), freight prepaid and invoiced to Customer, except Software delivered electronically, which shall be deemed delivered when made available to Customer for download. Mentor Graphics retains a security interest in all Products delivered under this Agreement, to secure payment of the purchase price of such Products, and Customer agrees to sign any documents that Mentor Graphics determines to be necessary or convenient for use in filing or perfecting such security interest. Mentor Graphics delivery of Software by electronic means is subject to Customers provision of both a primary and an alternate e-mail address. 2. GRANT OF LICENSE. The software installed, downloaded, or otherwise acquired by Customer under this Agreement, including any updates, modifications, revisions, copies, documentation and design data (Software) are copyrighted, trade secret and confidential information of Mentor Graphics or its licensors, who maintain exclusive title to all Software and retain all rights not expressly granted by this Agreement. Mentor Graphics grants to Customer, subject to payment of applicable license fees, a nontransferable, nonexclusive license to use Software solely: (a) in machine-readable, object-code form (except as provided in Subsection 5.2); (b) for Customers internal business purposes; (c) for the term of the license; and (d) on the computer hardware and at the site authorized by Mentor Graphics. A site is restricted to a one-half mile (800 meter) radius. Customer may have Software temporarily used by an employee for telecommuting purposes from locations other than a Customer office, such as the employee's residence, an airport or hotel, provided that such employee's primary place of employment is the site where the Software is authorized for use. Mentor Graphics standard policies and programs, which vary depending on Software, license fees paid or services purchased, apply to the following: (a) relocation of Software; (b) use of Software, which may be limited, for example, to execution of a single session by a single user on the authorized hardware or for a restricted period of time (such limitations may be technically implemented through the use of authorization codes or similar devices); and (c) support services provided, including eligibility to receive telephone support, updates, modifications, and revisions. For the avoidance of doubt, if Customer requests any change or enhancement to Software, whether in the course of
receiving support or consulting services, evaluating Software, performing beta testing or otherwise, any inventions, product improvements, modifications or developments made by Mentor Graphics (at Mentor Graphics sole discretion) will be the exclusive property of Mentor Graphics. 3. ESC SOFTWARE. If Customer purchases a license to use development or prototyping tools of Mentor Graphics Embedded Software Channel (ESC), Mentor Graphics grants to Customer a nontransferable, nonexclusive license to reproduce and distribute executable files created using ESC compilers, including the ESC run-time libraries distributed with ESC C and C++ compiler Software that are linked into a composite program as an integral part of Customers compiled computer program, provided that Customer distributes these files only in conjunction with Customers compiled computer program. Mentor Graphics does NOT grant Customer any right to duplicate, incorporate or embed copies of Mentor Graphics real-time operating systems or other embedded software products into Customers products or applications without first signing or otherwise agreeing to a separate agreement with Mentor Graphics for such purpose. BETA CODE. 4.1. Portions or all of certain Software may contain code for experimental testing and evaluation (Beta Code), which may not be used without Mentor Graphics explicit authorization. Upon Mentor Graphics authorization, Mentor Graphics grants to Customer a temporary, nontransferable, nonexclusive license for experimental use to test and evaluate the Beta Code without charge for a limited period of time specified by Mentor Graphics. This grant and Customers use of the Beta Code shall not be construed as marketing or offering to sell a license to the Beta Code, which Mentor Graphics may choose not to release commercially in any form. 4.2. If Mentor Graphics authorizes Customer to use the Beta Code, Customer agrees to evaluate and test the Beta Code under normal conditions as directed by Mentor Graphics. Customer will contact Mentor Graphics periodically during Customers use of the Beta Code to discuss any malfunctions or suggested improvements. Upon completion of Customers evaluation and testing, Customer will send to Mentor Graphics a written evaluation of the Beta Code, including its strengths, weaknesses and recommended improvements. 4.3. Customer agrees to maintain Beta Code in confidence and shall restrict access to the Beta Code, including the methods and concepts utilized therein, solely to those employees and Customer location(s) authorized by Mentor Graphics to perform beta testing. Customer agrees that any written evaluations and all inventions, product improvements, modifications or developments that Mentor Graphics conceived or made during or subsequent to this Agreement, including those based partly or wholly on Customers feedback, will be the exclusive property of Mentor Graphics. Mentor Graphics will have exclusive rights, title and interest in all such property. The provisions of this Subsection 4.3 shall survive termination of this Agreement. 5. RESTRICTIONS ON USE. 5.1. Customer may copy Software only as reasonably necessary to support the authorized use. Each copy must include all notices and legends embedded in Software and affixed to its medium and container as received from Mentor Graphics. All copies shall remain the property of Mentor Graphics or its licensors. Customer shall maintain a record of the number and primary location of all copies of Software, including copies merged with other software, and shall make those records available to Mentor Graphics upon request. Customer shall not make Products available in any form to any person other than Customers employees and on-site contractors, excluding Mentor Graphics competitors, whose job performance requires access and who are under obligations of confidentiality. Customer shall take appropriate action to protect the confidentiality of Products and ensure that any person permitted access does not disclose or use it except as permitted by this Agreement. Customer shall give Mentor Graphics written notice of any unauthorized disclosure or use of the Products as soon as Customer learns or becomes aware of such unauthorized disclosure or use. Except as otherwise permitted for purposes of interoperability as specified by applicable and mandatory local law, Customer shall not reverse-assemble, reverse-compile, reverse-engineer or in any way derive any source code from Software. Log files, data files, rule files and script files generated by or for the Software (collectively Files), including without limitation files containing Standard Verification Rule Format (SVRF) and Tcl Verification Format (TVF) which are Mentor Graphics proprietary syntaxes for expressing process rules, constitute or include confidential information of Mentor Graphics. Customer may share Files with third parties, excluding Mentor Graphics competitors, provided that the confidentiality of such Files is protected by written agreement at least as well as Customer protects other information of a similar nature or importance, but in any case with at least reasonable care. Customer may use Files containing SVRF or TVF only with Mentor Graphics products. Under no circumstances shall Customer use Software or Files or allow their use for the purpose of developing, enhancing or marketing any product that is in any way competitive with Software, or disclose to any third party the results of, or information pertaining to, any benchmark. 5.2. If any Software or portions thereof are provided in source code form, Customer will use the source code only to correct software errors and enhance or modify the Software for the authorized use. Customer shall not disclose or permit disclosure of source code, in whole or in part, including any of its methods or concepts, to anyone except Customers employees or contractors, excluding Mentor Graphics competitors, with a need to know. Customer shall not copy or compile source code in any manner except to support this authorized use. 5.3. Customer may not assign this Agreement or the rights and duties under it, or relocate, sublicense or otherwise transfer the Products, whether by operation of law or otherwise (Attempted Transfer), without Mentor Graphics prior written consent and payment of Mentor Graphics then-current applicable relocation and/or transfer fees. Any Attempted Transfer without Mentor Graphics prior written consent shall be a material breach of this Agreement and may, at Mentor Graphics option, result in the immediate termination of the Agreement and/or the licenses granted under this Agreement. The terms
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of this Agreement, including without limitation the licensing and assignment provisions, shall be binding upon Customers permitted successors in interest and assigns. 5.4. The provisions of this Section 5 shall survive the termination of this Agreement. 6. SUPPORT SERVICES. To the extent Customer purchases support services, Mentor Graphics will provide Customer updates and technical support for the Products, at the Customer site(s) for which support is purchased, in accordance with Mentor Graphics then current End-User Support Terms located at http://supportnet.mentor.com/about/legal/. AUTOMATIC CHECK FOR UPDATES; PRIVACY. Technological measures in Software may communicate with servers of Mentor Graphics or its contractors for the purpose of checking for and notifying the user of updates and to ensure that the Software in use is licensed in compliance with this Agreement. Mentor Graphics will not collect any personally identifiable data in this process and will not disclose any data collected to any third party without the prior written consent of Customer, except to Mentor Graphics outside attorneys or as may be required by a court of competent jurisdiction. LIMITED WARRANTY. 8.1. Mentor Graphics warrants that during the warranty period its standard, generally supported Products, when properly installed, will substantially conform to the functional specifications set forth in the applicable user manual. Mentor Graphics does not warrant that Products will meet Customers requirements or that operation of Products will be uninterrupted or error free. The warranty period is 90 days starting on the 15th day after delivery or upon installation, whichever first occurs. Customer must notify Mentor Graphics in writing of any nonconformity within the warranty period. For the avoidance of doubt, this warranty applies only to the initial shipment of Software under an Order and does not renew or reset, for example, with the delivery of (a) Software updates or (b) authorization codes or alternate Software under a transaction involving Software re-mix. This warranty shall not be valid if Products have been subject to misuse, unauthorized modification or improper installation. MENTOR GRAPHICS ENTIRE LIABILITY AND CUSTOMERS EXCLUSIVE REMEDY SHALL BE, AT MENTOR GRAPHICS OPTION, EITHER (A) REFUND OF THE PRICE PAID UPON RETURN OF THE PRODUCTS TO MENTOR GRAPHICS OR (B) MODIFICATION OR REPLACEMENT OF THE PRODUCTS THAT DO NOT MEET THIS LIMITED WARRANTY, PROVIDED CUSTOMER HAS OTHERWISE COMPLIED WITH THIS AGREEMENT. MENTOR GRAPHICS MAKES NO WARRANTIES WITH RESPECT TO: (A) SERVICES; (B) PRODUCTS PROVIDED AT NO CHARGE; OR (C) BETA CODE; ALL OF WHICH ARE PROVIDED AS IS. 8.2. THE WARRANTIES SET FORTH IN THIS SECTION 8 ARE EXCLUSIVE. NEITHER MENTOR GRAPHICS NOR ITS LICENSORS MAKE ANY OTHER WARRANTIES EXPRESS, IMPLIED OR STATUTORY, WITH RESPECT TO PRODUCTS PROVIDED UNDER THIS AGREEMENT. MENTOR GRAPHICS AND ITS LICENSORS SPECIFICALLY DISCLAIM ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT OF INTELLECTUAL PROPERTY. 9. LIMITATION OF LIABILITY. EXCEPT WHERE THIS EXCLUSION OR RESTRICTION OF LIABILITY WOULD BE VOID OR INEFFECTIVE UNDER APPLICABLE LAW, IN NO EVENT SHALL MENTOR GRAPHICS OR ITS LICENSORS BE LIABLE FOR INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES (INCLUDING LOST PROFITS OR SAVINGS) WHETHER BASED ON CONTRACT, TORT OR ANY OTHER LEGAL THEORY, EVEN IF MENTOR GRAPHICS OR ITS LICENSORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. IN NO EVENT SHALL MENTOR GRAPHICS OR ITS LICENSORS LIABILITY UNDER THIS AGREEMENT EXCEED THE AMOUNT RECEIVED FROM CUSTOMER FOR THE HARDWARE, SOFTWARE LICENSE OR SERVICE GIVING RISE TO THE CLAIM. IN THE CASE WHERE NO AMOUNT WAS PAID, MENTOR GRAPHICS AND ITS LICENSORS SHALL HAVE NO LIABILITY FOR ANY DAMAGES WHATSOEVER. THE PROVISIONS OF THIS SECTION 9 SHALL SURVIVE THE TERMINATION OF THIS AGREEMENT.
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10. HAZARDOUS APPLICATIONS. CUSTOMER ACKNOWLEDGES IT IS SOLELY RESPONSIBLE FOR TESTING ITS PRODUCTS USED IN APPLICATIONS WHERE THE FAILURE OR INACCURACY OF ITS PRODUCTS MIGHT RESULT IN DEATH OR PERSONAL INJURY (HAZARDOUS APPLICATIONS). NEITHER MENTOR GRAPHICS NOR ITS LICENSORS SHALL BE LIABLE FOR ANY DAMAGES RESULTING FROM OR IN CONNECTION WITH THE USE OF MENTOR GRAPHICS PRODUCTS IN OR FOR HAZARDOUS APPLICATIONS. THE PROVISIONS OF THIS SECTION 10 SHALL SURVIVE THE TERMINATION OF THIS AGREEMENT. 11. INDEMNIFICATION. CUSTOMER AGREES TO INDEMNIFY AND HOLD HARMLESS MENTOR GRAPHICS AND ITS LICENSORS FROM ANY CLAIMS, LOSS, COST, DAMAGE, EXPENSE OR LIABILITY, INCLUDING ATTORNEYS FEES, ARISING OUT OF OR IN CONNECTION WITH THE USE OF PRODUCTS AS DESCRIBED IN SECTION 10. THE PROVISIONS OF THIS SECTION 11 SHALL SURVIVE THE TERMINATION OF THIS AGREEMENT. 12. INFRINGEMENT. 12.1. Mentor Graphics will defend or settle, at its option and expense, any action brought against Customer in the United States, Canada, Japan, or member state of the European Union which alleges that any standard, generally supported Product acquired by Customer hereunder infringes a patent or copyright or misappropriates a trade secret in such jurisdiction. Mentor Graphics will pay costs and damages finally awarded against Customer that are attributable to the action. Customer understands and agrees that as conditions to Mentor Graphics obligations under this section Customer must: (a) notify Mentor Graphics promptly in writing of the action; (b) provide Mentor Graphics all reasonable information and assistance
to settle or defend the action; and (c) grant Mentor Graphics sole authority and control of the defense or settlement of the action. 12.2. If a claim is made under Subsection 12.1 Mentor Graphics may, at its option and expense, (a) replace or modify the Product so that it becomes noninfringing; (b) procure for Customer the right to continue using the Product; or (c) require the return of the Product and refund to Customer any purchase price or license fee paid, less a reasonable allowance for use. 12.3. Mentor Graphics has no liability to Customer if the action is based upon: (a) the combination of Software or hardware with any product not furnished by Mentor Graphics; (b) the modification of the Product other than by Mentor Graphics; (c) the use of other than a current unaltered release of Software; (d) the use of the Product as part of an infringing process; (e) a product that Customer makes, uses, or sells; (f) any Beta Code or Product provided at no charge; (g) any software provided by Mentor Graphics licensors who do not provide such indemnification to Mentor Graphics customers; or (h) infringement by Customer that is deemed willful. In the case of (h), Customer shall reimburse Mentor Graphics for its reasonable attorney fees and other costs related to the action. 12.4. THIS SECTION 12 IS SUBJECT TO SECTION 9 ABOVE AND STATES THE ENTIRE LIABILITY OF MENTOR GRAPHICS AND ITS LICENSORS FOR DEFENSE, SETTLEMENT AND DAMAGES, AND CUSTOMERS SOLE AND EXCLUSIVE REMEDY, WITH RESPECT TO ANY ALLEGED PATENT OR COPYRIGHT INFRINGEMENT OR TRADE SECRET MISAPPROPRIATION BY ANY PRODUCT PROVIDED UNDER THIS AGREEMENT. 13. TERMINATION AND EFFECT OF TERMINATION. If a Software license was provided for limited term use, such license will automatically terminate at the end of the authorized term. 13.1. Mentor Graphics may terminate this Agreement and/or any license granted under this Agreement immediately upon written notice if Customer: (a) exceeds the scope of the license or otherwise fails to comply with the licensing or confidentiality provisions of this Agreement, or (b) becomes insolvent, files a bankruptcy petition, institutes proceedings for liquidation or winding up or enters into an agreement to assign its assets for the benefit of creditors. For any other material breach of any provision of this Agreement, Mentor Graphics may terminate this Agreement and/or any license granted under this Agreement upon 30 days written notice if Customer fails to cure the breach within the 30 day notice period. Termination of this Agreement or any license granted hereunder will not affect Customers obligation to pay for Products shipped or licenses granted prior to the termination, which amounts shall be payable immediately upon the date of termination. 13.2. Upon termination of this Agreement, the rights and obligations of the parties shall cease except as expressly set forth in this Agreement. Upon termination, Customer shall ensure that all use of the affected Products ceases, and shall return hardware and either return to Mentor Graphics or destroy Software in Customers possession, including all copies and documentation, and certify in writing to Mentor Graphics within ten business days of the termination date that Customer no longer possesses any of the affected Products or copies of Software in any form. 14. EXPORT. The Products provided hereunder are subject to regulation by local laws and United States government agencies, which prohibit export or diversion of certain products and information about the products to certain countries and certain persons. Customer agrees that it will not export Products in any manner without first obtaining all necessary approval from appropriate local and United States government agencies. 15. U.S. GOVERNMENT LICENSE RIGHTS. Software was developed entirely at private expense. All Software is commercial computer software within the meaning of the applicable acquisition regulations. Accordingly, pursuant to US FAR 48 CFR 12.212 and DFAR 48 CFR 227.7202, use, duplication and disclosure of the Software by or for the U.S. Government or a U.S. Government subcontractor is subject solely to the terms and conditions set forth in this Agreement, except for provisions which are contrary to applicable mandatory federal laws. 16. THIRD PARTY BENEFICIARY. Mentor Graphics Corporation, Mentor Graphics (Ireland) Limited, Microsoft Corporation and other licensors may be third party beneficiaries of this Agreement with the right to enforce the obligations set forth herein. 17. REVIEW OF LICENSE USAGE. Customer will monitor the access to and use of Software. With prior written notice and during Customers normal business hours, Mentor Graphics may engage an internationally recognized accounting firm to review Customers software monitoring system and records deemed relevant by the internationally recognized accounting firm to confirm Customers compliance with the terms of this Agreement or U.S. or other local export laws. Such review may include FLEXlm or FLEXnet (or successor product) report log files that Customer shall capture and provide at Mentor Graphics request. Customer shall make records available in electronic format and shall fully cooperate with data gathering to support the license review. Mentor Graphics shall bear the expense of any such review unless a material non-compliance is revealed. Mentor Graphics shall treat as confidential information all information gained as a result of any request or review and shall only use or disclose such information as required by law or to enforce its rights under this Agreement. The provisions of this Section 17 shall survive the termination of this Agreement. 18. CONTROLLING LAW, JURISDICTION AND DISPUTE RESOLUTION. The owners of certain Mentor Graphics intellectual property licensed under this Agreement are located in Ireland and the United States. To promote consistency around the world, disputes shall be resolved as follows: excluding conflict of laws rules, this Agreement shall be governed by and construed under the laws of the State of Oregon, USA, if Customer is located in North or South America, and the laws of Ireland if Customer is located outside of North or South America. All disputes arising out of or in relation to this Agreement shall be submitted to the exclusive jurisdiction of the courts of Portland, Oregon when the laws of Oregon apply, or Dublin, Ireland when the laws of Ireland apply. Notwithstanding the foregoing, all disputes in Asia arising out of or in relation to this Agreement shall be resolved by arbitration in Singapore before a single arbitrator to be appointed by the chairman of the Singapore International
Arbitration Centre (SIAC) to be conducted in the English language, in accordance with the Arbitration Rules of the SIAC in effect at the time of the dispute, which rules are deemed to be incorporated by reference in this section. This section shall not restrict Mentor Graphics right to bring an action against Customer in the jurisdiction where Customers place of business is located. The United Nations Convention on Contracts for the International Sale of Goods does not apply to this Agreement. 19. SEVERABILITY. If any provision of this Agreement is held by a court of competent jurisdiction to be void, invalid, unenforceable or illegal, such provision shall be severed from this Agreement and the remaining provisions will remain in full force and effect. 20. MISCELLANEOUS. This Agreement contains the parties entire understanding relating to its subject matter and supersedes all prior or contemporaneous agreements, including but not limited to any purchase order terms and conditions. Some Software may contain code distributed under a third party license agreement that may provide additional rights to Customer. Please see the applicable Software documentation for details. This Agreement may only be modified in writing by authorized representatives of the parties. Waiver of terms or excuse of breach must be in writing and shall not constitute subsequent consent, waiver or excuse.
Rev. 100615, Part No. 246066

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Tessent DFTAdvisor Reference Manual

Software Version 9.0 June 2010

1991-2010 Mentor Graphics Corporation All rights reserved.

Tessent DFTAdvisor Reference Manual, V9.0 June 2010

Tessent DFTAdvisor Reference Manual, V9.0 June 2010

Tessent DFTAdvisor Reference Manual, V9.0 June 2010

End-User License Agreement

Tessent DFTAdvisor Reference Manual, V9.0 June 2010

Tessent DFTAdvisor Reference Manual, V9.0 June 2010

Tessent DFTAdvisor Reference Manual, V9.0 June 2010

Tessent DFTAdvisor Reference Manual, V9.0 June 2010

Inputs and Outputs

Tessent DFTAdvisor Reference Manual, V9.0 June 2010

Introduction Inputs and Outputs

File Redirection Operators

Tessent DFTAdvisor Reference Manual, V9.0 June 2010

Introduction Inputs and Outputs

Tessent DFTAdvisor Reference Manual, V9.0 June 2010

Introduction Inputs and Outputs

Tessent DFTAdvisor Reference Manual, V9.0 June 2010

Chapter 2 Command Dictionary

Command Line Syntax Conventions

Tessent DFTAdvisor Reference Manual, V9.0 June 2010

Command Dictionary Command Summary

Add Cell Models

Add Nonscan Models

Add Notest Points Add Output Masks

Add Pin Constraints

Tessent DFTAdvisor Reference Manual, V9.0 June 2010

Command Dictionary Command Summary

Add Scan Models

Add Scan Partition

Add Scan Pins

Add Seq_transparent Constraints Add Sub Chains

Add Subchain Clocks

Add Subchain Group

Tessent DFTAdvisor Reference Manual, V9.0 June 2010

Command Dictionary Command Summary

Add Tied Signals Add Write Controls Alias

Analyze Control Signals Analyze Input Control

Analyze Output Observe Analyze Testability

Delete Black Box Delete Buffer Insertion Delete Cell Models

Tessent DFTAdvisor Reference Manual, V9.0 June 2010

Command Dictionary Command Summary

Tessent DFTAdvisor Reference Manual, V9.0 June 2010

Command Dictionary Command Summary

Tessent DFTAdvisor Reference Manual, V9.0 June 2010

Command Dictionary Command Summary

Tessent DFTAdvisor Reference Manual, V9.0 June 2010

Command Dictionary Command Summary

Tessent DFTAdvisor Reference Manual, V9.0 June 2010

Command Dictionary Command Summary

Tessent DFTAdvisor Reference Manual, V9.0 June 2010

Command Dictionary Command Summary

Set Stability Check

Tessent DFTAdvisor Reference Manual, V9.0 June 2010

Command Dictionary Command Summary

Tessent DFTAdvisor Reference Manual, V9.0 June 2010

Command Dictionary Command Summary