Computer Architecture And Microprocessor

UNIT - IV
Introduction
Designing a counter is a frequent programming application. Counters are used primarily to keep track of events, while time delays are important in setting up reasonably accurate timing between two events. The process of designing counters and time delays using software instructions is far more flexible and less time consuming than the design process using hardware.

4.1 Objective
This lesson provides you the detailed study about counter, time delay. The content of the lesson starts with the counter and time delay. It gives you the detailed implementation of the counters and time delays with flow chart representation. It also provides knowledge about conversion , stack and subroutine.

4.2 Content
4.2.1 Counter
A counter is designed simply by loading an appropriate number into one of the registers and using the INR (Increment by One) or the DCR (Decrement by One) instructions. A loop is established to update the count, and each count is checked to determine whether it has reached the final number, if not, the loop is repeated. The flowchart shown in Figure 4.1 illustrates these steps. However, this counter has one major drawback; the counting is performed at such high speed that only the last count can be observed. To observe counting, there must be an appropriate time delay between counts.

Page 118

Computer Architecture And Microprocessor

Fig 4.1 Flowchart of a counter 4.2.2 Time Delay

The procedure used to design a specific delay is similar to that used to set up a counter. A register is loaded with a number, depending on the time delay required, and then the register is decremented until it reaches zero by setting up a loop with a conditional Jump instruction. The loop caused the delay, depending upon the clock period of the system, as illustrated in the next sections. Time Delay Using One Register The flowchart in Figure 4.2 shows a time-delay loop. A count is loaded in a register, and the loop is executed until the count reaches zero. The set of instructions necessary to set up the loop is also shown in Figure 4.2.

Page 119

Computer Architecture And Microprocessor

Fig 4.2 Time Delay Loop: Flowchart and Instructions The last column in the instructions shows the T-states (clock periods) required by the 8080A microprocessor to execute each instruction. For some instructions, the 8080A requires a different number of T-states than does the 8085. For example, the 8085 executes the instruction DCR in four T-states whereas the 8080A takes five T-states. The calculation shown here are based on the 8080A instructions. Figure 4.2 shows that instruction MVI requires seven clock periods. An 8080A based microcomputer with 2 MHz clock frequency will execute the instruction MVI in 3.5 s as follows: Clock frequency of the system f = 2 MHz Clock period T = 1/f x 10-6 = 0.5 s Time to execute MVI = 7 T-states x 0.5 = 3.5 s However, if the clock frequency of the system is 1 MHz, the microprocessor will require 7 s to execute the same instruction. To calculate the time delay in a loop, we must account for the T-states required for each instruction, and for the number of times the instructions are executed in the loop. In Figure 4.2, register C is loaded with the count FFH(25510) by the instruction MVI, which is executed once and takes seven T-states. The next two instructions, DCR and JNZ, form a loop with a total of fifteen (5 + 10) T-states. The loop is repeated 255 times until register C = 0. Page 120

Computer Architecture And Microprocessor

The time delay in the loop TL with 2 MHz clock frequency is calculated as TL = (T x Loop T-states x N10) Where TL = Time delay in the loop T = System clock period N10 = Equivalent decimal number of hexadecimal count loaded in the delay register = (0.5 x 10-6 x 15 x 255) = 1912.5 s = 1.9 ms In most applications, this approximate calculation of the time delay is considered reasonably accurate. However, to calculate the time delay more accurately, the time for the execution of the initial instruction MVI should be included in the total time delay T D as Delay TD = Time to Execute + Time to Execute Instructions Outside Loop Loop Instructions = TO + TL = (7 x 0.5 s) + 1912.5 s = 1916 s = 1.9 ms The difference between the two calculations is only 3.5 s and can be ignored in most instances. The time delay can be varied by changing the count number FF; however, to increase the time delay beyond 1.9 ms in 2 MHz microcomputer systems, you must use either additional instructions or a register pair. Time Delay Using a Register Pair The time delay can be considerably increased by setting a loop and using a register pair with a 16-bit number (maximum FFFH). The 16-bit number is decremented by using the instruction DCX. However, the instruction DCX does not set the Zero flag and, without the test flags, Jump instructions cannot be executed. Additional techniques, therefore, must be used to set the Zero flag. The following set of instructions uses a register pair to set up a time delay

Label

Opcode
LXI

Operand
B, 208FH B A, C B

Comments
;Load register pair BC with 16-bit count ;Decrement (BC) by one ;Load accumulator with contents of Register C ;OR (B) with (C) to set Zero flag

LOOP:

DCX MOV ORA

Page 121

Computer Architecture And Microprocessor

JNZ LOOP ;If result 0, jump back to LOOP

In this set of instructions, the instruction LXI B, 208FH loads register B with the number 20H, and register C with the number 8FH. The instruction DCX decrements the entire number by one (e.g., 208FH becomes 208EH). The next two instructions are used only to set the Zero flag; otherwise, they have no function in this problem. The OR instruction sets the Zero flag only when the contents of B and C are simultaneously zero. Therefore, the loop is repeated 208FH times, equal to the count set in the register pair. Time Delay The time delay in the loop is calculated as in the previous example. The loop includes four instructions: DCX, MOV, ORA, and JNZ, and takes 24 clock periods for execution. The loop is repeated 208FH times, which is converted to decimals as 208FH = 2 x (163) + 0 x (16)2 + 8 x (16)1 + 15(160) = 833510 If the clock period of the system = 0.5 s, the delay in the Loop TL TL = (0.5 x 24 x 833510) = 100 ms Total Delay TD = 100 ms + TO 100 ms (The instruction LXI adds only 5 s) A similar time delay can also be achieved by using the technique of two loops. For example, register C is used in the inner loop and register B is used in the outer loop (Figure 4.3). Furthermore, the time delay within a loop can be increased by using instructions that will not affect the program except to increase the delay. For example, the instruction NOP (No Operation) can add four T-states in the delay loop. The desired time delay can be obtained by using any or all available registers. The procedure for calculating time delays in an 8085 system is the same as explained for the 8085A except that appropriate T-states should be used in the delay calculations. However, the execution of a conditional Jump instruction adds a few complications to the calculations. The 8085 requires ten T-states to execute a conditional

Page 122

Computer Architecture And Microprocessor

Fig 4.3 Flowchart for Time Delay with Two Loops Jump instruction when it changes the sequence of the program, and seven T-states when the program continues in the same sequence. For example, the JNZ instruction in the last loop of Figure 4.2 is executed in seven T-states. This means the number of T-states in the loop will be reduced by three T-states, which can be easily ignored. Page 123

Computer Architecture And Microprocessor

Additional Techniques for Time Delay The disadvantages in using software delay techniques for real-time applications in which the demand for time accuracy is high, such as digital clocks, are as follows: 1. The accuracy of the time delay depends on the accuracy of the systems clock. 2. The microprocessor is occupied simply in a waiting loop; otherwise it could be employed to perform other functions. 3. The task of calculating accurate time delays is tedious. The real-time applications, timers (integrated timer circuits) are commonly used. The Inter 8253 (described in Chapter 15) is a programmable timer chip that can be interfaced with the microprocessor and programmed to provide timings with considerable accuracy. The disadvantages of using the hardware chip include the additional expense and the need for an extra chip in the system. 4.2.3 Counter Design with Time Delay

The design a counter with a time delay, the techniques illustrated in Figures 4.1 and 4.2 can be combined. The combined flowchart is shown in Figure 4.4. The blocks shown in the flowchart are similar to those in the generalized flowchart. The block numbers shown in Figure 4.4 correspond to the block numbers in the generalized flowchart. Note the following points about the counter flowchart (Figure 4.4): 1. The output (or display) block is a part of the counting loop. 2. The data processing block is replaced by the time-delay block. 3. The save-the-partial-answer block is eliminated because the count is saved in a counter register, and a register can be incremented or decremented without transferring the count to the accumulator. The flowchart in Figure 4.4 shows the basic building blocks. However, the sequence can be changed, depending upon the nature of the problem, as shown in Figure 4.5 a and b. The flowchart in Figure 4.4 displays the count after initialization. For example, an upcounter starting at zero can be initialized as 00H using the logic shown in Figure 4.4. However, the flowchart in Figure 4.5 (a) updates the counter immediately after initialization. In this case, an up-counter should be initialized at FFH in order to display the count 00H.

Page 124

Computer Architecture And Microprocessor

Fig 4.4 Flowchart of a counter with a Time Delay Similarly, the decision-making block differs slightly in these flowcharts. For example, if a counter was counting up to 9, the question in Figure 4.4 would be: Is the count 10? In Figure 4.5(a) the question would be: Is the count 9? The flowchart in Figure 4.5(b) illustrates another way of designing a counter. ILLUSTRATIVE PROGRAM: HEXADECIMAL COUNTER PROBLEM STATEMENT Write a program to count continuously in hexadecimal from FFH to 00H in a system with a 0.5 s clock period. Use register C to set up a one millisecond (ms) delay between each count and display the numbers at one of the output ports.

Page 125

Computer Architecture And Microprocessor

PROBLEM ANALYSIS The problem has two parts; the first is to set up a continuous down-counter, and the second is to design a given delay between two counts.

Fig 4.5 Variations of Counter Flowchart Page 126

Computer Architecture And Microprocessor

1. The hexadecimal counter is set up by loading a register with an appropriate starting number and decrementing it until it becomes zero (shown by the outer loop in the flowchart, Figure 4.6). After the zero count, the register goes back to FF because decrementing zero results in a (-1), which is FF in 2s complement. 2. The one millisecond (ms) delay between each count is set up by using the procedure explained previously in Time Delay Using One Register. Figure 4.2 is identical with the inner loop of the flowchart shown in Figure 4.6. The delay calculations are shown later.

Fig 4.6 Program and Flowchart for a Hexadecimal Counter

Page 127

Computer Architecture And Microprocessor

FLOWCHART AND PROGRAM The flowchart in Figure 4.6 shows the two loops discussed earlier one for the counter and another for the delay. The counter is initialized in the first block, and the counter is displayed in the outer loop. The delay is accomplished in the inner loop. This flowchart in Figure 4.6 is similar to that in Figure 4.5 (a). You should study the flowchart carefully to differentiate between the counter loop and the delay loop because they may at first appear to be similar. Delay Calculations. The delay loop includes two instructions: DCR C and JNZ with 15 T-states. Therefore, the time delay TL in the loop: TL = 15 T-states x T (Clock period) x Count = 15 x (0.5 x 10-6) x Count = (7.5 x 10-6) x Count The delay outside the loop includes the following instructions: DCR B 5T Delay Outside = 40 T-states x T MVI C, COUNT 10T the loop: To MOV A, B 5T = 40 x (0.5 x 10-6) OUT PORT 10T = 20 s JMP 10T ___________________ 40 T-states Total Time Delay TD = TO + TL 1 ms = 20 x 10-6 + (7.5 x 10-6) x Count Count = 1 x 10-3 20 x 10-6 7.5 x 10-6 Therefore, the delay count 82H (13010) must be loaded in register C to obtain 1 ms delay between each count. PROGRAM DESCRIPTION Register B is used as a counter, and register C is used for delay. Register B initially starts with number 00h; when it is decremented by the instruction DCR, the number becomes FFH. (Verify this by subtracting one from zero in 2s complement). Register C is loaded with the delay count 80H to provide a 1 ms delay in the loop. The instruction DCR C decrements the count and the instruction JNZ (Jump On No Zero) checks the Zero flag to see if the number in register C has reached zero. If the number is not zero, instruction = 13010

Page 128

Computer Architecture And Microprocessor

JNZ causes a jump back to the instruction labeled DELAY in order to decrement and, thus, the loop is repeated 12810 times. The count is displayed by moving (B) to the accumulator, and then to the output port. The instruction JMP causes an unconditional jump for the next count in register B, forming a continuous loop to count from FFH to 00H. After the count reaches zero, (B) is decremented, becoming FFH, and the counting cycle is repeated. PROGRAM OUTPUT When the program is executed, the actual output seen my vary according to the device used as the output for the display. The eye cannot see the changes in a count with a 1 ms delay. If the output port has eight LEDs, the LEDs representing the low-order bits will appear to be on continuously, and the LEDs with high-order bits will go on and off according to the count. If the output port is a seven-segment display, all segments will appear to be on; a slight flicker in the display can be noticed. However, the count and the delay can be measured on an oscilloscope. 4.2.4 Stack

The stack in an 8085/8080A microcomputer system can be described as a set of memory locations in the R/W memory, specified by a programmer in a main program. These memory locations are used to store binary information (bytes) temporarily during the execution of a program. The beginning of the stack is defined in the program by using the instruction LXI SP, which loads a 16-bit memory address in the stack pointer register of the microprocessor. Once the stack location is defined, storing of data bytes begins at the memory address that is one less than the address in the stack pointer register. For example, if the stack pointer register is loaded with the memory address 2099H (LXI SP, 2099H), the storing of data bytes begins at 2098H and continues in reversed numerical order (decreasing memory addresses such as 2098H, 2097H, etc). Therefore, as a general practice, the stack is initialized at the highest available memory location to prevent the program from being destroyed by the stack information. The size of the stack is limited only by the available memory. Data bytes in the register pairs of the microprocessor can be stored on the stack (two at a time) in reverse order (decreasing memory address) by using the instruction PUSH. Data bytes can be transferred from the stack to respective registers by using the instruction POP. The stack pointer register tracks the storage the retrieval of the information. Two data bytes are being stored at a time, the 16-bit memory address in the stack pointer register is decremented by two; when data bytes are retrieved, the address is incremented by two. An address in the stack pointer register indicates that the next two memory location (in descending numerical order) can be used for storage. The stack is hared by the programmer and the microprocessor. The programmer can store and retrieve the contents of a register pair by using PUSH and POP instructions. Page 129

Computer Architecture And Microprocessor

Similarly, the microprocessor automatically stores the contents of the program counter when a subroutine is called. The instructions necessary for using the stack are explained below. INSTRUCTIONS Opcode LXI PUSH PUSH PUSH PUSH PUSH Operand SP, 16-bit Rp B D H PSW Load the stack pointer register with a 16 bit address. This is a 1-byte instruction It copies the contents of the specified register pair on the stack as described below The stack pointer register is decremented, and the contents of the high-order register (e.g., register B) are copied in the location shown by the stack pointer register The stack pointer register is again decremented, and the contents of the low-order register (e.g., register C) are copied in that location The operands B, D, and H represent register pairs BC, DE, HL, respectively. The operand PSW represents Program Status Word, meaning the contents of the accumulator and the flags This is a 1-byte instruction It copies the contents of the top two memory locations of the stack into the specified register pair First, the contents of the memory location indicated by the stack pointer register are copied into the low-order register (e.g., register L), and then the stack pointer register is incremented by 1 The contents of the next memory location are copied into the high-order register (e.g., register H), and the stack pointer register is again incremented by 1.

POP POP POP POP POP

Rp B D H PSW

All three of these instructions belong to the data transfer (copy) group; thus, the contents of the source are not modified, and no flags are affected. Example : In the following set of instructions ( illustrated in Figure 4.7 ), the stack pointer is initialized, and the contents of register pair HL are stored on the stack by using the PUSH instruction. Register pair HL is used for delay counter ( actual instructions are not shown); and at the end of delay counter, the contents of HL are retrieved by using the instruction POP. Assuming the available user memory ranges from 2000H to 20FFH, show the contents of various registers when PUSH and POP instructions are executed. Solution. In this example, the first instruction LXI SP, 2099H loads the stack pointer register with the address 2099H (Figure 4.7.) This instruction indicates to the microprocessor that memory space is reserved in the R/W memory as the stack, and that Page 130

Computer Architecture And Microprocessor

the locations beginning at 2098H and moving upward can be used for temporary storage. This instruction also suggests that the stack can be initialized anywhere in the memory; however, the stack location should not interfere with a program. The next instruction LXI H loads data in the HL register pair, as shown in Figure 4.7.

Fig 4.7 Instructions and Register Contents in the above example. When instruction PUSH H is executed, the following sequence of data transfer takes place. After the execution, the contents of the stack and the register are as shown in Figure 4.8.

Fig 4.8 Contents on the Stack and in the Registers After the PUSH Instruction 1. The stack pointer register is decremented by one to 2098H, and the contents of the H register are transferred to memory location 2098H. 2. The stack pointer register is again decremented by one to 2097H, and the contents of the L register are transferred to memory location 2097H. 3. The contents of the register pair HL are not destroyed; however, HL is made available for the delay counter. Page 131

Computer Architecture And Microprocessor

After the delay counter, the instruction POP H restores the original contents of the register pair HL, as follows. Figure 4.9 illustrates the contents of the stack and the registers following the POP instruction.

Fig 4.9 Contents on the Stack and in the Registers After the POP Instruction. 1. The contents of the top of the stack location shown by the stack pointer are transferred to the L register, and the stack pointer register is incremented by one to 2098H. 2. The contents of the top of the stack (now it is 2098H) are transferred to the H register, and the stack pointer is incremented by one. 3. The contents of memory locations 2097h and 2098H are not destroyed until some other data bytes are stored in these locations.

Fig 4.10 Instructions and Register Content in Example.

Page 132

Computer Architecture And Microprocessor

The available user memory ranges from 2000H to 23FFH. A program of data transfer and arithmetic operations is stored in memory locations from 2000H to 2050H, and the stack pointer is initialized at location 2400H. Two sets of data are stored, starting at locations 2150H and 2280H. Registers HL and BC are used as memory pointers to the data locations. A segment of the program is shown in Figure 4.10.

Fig 4.11 Stack Contents After the Execution of PUSH Instructions. 1. Explain how the stack pointer can be initialized at one memory location beyond the available user memory. 2. Illustrate the contents of the stack memory and registers when PUSH and POP instructions are executed, and explain how memory pointers are exchanged. 3. Explain the various contents of the user memory. Solution. 1. The program initializes the stack pointer register at location 2400H, one location beyond the user memory (Figure 4.10). This procedure is valid because the initialized location is never used for storing information. The instruction PUSH first decrements the stack pointer register, and then stores a data byte 2. Figure 4.11 shows the contents of the stack pointer register and the contents of the stack locations after the three PUSH instructions are executed. After the execution of the PUSH (H, B, and PSW) instructions, the stack pointer moves upward (decreasing memory locations) as the information is stored. Thus the stack can grow upward in the user memory, even to the extent of destroying the program. Figure 4.12 shows how the contents of various register pairs are retrieved. To restore the original contents in the respective registers, follow the sequence Last-In-First-Out (LIFO0. In the example, the register contents were pushed on the stack in the order of Page 133

Computer Architecture And Microprocessor

HL, BC, and PSW. The contents should have been restored in the order of PSW, BC, and HL. However, the order is altered in this example to demonstrate how register contents are exchanged.

Fig 4.12 Register Content after the Execution of POP Instruction The instruction POP PSW transfers the contents of the two top locations to the flag register and the accumulator, respectively, and increments the stack pointer by two to 23FCH. The next instruction, POP H, takes the contents of the top two locations (23FC and 23FD), transfers them to registers L and H, respectively, while incrementing the stack pointer by two, to 23FEH. The instruction POP B transfers the contents of the next two locations to registers C and B, incrementing the stack pointer to 2400H.

Fig 4.13 R / W Memory Contents

Page 134

Computer Architecture And Microprocessor

By reversing the positions of two instructions, POP H and POP B, the contents of the BC pair are exchanged with those of the HL pair. It is important to remember that the instruction POP H does not restore the original contents of the HL pair; instead it transfers the contents of the top two locations shown by the stack pointer to the HL pair. 3. Figure 4.13 shows the sketch of the memory map. The R/W memory includes three types of information. The user program is stored from 2000H to 2050H. The data are stored, starting at locations 2150H and 2280H. The last section of the user memory is initialized as the stack where register contents are stored as necessary, using the PUSH instructions. In this example, the memory locations from 23FFH to 23FAH are used as the stack, which can be extended up to the locations of the second data set. Important Concepts The following points can be summarized from the preceding examples: 1. Memory locations in R/W memory can be employed as temporary storage for information by initializing (loading) a 16-bit address in the stack pointer register. 2. Read/Write memory generally is used for three different purposes. a. to write programs or some temporary instruction. b. To store data; c. To store information temporarily in defined memory locations called the stack during the execution of the program. 3. The stack space grows upward in the numerically decreasing order of memory addresses. 4. The stack can be initialized anywhere in the user memory map. However, as a general practice, the stack is initialized as the higher user memory location so that it will be less likely to interfere with a program. 5. A programmer can employ the stack to store the contents of register pairs by using the instruction PUSH and can restore the contents of register pairs by using the instruction POP. The address in the stack pointer register always points to the top of the stack, and the address is decremented or incremented as information is stored or retrieved. The storage and retrieval of data types on the stacks should follow the LIFO (Last-InFirst-Out) sequence. Information in stack locations is not destroyed until new information is stored in those locations. Illustrative Program: Resetting and Displaying Flags PROBLEM STATEMENT Write a program to perform the following functions: 1. Clear all the flags. 2. Load 00H in the accumulator, and demonstrate that the Zero flag is not affected by the data transfer instruction. Page 135

Computer Architecture And Microprocessor

3. Logically OR the accumulator with itself to set the Zero flag, and display the flag at PORT1 or store all the flags on the stack. PROBLEM ANALYSIS The problem concerns examining the Zero flag after instructions have been executed. There is no direct way of observing the flags; however, they can be stored on the stack by using the instruction PUSH PSW. The contents of the flag register can be retrieved in any one of the registers by using the instruction POP, and the flags can be displayed at an output port. In this example, the result to be displayed is different from the result to be stored on the stack memory. To display only the Zero flag, all other flags should be masked; however, the masking is not necessary in order to store all the flags. PROGRAM Memory Address XX00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0EE 0F 10 11 12 13 14 15 16 Machine Code 31 99 XX 2E 00 E5 F1 3E 00 F5 E1 7D D3 PORT0 B7 F5 E1 7D E6 40 D3 PORT1 76 Instructions LXI SP, XX99H MVI L, 00H PUSH H POP PSW MVI A, 00H PUSH PSW POP H MOV A, L OUT PORT0 ORA A PUSH PSW POP H MOV A, L ANI 40H OUT PORT1 HLT ;End of program Comments ;Initialize the stack ;Clear flag contents in L ;Place (L) on stack ;Clear flags ;Save flags on stack ;Retrieve flags in L ;Display flags ;Set flags and reset CY, AC ;Save flags on stack ;Retrieve flags in L ;Mask all flags except Z

Page 136

Computer Architecture And Microprocessor

_______________________________________________________________________ _ Storing in Memory: Alternative to Output Display _______________________________________________________________________ XX0C 0D 0E B7 F5 76 ORA A PUSH PSW HLT ;Set flags and reset CY and AC ;Save flags on stack ;End of program

Program Description. The stack pointer register is initialized at XX99H. The instruction MVI L clears (L), and (L) is placed on the stack, which is subsequently placed into the flag register to clear all the flags. To verify the flags after the execution of the MVI A instruction, the PUSH and POP instructions are used in the same way as these instructions were used to clear the flags, and the flags are displayed at PORT10. Similarly, the Zero flag is displayed at PORT1 after the instruction ORA. Program Output. Data transfer (copy) instructions do not affect the flags; therefore, no flags should be set after the instruction MVI A, even if (A) is equal to zero. PORT0 should display 00H. However, the instruction ORA will set the Zero and the Parity flags to reflect the data conditions in the accumulator, and it also reset the CY and AC flags. In the flag register, bit D6 represents the Z flag, and the ANI instruction masks all flags except the Z flag. PORT1 should display 40H as shown below. D7 0 S D6 1 Z D5 0 D4 0 AC D3 0 D2 1 P D1 0 D0 0 CY = 40H

Storing Output in Memory. If output ports are not available, the results can be stored in the stack memory. The machine code (F5) at memory location XX0BH saves the flags affected by the instruction MVI A, 00H. Then the instructions can be modified starting from memory location XXOCH. The alternative set of instructions is shown above; it sets the flags (using ORA instruction), and saves them on the stack without masking. The result (44H) includes the parity flag. The contents of the stack locations should be as shown in Figure 4.14.

Page 137

Computer Architecture And Microprocessor

Fig 4.14 Output Stored in Stack Memory 4.2.5 Subroutine A subroutine is a group of instructions written separately from the main program to perform a function that occurs repeatedly in the main program. For example, if a time delay is required between three successive events, three delays can be written in the main program. To avoid repetition of the same delay instructions, the subroutine technique is used. Delay instructions are written once, separately from the main program, and are called by the main program when needed. The 8085/8080A microprocessor has two instructions to implement subroutines: CALL (call a subroutine), and RET (return to main program from a subroutine). The CALL instruction is used in the main program to call a subroutine, and the RET instruction is used at the end of the subroutine to return to the main program. When a subroutine is called, the contents of the program counter, which is the address of the instruction following the CALL instruction, is stored on the stack and the program execution is transferred to the subroutine address. When the RET instruction is executed at the end of the subroutine, the memory address stored on the stack is retrieved, and the sequence of execution is resumed in the main program. This sequence of events is illustrated in Example further below. INSTRUCTIONS Opcode CALL Operand 16-Bit Memory Address of a Subroutine Call Subroutine Unconditionally This is 3-byte instruction that transfers the program sequence to a subroutine address. Saves the contents of the program counter (the address of the next instruction) on the stack. Decrements the stack pointer register by two. Jumps unconditionally to the memory location Specified by the second and third bytes. The Second byte specifies a line number and the third Byte specifies a page number. This instruction is accompanied by a return instruction in the subroutine. Return from Subroutine Unconditionally This is a 1-byte instruction. Inserts the two bytes from the top of the stack Into the program counter and increments the stack Pointer register by two. Unconditionally returns from a subroutine.

RET

The conditional Call and Return instructions will be described later in the chapter.

Page 138

Computer Architecture And Microprocessor

Example. Illustrate the exchange of information between the stack and the program counter for the following program if the available user memory ranges from 2000H to 23FFH. Memory Address 2000 2040 2041 2042 2043 205F 2070 207H 2080 2398 23FF 2400 Solution. LXI SP, 2400H CALL 2070H NEXT INSTRUCTION HLT First Subroutine Instruction RET Other subroutines Empty space ; The stack is initialized at 2400H After reviewing the above program note the following points: ; Initialize the stack pointer at 2400H ; Call the subroutine located at 2070H. This is a 3-byte instruction ; The address of the next instruction following the CALL instruction. ; End of the main program ; Beginning of the subroutine ; End of the subroutine

1. The available user memory is from 2000H to 23FFH (1024 or 1K bytes); however, the stack pointer register is initialized at 2400H, one location beyond the user memory. This allows maximum use of the memory because the actual stack begins at 23FFH. The stack can expand up to the location 2398H without overlapping with the program. 2. The main program is stored at memory locations from 2000H to 205FH. 3. The CALL instruction is located at 2040H to 2042H (3-byte instruction). The next instruction is at 2043H. 4. The subroutine begins at the address 2070H and ends at 207FH. PROGRAM EXECUTION The sequence of the program execution and the events in the execution of the CALL and subroutine are shown in Figure 4.15 and 4.16. CALL EXECUTION

Page 139

Computer Architecture And Microprocessor

Memory Address 2040 2041 2042 2043 Machine Code CD 70 20 NEXT Mnemonics CALL 2070H INSTRUCTION Comments ; Call subroutine located at the memory location 2070H

The sequence of events in the execution of the CALL instruction by the 8085 is shown in Figure 8.10. The instruction requires five machine cycles and eighteen T-states (seventeen T-states for the 8080A).

Fig 4.15 Subroutine Call and Program Transfer

Fig 4.16 Data Transfer During the Execution of the CALL instruction Page 140

Computer Architecture And Microprocessor

The sequence of events in each machine cycle is as follows. M1 Opcode Fetch: In this machine cycle, the contents of the program counter (2040H) are placed on the address bus, and the instruction code CD is fetched using the data bus. At the same time, the program counter is upgraded to the next memory address, 2041H. After the instruction is decoded and executed, the stack pointer register is decremented by one to 23FFH. 2. M2 and M3 - Memory Read: These are two Memory Read cycles during which the 16-bit address (2070H) of the CALL instruction is fetched. The low-order address 70H is fetched first and placed in the internal register Z. The high-order address 20H is fetched next, and placed in register W. During M3, the program counter is upgraded to 2043H, pointing to the next instruction. 3. M4 and M5 Storing of Program Counter: At the beginning of the M4 cycle, the normal operation of placing the contents of the program counter on the address bus is suspended, instead the contents of the stack pointer register 23FFH are placed on the address bus. The high-order byte of the program counter (PCH = 20H) is placed on the data bus and stored in the stack location 23FFH. At the same time, the stack pointer register is decremented to 23FEH. During machine cycle M5, the contents of the stack pointer 23FEH are placed on the address bus. The low-order byte of the program counter (PCL = 43H) is placed on the data bus and stored in stack location 23FEH. 4. Next Instruction Cycle: In the next instruction cycle, the program execution sequence is transferred to the CALL location 2070H by placing the contents of W and Z registers (2070H) on the address bus. During M 1 of the next instruction cycle, the program counter is upgraded to location 2071 (W, Z + 1).
1.

In summary: After the CALL instruction is fetched, the 16-bit address (the operand) is read during M2 and M3 and stored temporarily in W/Z registers. (Examine the contents of the address bus and the data bus in Figure 4.16). In the next two cycles, the contents of the program counter are stored on the stack. This is the address where the microprocessor will continue the execution of the program after the completion of the subroutine. Figure 4.17 shows the contents of the program counter, the stack pointer register, and the stack during the execution of the CALL instruction.

Fig 4.17 Contents of the Program Counter, the Stack Pointer, and the Stack During the Execution of CALL Instruction. Page 141

Computer Architecture And Microprocessor

RET EXECUTION At the end of the subroutine, when the instruction RET is executed, the program execution sequence is transferred to the memory location 2043H. (The address 2043H was stored in the top two location of the stack (23FEH and 23FFH) during the CALL instruction. Figure 4.18 shows the sequence of events that occurs as the instruction RET is executed.

Fig 4.18 Data Transfer During the Execution of the RET Instruction M1 is a normal Opcode Fetch cycle. However, during M2 the contents of the stack pointer register are placed on the address bus, rather than those of the program counter. Data byte 43H from the top of the stack is fetched and stored in the Z register, and the stack pointer register is upgraded to the next location, 23FFH. During M 2, the next byte 20H is copied from the stack and stored in register W, and the stack pointer register is again upgraded to the next location, 2400H. The program sequence is transferred to location 2043H by placing the contents of the W/Z registers on the address bus at the beginning of the next instruction cycle. Illustrative Program: Traffic Signal Controller PROBLEM STATEMENT Write a program to provide given on/off timer to three traffic lights (Green, Yellow, and Red) and two pedestrian signs (WALK and DONT WALK). The signal lights and signs are turned on/off by the data bits of an output port as shown below:

Page 142

Computer Architecture And Microprocessor

Lights 1. Green 2. Yellow 3. Red 4. WALK 5. DONT WALK Data Bits D0 D2 D4 D6 D7 On Time 15 seconds 5 seconds 20 seconds 15 seconds 25 seconds

The traffic and pedestrian flow are in the same direction; the pedestrian should cross the road when the Green light is on. PROBLEM ANALYSIS The problem is primarily concerned with providing various time delays for a complete sequence of 40 seconds. The on/off times for the traffic signals and pedestrian signs are as follows: Time Sequence in Seconds Code 0 (15) 15 (5) 20 (20) 40 Sending data byte 41H to the output port can turn on the Green light and the WALK sign. Using a 1-second subroutine and a counter with a count of 1510 can provide the 15second delay. Similarly, the next two bytes, 84H and 90H, will turn on/off the appropriate lights/signs as shown in the flowchart (Figure 4.19). Changing the values of the count in the counter provides the necessary time delays. PROGRAM Memory Address XX00 01 02 03 04 05 06 07 08 1 0 0 1 0 0 0 0 = 90H 1 0 0 0 0 1 0 0 = 84H 0 1 0 0 0 0 0 1 = 41H DONT WALK D7 D6 WALK D5 D4 Red D3 D2 Yellow D1 D0 Hex Green

Code 31 99 XX 3E 41 D3 PORT# 06 0F

Mnemonics LXI SP, XX99

Comments

;Initialize stack pointer at location XX99H ;High-order address of user memory START: MVI A, 41H ;Load accumulator with the pattern for Green light and WALK sign OUT PORT# ;Turn on Green light and WALK sign MVI B, 0FH ;Use B as a counter to count 15 seconds. B is decremented Page 143

Computer Architecture And Microprocessor

in the subroutine

Fig 4.19 Flowchart for Traffic Signal Controller 09 0A 0B 0C 0D 0E CD 50 XX 3E 84 D3 CALL DELAY ;Call delay subroutine located at XX50H ;High-order address of user memory ;Load accumulator with the bit pattern for Yellow light and DONT WALK ;Turn on Yellow light and DONT

OUT PORT# Page 144

Computer Architecture And Microprocessor

0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 PORT# 06 05 CD 50 XX 3E 90 D3 PORT# 06 14 CD 50 XX C3 03 XX MVI B, 05 CALL DELAY MVI A, 90H OUT PORT# MVI B, 14H CALL DELAY JMP START ;Go back to location START to repeat the sequence ;High-order address of user memory ;Load accumulator with the bit pattern for Red light and DONT WALK ;Turn on Red light, keep DONT WALK on, and turn off Yellow light ;Set up the counter for 20-second delay WALK and turn off Green light and WALK ;Set up 5-second delay counter

DELAY: This is a1-second delay subroutine and provides delay according to the parameter specified in register B ;Input: Number of seconds is specified in register B ;Output: None ;Registers Modified: Register B XX50 D5 DELAY: PUSH D ;Save contents of DE and accumulator 51 F5 PUSH PSW 52 11 SECOND: LXI D, Count ;Load register pair DE with data byte for 1-second delay 53 LO 54 HI 55 1B Loop: DCX D ;Decrement register pair DE 56 7A MOV A,D 57 B3 ORA E ;OR (D) and (E) to set Zero flag 58 C2 JNZ LOOP ;Jump to Loop if delay count is not equal to 0 59 55 5A XX 5B 05 DCR B ;End of 1 second delay; decrement the counter 5C C2 JNZ SECOND ;Is this the end of time needed? If not, go back to repeat 1-second delay Page 145

Computer Architecture And Microprocessor

5D 5E 5F 60 61 52 XX F1 D1 C9 POP PSW POP D RET ;High-order memory address of user memory ;Retrieve contents of saved registers ;Return to main program

Fig 4.20 Multiple Calling for a Subroutine PROGRAM DESCRIPTION Page 146

Computer Architecture And Microprocessor

The stack pointer register is initialized at XX99H so that return addresses can be stored on the stack whenever a CALL instruction is used. As shown in the flowchart this program loads the appropriate bit pattern in the accumulator, sends it to the output port, and calls the delay routine. Register B is loaded in the main program and used in the subroutine to provide appropriate timing. The DELAY subroutine is similar to the delays discussed in Chapter 7 except it requires the instruction RET at the end of the routine. This example illustrates the type of subroutine that is called many times from various locations in the main program, as illustrated in Figure 8.14. In this program, the subroutine is called from the locations XX09, 0A, and 0BH. The return address, XX0C, is stored on the stack, and the stack pointer is decremented by two to location XX97H. At the end of the subroutine, the contents of the top two locations of the stack (XXOC) are retrieved, the stack pointer register is incremented by two to the original location (XX99H), and the main program is resumed. This sequence is repeated two more times in the main program, as shown in Figure 4.20. 4.2.6 BCD TO BINARY CONVERSION

In most microprocessor-based products, data are entered and displayed in decimal numbers. For example, in an instrumentation laboratory, readings such as voltage and current are maintained in decimal numbers, and data are entered through a decimal keyboard. The system-monitor program of the instrument converts each key into an equivalent 4-bit binary number, and stores two BCD numbers in an 8-bit register or a memory location. These numbers are called packed BCD. Even if data are entered in decimal digits, it is inefficient to process data in BCD numbers because, in each 4-bit combination, digits A through F go unused. Therefore, BCD numbers are generally converted into binary numbers for data processing. The conversion of a BCD number into its binary equivalent employs the principle of positional weighting in a given number. For example: 7210 = 7 x 10 + 2 The digit 7 represents 70, based on its second position from the right. Therefore, converting 72BCD into its binary equivalent requires multiplying the second digit by 10, and adding the first digit. Converting a 2-digit BCD number into its binary equivalent requires the following steps: Separate an 8-bit packed BCD number into two 4-bit unpacked BCD digits: BCD1 and BCD2. 2. Convert each digit into its binary value according to its position. 3. Add both binary numbers to obtain the binary equivalent of the BCD number.
1.

Page 147

Computer Architecture And Microprocessor

Example. Convert (72)BCD into its binary equivalent Solution. 7210 = 0111 0010BCD

Step 1: 0111 0010

0000 0010 Unpacked BCD1 0000 0111 Unpacked BCD2 Step 2: Multiply BCD2 by 10 (7 x 10) Step 3: Add BCD1 to the answer in Step 2. The multiplication of BCD2 by 10 can be performed by various methods. One method is multiplication with repeated addition: add 10 seven times. This technique is illustrated in the next program. Illustrative Program: 2-Digit BCD to Binary Conversion PROBLEM STATEMENT A BCD number between 0 and 99 is stored in a R/W memory location called the Input Buffer. Write a main program and a conversion subroutine (BCDBIN) to convert the BCD number into its equivalent binary number. Store the result in a memory location defined as the Output Buffer. PROGRAM START: LXI SP, STACK LXI H, INBUF LXI B, OUTBUF MOV A, M CALL BCDBIN STAX B HLT BCDBIN: ;Initialize stack pointer ;Point HL index to the Input Buffer memory Location where BCD number is stored ;Point BC index to the Output Buffer memory Where binary number will be stored ;Get BCD number ;Call BCD to binary conversion routine ;Store binary number in the Output Buffer ;End of program

Function: This subroutine converts a BCD number into its binary Equivalent ;Input: A 2-digit packed BCD number in the accumulator ;Output: A binary number in the accumulator ;No other register contents are destroyed PUSH B PUSH D MOV B, A ANI 0FH MOV C, A MOV A, B ;Save BC registers ;Save DE registers ;Save BCD number ;Mask most significant four bits ;Save unpacked BCD1 in C ;Get BCD again Page 148

Computer Architecture And Microprocessor

ANI F0H RRC RRC RRC RRC MOV D, A XRA A MVI E, 0AH ADD E DCR D JNZ SUM ADD C POP D POP B RET ;Mask least significant four bits ;Convert most significant four ;bits into unpacked BCD2 ;Save BCD2 in D ;Clear accumulator ;Set E as multiplier of 10 ;Add 10 until (D) = 0 ;Reduce BCD2 by one ;Is multiplication complete? ;If not, go back and add again. ;Add BCD1 ;Retrieve previous contents

Sum:

PROGRAM DESCRIPTION 1. In writing assembly language programs, the use of labels is a common practice. Rather than writing a specific memory location or a port number, a programmer uses such labels as INBUF (Input Buffer) and OUTBUF (Output Buffer). Using labels gives flexibility and ease of documentation. 2. The main program initializes the stack pointer and two memory indexes. It brings the BCD number into the accumulator and passes that parameter to the subroutine. 3. After returning from the subroutine, the main program stores the binary equivalent in the Output Buffer memory. 4. The subroutine saves the contents of the BC and DE registers because these registers are used in the subroutine. Even if this particular main program does not use the DE registers, some other program in which the DE registers are being used may call the subroutine. Therefore, it is a good practice to save the registers that are used in the subroutine, unless parameters are passed to the subroutine. The accumulator contents are not saved because that information is passed on to the subroutine. 5. The conversion from BCD to binary is illustrated in the subroutine with the example of 72BCD converted to binary. The illustrated multiplication routine is easy to understand; however, it is rather long and inefficient. PROGRAM EXECUTION To execute the program on a single-board computer, complete the following steps: 1. Assign memory addresses to the instructions in the main program and in the subroutine.

Page 149

Computer Architecture And Microprocessor

2. Define STACK: the stack location with a 16-bit address in the R/W memory (such as 2099H). 3. Define INBUF (Input Buffer) and OUTBUF (Output Buffer): two memory locations in the R/W memory (e.g., 2050H and 2060H). 4. Enter a BCD byte in the Input Buffer (e.g., 2050H). 5. Enter and execute the program Check the contents of the Output Buffer memory location (2060H). 4.2.7 BINARY TO BCD CONVERSION

In most microprocessor-based products, numbers are displayed in decimal. However, if data processing inside the microprocessor is performed in binary, it is necessary to convert the binary results into their equivalent BCD numbers just before they are displayed. Results are quite often stored in R/W memory locations called the Output Buffer. Dividing the number by the powers of ten performs the conversion of binary to BCD; the division is performed by the subtraction method. 1 1 1 1 1 1 1 12 (FFH) = 25510

To represent this number in BCD requires twelve bits or three BCD digits, labeled here as BCD3 (MSB), BCD2, and BCD1(LSB), =0 0 1 BCD3 0 0 1 0 BCD2 1 0 1 0 BCD1 1

The conversion can be performed as follows: Step 1: If the number is less than 100, go to Step 2: Otherwise, divide by 100 or subtract 100 Repeatedly until the remainder is less than 100. The quotient is the most significant BCD digit BCD3. Step 2: If the number is less than 10, go to Step 3; Otherwise divide by 10 repeatedly until the Remainder is less than 10. The quotient is BCD2.

Example 255 -100 = -100 = BCD3 55 -10 = -10 = -10 = -10 = -10 = BCD2 BCD1

Quotient 155 5 = 45 35 25 15 05 = = 1 1 2 1 1 1 1 1 5 5

Step 3: The remainder from step 2 is BCD1. These steps can be converted into a program as illustrated next. Page 150

Computer Architecture And Microprocessor

Illustrative Program: Binary to Unpacked BCD Conversion PROBLEM STATEMENT A binary number is stored in memory location BINBYT. Convert the number into BCD, and store each BCD as unpacked BCD digits in the Output Buffer. To perform this task, write a main program and two subroutines: one to supply the powers of ten, and the other to perform the conversion. PROGRAM This program converts an 8-bit binary number into a BCD number; thus it requires twelve bits to represent three BCD digits. The result is stored as three unpacked BCD digits in three Output-Buffer memory locations. START; LXI SP, STACK LXI H, BINBYT MOV A, M CALL PWRTEN HLT ;Initialize stack pointer ;Point HL index where binary number is stored ;Transfer byte ;Call subroutine to load powers of 10

PWRTEN:

;This subroutine loads the powers of 10 in register B and calls the binary ;to BCD conversion routine ;Input: Binary number in the accumulator ;Output: Powers of ten and store BCD1 in the first Output-Buffer memory ;Calls BINBCD routine and modifies register B LXI H, OUTBUF MVI B, 64H CALL BINBCD MVI B, 0AH CALL BINBCD MOV M, A RET ;Point HL index to Output-Buffer memory ;Load 100 in register B ;Call conversion ;Load 10 in register B ;Store BCD1

BINBCD:

;This subroutine converts a binary number into BCD and stores BCD2 and ;BCD3 in the Out put Buffer. ;Input: Binary number in accumulator and powers of 10 in B ;Output: BCD2 and BCD3 in Output Buffer ;Modifies accumulator contents MVI M, FFH INR M SUB B ;Load buffer with (0 -1) ;Clear buffer and increment for each subtraction ;Subtract power of 10 from binary number Page 151

NXTBUF:

Computer Architecture And Microprocessor

JNC NXTBUF ADD B INX H RET PROGRAM DESCRIPTION This program illustrates the concepts of the nested subroutine and the multiple-call subroutine. The main program calls the PWRTEN subroutine; in turn, the PWRTEN calls the BINBCD subroutine twice. 1. The main program transfers the byte to be converted to the accumulator and calls the PWRTEN subroutine. 2. The subroutine PWRTEN supplies the powers of ten by loading register B and the address of the first Output-Buffer memory location, and calls conversion routine BINBCD. 3. In the BINBCD conversion routine, the Output-Buffer memory is used as a register. It is incremented for each subtraction loop. This step also can be achieved by using a register in the microprocessor. The BINBCD subroutine is called twice, once after loading register B with 64H(10010), again after loading register B with 0AH(1010). 4. During the first call of BINBCD, the subroutine clears the Output Buffer, stores BCD3, and points the HL registers to the next Output-Buffer location. The instruction ADD B is necessary to restore the remainder because one extra subtraction is performed to check the borrow. 5. During the second call of BINBCD, the subroutine again clears the output buffer, stores BCD2, and points to the next buffer location. BCD3 is already in the accumulator after the ADD instruction, which is stored in the third Output-Buffer memory by the instruction MOV M, A in the PWRTEN subroutine. This is an efficient subroutine; it combines the functions of storing the answer and finding a quotient. However, two subroutines are required, and the second subroutine is called twice for a conversion. 4.2.8 BCD TO SEVEN-SEGMENT LED CODE CONVERSION ;Is number > power of 10? If yes, add 1 to buffer ;If no, add power of 10 to get remainder ;Go to next buffer location

When a BCD number is to be displayed by a seven-segment LED, it is necessary to convert the BCD number to its seven-segment code. The code is determined by hardware considerations such as common cathode or common anode LED; the code has no direct relationship to binary numbers. Therefore, to display a BCD digit at a seven-segment LED, the table look-up technique is used. In the table look-up technique, the codes of the digits to be displayed are stored sequentially in memory. The conversion program locates the code of a digit based on its magnitude, and transfers the code to the MPU to send out to a display port. The table look-up technique is illustrated in the next program. Page 152

Computer Architecture And Microprocessor

Illustrative Program: BCD to Common Cathode LED Code Conversion PROBLEM STATEMENT A set of three packed BCD numbers (six digits) representing time and temperature are stored in memory locations starting at XX50H. The seven-segment codes of the digits 0 to 9 for a common cathode LED are stored in memory locations starting at XX70H, and the Output-Buffer memory is reserved at XX90H. Write a main program and two subroutines, called UNPAK and LEDCOD, to unpack the BCD numbers and select an appropriate seven-segment code for each digit. The codes should be stored in the Output-Buffer memory. PROGRAM LXI SP, STACK ;Initialize stack pointer LXI H, XX50H ;Point HL index where BCD digits are stored MVI D, 03H ;Number of digits to be converted is placed in D CALL UNPAK ;Call subroutine to unpack BCD numbers HLT ;End of conversion ;This subroutine unpacks the BCD number into two single digits. ;Input: Starting memory address of the packed BCD numbers in HL ;registers: Number of BCDs to be converted in register d ;Output: Unpacked BCD into accumulator and Output Buffer address in BC ;Calls subroutine LEDCOD LXI B, BUFFER MOV A, M ANI F0H RRC RRC RRC RRC CALL LEDCOD INX B MOV A, M ANI 0FH CALL LEDCOD INX B INX H DCR D JNZ NXTBCD ;Point BC index to the buffer memory ;Get packed BCD number ;Masked BCD1 ;Rotate four times to place BCD2 as unpacked ;single digit BCD ;Find seven-segment code ;Point to next buffer location ;Get BCD number again ;Separate BCD1 ;Point to next BCD ;One conversion complete, reduce BCD count ;If all BCDs are not yet converted, go back to ;convert next BCD Page 153

UNPAK:

NXTBCD:

Computer Architecture And Microprocessor

RET LEDCOD: ;This subroutine converts an unpacked BCD into its seven-segment LED ;code ;Input: An unpacked BCD in accumulator :Memory address of the buffer in BC register ;Output: Stores seven-segment code in the output buffer PUSH H LXI H, CODE ADD L MOV L, A MOV A, M STAX B POP H RET CODE: 06 5B 4F 66 6D 7D 07 7F 6F 00 3F ;Save HL contents of the caller ;Point index to beginning of 7-segment code ;Add BCD digit to starting address of code ;Point HL to appropriate code ;Get seven-segment code ;Store code in buffer

;Digit 0:Common cathode codes ;Digit 1 ;Digit 2 ;Digit 3 ;Digit 4 ;Digit 5 ;Digit 6 ;Digit 7 ;Digit 8 ;Digit 9 ;Invalid Digit

PROGRAM DESCRIPTION/OUTPUT 1. The main program initializes the stack pointer, the index for BCD digits, and the counter for the number of digits; and calls the UNPAK subroutine. 2. The UNPAK subroutine transfers a BCD number into the accumulator, and unpacks it into two BCD digits by using the instruction ANI and RRC. This subroutine also supplies the address of the buffer memory to the next subroutine, LEDCOD. The subroutine is repeated until counter D becomes zero. 3. The LEDCOD subroutine saves the memory address of the BCD number and points the HL register to the beginning address of the code. 4. The instruction ADD L adds the BCD digit in the accumulator to the starting address of the code. After storing the sum in register L, the HL register points to the seven-segment code of that BCD digit. 5. The code is transferred to the accumulator and stored in the buffer. This illustrative program uses the technique of the nested subroutine (one subroutine calling another). Parameters are passes from one subroutine to another; therefore, you Page 154

Computer Architecture And Microprocessor

should be careful in using Push instructions to store register contents on the stack. In addition, the LEDCOD subroutine does not account for a situation if by adding the register L a carry is generated 4.2.9 Binary to ASCII and ASCII to Binary Code Conversion

The American Standard Code for Information Interchange (known as ASCII) is used commonly in data communication. It is a seven-bit code, and its 128(2 7) combinations are assigned different alphanumeric characters. For example, the hexadecimal numbers 30H to 39H represent 0 to 9 ASCII decimal numbers, and 41H to 5AH represent capital letters A through Z; in this code, bit D7 is zero. In serial data communication, bit D7 can be used for parity checking. The ASCII keyboard is a standard input device for entering programs in a microcomputer. When an ASCII character is entered, the microprocessor receives the binary equivalent of the ASCII Hex number. For example, when the ASCII key for digit 9 is pressed, the microprocessor receives the binary equivalent of 39H, which must be converted to the binary 1001 for arithmetic operations. Similarly, to display digit 9 at the terminal, the microprocessor must send out the ASCII Hex code (39H). These conversions are done through software, as in the following illustrative program. Illustrative Program: Binary to ASCII Hex Code Conversion PROBLEM STATEMENT An 8-bit binary number (e.g., 9FH) is stored in memory location XX50H. 1. Write a program to a. Transfer the byte to the accumulator. b. Separate the two nibbles (as 09 and 0F). c. Call the subroutine to convert each nibble into ASCII Hex code. d. Store the codes in memory locations XX60H AND XX61H. 2. Write a subroutine to convert a binary digit (0 to F) into ASCII Hex code. MAIN PROGRAM LXI SP, STACK LXI H, XX50H LXI D, XX60H MOV A, M MOV B, A RRC RRC RRC RRC CALL ASCII ;Initialize stack pointer ;Point index where binary number is stored ;Point index where ASCII code is to be stored ;Transfer byte ;Save byte ;Shift high-order nibble to the position of low-order nibble

;Call conversion routine Page 155

Computer Architecture And Microprocessor

STAX D INX D MOV A, B CALL ASCII STAX D HLT ;Store first ASCII Hex in XX60H ;point to next memory location, get ready to store next byte ;Get number again for second digit

ASCII: ;This subroutine converts a binary digit between 0 and F to ASCII Hex ;code ;Input: Single binary number 0 to F in the accumulator ;Output: ASCII Hex code in the accumulator ANI 0FH CIP 0AH JC CODE ADI 07H ADI 30H RET ;Mask high-order nibble ;Is digit less than 1010? ;If digit is less than 1010, go to CODE to add 30H ;Add 7H to obtain code for digits from A to F ;Add base number 30H

CODE:

PROGRAM DESCRIPTION 1. The main program transfers the binary data byte from the memory location to the accumulator. 2. It shifts the high-order nibble into the low-order nibble, calls the conversion subroutine, and stores the converted value in the memory. 3. It retrieves the byte again and repeats the conversion process for the low-order nibble. In this program, the masking instruction ANI is used once in the subroutine rather than twice in the main program as illustrated in the program for BCD to Common Cathode LED Code Conversion. Illustrative Program: ASCII Hex to Binary Conversion PROBLEM STATEMENT Write a subroutine to convert an ASCII Hex number into its binary equivalent. A calling program places the ASCII number in the accumulator, and the subroutine should pass the conversion back to the accumulator. SUBROUTINE ASCBIN: ;This subroutine converts an ASCII Hex number into its binary ;Input: ASCII Hex number in the accumulator ;Output: Binary equivalent in the accumulator

Page 156

Computer Architecture And Microprocessor

SUI 30H CPI 0AH RC SUI 07H RET PROGRAM DESCRIPTION This subroutine subtracts the ASCII weighting digits from the number. This process is exactly opposite to that of the Illustrative Program that converted binary into ASCII Hex. However, this program uses two return instructions, an illustration of the multiple-ending subroutine. MULTIPLICATION Multiplication can be performed by repeated addition; this technique is used in BCD-tobinary conversion. It is, however an inefficient technique for a large multiplier. A more efficient technique can be devised by following the model of manual multiplication of decimal numbers. For example x Step 1: (108 x 5) Step 2: Shift left and add (108 x 1) = = 108 15 540 ;Subtract 0 bias from the number ;Check whether number is between 0 and 9 ;If yes, return to main program ;If not, subtract 7 to find number between A and F

+ 108 1620

In this example, the multiplier multiplies each digit of the multiplicand, starting from the farthest right, and adds the product by shifting to the left. The same process can be applied in binary multiplication. Illustrative Program: Multiplication of Two 8-Bit Unsigned Numbers PROBLEM STATEMENT A multiplicand is stored in memory location XX50H and a multiplier is stored in location XX51H. Write a main program to 1. Transfer the two numbers from memory locations to the HL registers. 2. Store the product in the Output Buffer at XX90H. Write a subroutine to 1. Multiply two unsigned numbers placed in registers H and L. 2. Return the result into the HL pair.

Page 157

Computer Architecture And Microprocessor

MAIN PROGRAM LXI SP, STACK LHLD XX50H XCHG CALL MLTPLY SHLD XX90H HLT ;Place contents of XX50 in L register and contents ;of XX51 in H register ;Place multiplier in D and multiplicand in E ;Multiply the two numbers ;Store the product in locations XX90 and 91H

Subroutine ;MLTPLY : This subroutine multiplies two 8-bit unsigned numbers ;Input : Multiplicand in register E and multiplier in register D ;Output : Results in HL register MLTPLY: MOV A, D MVI D, 00H LXI H, 0000H MVI B, 08H RAR JNC NOADD DAD D XCHG DAD H XCHG DCR B JNZ NXTBIT RET ;Transfer multiplier to accumulator ;Clear D to use in DAD instruction ;Clear HL ;Set up register B to count eight rotations ;Check if multiplier bit is 1 ;If not, skip adding multiplicand ;If multiplier is 1, add multiplicand to HL and place ;partial result in HL ;Place multiplicand in HL ;And shift left ;Retrieve shifted multiplication ;One operation is complete, decrement counter ;Go back to next bit

NXTBIT:

NOADD:

PROGRAM DESCRIPTION 1. The objective of the main program is to demonstrate use of the instruction LHLD, SHLD, and XCHG. The main program transfers the two bytes (multiplier and multiplicand) from memory locations to the HL registers by using the instruction LHLD, places them in the DE register by the instruction XCHG, and places the result in the Output Buffer by the instruction SHLD. 2. The multiplier routine follows the format add and shift to the left illustrated at the beginning. The routine places the multiplier in the accumulator and rotates it eight times until the counter (B) becomes zero. The reason for clearing D is to use the instruction DAD to add register pairs.

Page 158

Computer Architecture And Microprocessor

3. After each rotation, when a multiplier bit is 1, the instruction DAD D performs the addition, and DAD H shift bits to the left. When a bit is 0, the subroutine skips the instruction DAD D and just shifts the bits. 4.2.10 Software Development System

A software development system is simply a computer that enables the user to write, modify, debut, and test programs. In a microprocessor-based development system, a microcomputer is used to develop software for a particular microprocessor. Generally, the microcomputer has a large R/W memory (64K), disk storage, and a video terminal with ASCII keyboard. The system includes programs that enable the user to develop software either assembly language or high-level languages. This text will focus on developing programs in the 8085/8080A assembly language. Conceptually, this type of microcomputer is similar to a single-board microcomputer except that it has features that can assist in developing large programs. Programs are accessed and stored under a file name (title), and they are written by using other programs such as text editors and assembler. The system (I/Os, files, programs, etc.) is managed by a program called the operating system. Operating Systems and CP/M The operating system of a computer is a group of programs that manages or oversees all the operations of the computer. The computer transfers information constantly among peripherals such as floppy disk, printer, keyboard, and video monitor. It also stores user programs under file names on a disk. A file is defined as related records stored as a single entity. The operating system is responsible primarily for managing the files on the disk and the communication between the computer and its peripherals. Each computer has its own operating system. CP/M (Control Program/Monitor) is by far the most widely used operating system for microcomputers designed around the 8085/8080A and the Z-80 microprocessors. The CP/M design is, for the most part independent of the machine, so that microcomputer manufacturers can adapt it to their own designs with minimum changes. Other popular microcomputers, such as the TRS-80 (Radio Shack), Cromemco, or North Star, have their own operating systems. To illustrate the operation of a software development system, CP/M is briefly described in reference to a system with 64 R/W memory. CP/M The operating system is divided into three components: BIOS (Basic Input/Output System), BDOS (Basic Disk Operating System), and CCP (Console Command Processor). BIOS The BIOS program consists of input/output routines; it manages data transfer between the microprocessor and various peripherals. This section of CP/M is accessible to the user. Page 159

Computer Architecture And Microprocessor

Each manufacturer modifies I/O port addresses in this section according to the hardware design in a particular system. BDOS The BDOS program directs the activities of the disk controller and manages the file allocation on the disk and is not accessible to the user. The BDOS program allocates memory spaces under a file name.

Fig 4.21 CP / M Memory Map with 64K R / W Memory CCP The CCP program reads and interprets the CP/M commands from the keyboard. These commands include operations such as listing the programs on the disk, copying, erasing, and renaming a file. CCP also transfers the program control from CP/M to user or other programs. When CP/M is loaded into a systems R/W memory, it occupies approximately 6K of memory at the highest available locations, as shown in Figure 4.21. In addition, the first 256 location (from 0000 to 00FFH) are reserved for system parameters. The rest of the R/W memory (approximately 58K) is available for the user. Once the operating system is loaded into R/W memory, the user can write, assemble, test, and debug programs by using utility programs. Tools for Developing Assembly Language Programs The CP/M operating system includes programs called utility programs. These programs can be classified in two categories; file management utilities, and program development utilities. The file management utilities are programs that enable the user to perform functions such as copying, printing, erasing, and renaming files. The program Page 160

Computer Architecture And Microprocessor

development utilities enable the user to write, assemble, and test assembly language programs; they include programs such as Editor, Assembler, Loader, and Debugger. EDITOR The Editor is a program that allows the user to enter, modify, and store a group of instructions or text under a file name. To write text, the user must call the Editor under CP/M control. As soon as the Editor program is transferred from the disk to the system memory, the program control is transferred from CP/M to the Editor program. The Editor has its own commands, and the user can enter and modify text by using those commands. Some Editor programs, such as Word Star, are very easy to use. At the completion of writing a program, the exit command of the Editor will save the program on the disk under the file name, and will transfer the program control to CP/M. This file is known as a source file or a source program. If the source file is intended to be a program in the 8085/8080A assembly language, the user should follow the syntax of the assembly language and the rules of the assembler program that is described next. The Editor program is not concerned with whether one is writing a letter or an assembly language program. ASSEMBLER The Assembler (ASM) is a program that translates mnemonics into the Intel Hex code of 8085/8080A microprocessor and generates a file called the Hex file. This function is similar to manual assembly, whereby the user looks up the code for each mnemonic in the listing. In addition to translating mnemonics, the Assembler performs various functions, such as error checking and memory allocations. The Assembler is described in more detail in Section 10.2. LOADER The Loader (LOAD) is a program that takes the Hex file generated by the assembler and generates a file in binary code called COM file or the object code. The COM file is the only executable file: i.e., the only file that can be executed by the microcomputer. To execute the program, the COM file is called under CP/M control and executed. DEBUGGER The Debugger, also known as DDT (Dynamic Debugging Tool), is a program that allows the user to test and debug the object file. The user can employ this program to perform the following functions: 1. Make changes in the object code. 2. Examine and modify the contents of memory. 3. Set breakpoints, execute a segment of the program, and display register contents after the execution. 4. Trace the execution of the specified segment of the program, and display the register and memory contents after the execution of each instruction. 5. Disassemble a section of the program; i.e., convert the object code into the source code or mnemonics.

Page 161

Computer Architecture And Microprocessor

In the CP/M assembler, translating mnemonics into binary code is a two-step process: first, the source file is converted into the Hex file by the ASM program; then, the Hex file is converted into the binary object file by the LOAD program. This is called program assembly, and the two programs in combination (ASM and LOAD) can be viewed as the CP/M assembler. In addition, the assembler also generates the print (PRN) file and the backup (BAK) file. The PRN file is generated for documentation, and the BAK file is generated when the user calls the ASM file for reediting; the BAK file is the copy of the previous file before the user begins to reedit. The BAK file is generated as a precautionary measure, in the event the user wishes to go back to the previous file. At the completion of the assembly process, the CP/M user will have the following five files: ASM File: This is the source file written by the user. HEX File: This is generated by the assembler program and contains the program code in hexadecimal notations. PRN File: This is the print file generated by the assembler program for documentation purposes. It contains memory locations, Hex code, mnemonics, and comments. COM File: This is the executable file generated by the loader program, and it contains binary code. BAK File: When the ASM file is called for reediting, the previous file is saved as the BAK file.

Page 162

Computer Architecture And Microprocessor

4.3

Revision Points

Counter The counter is designed simply by loading an appropriate number into one of the registers and using the INR or the DCR. Time Delay The procedure used to design a specific delay is similar to that used to set up a counter. A register is loaded with a number, depending on the time delay required, and then the register is decremented until it reaches zero by setting up a loop with a conditional Jump instruction. The loop caused the delay, depending upon the clock period of the system Stack The stack in an 8085/8080A microcomputer system can be described as a set of memory locations in the R/W memory, specified by a programmer in a main program. Subroutine A subroutine is a group of instructions written separately from the main program to perform a function that occurs repeatedly in the main program.

4.4

Intext Questions
1. What is time delay? 2. What is a stack 3. Explain the need for a subroutine? 4. Explain the stack operations? 5. Explain use of a counter?

4.5

Summary
Counters are used primarily to keep track of events, while time delays are important in setting up reasonably accurate timing between two events. The stack in an 8085/8080A microcomputer system can be described as a set of memory locations in the R/W memory, specified by a programmer in a main program.

Page 163

Computer Architecture And Microprocessor

The beginning of the stack is defined in the program by using the instruction LXI SP, which loads a 16-bit memory address in the stack pointer register of the microprocessor. The stack space grows upward in the numerically decreasing order of memory addresses. The stack can be initialized anywhere in the user memory map. A subroutine is a group of instructions written separately from the main program to perform a function that occurs repeatedly in the main program. The operating system is divided into three components: BIOS (Basic Input/Output System), BDOS (Basic Disk Operating System), and CCP (Console Command Processor). The Assembler (ASM) is a program that translates mnemonics into the Intel Hex code of 8085/8080A microprocessor and generates a file called the Hex file. The Loader (LOAD) is a program that takes the Hex file generated by the assembler and generates a file in binary code called COM file or the object code.

Terminal Exercises
1. What is counter? 2. Why assembler is needed? 3. What happens when RET instruction is encountered? 4. What does POP and PUSH do?

Supplementary Materials
1. Ramesh S. Goankar, Microprocessor Architecture & Applications, Third Edition, Penram international Publishing (India), 1997. 2. Mathur, Introduction to Microprocessors, Third Edition, TMH.

Page 164

Computer Architecture And Microprocessor 4.8 Assignments

Discuss in detail about stack and its operations 1. Write a program with subroutine.

4.9

Suggested Reading/Reference Books/Set Books

1. Introduction to Microprocessor, Software, Hardware programming , L.A.Levanthal. 2. Fundamentals of Microprocessor, B.Ram, Dhanapat Rai & Sons

4.10 Learning Activities

Programming sequences, hence there are no learning activities.

4.11 Keywords
INR DCR CALL RET POP PUSH

Page 165