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SN54/74LS240 SN54/74LS241 SN54/74LS244: Low Power Schottky

SN54 / 74LS240, 241 and 244 are Octal Buffers and Line Drivers. Designed to be employed as memory address drivers, clock drivers and bus-oriented transmitters / receivers which provide improved PC board density.

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0% found this document useful (0 votes)
137 views

SN54/74LS240 SN54/74LS241 SN54/74LS244: Low Power Schottky

SN54 / 74LS240, 241 and 244 are Octal Buffers and Line Drivers. Designed to be employed as memory address drivers, clock drivers and bus-oriented transmitters / receivers which provide improved PC board density.

Uploaded by

Douglas Cordero
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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OCTAL BUFFER/LINE DRIVER WITH 3-STATE OUTPUTS

The SN54 / 74LS240, 241 and 244 are Octal Buffers and Line Drivers designed to be employed as memory address drivers, clock drivers and bus-oriented transmitters/receivers which provide improved PC board density.

SN54/74LS240 SN54/74LS241 SN54/74LS244

OCTAL BUFFER / LINE DRIVER WITH 3-STATE OUTPUTS


LOW POWER SCHOTTKY

Hysteresis at Inputs to Improve Noise Margins 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers Input Clamp Diodes Limit High-Speed Termination Effects
LOGIC AND CONNECTION DIAGRAMS DIP (TOP VIEW) SN54 / 74LS240
VCC 2G 20 19 1Y1 18 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1 17 16 15 14 13 12 11
20 1

J SUFFIX CERAMIC CASE 732-03

20 1

N SUFFIX PLASTIC CASE 738-03

1 1G

2 1A1

3 4 5 2Y4 1A2 2Y3

6 8 9 10 7 1A3 2Y2 1A4 2Y1 GND


20 1

SN54 / 74LS241
VCC 2G 20 19 1Y1 18 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1 17 16 15 14 13 12 11

DW SUFFIX SOIC CASE 751D-03

ORDERING INFORMATION
SN54LSXXXJ Ceramic SN74LSXXXN Plastic SN74LSXXXDW SOIC 1 1G 2 1A1 3 4 5 2Y4 1A2 2Y3 6 8 9 10 7 1A3 2Y2 1A4 2Y1 GND

SN54 / 74LS244
VCC 2G 20 19 1Y1 18 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1 17 16 15 14 13 12 11

1 1G

2 1A1

3 4 5 2Y4 1A2 2Y3

8 9 10 6 7 1A3 2Y2 1A4 2Y1 GND

FAST AND LS TTL DATA 5-1

54LS245 DM54LS245 DM74LS245 TRI-STATE Octal Bus Transceiver

June 1989

54LS245 DM54LS245 DM74LS245 TRI-STATE Octal Bus Transceiver


General Description
These octal bus transceivers are designed for asynchronous two-way communication between data buses The control function implementation minimizes external timing requirements The device allows data transmission from the A bus to the B bus or from the B bus to the A bus depending upon the logic level at the direction control (DIR) input The enable input (G) can be used to disable the device so that the buses are effectively isolated
Y Y Y Y Y

Features
Y Y

Bi-Directional bus transceiver in a high-density 20-pin package TRI-STATE outputs drive bus lines directly

PNP inputs reduce DC loading on bus lines Hysteresis at bus inputs improve noise margins Typical propagation delay times port-to-port 8 ns Typical enable disable times 17 ns IOL (sink current) 54LS 12 mA 74LS 24 mA IOH (source current) b 12 mA 54LS b 15 mA 74LS Alternate Military Aerospace device (54LS245) is available Contact a National Semiconductor Sales Office Distributor for specifications

Connection Diagram
Dual-In-Line Package

TL F 6413 1

Order Number 54LS245DMQB 54LS245FMQB 54LS245LMQB DM54LS245J DM54LS245W DM74LS245WM or DM74LS245N See NS Package Number E20A J20A M20B N20A or W20A

Function Table
Enable G L L H Direction Control DIR L H X Operation

B data to A bus A data to B bus Isolation

H e High Level L e Low Level X e Irrelevant


TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation

TL F 6413

RRD-B30M105 Printed in U S A

Absolute Maximum Ratings (Note)


If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage 7V Input Voltage DIR or G 7V A or B 5 5V Operating Free Air Temperature Range b 55 C to a 125 C DM54LS and 54LS DM74LS 0 C to a 70 C b 65 C to a 150 C Storage Temperature Range Note The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits The parametric values defined in the Electrical Characteristics table are not guaranteed at the absolute maximum ratings The Recommended Operating Conditions table will define the conditions for actual device operation

Recommended Operating Conditions


Symbol VCC VIH VIL IOH IOL TA Parameter Min Supply Voltage High Level Input Voltage Low Level Input Voltage High Level Output Current Low Level Output Current Free Air Operating Temperature
b 55

DM54LS245 Nom 5 Max 55 Min 4 75 2 07


b 12

DM74LS245 Nom 5 Max 5 25

Units V V 08
b 15

45 2

V mA mA C

12 125 0

24 70

Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol VI HYS VOH Parameter Input Clamp Voltage Hysteresis (VT a b VTb) High Level Output Voltage Conditions VCC e Min II e b18 mA VCC e Min VCC e Min VIH e Min VIL e Max IOH e b1 mA VCC e Min VIL e Min VIL e Max IOH e b3 mA VCC e Min VIH e Min VIL e 0 5V IOH e Max VOL Low Level Output Voltage VCC e Min VIL e Max VIH e Min VCC e Max VIL e Max VIH e Min VCC e Max IOL e 12 mA IOL e Max VO e 2 7V VO e 0 4V A or B DIR or G VCC e Max VI e 2 7V VCC e Max VI e 0 4V VCC e Max (Note 2) Outputs High Outputs Low Outputs at Hi-Z
Note 1 All typicals are at VCC e 5V TA e 25 C Note 2 Not more than one output should be shorted at a time not to exceed one second duration

Min

Typ (Note 1)

Max
b1 5

Units V V

02 DM74 DM54 DM74 DM54 DM74 DM74 DM54 DM74 27 24 2

04

34

04 04 05 20
b 200

IOZH IOZL II IIH IIL IOS ICC

Off-State Output Current High Level Voltage Applied Off-State Output Current Low Level Voltage Applied Input Current at Maximum Input Voltage High Level Input Current Low Level Input Current Short Circuit Output Current Supply Current

mA mA mA mA mA mA

VI e 5 5V VI e 7V

01 01 20
b0 2 b 40 b 225

VCC e Max

48 62 64

70 90 95 mA

Switching Characteristics VCC e 5V


Symbol Parameter

TA e 25 C (See Section 1 for Test Waveforms and Output Load) DM54 74 Conditions Min LS245 Max 12 CL e 45 pF RL e 667X 12 40 40 CL e 5 pF RL e 667X 25 25 16 CL e 150 pF RL e 667X 17 45 45 ns ns ns ns ns ns ns ns ns ns Units

tPLH tPHL tPZL tPZH tPLZ tPHZ tPLH tPHL tPZL tPZH

Propagation Delay Time Low-to-High-Level Output Propagation Delay Time High-to-Low-Level Output Output Enable Time to Low Level Output Enable Time to High Level Output Disable Time from Low Level Output Disable Time from High Level Propagation Delay Time Low-to-High-Level Output Propagation Delay Time High-to-Low-Level Output Output Enable Time to Low Level Output Enable Time to High Level

Physical Dimensions inches (millimeters)

Ceramic Leadless Chip Carrier Package (E) Order Number 54LS245LMQB NS Package Number E20A

20-Lead Ceramic Dual-In-Line Package (J) Order Number 54LS245DMQB or DM54LS245J NS Package Number J20A 4

Physical Dimensions inches (millimeters) (Continued)

20-Lead Small Outline Molded Package (M) Order Number DM74LS245WM NS Package Number M20B

20-Lead Molded Dual-In-Line Package (N) Order Number DM74LS245N NS Package Number N20A

54LS245 DM54LS245 DM74LS245 TRI-STATE Octal Bus Transceiver

Physical Dimensions inches (millimeters) (Continued)

20-Lead Ceramic Flat Package (W) Order Number 54LS245FMQB or DM54LS245W NS Package Number W20A

LIFE SUPPORT POLICY NATIONALS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user
National Semiconductor Corporation 1111 West Bardin Road Arlington TX 76017 Tel 1(800) 272-9959 Fax 1(800) 737-7018

2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness

National Semiconductor Europe Fax (a49) 0-180-530 85 86 Email cnjwge tevm2 nsc com Deutsch Tel (a49) 0-180-530 85 85 English Tel (a49) 0-180-532 78 32 Fran ais Tel (a49) 0-180-532 93 58 Italiano Tel (a49) 0-180-534 16 80

National Semiconductor Hong Kong Ltd 13th Floor Straight Block Ocean Centre 5 Canton Rd Tsimshatsui Kowloon Hong Kong Tel (852) 2737-1600 Fax (852) 2736-9960

National Semiconductor Japan Ltd Tel 81-043-299-2309 Fax 81-043-299-2408

National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications

SN54/74LS240 SN54/74LS241 SN54/74LS244


TRUTH TABLES SN54 / 74LS240
INPUTS OUTPUT 1G, 2G L L H D L H X H L (Z) 1G, 2G L L H D L H X L H (Z)

SN54 / 74LS244
INPUTS OUTPUT

SN54 / 74LS241
INPUTS 1G L L H D L H X OUTPUT 2G L H (Z) H H L D L H X L H (Z) INPUTS OUTPUT

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = HIGH Impedance

GUARANTEED OPERATING RANGES


Symbol VCC TA IOH Supply Voltage Operating Ambient Temperature Range Output Current High Parameter 54 74 54 74 54, 74 54 74 IOL Output Current Low 54 74 Min 4.5 4.75 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 3.0 12 15 12 24 Unit V C mA mA mA

FAST AND LS TTL DATA 5-2

SN54/74LS240 SN54/74LS241 SN54/74LS244


DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits Symbol S b l Parameter P Min Typ Max Unit U i Test C di i T Conditions

FAST AND LS TTL DATA 5-3

SN54/74LS240 SN54/74LS241 SN54/74LS244

AC WAVEFORMS

VIN

1.3 V tPLH

1.3 V tPHL 1.3 V

VCC RL SW1

VOUT

1.3 V

Figure 1

TO OUTPUT UNDER TEST VIN 1.3 V tPHL VOUT 1.3 V 1.3 V tPLH 1.3 V CL* 5 k SW2

Figure 2

VE VE VOUT

1.3 V tPZL 1.3 V

1.3 V tPLZ 1.3 V VOL 0.5 V SYMBOL tPZH tPZL tPLZ tPHZ

SWITCH POSITIONS
SW1 Open Closed Closed Closed SW2 Closed Open Closed Closed

Figure 3

Figure 5
VE 1.3 V VE VOUT tPZH 1.3 V 1.3 V tPHZ VOH 1.3 V 0.5 V

Figure 4

FAST AND LS TTL DATA 5-4

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