VHDL Program

the VHDL code for 2-4 decoder. ibrary ieee; use ieee.std_logic_1164.
all; entity decoder_2_4 is port( a: in std_logic_vector(1 downto 0); en: in std_logic; y: out std_logic_vector(3 downto 0) ); end decoder_2_4; architecture arch of decoder_2_4 is begin y <= "0000" when (en='0') else "0001" when (a="00") else "0010" when (a="01") else "0100" when (a="10") else "1000"; -- a="11" end arch; VHDL Code for 4 Bit Comparator LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_arith.all ; ENTITY compare IS PORT ( A, B : IN SIGNED(3 DOWNTO 0) ; AeqB, AgtB, AltB : OUT STD_LOGIC ) ; END compare ; ARCHITECTURE Behavior OF compare IS BEGIN AeqB <= 1 WHEN A = B ELSE 0 ; AgtB <= 1 WHEN A > B ELSE 0 ; AltB <= 1 WHEN A < B ELSE 0 ; END Behavior ; VHDL Code for JK flip flop --libraries to be used are specified here library IEEE; use IEEE.STD_LOGIC_1164.ALL; --entity declaration with port definitions entity JK_Flipflop is port ( clk: in std_logic; J, K: in std_logic; Q, Qbar: out std_logic; reset: in std_logic );
end JK_Flipflop; --architecture of entity architecture Behavioral of JK_Flipflop is --signal declaration. signal qtemp,qbartemp : std_logic :='0'; begin Q <= qtemp; Qbar <= qbartemp; process(clk,reset) begin if(reset = '1') then --Reset the output. qtemp <= '0'; qbartemp <= '1'; elsif( rising_edge(clk) ) then if(J='0' and K='0') then --No change in the output NULL; elsif(J='0' and K='1') then --Set the output. qtemp <= '0'; qbartemp <= '1'; elsif(J='1' and K='0') then --Reset the output. qtemp <= '1'; qbartemp <= '0'; else --Toggle the output. qtemp <= not qtemp; qbartemp <= not qbartemp; end if; end if; end process; end Behavioral; VHDL Code for T flip flop library ieee; use ieee.std_logic_1164.all entity tff is port( clk: in std_logic; reset: in std_logic; t: in std_logic; q: out std_logic ); enf tff; architecture behave of tff is signal q_reg: std_logic; signal q_next: std_logic; begin
process begin if (reset = '1') then q_reg <= '0'; elsif (clk'event and clk = '1') then q_reg <= q_next; end if; end process; q_next <= q_reg when t = '0' else not(q_reg); q <= q_reg; end behave; 4-Bit BCD Up Counter with Clock Enable library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Counter2_VHDL is port( Clock_enable: in std_logic; Clock: in std_logic; Reset: in std_logic; Output: out std_logic_vector(0 to 3)); end Counter2_VHDL; architecture Behavioral of Counter2_VHDL is signal temp: std_logic_vector(0 to 3); begin process(Clock,Reset) begin if Reset='1' then temp <= "0000"; elsif(Clock'event and Clock='1') then if Clock_enable='0' then if temp="1001" then temp<="0000"; else temp <= temp + 1; end if; else temp <= temp; end if; end if; end process; Output <= temp; end Behavioral;
VHDL code for Full Adder using dataflow style LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY fulladd IS PORT ( Cin, x, y s, Cout : OUT END fulladd ; : IN STD_LOGIC ; STD_LOGIC ) ;
ARCHITECTURE beh OF fulladd IS BEGIN s <= x XOR y XOR Cin ; Cout <= (x AND y) OR (Cin AND x) OR (Cin AND y) ; END beh ;
VHDL code for Full Adder using structural style

library IEEE; use IEEE.std_logic_1164.all; entity bejoy_fa is port(In1,In2,c_in : in std_logic; sum, c_out : out std_logic); end bejoy_fa; architecture arc of bejoy_fa is component half_adder port(a,b : in std_logic; sum, carry : out std_logic); end component; component or_2 port(a,b : in std_logic; c : out std_logic); end component; signal s1, s2, s3 : std_logic; begin H1: half_adder port map(a=>In1, b=>In2, sum=>s1, carry=>s3); H2: half_adder port map(a=>s1, b=>c_in, sum=>sum, carry=>s2); O1: or_2 port map(a=> s2, b=>s3, c=>c_out); end arc; entity half_adder is port (a,b : in bit ; sum,carry : out bit);
end half_adder; architecture arc of half_adder is begin sum<= a xor b; carry <= a and b; end arc; entity or_2 is port (a,b : in bit ; c : out bit); end or_2; architecture arc of or_2 is begin c<= a or b; end arc;
--VHDL code for BEHAVIORAL model of Full Adder library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity FA_Bhr is port(Fx, Fy, Fcin : in BIT; Fs, Fcout : out BIT); end FA_Bhr; architecture FA_struct of FA_Bhr is component HAport (hx, hy :in BIT; hs, hcout: out BIT); end component; signal s1, c1, c2 : BIT; begin HA1: HA port map (Fx, Fy, s1, c1); HA2: HA port map (s1, Fcin, Fs, c2); Fcout <= c1 OR c2; end FA_struct;

VHDL Program

Uploaded by

Copyright:

Available Formats

VHDL Program

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

VHDL Program

Uploaded by

Copyright:

Available Formats

the VHDL code for 2-4 decoder. ibrary ieee; use ieee.std_logic_1164.

VHDL code for Full Adder using structural style

You might also like

Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.