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CAD For VLSI Design - 1: V. Kamakoti and Shankar Balachandran

This document outlines the design of flip-flops using CMOS transistors and discusses different levels of abstraction for representing circuits and systems. It then presents a case study of designing a 4-bit adder at different levels of abstraction, including behavioral, structural, and physical representations. The 4-bit adder is designed using primitive full adders and carry modules, which are then instantiated and connected to implement the full adder behavior structurally using a Hardware Description Language (HDL).

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Rajeev Pandey
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101 views

CAD For VLSI Design - 1: V. Kamakoti and Shankar Balachandran

This document outlines the design of flip-flops using CMOS transistors and discusses different levels of abstraction for representing circuits and systems. It then presents a case study of designing a 4-bit adder at different levels of abstraction, including behavioral, structural, and physical representations. The 4-bit adder is designed using primitive full adders and carry modules, which are then instantiated and connected to implement the full adder behavior structurally using a Hardware Description Language (HDL).

Uploaded by

Rajeev Pandey
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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CAD for VLSI Design - 1

V. Kamakoti and Shankar Balachandran Lecture 4

Outline of this Lecture Design of Flipflops using CMOS Transistors Representation of circuits and systems Levels of Abstraction Case study of a 4-bit adder

i c

o o c i

FLIP FLOP

Circuit and Systems Representation


Behavioral Structural Physical Domains

Behavioral Representation
Specifies what a particular system does HDLs are used for this

Structural Representation
Specifies how entities are connected together to effect the prescribed behavior HDLs are used for this also

Physical Domains
How to actually build a structure that has the required connectivity to implement the prescribed behavior

Four Bit Adder


module carry (co, a, b, c) ; output co; input a,b,c; assign co = (a&b) | (a&c) | (b&c); endmodule Algorithm level Description Boolean Optimization to be done

Four Bit Adder


primitive carry (co,a,b,c); output co; input a,b,c; table // a b c co 11?:1; 1?1:1; ?11:1; 0 0?:0; 0 ?0:0; ? 00:0; endtable endmodule

Four bit adder


module carry(co,a,b,c); output co; input a,b,c; wire #10 co = (a&b) | (a&c) | (b&c); endmodule co signal changes 10 units of time after a or b or c changes

Structural Representation
module add4(s,c4,ci,a,b) input [3:0] a,b; input ci; output [3:0] s; output c4; wire [2:0] co; add a0 (co[0],s[0],a[0],b[0],ci); add a1 (co[1],s[1],a[1],b[1],co[0]); add a2 (co[2],s[2],a[2],b[2],co[1]); add a3 (c4,s[3],a[3],b[3],co[2]); endmodule

4-bit adder
module add (co,s,a,b,c) input a,b,c; output s,co; sum s1 (s,a,b,c); carry c1 (co,a,b,c); endmodule

4-bit adder
module carry (co,a,b,c) input a,b,c; output co; wire x,y,z; and g1 (x,a,b); and g2 (y,a,c); and g3 (z,b,c); or g4 (co,x,y,z); endmodule

4-bit adder
module carry(co,a,b,c); input a,b,c; output co; wire i1,i2,i3,i4,cn; nmos n1 (i1,gnd,a); //drain,src,gate nmos n2 (i1,gnd,b); nmos n3 (cn,i1,c); nmos n4 (i1,gnd,a); nmos n5 (cn,i2,a); pmos p1 (i3,vdd,b); pmos p2 (cn,i3,a); pmos p3 (cn,i4,c); pmos p4 (i4,vdd,b); pmos p5 (i4,vdd,a); pmos p6 (co,vdd,cn); nmos n6(co,gnd,cn); endmodule

Appreciating the OO
Object Orientedness A 4-bit adder has
4-full adders 4 carry modules and 4 sum modules

Note that each of them were coded once and instantiated 4 times
A way to create circuits with millions of transistors using thousands of lines of HDL code

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