STi 7105

STi7105
Advanced HD decoding IC for STB

Preliminary Data
Features

32-bit DDR1/DDR2 compatible local memory interface Multi-stream, DVR capable transport stream processing
Information classified Confidential - Do not copy (See last page for obligations)
1
Advanced high definition video decoding (H264/VC-1/MPEG2) Advanced standard definition video decoding (H264/VC-1/MPEG2/AVS) Advanced multi-channel audio decoding (MPEG 1, 2, MP 3, DD/DD+, AAC/AAC+, and WMA9/WMA9pro) Linux, Windows CE, and OS21 compatible ST40 applications CPU (450 MHz)
6-channel S/PDIF out PCM out 2-ch Audio L/R PCM in out
Extensive connectivity (dual USB 2.0 hosts, eSATA, Ethernet MAC/MII/RMII, and PCI) Advanced security and DRM support including SVP, MS-DRM, and DTCP-IP DVD data decryption
Confidential
JTAG
DDR1 DDR2 SDRAM
Serial ATA HDD, int/ext
Digital video in
Dual USB 2.0 hosts
Line side DAA

Serial Peripheral I/O and external interrupts FLASH
16/32 ST40-300 core 450 MHz UDI TMUs/INTC MMU LMI
Audio DACs Audio decoder players and interfaces ST231 core DVP
eSATA interface
Key Scan USB 2.0 USB 2.0 2x I/F SmCard
Comms SPI IR Tx/Rx UHF Rx ILC MAFE interface 4x UARTs 4x SSC/I2C PWM
32 K I cache
32 K D cache
CPU/FPU core
System side DAA
GPIOs
STBus Capture Sec Dual PTI 3 SWTS 2 2 CP NSK PDES DUAL FDMA Delta Mu advanced video decoder ST231 Bdisp blitter Main/aux display compositor and pass through Main video display DEI
Clock gen and system services
Aux video display
PCI EMI
TSmerger/router
Ethernet, MAC
Output stage
TXT
DENC
6 DACs HDMI
VTGs
DVO0
DVO1
TS TS TS TS IN0 IN2 IN3 IN1/OUT0
Resets/ clocks/ modes
MII/RMII
Analog video output (HD/SD)
TMDS
Digital Digital video video output 0 output 1
FLASH NOR/NAND SFLASH
February 2009
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www.st.com
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Contents
STi7105
Contents
1 Related documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.1 1.2 STi7105 programming manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 CPU documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1 2.2 2.3 2.4 2.5 2.6 Transport . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Audio/Video decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Graphics and display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Audio/Video outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Processors and memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 DVR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 STB peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Confidential
2.7 2.8
System on chip subsystem overview . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.1 3.2 3.3 3.4 3.5 STBus interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Processor core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 External memory interface (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Local memory interface (LMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 STB transport subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.5.1 3.5.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Dual Programmable transport interface (PTI) . . . . . . . . . . . . . . . . . . . . 19
3.6 3.7 3.8 3.9
DVD decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Video decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Main and auxiliary display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Compositor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.9.1 3.9.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Compositor layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.10
Video output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.10.1 3.10.2 Main HDTV video output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Auxiliary SDTV video flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.11
2D blitter display engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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3.12 3.13 3.14
Audio subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 FDMA controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.14.1 3.14.2 3.14.3 Internal peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Ethernet controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Dual smartcard interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.15 3.16
Clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 System services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.1 4.2 27 x 27 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Environmentally friendly packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
BGA footprint and pin lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

5.1 5.2 Ball grid array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Pin lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.2.1 Full pin list sorted by pin number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Confidential
Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 6.13 6.14 6.15 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Transport interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Display analog output interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 HDMI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Audio digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Audio analog interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Serial ATA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 FDMA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Programmable inputs/outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 External memory interface (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Local memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 USB 2.0 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
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6.16
Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6.16.1 6.16.2 6.16.3 6.16.4 6.16.5 6.16.6 6.16.7 6.16.8 DAA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Asynchronous serial controller (ASC) . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Infrared transmitter/receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Modem analog front-end interface (MAFE) . . . . . . . . . . . . . . . . . . . . . . 92 Pulse width modulator (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Smartcard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Synchronous serial controller (SSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Key Scanner (KS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
6.17
Pad reset conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Basic chip operating modes and multiplexing scenarios . . . . . . . . . . 98

7.1 7.2 Transport interfaces multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Ethernet interface multiplexing in standard mode . . . . . . . . . . . . . . . . . 109 DVB common interface (DVB-CI) transport mode . . . . . . . . . . . . . . . . . 111 External memory interface (EMI) operating modes . . . . . . . . . . . . . . . . 112
7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 7.4.6 7.4.7 7.4.8 7.4.9 Peripheral/SRAM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Asynchronous NOR-Flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Synchronous NOR-Flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 NAND-Flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Serial-Flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 DVB-CI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 ATAPI-PIO modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 PCI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Multi-chip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Confidential
7.3 7.4
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

8.1 Global Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Interrupt networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

9.1 Interrupt network organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
9.1.1 9.1.2 9.1.3 STi7105 interrupt network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 ST40 interrupt network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 DeltaMU and LX_AUDIO ST231 interrupt network . . . . . . . . . . . . . . . 136
10
FDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
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10.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
10.1.1 10.1.2 10.1.3 10.1.4 10.1.5 FDMA0 and FDMA1 Partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Peripheral and memory access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 FDMA processing power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 FDMA firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 FDMA features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
10.2 10.3 10.4
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Examples of DMA Data flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
11
Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
11.1 11.2 11.3 Clock input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Clock domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 CPUs and interconnect clock generation (ClockGen A) . . . . . . . . . . . . . 155
11.3.1 11.3.2 11.3.3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Clockoff and reduced power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Clock observability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Confidential
11.4
Video decoder, display, and Comms clock generation (ClockGen B) 157

11.4.1 11.4.2 11.4.3 11.4.4 11.4.5 11.4.6 Clock signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Clock generator B startup configuration . . . . . . . . . . . . . . . . . . . . . . . 159 Clock frequency change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Clock frequency reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Clocks observation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Frequency synthesizers reference clock . . . . . . . . . . . . . . . . . . . . . . . 163
11.5 11.6
Audio clock generation (ClockGen C) . . . . . . . . . . . . . . . . . . . . . . . . . . 163

11.5.1 Frequency synthesizer reference clock . . . . . . . . . . . . . . . . . . . . . . . . 164
LMI memory clocks (ClockGen D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

11.6.1 11.6.2 11.6.3 Clock signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Reference clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Clock frequency reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
11.7
MPEG clock recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

11.7.1 Clock recovery principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
12
Power-On-Reset and system reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

12.1 Reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
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12.2 12.3
POR reset (cold reset) vs. system reset (warm reset) . . . . . . . . . . . . . . 167 Reset test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
13 14
Mode pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Low power control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

14.1 14.2 14.3 14.4 14.5 Entering low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Exiting low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 DDR self-refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
EMI and PCI clocks stopping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 ST40 sleep and standby modes overview . . . . . . . . . . . . . . . . . . . . . . . 175
15
System config module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

15.1 Brief overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
15.1.1 15.1.2 15.1.3 15.1.4 15.1.5 Register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Device ID register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 System status register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 System configuration register description . . . . . . . . . . . . . . . . . . . . . . 189 INTC2 registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Confidential
16
External circuitry recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . 233

16.1 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
16.1.1 16.1.2 Decoupling recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 Power-up recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
16.2 16.3 16.4
System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 Display analog output interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

16.4.1 16.4.2 16.4.3 Video DACs description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 Power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 Video DACs output-stage adaptation and amplification . . . . . . . . . . . . 235
16.5 16.6 16.7 16.8 16.9
HDMI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 Audio digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 Audio analog interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 Programmable inputs/outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 External memory interface (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
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16.10 Local memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 16.11 Ethernet interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 16.12 USB interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 16.13 SATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 16.14 Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
17
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

17.1 17.2 17.3 17.4 17.5 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 Audio DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
17.3.1 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Triple HD video DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 DAA electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 DDR electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
17.6.1 17.6.2 17.6.3 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 Output buffer DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 Input buffer DC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
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17.6
17.7
SATA PHY electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

17.7.1 17.7.2 17.7.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 General electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
17.8 17.9
External memory interface (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
18
Timing interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

18.1 18.2 18.3 Digital audio interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
18.1.1 Digital PCM reader input interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Digital PCM player output interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253

18.2.1 PCM player output timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Transport stream input AC specification . . . . . . . . . . . . . . . . . . . . . . . . . 254

18.3.1 18.3.2 Parallel transport stream input interface . . . . . . . . . . . . . . . . . . . . . . . 254 Serial transport stream input interface . . . . . . . . . . . . . . . . . . . . . . . . . 255
18.4 18.5 18.6
Transport stream output AC specification . . . . . . . . . . . . . . . . . . . . . . . . 255 JTAG interfaces AC specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 EMI timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
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STi7105 Synchronous devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
18.7 18.8 18.9
LMI DDR2-SDRAM timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 PIO output AC specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 Ethernet interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
18.9.1 18.9.2 MII interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 RMII interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
19
Alternate functions on PIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

19.1 19.2 19.3 19.4 19.5 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 PIO0 alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 PIO1 alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 PIO2 alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 PIO3 alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 PIO4 alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 PIO5 alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 PIO6 alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 PIO7 alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
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19.6 19.7 19.8 19.9
19.10 PIO8 alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 19.11 PIO9 alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 19.12 PIO10 alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 19.13 PIO11 alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 19.14 PIO12 alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 19.15 PIO13 alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 19.16 PIO14 alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 19.17 PIO15 alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 19.18 PIO16 alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
20 21
Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
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Related documents
Related documents
This datasheet is part of the STi7105 documentation suite which forms a complete system description and programming guide. This datasheet is intended for hardware engineers, and describes the pins, package, electrical characteristics, and timing information for the STi7105 device. The documents related to this datasheet are described in the sections below.
The STi7105 programing manual describes how to program and configure the STi7105 device. It is intended for software and system engineers.
1.2
CPU documentation
The ST40 core and its instruction set are documented in the ST40 32-bit CPU Core Architecture manual. The ST231 core and its instruction set are documented in the ST231 CPU Core and Instruction Set Architecture Manual.
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Description
STi7105
Description
The STi7105 includes in a single IC, multi-stream transport de-multiplexing and descrambling, an ST40 applications CPU, advanced audio/video decoding, video processing, graphics and display composition, advanced security, STB peripherals, audio/video DACs, HDMI, Digital A/V outputs, two Host USB ports, e-SATA port HDD interface, and Ethernet MAC/MII/RMII.
2.1
Transport
The STi7105 receives transport streams from broadcast networks through three parallel/serial transport stream inputs and one serial transport stream input. The fourth transport interface can be configured as a fourth input or as an output. ST provides a range of front end channel decoder ICs for cable, satellite and terrestrial networks that can be interfaced directly with the STi7105. Transport stream routing for DVB-CI+ (HD/SD profiles) modules can also be supported. Transport streams are processed by two integrated programmable transport stream engines (PTIs). These perform demultiplexing, descrambling, and section filtering on multiple transport streams received from Broadcast, IP, and HDD sources. Information classified Confidential - Do not copy (See last page for obligations)
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2.2
Connectivity
The STi7105 has a wide range of options for connecting to external peripherals or IP network devices, such as wired ethernet, xDSL, and Wi-fi. These interfaces enable the delivery of IP streams received over broadband networks and support streaming over home networks. These interfaces include 2 USB host ports, a 32-bit PCI interface, and a high speed Ethernet MAC/MII/RMII interface. PCI uses the same physical interface as the EMI with dynamic interleaving of access types possible. Transport streams received through IP can be routed internally to the PTIs for demultiplexing and descrambling similar to the broadcast TS streams. The PTIs can concurrently process multiple TS streams from both sources.
2.3
Audio/Video decoding
The STi7105 can decode H264, VC -1/WMV9, and MPEG2 HD and SD streams with concurrent decoding of one HD stream and one SD stream possible for PIP applications. AVS SD decoding is also supported. Multiple decoding of lower resolution streams can also be supported for Mosaic applications. The decoder is well proven in the industry and is powerful and flexible enough to decode other video formats, such as MPEG4 part2 and DivX (3.x, 4.x, and 5.x). It can also support concurrent H263 encode and decode for video conference applications. A programmable ST231 CPU core provides the flexibility and performance for decoding multi-channel advanced audio streams. Concurrent decoding of an audio description channel is also supported.
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2.4
Graphics and display

The STi7105 integrates a graphics and display sub-system that can deliver a high quality visual experience for applications. Graphics generation can use both the CPU and an independent multi-operator graphics accelerator that supports 2D graphics and 3D user interface effects. Graphics can be displayed on any one of three graphics planes. The graphics planes are combined, with video, using alpha blending and color keying. The graphics and video are combined by two independent display compositors, one for the Main TV and a second for output to a VCR or DVD-R. Two video planes are available for PIP on the main composition or downscaled video on the second composition. Video postprocessing can be applied to resize, reformat and de-interlace video between the encoded and intended display formats prior to composition. Advanced de-blocking processing can be applied to decoded MPEG2 SD video. With such capabilities, feature-rich displays can be generated including PIP, POP, Mosaics, animations, highlighting, blended overlays, scrolling subtitles etc.
2.5
Audio/Video outputs
The STi7105 has both HDMI and analog interfaces for outputting video to the TV/panel. In addition to the standard 720p and 1080i HD formats, the STi7105 supports 1080p60 display output on the HDMI interface. The Analog interface comprises 6 Video DACs with CGMS-A, Macrovision and Dwight-Cavendish copy protection, whilst the HDMI interface supports HDCP copy protection. HDMI interface is in full compliance with all features of v1.3a except deep color, enhanced colorimetry (xvYCC, gamut metadata), and DST/DSD audio features. Audio is output over HDMI, SPDIF, stereo analog DACs, and a digital PCM output interface. It is possible to output both compressed and decoded audio streams at the same time over different interfaces (for example, Dolby Digital 5.1 over SPDIF with decoded and downmixed AAC-plus audio via the analog output). A 2-channel PCM input is also available for inputting audio from external sources such as a microphone (for example, for VOIP telephony).
2.6
Processors and memory

The STi7105 embeds the latest ST40 class applications processor, the ST40-300 with 2 way, set associative caches, a 32 K instruction cache, and a 32 K data cache. At an operating frequency of 450 MHz it can deliver > 800 DMIPs performance. The STi7105 supports the latest DDR2 memory technology on its 32-bit local memory interface (LMI) providing a high bandwidth unified memory for code, data, audio and video buffers, graphics etc. With two 2-Gbit devices in a x16 configuration, up to 512 Mbytes capacity can be supported. The STi7105 also retains the ability to support DDR1 memory types. A 16-bit External memory interface is used for connecting to FLASH and SRAM/peripherals supporting a standard 8/16-bit asynchronous read/write protocol. Synchronous or burst mode FLASH can also be supported. Both NOR and NAND Flash types can be used, with the ability to boot from, and perform code authentication checking from both types. Interfacing and booting from Serial FLASH attached through SPI is also supported.
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Description
STi7105
2.7
DVR
The STi7105 supports attachment of an HDD through e-SATA, USB, or EIDE (PIO mode) allowing DVR STBs to be developed. The e-SATA interface can independently support either internal or external SATA drive attachment. The STi7105 can support recording of up to four HD streams with local playback of an HD stream with trick modes, as well as playback of additional streams for export to client STBs over a home network. Streams can be encrypted to/from the HDD and to/from a home network for copy protection using AES, TDES, or DES ciphers.
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The STi7105 integrates a range of peripherals and interfaces to minimize or eliminate the external cost of implementing basic STB functions. These include UARTs and SSCs used for serial interfaces, I2C control busses, two smart card controllers, a PWM module, IR receiver and transmitter, general purpose programmable I/O, external interrupt inputs, and a controller for scanning/debouncing a 4 x 4 key matrix. There are also two options available for implementing a software modem on the STi7105; a MAFE interface to connect to an external modem codec and integration of a system-side DAA circuit to connect to an external line-side DAA device. For HDMI interfacing, a dedicated I2C port is available, together with a hardware CEC line controller.
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STB peripherals
STi7105 Figure 1. Typical DVR cable STB with DOCSIS

SDRAM RJ45 Cable tuner USB 2.0 PHY
Description
Cable tuner
STV0498 + STV0130
MII USB ST8024 SMARTCARD
Cable tuner 2 x TSin Cable tuner
RJ11 HDMI
TMDS/I2C
STV0297E
I2C 30 MHz I2C LMI
E2PROM
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DDR2
FLASH EMI e-SATA RGB YC, CVBS Analog audio L/R STV641x
AUX/Loop-thru
HDD
SPI or UART Front panel display and controls KEYSCAN / PIOs
SPDIF
IR Tx/Rx
RESET
JTAG DCU
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MAFE
MAFE DAA
Description Figure 2. IP client

2x
STi7105
USB 2.0
Ethernet RJ45
MII PHY TMDS/I2C HDMI
Wi-fi module PCI FLASH EMI
I2C
E2PROM
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LMI DDR2 30 MHz Front panel display and controls KEYSCAN / PIOs
IR
RESET
JTAG DCU
Tx/Rx
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STi7105 Figure 3. High definition DVR satellite STB
Description
RJ45 2x USB 2.0 PHY MII
LNB H24 DiSEqC I2C MAFE STV6110 STV6110 MAFE/ DAA RJ11 HDMI ST8024 SMARTCARD
STV900D
TSin TSin
TMDS/I2C 30 MHz I2C
E2PROM
LMI
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NAND DDR2 FLASH
STi7105
YPbPr
Y Pb Pr
STV6440AJ
EMI YC, CVBS
Y C
e-SATA
CVBS Analog audio L/R Left Right SPDIF Audio
HDD
SPI or UART Front panel display and controls KEYSCAN / PIOs
IR Rx
UHF Tx/Rx
RESET
JTAG DCU
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Description Figure 4. Hybrid DTT/Broadband STB with DVR and Wi-fi home network
Ethernet RJ45 2x USB 2.0 PHY
STi7105
MII
TSin Tuner STV036x I2C
ST8024
SMARTCARD
TMDS/I2C
HDMI
30 MHz WiFi module PCI FLASH EMI I2C
E2PROM
STi7105
AUX/Loop-thru RGB LMI
DDR2 e-SATA
YC, CVBS Analog AUDIO L/R
STV641x
HDD
Front panel display and controls KEYSCAN / PIOs SPDIF
IR Tx/Rx
RESET
JTAG DCU
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System on chip subsystem overview

This section gives a top-level overview of the device components.
3.1
STBus interconnect
The STBus multipath unified interconnect provides high on-chip bandwidth and low latency accesses between modules. The interconnect operates hierarchically, with latency-critical modules placed at the top level. The multipath router allows simultaneous access paths between modules, and simultaneous read and write phases from different transactions to and from the modules. Split transactions maximize the use of the available bandwidth.
3.2
Processor core
The STi7105 integrates a 450 MHz ST40-300 processor core that features a 32-bit superscalar RISC CPU and IEEE-754 compliant floating point unit (FPU). The ST40-300 includes 2-way, set-associative caches and an interrupt controller with 15 user interrupt sources and an interrupt expansion port.
3.3
External memory interface (EMI)

The EMI is a general-purpose interface for attaching Flash memory and peripherals. The EMI features are: 5 banks

Addressing up to at least 64 Mbytes of NOR Flash External bus master support through BUSREQ/BUSGNT signals Slave Mode EMI support Single level cell (SLC) NAND Flash and boot from SLC NAND Flash Serial Flash support PCI interface, host and device selected on boot ATAPI PIO mode 4 DVB-CI+
3.4
Local memory interface (LMI)

The STi7105 integrates one 32-bit DDR2-DDR1 interface. The interface can run up to 400 MHz when configured in DDR2 mode or up to 250 MHz when in DDR1 mode. The LMI supports 16-bit and 32-bit configurations. The following 32-bit configurations are supported:

2 x 512 Mbits (x16) devices resulting in 128 Mbytes memory space 4 x 512 Mbits (x8) devices resulting in 256 Mbytes memory space 2 x 1 Gbits (x16) devices resulting in 256 Mbytes memory space 2 x 2 Gbits (x16) devices resulting in 512 Mbytes memory space
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3.5
3.5.1
STB transport subsystem

Overview
The transport subsystem (TS) is able to receive ATSC, DVB, DIRECTV, DCII, OpenCable, ARIB BS4 transport streams containing high definition (HD) and standard definition (SD) programs. It demultiplexes and descrambles the transport streams to deliver PES packets to the video and audio decoders.
Figure 5.
Transport subsystem block diagram Information classified Confidential - Do not copy (See last page for obligations)
Smartcard interface
PIO
Descrambler
PDES_IRQ
System interconnect
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Comms SC
PDES stream in / out PTI_IRQ
TSin0 (multiplexed) TSin1 or TSOUT (multiplexed)
Parallel / serial
PTI x2
TSbus in Parallel / serial Parallel / serial Serial
TSMerger
ALT-OUT* TSbus out CD_REQ SVP_MODE SWTS (playback stream)
TSin2 (multiplexed) TSin3 (multiplexed)
Parallel / serial
Transport subsystem
FDMA_REQ SWTS
FDMA x2
*Note: The ALT_OUT function is not usually supported in firmware. Contact STMicroelectronics for information if the ALT_OUT function is required by your application. Transport streams are input to the STi7105 through the four TS interfaces. Two of these interfaces (TSin0 and TSin2) are parallel inputs that can also be configured as serial inputs. The third interface is a bidirectional interface that can be configured as a third parallel input (TSin1) or a third serial input (TSin1), or can be configured as a parallel output(TSOUT). Also, a serial input interface (TSin3) is available if four TS inputs are required. The serial formats of each, TSin1 and TSin2, are available multiplexed with PIOs in two different locations to maximize the availability of chip functions for a given application.
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System on chip subsystem overview Transport streams can also be input to the STi7105 from network or HDD. These streams can be input through the MII, PCI, or USB interfaces (and e-SATA for HDD) buffered in memory and merged with the transport streams from the TS inputs. These merged TS streams are then forwarded to the PTIs for processing. Streams can also be output to a network or HDD.
3.5.2
Dual Programmable transport interface (PTI)

Each PTI is a dedicated transport engine and integrates its own CPU to handle the transport stream PID filtering, demultiplexing, descrambling, and data filtering. It interfaces with the programmable descrambler (PDES) for descrambling. Each PTI receives a transport stream from a dedicated input port, processes it, and outputs it either to the memory through its DMA channels or to a dedicated transport output port. The PTIs perform PID filtering, demultiplexing, descrambling, and data filtering on up to four transport streams. The PTIs extract PCRs with time stamps and make them available to the CPU for clock recovery and audio/video synchronization. PES data is transferred by DMA to memory buffers. Section data is transferred by DMA to separate buffers for further processing by the CPU. The PTIs extract indexing information and transfer packets, using DMA, to an intermediate buffer for writing to HDD.
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WMV9/WMA9 streaming content in ASF files using client server interaction parsing of MP3 or MPEG 4 AAC audio from Audio File format versions 2, 3 and 4 A/V streams, such as DivX, delivered in AVI files WAV and AIFF files
Each PTI performs PID filtering to select audio, video, and data packets to be processed. It supports up to 151 PID slots, and routes streams to and from the descrambler. Streams can be descrambled using: DES TDES AES Multi-2 DVB-CSA
NDS ICAM
The PTI has a 64 x 16 byte section filter core. Four filtering modes are available: wide match mode: 64 x 16 byte filters long match mode: 128 x 8 byte filters positive/negative mode: 64 x 8 byte filters with positive/negative filtering at the bit level APG filtering mode Matching sections are transferred to memory buffers for processing by software.
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The following transport streams are supported: AVS video MPEG2 transport stream demultiplexing, and service information extraction, conforming to: MPEG2 systems MPEG4 systems DVB DirecTV DSS format DirecTV AMC stream format MPEG2 TS audio/visual formats: MPEG2 A/V over MPEG2 TS H264 video over MPEG2 TS VC-1 over MPEG2 TS WMA9, WMA9 pro over MPEG2 TS AAC and AAC+ audio over MPEG2 TS A/V streams encapsulated in RTP packets according to these protocols (parsing): MPEG2 A/V in RTP MPEG 4 pt2 video in RTP MPEG 4 audio including AAC and AAC+ in RTP H264 video in RTP VC-1 video in RTP AVS video in RTP processing of:
STi7105
3.6
DVD decryption
CSS (DVD-video), CPRM (DVD-RW), and CPPM (DVD-audio) decryption is provided for the DVD stream.
3.7
Video decoder
The STi7105 video decoding subsystem includes the Delta-Rasta core capable of decoding H264/VC-1/MPEG2 HD/SD streams and AVS SD streams.

Supports non-real-time MPEG2 to H264 transcoding
The decoder is partially implemented in software which is executed on a dedicated ST231 CPU core. The decoder gets its data from memory and stores decoded data back into memory. The decoder uses a mixed hardware and firmware architecture with a hardwired data path and an ST231 core engine. It provides flexibility for firmware upgrades, error concealment, or trick modes. The ST231 core can be used for other coders or decoders at lower resolution, when the VC-1, H264, AVS SD, or MPEG2 decoders are not running. Streams are decoded picture-by-picture from an elementary stream buffer. Decoding, reconstruction, and prediction buffers are set up by the CPU. CPU control of bit-buffer pointers provides flexibility for trick modes and out-of-sequence decoding. Semantic or syntax errors are detected by the decoder and failing slices are replaced up to the next slice or picture.
3.8
Main and auxiliary display

The main and auxiliary display pipelines form a high-quality scaling engine for video display processing. The two display pipelines are shown in Figure 6.
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The following are Delta-Rasta features: Supports H264 in-loop deblocking filter, VC-1 deblocking filter and overlapped transform, AVS deblocking filter, and deblocking post processing algorithm for MPEG2
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System on chip subsystem overview Figure 6. Display pipelines block diagram

STBus LMI External SDRAM
STi7105
Main display
DEI HD
VHSRC
IQI
Pixel FIFO
YUV
Compositor Auxiliary display
Analog and digital outputs
SD/HD
VHSRC
Pixel FIFO
YCrCb
The same video is displayed through both displays, but each display processor can be set up to format the video differently and display video with different timing. Separate video timing generators (VTGs) are provided to support this feature. The display processors adapt the decoded video to a format suitable for display, taking into account differences in scanning method, resolution, aspect ratio, and scanning frequency. The main-display processor receives decoded or acquired video from memory, and performs block-to-line conversion, pan and scan, and vertical and horizontal format conversion. There is also a de-interlacer (DEI) to perform interlace-to-progressive conversion using motion estimation. This is used to display 480i, 576i, or 1080i interlaced sources on a progressive display (480p, 720p, or 1080p). The main display processor has IQI that improves the subjective image quality by methods, such as high frequency peaking and edge sharpening. The auxiliary-display processor receives decoded or acquired (and possibly decimated) video, and performs pan and scan, vertical format conversion, horizontal format conversion and color tint and saturation control. The output line size is limited to SD on the auxiliarydisplay processor and is intended to output video for VCR recording.
3.9
3.9.1
Compositor
Overview
The compositor comprises two real-time, multiplane digital mixers.
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System on chip subsystem overview The main mixer (mixer A), which is intended for main HDTV video output, is composed of: one background color two video planes three graphics planes one cursor plane The auxiliary mixer (mixer B), which is intended for auxiliary SDTV video output, is composed of: one background color the video 2 plane the graphics 3 plane The compositor receives the video planes from the video display processor, and the 2D graphics planes from the memory through GDP. Each mixer alpha blends graphics and video layers on a pixel basis based on alpha component values provided by each layer. After real-time processing by the display plane pipelines, pixel data is mixed in mixer A or mixer B. The output of mixer A supports up to full HD resolutions and is intended as the main TV display (Figure 7). The output of mixer B (Figure 8) supports up to full SD resolutions and is intended as an auxiliary display for applications, including connection to a VCR. The mixer outputs are fed to the STi7105s output stage. The mixers provide RGB and/or YCbCr digital outputs that are used by the video output subsystem to produce the HDTV video outputs (analog, digital, and composite) and the SDTV video outputs (analog and digital).
Figure 7.
Mixer A planes
Background color GDP 1 VID 1 VID 2 GDP 2 GDP 3
Cross-bar router
cursor
Channel 5
Replay
Score
Stats
Replay
Score
Stats
Channel 5
The compositor also comprises additional components that can be used to enhance the display presentation of video and graphics. These include an alpha plane attachment and a
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cross-bar router. A capture pipeline is also provided for capturing main video streams or mixer A or B output streams and storing them in memory. Figure 8. Mixer B planes
Background color VID2 GDP3 Information classified Confidential - Do not copy (See last page for obligations)
Cross-bar router
Confidential
3.9.2
Compositor layout
Figure 9 shows a block diagram of the compositor. It presents the dataflow and memory access of all the compositor modules. The graphics and cursor pipelines read pixel data and related control information directly from memory. The video input pipelines accept data from the main and auxiliary video display pipelines. Video and graphics data (captured for the compositor data flow by the capture pipeline) is written back to memory with a resolution up to 32 bits/pixel. The realtime processing performed by each pipeline is controlled by register programming. Digital mixer A successively blends video layers VID1, VID2, graphics layers (GDP1, GDP2, and GDP3), the cursor layer (CUR), and a background color. A cross-bar router enables the hierarchy of the GDP1, GDP2, GDP3 and VID1, VID2 layers to be programmed. Each layer can be independently enabled or disabled. The blending operates in the RGB color domain, so each layer supplies an RGB signal (3x12 bits), with transparency information that provides the weighting coefficients for the mixing operation at a given depth. Digital mixer B successively blends one video layer (VID2) with one graphics layer (GDP3) and a background color. A cross-bar router enables the hierarchy of the GDP3 and VID2 layers to be programmed. In Digital mixer B, each layer can be independently enabled or disabled, and blending operates in the RGB color domain. All sub-blocks are controlled by hardware registers. All these registers can be read but not necessarily written. The graphics planes are link-list based and have their register set written through the memory (register download is controlled directly by the hardware after initialization). All other registers can be written. Each plane block supports a specific set of bitmap formats. Each plane starts reading data from memory when it is enabled in mixer A or mixer B.
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STi7105 Figure 9. Graphics and video subsystem block diagram
Compositor BKC
Video display
VID1
YCbCr 4:4:4 3x10 bits
STBus
9-channel digital mixer
Alpha attachment
GDP2 GDP3
RGB 4:4:4 3x10 bits
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Cross-bar
CUR Mixer A main CAP
Alpha attachment
YCbCr 4:4:4 3x8 bits 3-channel digital mixer
Auxiliary video display
VID2 BKC Mixer B auxiliary
RGB 4:4:4 3x8 bits
3.10
Video output
The Video Output subsystem is the unit responsible for reading decoded video frames and graphics data from external memory to reformat, rasterize, and mix them for display. The STi7105 can output video program on main HD TV Out and on aux SD TV (VCR) Out with separate timebase if required (VTG0, VTG1). It is also able to deliver the same SD video on both main and auxiliary video outputs using the capture feature. The main data paths corresponding to these typical configurations are shown in Figure 10 as well as the principal units which constitute the Video Output Stage.
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Analog and digital outputs
RGB 4:4:4:4 32-bit
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Output stage
System on chip subsystem overview Figure 10. Video output stage block diagram
STi7105
Main HD stream Audio from sub audio
Analog HD 3x VDac HDMI Dig Out Digital HD Digital video SD/HD Digital graphic/video SD/HD HD TV
From compo pass through
Aux SD stream
3x VDac
Analog SD SCART SD TV (VCR)
7105 VIDEO OUT
3.10.1
Main HDTV video output

The following are the main functional blocks included in the main video flow: Main VDP, including High Definition Display Pipeline with IQI and DEI engines VTG0 (free running or master of the aux VTG1) Capture output port with vertical and horizontal resizing, shared with auxiliary video flow
CompositorMixer five to four (in: video: RGB or YCbCr, 3x graphic: RGB; out: 2x video: RGB and YCbCr, pass through, capture), shared GDP3 and VDP aux with auxiliary compositor TV Outreceives its data from the compositor channel (video: RGB or YCbCr, graphic: RGB); the video data is then formatted and output in digital and analog and audio-video composite to be used by external devices DVI-HDCP or HDMI compliant copy-protected digital output Player multichannel (8-ch) and GP FIFO S/PDIF Player and GP FIFO Four S/PDIF Players with I2S to S/PDIF converters Triple HD/SD DAC (analog output) Two digital video outputs, i.e., DVO0 (video) is 8-bit or 16-bit and DVO1(GFX) is 24-bit AWGarbitrary waveform generator (Dwight Cavendish and Macrovision copy protection support)
Note:
The compositor includes a pipeline, which is able to mix one cursor, one or two video, up to three graphic layers, and one background layer. The data is then delivered to the TV Out. The capture port supports vertical and horizontal resizing output data with filtering for upsizing.
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3.10.2
Auxiliary SDTV video flow

The following are the main functional blocks included in the auxiliary video flow: VTG1free running or slave of the main HDTV VTG0 Video Display Pipe High-definition (VDP aux) Capture output port with vertical and horizontal resizing, shared with main HDTV video flow

Note:
The Compositor includes a pipeline, which is able to mix one video, one graphic layer, and one background layer. The data is then delivered to the TV Out. The capture port supports vertical and horizontal resizing output data with filtering for upsizing.
3.11
2D blitter display engine

The 2D blitter display engine (BDisp 2 engine) is a software controlled output display generator, which can also be used as a CPU accelerator for graphics picture handling. The BDisp 2 engine, is an evolution of BDisp engine. It is a triple-source 2D DMA, with a set of powerful operators. The 2D blitter display engine retrieves data from the local memory through three input sources, source 1, source 2, and source 3. Sources 1, 2, and 3 are used simultaneously for read/modify/write operations.
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Compositormixer two to three (YCbCr 8-bit and RGB 8-bit and capture), shared GDP3, and VDP aux with main HDTV compositor SD DENCSDTV/VCR Video Encoder AWGarbitrary waveform generator (Dwight Cavendish and Macrovision copy protection support) Triple HD/SD DAC (analog output)The DAC outputs can be components (Y/C) or composite (PAL, SECAM, NTSC CVBS); all 6 DACs can output the auxiliary display in SD format for SCART output
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2D blitter display engine functions are as follows: Solid color fill of rectangular window Solid color shade (fill and alpha blending) 1 source copy, with one or several operators enabled (color format conversion, 2D scaling)

2 source copy with alpha blending 4:2:2 / 4:20 capabilities, as source format Fully programmable matrix used for color space conversion, PSI, special effects Color expansion (CLUT to true color) Color correction (gamma, contrast, gain) 2D resize engine with high quality filtering Adaptive flicker filter from memory-to-memory Rectangular clipping VC-1 range mapping/range reduction compensation algorithm Programmable source/target scanning direction, both horizontally and vertically, to cope correctly with overlapping source and destination area.
3.12
Audio subsystem
Overview
The main function of the STi7105 Audio subsystem is to decode and play different standards of multi-channel compressed audio streams. The audio stream (encoded or decoded) is received either from an external source through the PCM input interface or an internal source, such as the Transport subsystem through memory.
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2D blitter display engine features are as follows: 2 composition queues 4 application queues Subbyte S1 and S2 access 5-tap vertical filters 8-tap horizontal filters Flicker filter adaptative Matrix conversion on input and output for: rgb2ycbcr, ycbcr2rgb,bt601, and bt709 CLUT 1/2/4/8 Color reduction Logical operation Clipmask Rotation Plane mask Color key capability BlueRay Disc run-length decoder (BD RLD) High definition-DVD 2/8-bit run-length decoder (HD-DVD RLD)
STi7105
System on chip subsystem overview The audio decoder may have to decode simultaneously two different encoded audio streams when an audio description channel is provided (the main audio stream and a 2channel audio description channel) or when recording and listening to two different audio streams.
PCM mixing
The decoded audio stream can be mixed with a PCM file stored in memory following an optional sample rate conversion to adapt the sampling rate of the two streams. PCM mixing is also used when a description channel is decoded and then mixed with the main audio stream. The PCM mixing is fully implemented in the software running on the ST231. Information classified Confidential - Do not copy (See last page for obligations)
PCM output: downmixing

The multi-channel decoded PCM stream can be downmixed to generate a 2-channel PCM stream. This down mixed stream can be then output unmixed through a stereo 24-bit DAC while the PCM-mixed decoded audio stream can be delivered onto a 6-channel digital PCM output and a digital S/PDIF output.
Compressed data: S/PDIF output
Confidential
Compressed audio data can also be delivered on the S/PDIF output to be decoded by an external decoder/amplifier.
HDMI output
The STi7105 HDMI output can deliver audio data to an HDMI sink device. The audio data is delivered by the audio subsystem to the HDMI subsystem through internal I2S-S/PDIF players/converters (see Figure 11).
Audio decoder features

The audio decoder features are as follows: Decoding of the following audio formats: MPEG1 layer I/II, MP3, MPEG2- Layer II, Dolby Digital, Dolby Digital Plus (up to 7.1), MPEG4 AAC-LC, MPEG4 AACplus (HEAAC, AAC+SBR) v1 and v2 (up to 5.1), WMA9, WMA9pro (up to 7.1) PCM mixing with internal or external source with sample rate conversion (32, 44.1, 48 kHz)

Encoded (IEC 61937) or decoded (IEC 60958) digital audio on S/PDIF output Multi-channel down-mixing for output over HDMI (up to 8 channels), PCM output (up to 6 channels), and analog output (up to 2 channels) PCM audio input (I2S format) Audio description channel decoding Postprocessing (channel virtualization)Dolby Prologic downmix, volume control, and bass redirection
Audio transcoding
The STi7105 supports the transcoding of advanced audio formats for output over S/PDIF as formats recognized by external audio decoders. The following two transcode operations are available:

Dolby Digital Plus to Dolby Digital MPEG4 AACplus to DTS
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Audio subsystem blocks

The audio subsystem includes the following functional units. One audio processor ST231 core, running at 450 MHz, which executes the decoding algorithms, the sample-rate conversion, the post-processing and the volume control. One PCM reader, which captures the data at the PCM input and stores it in memory through an FDMA channel. (This is mutually exclusive with PCM player 0 since they share the same pads.) Two PCM players, which get decoded PCM data from memory through FDMA channels. One PCM player delivers the down-mixed PCM output to the audio DAC. The other PCM player produces the stereo or multi-channel decoded audio stream on a 7wire PCM output (I2S protocol).
Two quad-frequency synthesizers, which generate the PCM clock (oversampling clock 256 x Fs), used by the S/PDIF, PCM players, and audio DAC. One synthesizer clocks the S/PDIF, one clocks the PCM player associated to the audio DAC and one clocks the PCM player associated to the PCM output. One stereo 24-bit audio DAC with differential outputs. An S/PDIF player, which reads decoded PCM data or encoded data from memory through an FDMA channel, and outputs them on the S/PDIF output.
See Figure 11 for a detailed block diagram of the audio subsystem.
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STi7105 Figure 11. Audio subsystem block diagram
2-channel PCM reader 0 2-channel PCMI
Ch 0/1
2-channel
2-channel PCM ST Bus multi-channel PCM player 0 8-channel PCM
Audio DACs
6-channel PCMO
Ch 0/1 Ch 2/3 Ch 4/5
HDMI Audio
Audio ST231
4 x I2S to S/PDIF conversion Compressed audio
Multi-channel PCM (up to 8-ch) 2-ch PCM or compressed audio S/PDIF
HDMI audio
S/PDIF player
IEC 60958 IEC 61937
The host CPU and the FDMA assist in the audio decoding process. Since the audio decoder is a frame decoder, the host CPU (ST40 core) controls the audio processor frame by frame. A mailbox is used for communication between the two processors. The host CPU is also required to do the PES parsing and the frame syncword detection. The FDMA builds the ES buffer to feed the PCM and S/PDIF players, and stores the data captured by the PCM reader in memory. The PCM reader, PCM player, and S/PDIF player transfer data to/from memory through FDMA.
3.13
FDMA controllers
The STi7105 has two multichannel, burst-capable, direct memory access controllers: FDMA0real-time paced channels: S/PDIF, PcmPlayer 0-1, and SWTS FDMA1PES Parsing, PCI-Master, SWTS when streaming from Ethernet or USB, UART, SSC, and free-running general purpose DMAs
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L R
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System on chip subsystem overview External pacing signals are available for DMA transfers with external peripherals.
STi7105
3.14
3.14.1
Interfaces
Internal peripherals
The STi7105 has many dedicated internal peripherals, including: 4 ASCs (UARTs), two of which are generally used by the smartcard controllers, one to support hardware flow control signals 2 smartcard interfaces and clock generators 4 external SSCs for I2C/SPI master/slave interfaces 1 four-channel PWM module with 2 PWM outputs and programmable frequency 1 teletext serializer 17 GPIO ports (3.3 V tolerant)

1 modem analog front end (MAFE) interface 1 single infrared transmitter/receiver supporting RC5, RC6 and RECS80, RC-MM 1.5, DIRECTV and Echostar codes 1 UHF remote control digital input 1 interrupt level controller with external interrupt inputs 2 independent USB 2.0 host controllers each with its own integrated PHY 1 front panel key scanning support 1 e-SATA interface
3.14.2
Ethernet controller
The STi7105 has an integrated Ethernet controller and MAC processor for delivery of IP based A/V streams in hybrid IP STBs and for home network connectivity. It also includes an MII/RMII port for connection to an external PHY. Ethernet features are as follows:

Half/full duplex, full duplex flow control VLAN tagging support MII and RMII external interface Direct interface with STE101P and similar PHYs through MII or RMII Able to accept clock from external PHY/Home network Device in MII mode Dedicated scatter/gather link list DMA 100 Mbits/s sustained transfer rates to and from memory 32 H/W perfect match MAC address filters
The controller can also be used to interface through overclocked MII interface (up to 300 Mbits/s) to an external non-Ethernet Phy as a MoCA Phy for example.
3.14.3
Dual smartcard interfaces

Both smartcard interfaces are ISO7816, EMV2000 and NDS compliant, with the addition of a simple external power switch. A programmable hardware power control feature allows the power control signal to be switched when card insertion or removal is detected.
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3.15
Clock generation
The STi7105 features five clock generation blocks: ClockGen A: 2 x PLLs main for CPU and interconnect clocks ClockGen B: 2 x FreqSynth for video, display and peripheral clocks ClockGen C: 1 x FreqSynth for audio clocks ClockGen D: 1 x PLL for memory clocks
3.16
System services
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The STi7105 supports a number of on-chip system service functions including: integrated VCXOs (DCOs) for clock recovery debug through a single JTAG port reset and watchdog controller two power saving modes: reduced power mode and low power/standby mode
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Package mechanical data
STi7105
4
4.1

27 x 27 package
Package type: PBGA 620 balls. Body: 27 x 27 mm. Figure 12. Top view
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STi7105 Figure 13. Bottom view
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Package mechanical data Table 1. Dimension

A A1 A2 A3 A4 b D D1 D2 E E1 E2 26.80 0.45 26.80 0.27 1.72 0.52 1.20 0.50 27.00 24.80 24.00 27.00 24.80 24.00 0.80 1.10 0.20 0.15 0.08 27.20 1.055 0.55 27.20 0.0177 1.055
STi7105
JEDEC standard package dimensions Millimeters Min Typ Max

2.19 0.0106 0.0677 0.0205 0.0472
Inches Min Typ Max

0.8622
Notes
(1)
1.063 0.9764 0.9449 1.063 0.9764 0.9449 0.0315 0.0433
1.070
1.070
e F ddd eee fff
0.0079 0.0059 0.0315

(3) (4)
1. FPBGA stands for Fine pitch Plastic Ball Grid Array. Fine pitch: e < 1.00 mm The total profile height (Dim A) is measured from the seating plane to the top of the component. The maximum total package height is calculated by the following methodology: A2 Typ+A1 Typ + V (A1+A3+A4 tolerance values) 2. The typical ball diameter before mounting is 0.50mm. 3. The tolerance of position that controls the location of the pattern of balls with respect to datums A and B. For each ball there is a cylindrical tolerance zone eee perpendicular to datum C and located on true position with respect to datums A and B as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone 4. The tolerance of position that controls the location of the balls within the matrix with respect to each other. For each ball there is a cylindrical tolerance zone fff perpendicular to datum C and located on true position as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone. Each tolerance zone fff in the array is contained entirely in the respective zone eee above. The axis of each ball must lie simultaneously in both tolerance zones. The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or metallized markings, or other feature of package body or integral heatslug. A distinguishing feature is allowable on the bottom surface of the package to identify the terminal A1 corner. Exact shape of each corner is optional.
4.2
Environmentally friendly packages

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.
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0.0217
(2)
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BGA footprint and pin lists
5
5.1

Ball grid array
The ball grid array (BGA) diagrams give the allocation of pins to the package, shown from the top looking down using the PCB footprint. Signal names are prefixed by NOT if they are active low; otherwise they are active high. Some signal names in BGA diagrams have been abbreviated. Cross refer with Table 3: Pin list on page 42 for the full signal names. Table 2.
Function Transport PIO/peripheral Video Audio
Key to BGA diagrams

Type SIG SIG SIG SIG SIG SIG VCC/VDD VSS/GND NC Key
System (JTAG, interrupts) Memory (EMI, LMI) Power Ground No connect No ball
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BGA footprint and pin lists Figure 14. Top-left quadrant

1 A B C D E F G
NOTTRST
STi7105
8
LMIDATAM ASK[2]
10
11
12
13
14
15
16
17
NOTLMICL LMIDATA[2 K[1] 1]
LMIADDR[ NOTLMICL 11] K[0]
TDO
TDI
LMIDATA[1 LMIDATA[1 8] 6]
LMIDATAM NOTLMIC ASK[3] S[0]
LMIBA[2]
LMIADDR[ LMICLK[0] 13]
TCK
TMS
LMICLK[1]
LMIDATA[2 LMIDQS[2] 3]
LMIDATA[3 LMIDQSN[ NOTLMIC LMIDATA[2 1] 3] AS 5]
LMIADDR[ LMIADDR[ LMIDUMM LMIADDR[ 8] 6] Y[1] 12]
PIO7[0]
PIO7[1]
PIO7[2]
NOTLMIC LMIDQSN[ LMIDATA[2 LMI_GND1 NOTLMIR LMIDATA[2 LMIDATA[2 LMIDQS[3] S[1] 2] 6] V8 AS 7] 2]
LMIBA[0]
LMIADDR[ LMIDUMM LMI_GND1 LMI_GND1 2] Y[0] V8 V8
PIO6[1]
PIO6[2]
PIO6[0]
LMICLKEN LMIDATA[2 [1] 4]
ODT[0]
LMI_GND1 LMI_GND1 LMIDATA[3 LMIDATA[1 LMIDATA[2 LMIADDR[ LMI_GND1 LMI_GND1 LMI_GND1 LMIBA[1] V8 V8 0] 7] 0] 4] V8 V8 V8
PIO6[4]
PIO6[5]
PIO6[3]
LMIDATA[2 LMIPLL_A LMIPLL_A LMI_GND1 LMIDATA[2 LMIDATA[1 LMIVREF[ LMI_GND1 LMI_GND1 LMI_GND1 LMI_GND1 VDD1V2 9] GND2V5 GND1V2 V8 8] 9] 1] V8 V8 V8 V8
PIO6[7]
PIO6[6]
PIO7[3]
VDD1V2
VDD1V2
LMIPLL_A LMIPLL_A LMI_GND1 LMI_GND1 LMIADDR[ VDD1V8_2 LMI_GND1 LMI_GND1 LMI_GND1 LMI_GND1 VDD2V5 VDD1V2 V8 V8 0] V5 V8 V8 V8 V8
H J K L M N P R T U V W Y
PIO13[2]
PIO13[3]
PIO13[0]
VDD3V3
VDD3V3
VDD3V3
PIO12[6]
PIO12[5]
PIO13[1]
VDD3V3
VDD3V3
PIO12[2]
PIO12[4]
PIO12[0]
PIO12[7]
VDD1V8_2 VDD1V8_2 VDD1V8_2 V5 V5 V5
PIO12[1]
PIO14[7]
PIO12[3]
DGND
DGND
VDD1V8_2 VDD1V8_2 V5 V5
PIO14[4]
PIO14[6]
DGND
DGND
DGND
VDD1V8_2 VDD1V2 V5
VDD1V2
VDD1V8_2 VDD1V8_2 V5 V5
PIO14[2]
PIO14[1]
PIO14[5]
DGND
DGND
DGND
DGND
VDD1V2
VDD1V2
VDD1V2
PIO13[6]
PIO14[0]
PIO13[4]
PIO14[3]
VDD1V2
DGND
DGND
VDD1V2
VDD1V2
PIO13[5]
NOTEMIC CKGA1_D CKGA0_D PIO13[7] SA GND1V2 GND1V2
VDD1V2
VDD1V2
DGND
DGND
DGND
DGND
NOTEMIC NOTEMIC NOTEMIC CKGA0_A CKGA1_D CKGA0_D SC SB SE GND2V5 VDD1V2 VDD1V2
VDD3V3
VDD1V2
VDD1V2
DGND
DGND
DGND
NOTEMIC EMIFLASH NOTEMIB CKGA1_A CKGA1_A CKGA0_A SD CLK AA GND2V5 VDD2V5 VDD2V5
VDD3V3
VDD1V2
VDD1V2
DGND
DGND
DGND
EMITREA EMIADDR[ EMIADDR[ EMIADDR[ EMIADDR[ DYORWAI 3] 2] 4] 5] T
VDD1V2
VDD1V2
DGND
DGND
VDD1V2
DGND
EMIADDR[ EMIADDR[ EMIADDR[ EMIADDR[ 7] 1] 12] 6]
VDD1V2
DGND
DGND
VDD1V2
DGND
EMIADDR[ NOTEMIO EMIADDR[ 10] E 11]
VDD3V3
VDD3V3
DGND
DGND
VDD1V2
VDD1V2
DGND
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STi7105 Figure 15. Top-right quadrant

18 19 20 21 22 23 24 25
LMIDQS[0]
26
27
28
29
30
31
32 A B C D E F
WDOGRS SYSITRQ[ SYSITRQ[ SYSITRQ[ TOUT 3] 1] 0]
LMIDATA[2 ]
LMIDQSN[ LMIDQSN[ 1] 0]
LMIDATA[3 NOTASEB SYSITRQ[ TRIGGERI NOTRESE ] RK 2] N TIN
LMIDATA[0 LMIADDR[ ] 9]
LMICLKEN LMIDATA[1 LMIDATA[1 LMIDATA[6 LMIDATA[4 TRIGGER SYSCLKIN LMIDQS[1] [0] 4] 1] ] ] OUT ALT
NMI
SYSCLKO UT
LMIDATA[5 LMIADDR[ LMIDATA[1 ] 7] 0]
LMIADDR[ NOTLMIW LMIDATAM LMIDATA[9 LMIDATA[1 VDD3V3 1] E ASK[1] ] ]
NC
PIO16[2]
PIO16[4]
PIO16[3]
VDD1V8_2 LMIDATA[7 LMIDATA[1 LMIADDR[ V5 ] 3] 3]
ODT[1]
LMIDATAM VDD3V3 ASK[0]
VDD3V3
LMIDATA[1 LMIVREF[ PIO11[7] 2] 0]
PIO16[1]
PIO16[0]
VDD1V8_2 VDD1V8_2 LMIADDR[ LMIDATA[1 LMIADDR[ VDD1V8_2 LMI_COM GND_SEN VDD3V3 PIO11[4] V5 V5 5] 5] 10] V5 P_GND SE
PIO11[6]
PIO11[5]
VDD1V8_2 VDD1V8_2 VDD1V8_2 LMIDATA[8 VDD1V8_2 VDD1V8_2 LMI_COM VDD_SEN VDD3V3 VDD1V2 V5 V5 V5 ] V5 V5 P_REF SE
PIO16[7]
PIO11[3]
PIO11[2]
G
PIO15[6] PIO15[7]
VDD2V5
VDD1V2
VDD1V2
PIO16[6]
H J K L M
FDMAREQ PIO16[5] [3]
PIO9[7]
DAA_C2A DAA_C1A
DGND
DGND
DGND
PIO5[3]
FDMAREQ FDMAREQ FDMAREQ [2] [0] [1]
DGND
DGND
DGND
VDD3V3
PIO5[0]
PIO5[2]
PIO5[1]
VDD1V2
VDD1V2
DGND
DGND
DGND
VDD3V3
PIO4[6]
PIO4[7]
VDD1V2
DGND
DGND
DGND
VDD3V3
PIO4[3]
PIO4[5]
PIO4[4]
N
PIO4[1]
DGND
DGND
VDD1V2
DGND
PIO4[2]
PIO4[0]
P
PIO3[6]
DGND
DGND
VDD1V2
VDD1V2
VDD2V5
VDD1V2
PIO3[5]
PIO3[7]
R
PIO5[7]
DGND
DGND
VDD3V3
VDD3V3
CKGB1_D CKGB1_D GND1V2 VDD1V2
DGND
PIO3[4]
PIO5[6]
T U V W Y
DGND
DGND
VDD3V3
VDD3V3
CKGB0_A CKGB1_A VDD2V5 VDD2V5
DGND
PIO5[4]
PIO2[7]
PIO5[5]
DGND
DGND
VDD1V2
VDD1V2
CKGB0_D CKGB_AG GND1V2 ND2V5
PIO2[4]
PIO2[6]
PIO2[5]
DGND
DGND
DGND
CKGB0_D VDD1V2
PIO2[3]
PIO2[1]
PIO2[2]
VDD1V2
DGND
DGND
DGND
DGND
PIO1[6]
PIO2[0]
PIO1[7]
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BGA footprint and pin lists Figure 16. Bottom-left quadrant

AA AB AC AD AE AF AG AH
EMIADDR[ EMIRDNO 13] TWR VDD3V3 VDD3V3 DGND DGND VDD1V2 VDD1V2
STi7105
VDD1V2
DGND
EMIADDR[ EMIADDR[ EMIADDR[ 8] 16] 14]
VDD3V3
DGND
DGND
DGND
EMIADDR[ EMIADDR[ NOTEMIB EMIADDR[ 9] 18] E[0] 17]
DGND
DGND
DGND
EMIADDR[ EMIADDR[ EMIADDR[ EMIBUSR VDD1V2 21] 22] 20] EQ
NOTEMIB EMIADDR[ EMIBUSG VDD1V2 E[1] 15] NT
VDD1V2
VDD1V2
EMIADDR[ EMIDATA[2 EMIADDR[ VDD1V2 25] ] 24]
PIO9[4]
PIO9[6]
PIO8[3]
ANA1_VD ANA1_VD CKGC_AV CKGC_AG PIO10[0] D2V5 D2V5 DD2V5 ND2V5
VDD3V3
SATAVSS
NC
NOTEMILB NANDWAI EMIADDR[ PIO9[3] A T 19]
PIO8[4]
PIO10[7]
ANA1_GN CKGC_DG AUDA_DV CKGC_DV SATAVDD PIO10[4] VDD3V3 SATAVDDT D2V5 ND1V2 DD1V2 DD1V2 R
EMIDATA[1 EMIDATA[6 EMIDATA[1 PIO15[5] 1] ] 3]
PIO7[7]
DGND
ANA1_GN D2V5
PIO8[5]
PIO9[5]
AUDA_DG PIO11[1] ND1V2
PIO10[1]
VDD3V3
VDD3V3
DGND
AJ AK AL AM
EMIDATA[1 EMIDATA[1 EMIADDR[ PIO15[2] 5] 4] 23]
PIO7[6]
PIO9[2]
DGND
PIO8[6]
PIO10[5]
PIO10[6]
PIO11[0]
PIO10[2]
DGND
DGND
DGND
EMIDATA[4 EMIDATA[1 EMIDATA[7 EMIDATA[5 PIO15[4] ] ] ] ]
PIO8[1]
PIO8[2]
PIO7[5]
PIO7[4]
PIO9[0]
PIO10[3]
AUDA_RIG AUDA_GN HTOUTN DAS
DGND
EMIDATA[8 EMIDATA[3 EMIDATA[1 PIO15[1] ] ] 0]
PIO15[3]
PIO8[0]
PIO8[7]
AUDA_RIG AUDA_IRE AUDA_LEF HTOUTP F TOUTN
EMIDATA[0 EMIDATA[1 EMIDATA[9 PIO15[0] ] 2] ]
PIO9[1]
AUDA_VB AUDA_LEF GOUT TOUTP
10
11
12
13
14
15
16
17
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STi7105 Figure 17. Bottom-right quadrant

VDD1V2 VDD1V2 DGND DGND DGND DGND PIO1[4] PIO1[5]
AA
PIO1[2]
VDD1V2
DGND
DGND
DGND
PIO1[1]
PIO1[3]
AB
PIO0[7]
VDD1V2
DGND
HDMI_GN D3V3
HDMIPLL_ PIO1[0] AVDD1V2
PIO0[6]
AC
PIO0[4]
HDMIPLL_ HDMIPLL_ PIO0[3] AGND1V2 AGND2V5
PIO0[5]
AD
PIO0[1]
ANA2_VD HDMIPLL_ ANA2_GN DE2V5 AVDD2V5 DE2V5
PIO0[2]
PIO0[0]
AE AF AG AH AJ AK AL AM
SATAVDD_ PLL
NC
SATAVDD2 USB_GND USB_VDD USB_VDD TMDS_GN HDMI_VD THS_AVD GNDSATA _PLL 2V5 1V2 1V2 D D3V3 D2V5
PIO3[3]
PIO3[0]
PIO3[2]
USB_GND SATAVSS_ USB_VDD SATARXN 2V5 PLL 2V5
REXT
USB_GND TMDS_VD TMDS_GN TMDS_GN VIDA0_GN VIDA1_GN VIDA1_YO PIO3[1] 1V2 D1V2 D D DAS DA1 UT
DGND
SATAREF SATATXN SATARXP
SYSCLKO USB1VDD TMDS_VD TMDS_VD TMDSTX1 TMDSTX2 HDMI_CE VIDA1_GN VIDA1_ID VIDA1_CV SC B3V3 D1V2 D1V2 N N C DA2 UMP OUT
NC
NC
SATATXP
SYSCLKIN USB1DP
USB2VDD HDMI_VD TMDSTX0 TMDSTX1 TMDSTX2 VIDA0_GN VIDA1_GN VIDA1_VC VIDA1_CO B3V3 D1V2 N P P DA1 DAS CA1 UT
NC
NC
USB1DM
USB2DP
TMDSTXC TMDSTX0 P P
VIDA0_MA VIDA0_GN VIDA0_VC VIDA1_VC VIDA1_RE SSQUIET DA2 CA2 CA2 XT
NC
USB2DM TMDSREF
VIDA0_RE VIDA0_VC VIDA0_ID VIDA1_MA XT CA1 UMP SSQUIET
TMDSTXC N
VIDA0_BO VIDA0_RO VIDA0_GO UT UT UT
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
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STi7105
5.2
5.2.1
Pin lists
Full pin list sorted by pin number
Table 3. Pin list
Net name NOTTRST NOTLMICLK[1] LMIDATA[21] LMIDATAMASK[2] LMIADDR[11] NOTLMICLK[0] LMIDQS[0] WDOGRSTOUT SYSITRQ[3] SYSITRQ[1] SYSITRQ[0] TDO TDI LMIDATA[18] LMIDATA[16] LMIDATAMASK[3] NOTLMICS[0] LMIBA[2] LMIADDR[13] LMICLK[0] LMIDATA[2] LMIDQSN[1] LMIDQSN[0] LMIDATA[3] NOTASEBRK SYSITRQ[2] TRIGGERIN NOTRESETIN TCK TMS LMICLK[1]
Pin number A1 A2 A3 A8 A16 A17 A25 A29 A30
A31 A32 B1 B2 B3 B4 B8 B9 B15 B16 B17 B18 B24 B25 B28 B29 B30 B31 B32 C1 C2 C3
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STi7105 Table 3. Pin list (continued)

Net name LMIDATA[23] LMIDQS[2] LMIDATA[31] LMIDQSN[3] NOTLMICAS LMIDATA[25]
Pin number C4 C5 C7 C8 C9 C10 C14 C15 C16 C17 C18 C19
LMIADDR[6] LMIDUMMY[1] LMIADDR[12] LMIDATA[0] LMIADDR[9] LMICLKEN[0] LMIDQS[1] LMIDATA[14] LMIDATA[11] LMIDATA[6] LMIDATA[4] TRIGGEROUT SYSCLKINALT NMI SYSCLKOUT PIO7[0] PIO7[1] PIO7[2] NOTLMICS[1] LMIDQSN[2] LMIDATA[26] LMIDQS[3] LMI_GND1V8 NOTLMIRAS LMIDATA[27] LMIDATA[22] LMIBA[0] LMIADDR[2]
Confidential
C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D13 D14
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LMIADDR[8]
BGA footprint and pin lists Table 3. Pin list (continued)

Net name LMIDUMMY[0] LMI_GND1V8 LMI_GND1V8 LMIDATA[5] LMIADDR[7] LMIDATA[10]
STi7105
Pin number D15 D16 D17 D18 D19 D20 D22 D23 D24 D25 D26 D27
NOTLMIWE LMIDATAMASK[1] VDD3V3 LMIDATA[9] LMIDATA[1] NC PIO16[2] PIO16[4] PIO16[3] PIO6[1] PIO6[2] PIO6[0] LMICLKEN[1] LMIDATA[24] ODT[0] LMI_GND1V8 LMI_GND1V8 LMIDATA[30] LMIDATA[17] LMIDATA[20] LMIADDR[4] LMIBA[1] LMI_GND1V8 LMI_GND1V8 LMI_GND1V8 VDD1V8_2V5 LMIDATA[7] LMIDATA[13]
Confidential
D28 D29 D30 D31 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20
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LMIADDR[1]

Net name LMIADDR[3] ODT[1] LMIDATAMASK[0] VDD3V3 VDD3V3 LMIDATA[12]
Pin number E21 E22 E23 E24 E25 E26 E27 E28 E29 E30 F3 F4
PIO11[7] PIO16[1] PIO16[0] PIO6[4] PIO6[5] PIO6[3] LMIDATA[29] VDD1V2 LMIPLL_AGND2V5 LMIPLL_AGND1V2 LMI_GND1V8 LMIDATA[28] LMIDATA[19] LMIVREF[1] LMI_GND1V8 LMI_GND1V8 LMI_GND1V8 LMI_GND1V8 VDD1V8_2V5 VDD1V8_2V5 LMIADDR[5] LMIDATA[15] LMIADDR[10] VDD1V8_2V5 LMI_COMP_GND VDD3V3 GND_SENSE PIO11[4]
Confidential
F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27
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LMIVREF[0]

Net name PIO11[6] PIO11[5] PIO6[7] PIO6[6] PIO7[3] VDD1V2
STi7105
Pin number F28 F29 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12
LMIPLL_AVDD2V5 LMIPLL_AVDD1V2 LMI_GND1V8 LMI_GND1V8 LMIADDR[0] VDD1V8_2V5 LMI_GND1V8 LMI_GND1V8 LMI_GND1V8 LMI_GND1V8 VDD1V8_2V5 VDD1V8_2V5 VDD1V8_2V5 LMIDATA[8] VDD1V8_2V5 VDD1V8_2V5 LMI_COMP_REF VDD3V3 VDD_SENSE VDD1V2 PIO16[7] PIO11[3] PIO11[2] PIO13[2] PIO13[3] PIO13[0] VDD3V3 VDD3V3
Confidential
G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 G30 H1 H2 H3 H4 H5
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VDD1V2

Net name VDD3V3 VDD2V5 VDD1V2 VDD1V2 PIO16[6] PIO15[6]
Pin number H6 H27 H28 H29 H30 H31 H32 J2 J3 J4 J5 J6
PIO12[6] PIO12[5] PIO13[1] VDD3V3 VDD3V3 FDMAREQ[3] PIO16[5] PIO9[7] DAA_C2A DAA_C1A PIO12[2] PIO12[4] PIO12[0] PIO12[7] VDD1V8_2V5 VDD1V8_2V5 VDD1V8_2V5 DGND DGND DGND PIO5[3] FDMAREQ[2] FDMAREQ[0] FDMAREQ[1] PIO12[1] PIO14[7] PIO12[3] DGND
Confidential
J27 J28 J29 J30 J31 K3 K4 K5 K6 K10 K11 K12 K21 K22 K23 K27 K28 K29 K30 L4 L5 L6 L10
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PIO15[7]

Net name DGND VDD1V8_2V5 VDD1V8_2V5 DGND DGND DGND
STi7105
Pin number L11 L12 L13 L20 L21 L22 L23 L27 L28 L29 M5 M6
PIO5[0] PIO5[2] PIO5[1] PIO14[4] PIO14[6] DGND DGND DGND VDD1V8_2V5 VDD1V2 VDD1V2 VDD1V8_2V5 VDD1V8_2V5 VDD1V2 VDD1V2 DGND DGND DGND VDD3V3 PIO4[6] PIO4[7] PIO14[2] PIO14[1] PIO14[5] DGND DGND DGND DGND
Confidential
M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 M23 M27 M28 N4 N5 N6 N11 N12 N13 N14
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VDD3V3

Net name VDD1V2 VDD1V2 VDD1V2 VDD1V2 DGND DGND
Pin number N15 N16 N17 N18 N19 N20 N21 N22 N27 N28 N29 P3
VDD3V3 PIO4[3] PIO4[5] PIO4[4] PIO13[6] PIO14[0] PIO13[4] PIO14[3] VDD1V2 DGND DGND VDD1V2 VDD1V2 DGND DGND VDD1V2 DGND PIO4[2] PIO4[0] PIO4[1] PIO13[5] NOTEMICSA PIO13[7] CKGA1_DGND1V2 CKGA0_DGND1V2 VDD1V2 VDD1V2 DGND
Confidential
P4 P5 P6 P12 P13 P15 P16 P17 P18 P20 P21 P27 P28 P29 P30 R2 R3 R4 R5 R6 R12 R13 R14
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DGND

Net name DGND DGND DGND DGND DGND VDD1V2
STi7105
Pin number R15 R16 R17 R18 R19 R20 R21 R27 R28 R29 R30 R31
VDD2V5 VDD1V2 PIO3[5] PIO3[7] PIO3[6] NOTEMICSC NOTEMICSB NOTEMICSE CKGA0_AGND2V5 CKGA1_DVDD1V2 CKGA0_DVDD1V2 VDD3V3 VDD1V2 VDD1V2 DGND DGND DGND DGND DGND VDD3V3 VDD3V3 CKGB1_DGND1V2 CKGB1_DVDD1V2 DGND PIO3[4] PIO5[6] PIO5[7] NOTEMICSD
Confidential
T1 T2 T3 T4 T5 T6 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T27 T28 T29 T30 T31 T32 U1
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VDD1V2

Net name EMIFLASHCLK NOTEMIBAA CKGA1_AGND2V5 CKGA1_AVDD2V5 CKGA0_AVDD2V5 VDD3V3
Pin number U2 U3 U4 U5 U6 U12 U13 U14 U15 U16 U17 U18
VDD1V2 DGND DGND DGND DGND DGND VDD3V3 VDD3V3 CKGB0_AVDD2V5 CKGB1_AVDD2V5 DGND PIO5[4] PIO2[7] PIO5[5] EMIADDR[3] EMITREADYORWAIT EMIADDR[2] EMIADDR[4] EMIADDR[5] VDD1V2 VDD1V2 DGND DGND VDD1V2 DGND DGND DGND VDD1V2
Confidential
U19 U20 U21 U27 U28 U29 U30 U31 U32 V2 V3 V4 V5 V6 V12 V13 V14 V15 V16 V17 V18 V19 V20
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VDD1V2

Net name VDD1V2 CKGB0_DGND1V2 CKGB_AGND2V5 PIO2[4] PIO2[6] PIO2[5]
STi7105
Pin number V21 V27 V28 V29 V30 V31 W3 W4 W5 W6 W12 W13
EMIADDR[1] EMIADDR[12] EMIADDR[6] VDD1V2 DGND DGND VDD1V2 DGND DGND DGND DGND CKGB0_DVDD1V2 PIO2[3] PIO2[1] PIO2[2] EMIADDR[10] NOTEMIOE EMIADDR[11] VDD3V3 VDD3V3 DGND DGND VDD1V2 VDD1V2 DGND VDD1V2 DGND DGND
Confidential
W15 W16 W17 W18 W20 W21 W27 W28 W29 W30 Y4 Y5 Y6 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20
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EMIADDR[7]

Net name DGND DGND PIO1[6] PIO2[0] PIO1[7] EMIADDR[13]
Pin number Y21 Y22 Y27 Y28 Y29 AA5 AA6 AA10 AA11 AA12 AA13 AA14
VDD3V3 VDD3V3 DGND DGND VDD1V2 VDD1V2 VDD1V2 DGND VDD1V2 VDD1V2 DGND DGND DGND DGND PIO1[4] PIO1[5] EMIADDR[8] EMIADDR[16] EMIADDR[14] VDD3V3 DGND DGND DGND VDD1V2 DGND DGND DGND PIO1[1]
Confidential
AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA27 AA28 AB4 AB5 AB6 AB10 AB11 AB12 AB13 AB20 AB21 AB22 AB23 AB27
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EMIRDNOTWR

Net name PIO1[3] PIO1[2] EMIADDR[9] EMIADDR[18] NOTEMIBE[0] EMIADDR[17]
STi7105
Pin number AB28 AB29 AC3 AC4 AC5 AC6 AC10 AC11 AC12 AC21 AC22 AC23
DGND DGND VDD1V2 DGND HDMI_GND3V3 HDMIPLL_AVDD1V2 PIO1[0] PIO0[6] PIO0[7] EMIADDR[21] EMIADDR[22] EMIADDR[20] VDD1V2 EMIBUSREQ HDMIPLL_AGND1V2 HDMIPLL_AGND2V5 PIO0[3] PIO0[5] PIO0[4] NOTEMIBE[1] EMIADDR[15] EMIBUSGNT VDD1V2 VDD1V2 VDD1V2 ANA2_VDDE2V5 HDMIPLL_AVDD2V5 ANA2_GNDE2V5
Confidential
AC27 AC28 AC29 AC30 AD2 AD3 AD4 AD5 AD6 AD27 AD28 AD29 AD30 AD31 AE1 AE2 AE3 AE4 AE5 AE6 AE27 AE28 AE29
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DGND

Net name PIO0[2] PIO0[0] PIO0[1] EMIADDR[25] EMIDATA[2] EMIADDR[24]
Pin number AE30 AE31 AE32 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11
PIO9[4] PIO9[6] PIO8[3] ANA1_VDD2V5 ANA1_VDD2V5 CKGC_AVDD2V5 CKGC_AGND2V5 PIO10[0] VDD3V3 SATAVSS NC SATAVDD_PLL NC SATAVDD2_PLL USB_GND2V5 GNDSATA USB_VDD1V2 USB_VDD1V2 TMDS_GND HDMI_VDD3V3 THS_AVDD2V5 PIO3[3] PIO3[0] PIO3[2] NOTEMILBA NANDWAIT EMIADDR[19] PIO9[3]
Confidential
AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 AF27 AF28 AF29 AF30 AG4 AG5 AG6 AG7
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VDD1V2

Net name PIO8[4] PIO10[7] ANA1_GND2V5 CKGC_DGND1V2 AUDA_DVDD1V2 PIO10[4]
STi7105
Pin number AG8 AG9 AG10 AG11 AG12 AG13 AG14 AG15 AG16 AG17 AG18 AG19
VDD3V3 SATAVDDR SATAVDDT USB_GND2V5 SATAVSS_PLL USB_VDD2V5 SATARXN REXT USB_GND1V2 TMDS_VDD1V2 TMDS_GND TMDS_GND VIDA0_GNDAS PIO3[1] VIDA1_GNDA1 VIDA1_YOUT EMIDATA[11] EMIDATA[6] EMIDATA[13] PIO15[5] PIO7[7] DGND ANA1_GND2V5 PIO8[5] PIO9[5] AUDA_DGND1V2 PIO11[1] PIO10[1]
Confidential
AG20 AG21 AG22 AG23 AG24 AG25 AG26 AG27 AG28 AG29 AG30 AH3 AH4 AH5 AH6 AH7 AH8 AH9 AH10 AH11 AH12 AH13 AH14
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CKGC_DVDD1V2

Net name VDD3V3 VDD3V3 DGND DGND SATAREF SATATXN
Pin number AH15 AH16 AH17 AH18 AH19 AH20 AH21 AH22 AH23 AH24 AH25 AH26
SYSCLKOSC USB1VDDB3V3 TMDS_VDD1V2 TMDS_VDD1V2 TMDSTX1N TMDSTX2N HDMI_CEC VIDA1_GNDA2 VIDA1_IDUMP VIDA1_CVOUT EMIDATA[15] EMIDATA[14] EMIADDR[23] PIO15[2] PIO7[6] PIO9[2] DGND PIO8[6] PIO10[5] PIO10[6] PIO11[0] PIO10[2] DGND DGND DGND NC NC SATATXP
Confidential
AH27 AH28 AH29 AH30 AH31 AJ2 AJ3 AJ4 AJ5 AJ6 AJ7 AJ8 AJ9 AJ10 AJ11 AJ13 AJ14 AJ15 AJ16 AJ17 AJ18 AJ19 AJ20
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SATARXP

Net name SYSCLKIN USB1DP USB2VDDB3V3 HDMI_VDD1V2 TMDSTX0N TMDSTX1P
STi7105
Pin number AJ22 AJ23 AJ24 AJ25 AJ26 AJ27 AJ28 AJ29 AJ30 AJ31 AJ32 AK1
VIDA0_GNDA1 VIDA1_GNDAS VIDA1_VCCA1 VIDA1_COUT EMIDATA[4] EMIDATA[1] EMIDATA[7] EMIDATA[5] PIO15[4] PIO8[1] PIO8[2] PIO7[5] PIO7[4] PIO9[0] PIO10[3] AUDA_RIGHTOUTN AUDA_GNDAS DGND NC NC USB1DM USB2DP TMDSTXCP TMDSTX0P VIDA0_MASSQUIET VIDA0_GNDA2 VIDA0_VCCA2 VIDA1_VCCA2
Confidential
AK2 AK3 AK4 AK5 AK6 AK7 AK8 AK9 AK10 AK14 AK15 AK16 AK17 AK18 AK19 AK23 AK24 AK25 AK26 AK28 AK29 AK30 AK31
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TMDSTX2P

Net name VIDA1_REXT EMIDATA[8] EMIDATA[3] EMIDATA[10] PIO15[1] PIO15[3]
Pin number AK32 AL1 AL2 AL3 AL4 AL5 AL8 AL9 AL15 AL16 AL17 AL18
PIO8[7] AUDA_RIGHTOUTP AUDA_IREF AUDA_LEFTOUTN NC USB2DM TMDSREF VIDA0_REXT VIDA0_VCCA1 VIDA0_IDUMP VIDA1_MASSQUIET EMIDATA[0] EMIDATA[12] EMIDATA[9] PIO15[0] PIO9[1] AUDA_VBGOUT AUDA_LEFTOUTP TMDSTXCN VIDA0_BOUT VIDA0_ROUT VIDA0_GOUT
Confidential
AL24 AL25 AL29 AL30 AL31 AL32 AM1 AM2 AM3 AM4 AM8 AM16 AM17 AM25 AM30 AM31 AM32
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PIO8[0]
Connections
STi7105
Connections
This chapter contains detail of pins, pad reset conditions, alternative functions and connection diagrams, listed in the following functional groups: power supplies (analog and digital) on page 60 system on page 71 JTAG on page 71 transport interface on page 72 Ethernet on page 88 display analog output interface on page 74 HDMI interface on page 75 audio digital interface on page 75 audio analog interface on page 76 SATA interface on page 76 FDMA interface on page 77 programmable I/O (PIO) on page 78 external memory interface (EMI) on page 82 local memory interface on page 85 USB 2.0 interface on page 90 peripherals: DAA interface on page 91 asynchronous serial controller (ASC) on page 91 infrared transmitter/receiver on page 92 modem analog front-end interface on page 92 PWM on page 92 smartcard on page 93 synchronous serial controller (SSC) on page 93 pad reset conditions on page 94 for external circuitry information, refer to External circuitry recommendations on page 233.
6.1
Table 4.
Pin USB 2.0 AF23 AF24 AG20 AG23
Power supplies
Power/ground pins
Assignment Voltage Type Description
USB_VDD1V2 USB_VDD2V5 USB_GND1V2
1.2 2.5 0
Analog Analog
USB 1.2 V power USB 2.5 V power USB ground
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STi7105 Table 4.
Pin AF21 AG18 AH23 AJ24 SATA AF16 AF17 AG16 AG17 AF18 AG19 AF20 AJ18 SATAVSS NC SATAVDDR SATAVDDT SATAVDD_PLL SATAVSS_PLL SATAVDD2_PLL NC NC GNDSATA 0 0 1.2 1.2 1.2 0 2.5 0 Analog Analog Analog Analog SATA ground
Connections Power/ground pins (continued)

Assignment USB_GND2V5 USB1VDDB3V3 USB2VDDB3V3 Voltage 0 3.3 3.3 Analog Analog Type USB ground USB1 3.3 V power USB2 3.3 V power Description
SATA power SATA power SATA PLL power SATA PLL ground SATA PLL power No connect No connect SATA ground
AF19 AF22 HDMI AG24 AH24 AH25 AF25 AG25 AG26 AE28 AD28 AC27 AD27 AC23 AF26 AJ25 LMIPLL G8 F8 G9 F9
TMDS_VDD1V2
1.2
Analog
TMDS 1.2 V power
TMDS_GND
TMDS ground
HDMIPLL_AVDD2V5 HDMIPLL_AGND2V5 HDMIPLL_AVDD1V2 HDMIPLL_AGND1V2 HDMI_GND3V3 HDMI_VDD3V3 HDMI_VDD1V2
2.5 0 1.2 0 0 3.3 1.2
Analog
HDMI PLL 2.5 V power HDMI PLL ground
Analog
HDMI PLL power HDMI PLL ground HDMI ground
Digital Digital
HDMI 3.3 V power HDMI 1.2 V power
LMIPLL_AVDD2V5 LMIPLL_AGND2V5 LMIPLL_AVDD1V2 LMIPLL_AGND1V2
2.5 0 1.2 0
Analog
LMI PLL 2.5 V power LMI PLL ground
Analog
LMI PLL 1.2 V power LMI PLL ground
Video DACs AG27 VIDA0_GNDAS 0
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SATA ground
Confidential
Connections Table 4.
Pin AK29 AK30 AL30 AJ29 AJ30 AH29 AK31 AJ31 AG29 AE27 AE29
STi7105
Power/ground pins (continued)

Assignment VIDA0_GNDA2 VIDA0_VCCA2 VIDA0_VCCA1 VIDA0_GNDA1 VIDA1_GNDAS VIDA1_GNDA2 VIDA1_VCCA2 VIDA1_VCCA1 VIDA1_GNDA1 ANA2_VDDE2V5 ANA2_GNDE2V5 Voltage 0 2.5 2.5 0 0 0 2.5 2.5 0 2.5 0 Analog Analog Analog Analog Analog Type Description
Audio DAC AG10 ANA1_GND2V5 0
AH9 AF10 AF11 AH12 AG12 AK16
ANA1_VDD2V5 AUDA_DGND1V2 AUDA_DVDD1V2 AUDA_GNDAS
2.5 0 1.2 0
Analog ADCAC 1.2 V ground Digital ADCAC 1.2 V power
ClockGenA R5 T5 U4 U5 R6 T6 T4 U6 CKGA1_DGND1V2 CKGA1_DVDD1V2 CKGA1_AGND2V5 CKGA1_AVDD2V5 CKGA0_DGND1V2 CKGA0_DVDD1V2 CKGA0_AGND2V5 CKGA0_AVDD2V5 0 1.2 0 2.5 0 1.2 0 2.5 Analog Digital Analog Digital CKGA PLL1 1.2 ground CKGA PLL1 1.2 power CKGA PLL1 2.5 V ground CKGA PLL1 2.5 V power CKGA PLL0 1.2 ground CKGA PLL0 1.2 power CKGA PLL0 2.5 V ground CKGA PLL0 2.5 V power
ClockGenB U27 V28 U28 W27 V27 T27 T28 CKGB0_AVDD2V5 CKGB_AGND2V5 CKGB1_AVDD2V5 CKGB0_DVDD1V2 CKGB0_DGND1V2 CKGB1_DGND1V2 CKGB1_DVDD1V2 2.5 0 2.5 1.2 0 0 1.2 Digital Analog Digital Analog CKGB FS0 2.5 V power CKGB FS0,1 2.5 V ground CKGB FS1 2.5 V power CKGB FS 1.2 V power CKGB FS 1.2 V ground CKGB FS1 1.2 V ground CKGB FS1 1.2 V power
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STi7105 Table 4.
Pin ClockGenC AG11 AG14 AF13 AF12 LMI CKGC_DGND1V2 CKGC_DVDD1V2 CKGC_AGND2V5 CKGC_AVDD2V5 0 1.2 0 2.5 Analog Digital CKGC FS 1.2 ground CKGC FS 1.2 power CKGC FS 2.5 V ground CKGC FS 2.5 V power

F18 F19 F23 G13 G18 G19
G20 G22 G23 K10 K11 K12 L12 L13 M13 M16 M17 VDD1V8_2V5 1.8 Digital LMI DDR2 1.8/2.5 V power
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E18
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Pin D8 D16 D17 E8 E9 E15 E16 E17 F10 F14 F15 F16 F17 LMI_GND1V8 0 LMI 1.8 V ground
STi7105

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G10 G11 G14 G15 G16 G17 Analog 2.5V H27 VDD2V5 2.5 Analog Analog 2.5 V power
Digital 2.5V R27 Tsensor AF27 THS_AVDD2V5 2.5 Analog Thermal sensor analog supply VDD2V5 2.5 Digital Digital 2.5 V power
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STi7105 Table 4.
Pin Digital 3.3 V

D25 E24 E25 F25 G25 H5 H6 J5 J6 L23 M23 N22 T12 T20 T21 U12 U20 U21 Y11 Y12 AA10 AA11 AB10 AF15 AG15 AH15 AH16
DGND VDD3V3 3.3 Digital Digital 3.3 V power
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H4
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Pin K21 K22 K23 L10 L11 L20 L21 L22 M10 M11 M12 M20 M21
STi7105

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M22 N11 N12 N13 N14 N19 N20 N21 P13 P15 P18 P20 P27 R14 R15 R16 R17 R18 R19 T15 T16 T17 T18 DGND 0 Digital 3.3/2.5/1.2 V ground
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STi7105 Table 4.
Pin T19 T29 U15 U16 U17 U18 U19 U29 V14 V15 V17 V18 V19

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W13 W15 W17 W18 W20 W21 Y13 Y14 Y17 Y19 Y20 Y21 Y22 AA12 AA13 AA17 AA20 AA21 AA22 AA23 AB11 AB12 DGND 0 Digital 3.3/2.5/1.2 V ground
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Pin AB13 AB21 AB22 AB23 AC10 AC11 AC12 AC22 AH8 AH17 AH18 AJ8 AJ15 DGND 0 Digital 3.3/2.5/1.2 V ground
STi7105

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AJ16 AJ17 AK17
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STi7105 Table 4.
Pin Digital 1.2 V F7 G6 G7 G27 H28 H29 M14 M15 M18 M19 N15 N16

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N17 N18 P12 P16 P17 P21 R12 R13 R20 R21 R28 T13 T14 U13 U14 V12 V13 V16 V20 VDD1V2 1.2 Digital Digital power 1.2 V core power
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Pin V21 W12 W16 Y15 Y16 Y18 AA14 AA15 AA16 AA18 AA19 AB20 AC21 VDD1V2 1.2 Digital Digital 1.2 V core power
STi7105

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AD5 AE4 AE5 AE6 AF6
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STi7105
Connections
6.2
Table 5.
Pin B32 A29 B29 B31 C29 A32 A31 B30 A30 C31
System
System pins
Assignment NOTRESETIN WDOGRSTOUT NOTASEBRK TRIGGERIN TRIGGEROUT SYSITRQ[0] SYSITRQ[1] I/O SYSITRQ[2] SYSITRQ[3] NMI SYSCLKINALT SYSCLKOUT SYSCLKIN SYSCLKOSC GND_SENSE VDD_SENSE I I O I O A A 3.3 3.3 3.3 2.5 2.5 Nonmaskable interrupt 2nd system alternate clock (30 MHz) with external VCXO Programmable output clock for debug 30 MHz oscillator (USB/SATA) with internal VCXO Ground voltage sense Voltage sense 3.3 Interrupt line Interrupts I O I/O I O I/O Voltage 3.3 3.3 3.3 3.3 3.3 Description System reset-in System reset-out (from System resetin or Internal watchdog timer reset) ST40 debugger breakpoint ST231 debugger controller in ST231 debugger controller out CPUs debug System reset Comments
C30 C32 AJ22 AH22 F26 G26
6.3
Table 6.
Pin B2
JTAG
JTAG pins
Assignment TDI TMS TCK NOTTRST TDO I I I I O I/O Voltage 3.3 3.3 3.3 3.3 3.3 Description CPUs debug port and TAP data input CPUs debug port and TAP mode select CPUs debug port and TAP clock CPUs debug port and TAP logic reset CPUs debug port and TAP data output No internal pullup or pull-down resistors Comments
C2
C1 A1 B1
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Connections
STi7105
6.4
Transport interface
This transport interface is an alternative to the PIO bits. By default, the PIO is bypassed. To enable the transport interface, the PIO setting must be done at boot (refer to Chapter 19: Alternate functions on PIO on page 263 for programming details).
Note: Table 7.
The parallel/serial mode selection is done by selecting the TSmerger channel. Parallel mode transport pins
Pad I/O I/O I/O I/O I/O Voltage 3.3 3.3 3.3 3.3 PIO PIO13[5] PIO13[6] TSIN0 control signals PIO13[7] PIO14[0] PIO14[7] PIO14[6] PIO14[5] PIO14[4] I/O 3.3 PIO14[3] PIO14[2] PIO14[1] PIO13[4] I I I I 3.3 3.3 3.3 3.3 PIO12[1]/ PIO15[1] PIO12[2]/ PIO15[2] TSIN1 control signals PIO12[3]/ PIO15[3] PIO12[4]/ PIO15[0] PIO13[3] PIO13[2] PIO13[1] PIO13[0] I 3.3 PIO12[7] PIO12[6] PIO12[5] PIO12[0]/ PIO15[4] TSIN1 parallel data TSIN0 parallel data Description Comments
TSIN0BYTECLK TSIN0BYTECLKVALID TSIN0ERROR TSIN0PACKETCLK TSIN0DATA[0] TSIN0DATA[1] TSIN0DATA[2]
TSIN0DATA[3] TSIN0DATA[4] TSIN0DATA[5] TSIN0DATA[6] TSIN0DATA[7] TSIN1BYTECLK TSIN1BYTECLKVALID TSIN1ERROR TSIN1PACKETCLK TSIN1DATA[0] TSIN1DATA[1] TSIN1DATA[2] TSIN1DATA[3] TSIN1DATA[4] TSIN1DATA[5] TSIN1DATA[6] TSIN1DATA[7]
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STi7105 Table 7. Parallel mode transport pins (continued)

Pad TSIN2BYTECLK TSIN2BYTECLKVALID TSIN2ERROR TSIN2PACKETCLK TSIN2DATA[0] TSIN2DATA[1] TSIN2DATA[2] TSIN2DATA[3] TSIN2DATA[4] TSIN2DATA[5] I 3.3 I I I I I/O Voltage 3.3 3.3 3.3 3.3 PIO PIO6[1], PIO14[2] PIO6[2], PIO14[3] TSIN2 control signals PIO6[3], PIO14[4] PIO6[4], PIO14[5] PIO7[3] PIO7[2] PIO7[1] PIO7[0] PIO6[7] PIO6[6] PIO6[5] PIO6[0], PIO14[1] I I I I 3.3 3.3 3.3 3.3 PIO12[6] PIO12[7] TSIN3 control signals TSIN3ERROR TSIN3PACKETCLK PIO13[0] PIO13[1] TSIN2 parallel data Description
Connections
Comments
TSIN2DATA[6] TSIN2DATA[7] TSIN3BYTECLK TSIN3BYTECLKVALID
Table 8.
Serial mode transport pins

Pad I/O I I I I O Voltage 3.3 3.3 3.3 3.3 3.3 PIO PIO13[4] PIO12[0]/ PIO15[4] PIO6[0]/ PIO14[1] PIO12[5] PIO12[0] Description TSIN0 serial data TSIN1 serial data TSIN2 serial data TSIN3 serial data TSOUT serial data Comments
TSIN0SER/DATA[7] TSIN1SER/DATA[7] TSIN2SER/DATA[7] TSIN3SER/DATA[7 TSOUTSER/DATA[7]
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Connections Table 9. 1394OUT mode transport pins

Signal TSOUTBYTECLK TSOUTBYTECLKVALID TSOUTERROR TSOUTPACKETCLK TSOUTDATA[0] TSOUTDATA[1] TSOUTDATA[2] TSOUTDATA[3] TSOUTDATA[4] TSOUTDATA[5] TSOUTDATA[6] O 3.3 I/O O O O O Voltage 3.3 3.3 3.3 3.3 PIO PIO12[1] PIO12[2] TSOUT control signals PIO12[3] PIO12[4] PIO13[3] PIO13[2] Description Comments
STi7105
PIO13[0] PIO12[7] PIO12[6] PIO12[5]
TSOUT parallel data
6.5
Table 10.
Pin AM31 AM32 AM30 AL29
Display analog output interface

Display analog output pins
Assignment VIDA0_ROUT VIDA0_GOUT VIDA0_BOUT VIDA0_REXT I/O O O O Voltage
(a)
Description Analog main display - red output Analog main display -green output Analog main display - blue output
Comments
Connect an external 140 1% resistor between these pins and analog ground.
Connect an external 7.81 k VDAC0 external resistor interface 1% resistor between each of these pins Analog auxiliary display chrominance output Analog auxiliary display - CVBS output Analog auxiliary display luminance output Connect an external 7.81 k VDAC1 external resistor interface 1% resistor between each of these pins It must be connected to noiseless board analog ground because it is sensitive pin for DAC output signal performance. It is tied to PCB ground plane. Connect an external 140 1% resistor between these pins and analog ground.
AJ32 AH31 AG30
VIDA1_COUT VIDA1_CVOUT VIDA1_YOUT
O O O
AK32
VIDA1_REXT
AK28
VIDA0_MASSQUIET
Analog ground connection
AL31
VIDA0_IDUMP
Current return path for the DAC output
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PIO13[1]
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STi7105 Table 10.

Pin
Connections Display analog output pins (continued)

Assignment I/O Voltage
(a)
Description
Comments It must be connected to noiseless board analog ground because it is sensitive pin for DAC output signal performance It is tied to PCB ground plane
AL32
VIDA1_MASSQUIET
Analog ground connection
AH30
VIDA1_IDUMP
Current return path for the DAC output
6.6
Table 11.
Pin AK25
HDMI interface
HDMI pins
Assignment TMDSTXCP TMDSTXCN TMDSTX0P TMDSTX0N TMDSTX1P TMDSTX1N TMDSTX2P TMDSTX2N I/O O O O O O O O O Voltage(a) Description TMDS Control plus TMDS Control minus TMDS Data0 plus TMDS Data0 minus TMDS Data1 plus TMDS Data1 minus TMDS Data2 plus TMDS Data2 minus Used by compensation cell to determine the current drive of output buffers. Pulled up externally to 3.3 V using a 50 resistor. Comments
)
AM25 AK26 AJ26 AJ27 AH26 AJ28 AH27
AL25
TMDSREF
TMDS voltage reference
AH28
HDMI_CEC
I/O
HDMI CEC line
a. For voltage values, please contact your local ST representative to provide you specific internal document.
HDMI pins as PIO alternates

Assignment HDMI_PLUGIN I I/O Voltage(a) Description HDMI HOT PLUG detection input Comments PIO9[7]
6.7
Audio digital interface

For audio digital pins, refer to PIO10 and PIO11 alternate functions in Alternate functions on PIO.
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a. For voltage values, please refer Section 17.4: Triple HD video DACs on page 244.
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Connections
STi7105
6.8
Table 12.
Pin
Audio analog interface

Audio analog pins
Assignment I/O O O O O O Voltage
(a)
Description DAC left channel positive differential current output DAC left channel negative differential current output
Comments
AM17 AUDA_LEFTOUTP AL17 AUDA_LEFTOUTN AL15 AUDA_RIGHTOUTP AK15 AUDA_RIGHTOUTN AM16 AUDA_VBGOUT AL16 AUDA_IREF
DAC right channel negative differential current output DAC output bandgap voltage DAC output reference current Connect an external 575 1% resistor to AUDA_AGND2V5
Confidential
a. For voltage values, please refer Section 17.3: Audio DAC on page 243.
6.9
Table 13.
Pin AJ20
Serial ATA interface

SATA pins
Assignment SATATXP I/O O O I I Voltage
(a)
Description SATA transmit plus No connect SATA transmit minus No connect SATA receive plus No connect SATA receive minus No connect
Comments
AK18 AH20 SATATXN AK19 AH21 SATARXP AJ19 -
AG21 SATARXN AL18 -
AH19 SATAREF
I/O
SATA external reference
It is an external 475 resistor with the other end connected to AF18 pin (SATAVDD_PLL).
a. For voltage values, please refer Section 17.7: SATA PHY electrical characteristics on page 248.
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DAC right channel positive differential current output
STi7105
Connections
6.10
Table 14.
Pin K29 K30 K28 J27
FDMA interface
FDMA pins
Assignment FDMAREQ[0] FDMAREQ[1] FDMAREQ[2] FDMAREQ[3] I/O I/O I/O I/O I/O Voltage 3.3 3.3 3.3 3.3 Description FDMA request FDMA request FDMA request FDMA request Comments
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Connections
STi7105
6.11
Note:
Programmable inputs/outputs
All PIO pins are rated at 4 mA sink/source. Table 15.
Pin AE31 AE32 AE30 AD29 AD31 AD30 AC29 AC30 AC28
PIO pins
Assignment I/O PIO0[0] PIO0[1] PIO0[2] I/O PIO0[4] PIO0[5] PIO0[6] PIO0[7] PIO1[0] PIO1[1] PIO1[2] PIO1[3] I/O 3.3 Programmable input/output bank1 PIO1[4] PIO1[5] PIO1[6] PIO1[7] PIO2[0] PIO2[1] PIO2[2] PIO2[3] I/O 3.3 Programmable input/output bank2 PIO2[4] PIO2[5] PIO2[6] PIO2[7] PIO3[0] PIO3[1] PIO3[2] PIO3[3] I/O 3.3 Programmable input/output bank3 PIO3[4] PIO3[5] PIO3[6] PIO3[7] 3.3 Programmable input/output bank0 Voltage Description
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AB27 AB29 AB28 AA27 AA28 Y27 Y29 Y28 W29 W30 W28 V29 V31 V30 U31 AF29 AG28 AF30 AF28 T30 R29 R31 R30
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PIO0[3]
STi7105 Table 15.

Pin P29 P30 P28 N27 N29 N28 M27 M28 L27 L29 L28 K27
Connections PIO pins (continued)

Assignment I/O PIO4[0] PIO4[1] PIO4[2] PIO4[3] I/O PIO4[4] PIO4[5] 3.3 Programmable input/output bank4 Voltage Description
PIO4[7] PIO5[0] PIO5[1] PIO5[2] PIO5[3] I/O 3.3 Programmable input/output bank5 PIO5[4] PIO5[5] PIO5[6] PIO5[7] PIO6[0] PIO6[1] PIO6[2] PIO6[3] I/O 3.3 Programmable input/output bank6 PIO6[4] PIO6[5] PIO6[6] PIO6[7] PIO7[0] PIO7[1] PIO7[2] PIO7[3] I/O 3.3 Programmable input/output bank7 PIO7[4] PIO7[5] PIO7[6] PIO7[7]
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U30 U32 T31 T32 E4 E2 E3 F5 F3 F4 G4 G3 D1 D2 D3 G5 AK9 AK8 AJ6 AH7
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PIO4[6]

Pin AL8 AK6 AK7 AF9 AG8 AH10 AJ9 AL9 AK10 AM8 AJ7 AG7
STi7105 PIO pins (continued)

PIO8[7] PIO9[0] PIO9[1] PIO9[2] PIO9[3] I/O 3.3 Programmable input/output bank9 PIO9[4] PIO9[5] PIO9[6] PIO9[7] PIO10[0] PIO10[1] PIO10[2] PIO10[3] I/O 3.3 Programmable input/output bank10 PIO10[4] PIO10[5] PIO10[6] PIO10[7] PIO11[0] PIO11[1] PIO11[2] PIO11[3] I/O 3.3 Programmable input/output bank11 PIO11[4] PIO11[5] PIO11[6] PIO11[7]
Confidential
AF7 AH11 AF8 J29 AF14 AH14 AJ14 AK14 AG13 AJ10 AJ11 AG9 AJ13 AH13 G30 G29 F27 F29 F28 E28
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PIO8[6]
STi7105 Table 15.

Pin K5 L4 K3 L6 K4 J3 J2 K6 H3 J4 H1 H2
Connections PIO pins (continued)

PIO12[7] PIO13[0] PIO13[1] PIO13[2] PIO13[3] I/O 3.3 Programmable input/output bank13 PIO13[4] PIO135] PIO13[6] PIO13[7] PIO14[0] PIO14[1] PIO14[2] PIO14[3] I/O 3.3 Programmable input/output bank14 PIO14[4] PIO14[5] PIO14[6] PIO14[7] PIO15[0] PIO15[1] PIO15[2] PIO15[3] I/O 3.3 Programmable input/output bank15 PIO15[4] PIO15[5] PIO15[6] PIO15[7]
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P5 R2 P3 R4 P4 N5 N4 P6 M5 N6 M6 L5 AM4 AL4 AJ5 AL5 AK5 AH6 H31 H32
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PIO12[6]

Pin E30 E29 D29 D31 D30 J28 H30 G28
STi7105 PIO pins (continued)

PIO16[7]
6.12
Note: Table 16.
Pin R3 T2 T1 U1 T3 AC5 AE1 Y5 AG4 U3 V3 AA6

The various configurations of the EMI (SRAM, FLASH, PCI) are shown in Section 7.4. EMI pins
Assignment NOTEMICSA NOTEMICSB NOTEMICSC NOTEMICSD NOTEMICSE NOTEMIBE[0] I/O NOTEMIBE[1] NOTEMIOE NOTEMILBA NOTEMIBAA EMITREADYORWAIT EMIRDNOTWR O2 I/O I/O I/O I/O 3.3 3.3 3.3 3.3 3.3 External device output enable Flash device load burst address Flash burst address advanced External memory device target ready indicator External read/write access indicator. Common to all devices. 3.3 External device databus byte enable I/O I/O I/O I/O I/O I/O Voltage 3.3 3.3 3.3 3.3 3.3 Description Peripheral chip select A Peripheral chip select B Peripheral chip select C Peripheral chip select D Peripheral chip select E Comments
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PIO16[6]
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STi7105 Table 16.

Pin AM1 AK2 AF4 AL2 AK1 AK4 AH4 AK3 AL1 AM3 AL3 AH3
Connections EMI pins (continued)

Assignment EMIDATA[0] EMIDATA[1] EMIDATA[2] EMIDATA[3] EMIDATA[4] EMIDATA[5] I/O Voltage Description Comments
EMIDATA[7] I/O EMIDATA[8] EMIDATA[9] EMIDATA[10] EMIDATA[11] EMIDATA[12] EMIDATA[13] EMIDATA[14] EMIDATA[15] 3.3 External common data bus
Confidential
AM2 AH5 AJ3 AJ2
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EMIDATA[6]

Pin W4 V4 V2 V5 V6 W6 W3 AB4 AC3 Y4 Y6 W5
STi7105
EMI pins (continued)

Assignment I/O Voltage Description Comments
EMIADDR[1] EMIADDR[2] EMIADDR[3] EMIADDR[4] EMIADDR[5] EMIADDR[6]
EMIADDR[8] EMIADDR[9] EMIADDR[10] EMIADDR[11] EMIADDR[12] EMIADDR[13] EMIADDR[14] EMIADDR[15] EMIADDR[16] EMIADDR[17] EMIADDR[18] EMIADDR[19] EMIADDR[20] EMIADDR[21] EMIADDR[22] EMIADDR[23] EMIADDR[24] EMIADDR[25] EMIFLASHCLK EMIBUSREQ EMIBUSGNT NANDWAIT I/O I/O I/O 3.3 3.3 3.3 3.3 Flash clock Bus access request Bus access grant For master/slave configuration O 3.3 External common address bus 23-bit address(a)
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AA5 AB6 AE2 AB5 AC6 AC4 AG6 AD4 AD2 AD3 AJ4 AF5 AF3 U2 AD6 AE3 AG5
a. No pull-up. External resistors to define mode at boot.
Table 17.
EMI pins as PIO alternates

Signal I/O I I Voltage 3.3 3.3 Description Access Pending Flag SPI boot data in Comments PIO15[2] PIO15[3]
EMI_SS_BUS_FREE_ACCESSPE ND/EMI_SS_BUS_FREE_OUT SPIBOOT_DATA_IN
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EMIADDR[7]
STi7105 Table 17. EMI pins as PIO alternates (continued)

Signal SPIBOOT_DATA_OUT SPIBOOT_CLOCK SPIBOOT_CS I/O O O O Voltage 3.3 3.3 3.3 Description SPI boot data out SPI boot clock SPI boot chip select
Connections
Comments PIO15[1] PIO15[0] PIO15[2]
Table 18.
PCI pins as PIO alternates

Assignment I/O I I I I O Voltage 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 Description PCI lock function PCI interrupt input (when host) PCI interrupt input (when host) PCI interrupt input (when host) PCI interrupt output (when device) PCI reset input (when host) PCI error flag PCI pme function Bus access grant Bus access grant Bus access req Bus access req Comments
PCI_INT_FROM_DEVICE[0] PCI_INT_FROM_DEVICE[1] PCI_INT_FROM_DEVICE[2] PCI_INT_TO_HOST
PIO6[0], PIO15[3] PIO6[1] PIO6[2] PIO6[0], PIO15[3] PIO15[7] PIO15[4] PIO15[6] PIO7[1] PIO7[2] PIO6[5] PIO6[6]
PCI_RESETN_FROM_HOST_TO_D I EVICE PCI_SYSTEM_ERROR PCI_PME_IN PCI_BUS_GNT[1] PCI_BUS_GNT[2] PCI_BUS_REQ[1] PCI_BUS_REQ[2] O I O O I I
6.13
Table 19.
Pin B17 A17 C3 A2 B9 D4 D9 C9 D23
Local memory interface

LMI pins
Assignment LMICLK[0] NOTLMICLK[0] LMICLK[1] NOTLMICLK[1] NOTLMICS[0] NOTLMICS[1] NOTLMIRAS NOTLMICAS NOTLMIWE I/O O O O O O O O O O Voltage 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 Description Clock to DDR0 Inverted clock to DDR0 Clock to DDR1 Inverted clock to DDR1 Chip select0 Chip select1 Row address strobe Column address strobe Write enable Comments
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PCI_LOCK_IN
PIO7[0], PIO15[5]
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Pin G12 D22 D14 E21 E13 F20 C15 D19 C14 C19 F22 A16
STi7105
LMI pins (continued)

Assignment LMIADDR[0] LMIADDR[1] LMIADDR[2] LMIADDR[3] LMIADDR[4] LMIADDR[5] O LMIADDR[7] LMIADDR[8] LMIADDR[9] LMIADDR[10] LMIADDR[11] LMIADDR[12] LMIADDR[13] 1.8 Address I/O Voltage Description Comments
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C17 B16
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LMIADDR[6]
STi7105 Table 19.

Pin C18 D27 B18 B28 C28 D18 C27 E19 G21 D26 D20 C26
Connections LMI pins (continued)

Assignment LMIDATA[0] LMIDATA[1] LMIDATA[2] LMIDATA[3] LMIDATA[4] LMIDATA[5] I/O Voltage Description Comments
LMIDATA[7] LMIDATA[8] LMIDATA[9] LMIDATA[10] LMIDATA[11] LMIDATA[12] LMIDATA[13] LMIDATA[14] LMIDATA[15] I/O 1.8 Bidirectional data bus LMIDATA[16] LMIDATA[17] LMIDATA[18] LMIDATA[19] LMIDATA[20] LMIDATA[21] LMIDATA[22] LMIDATA[23] LMIDATA[24] LMIDATA[25] LMIDATA[26] LMIDATA[27] LMIDATA[28] LMIDATA[29] LMIDATA[30] LMIDATA[31]
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E26 E20 C25 F21 B4 E11 B3 F12 E12 A3 D11 C4 E6 C10 D6 D10 F11 F6 E10 C7
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LMIDATA[6]

Pin E23 D24 A8 B8 E27 F13 C23 E5 E7 E22 G24 F24
STi7105
LMI pins (continued)

Assignment LMIDATAMASK[0] LMIDATAMASK[1] O LMIDATAMASK[2] LMIDATAMASK[3] LMIVREF[0] LMIVREF[1] LMICLKEN[0] LMICLKEN[1] ODT[0] ODT[1] LMI_COMP_REF LMI_COMP_GND LMIDUMMY[0] LMIDUMMY[1] LMIDQS[0] LMIDQS[1] I/O 1.8 Write/read data strobe LMIDQS[2] LMIDQS[3] LMIDQSN[0] LMIDQSN[1] I/O 1.8 Write/read data strobe LMIDQSN[2] LMIDQSN[3] LMIBA[0] LMIBA[1] LMIBA[2] O 1.8 Bank select I I O O O O A A A A 1.8 1.8 1.8 1.8 1.8 1.8 SSTL reference voltage0 SSTL reference voltage1 1.8 Data write mask I/O Voltage Description Comments
Memory clock enable Memory on-die termination Memory on-die termination LMI compensation external resistor LMI compensation ground LMI pcb track delay estimator LMI pcb track delay estimator
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D15 C16 A25 C24 C5 D7 B25 B24 D5 C8 D13 E14 B15
6.14
Note:
Ethernet
This Ethernet interface is an alternative of PIO bits. By default, the PIO is selected. To enable the Ethernet interface, the PIO setting must be done at boot (refer to Chapter 19: Alternate functions on PIO on page 263 for programming details).
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STi7105 Table 20.

Pad MIITXCLK MIITX_EN MIITXD[3] MIITXD[2] MIITXD[1] MIITXD[0] MIIRXCLK MIIRX_DV MIIRX_ER MIIRXD[3] I O O O O O I I I I I I I I I
Connections MII interface pin mapping

I/O Voltage 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 PIO mapping PIO9[2] PIO8[2] PIO8[1] PIO8[0] Data signals driven by the MAC PIO7[6] PIO8[5] PIO7[4] PIO7[5] PIO9[1] PIO9[0] PIO8[7] PIO8[6] PIO9[4] PIO9[3] Asserted when either the transmit or receive medium is not idle Asserted on detection of a collision on the medium Timing reference for transfer of information on the ETHMII_MDIO signals Management Data input/output signal Management data interrupt from PHY PHY clock Data signals that transition synchronously with respect to ETHMII_RXCLK Timing reference for ETHMII_RXDV, ETHMII_RXER, and ETHMII_RXD Receive data valid Receive error Description Timing reference for ETHMII_TXEN and ETHMII_TXD Indicates that the MAC is presenting nibbles on the MII for transmission Comments
MIIRXD[2] MIIRXD[1] MIIRXD[0] MIICRS MIICOL
MIIMDC MIIMDIO MIIMDINT MIIPHYCLK
O I/O I O
.
3.3 3.3 3.3 3.3
PIO8[4] PIO8[3] PIO9[6] PIO9[5]
Table 21.
RMII interface pin mapping

I/O O O O I I I Voltage 3.3 3.3 3.3 3.3 3.3 3.3 PIO mapping PIO8[2] PIO7[7] Data signals driven by the MAC PIO7[6] PIO8[7] Data signals received by the MAC PIO8[6] PIO7[4] Asserted when either the transmit or receive medium is not idle Description Indicates that the MAC is presenting nibbles on the MII for transmission Comments
Assignment RMIITX_EN RMIITXD[1] RMIITXD[0] RMIIRXD[1] RMIIRXD[0] RMIICRS_DV
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PIO7[7]
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Connections Table 21. RMII interface pin mapping (continued)

I/O I O I/O I I/O Voltage 3.3 3.3 3.3 3.3 3.3 PIO mapping PIO7[5] PIO8[4] PIO8[3] PIO9[6] PIO9[5] Timing reference for transfer of information on the ETHMII_MDIO signals Management Data input/output signal Management data interrupt from PHY Description Comments
STi7105
Assignment RMIIRX_ER RMIIMDC RMIIMDIO RMIIMDINT RMIIREF_CLK
6.15
Table 22.
Pin
USB 2.0 interface

USB pins
Assignment USB1DM USB1DP USB2DM USB2DP REXT I/O I/O I/O I/O I/O Voltage 2.5 2.5 2.5 2.5 Description USB receive minus USB receive plus USB receive minus USB receive plus External register 1.5 k resistor Comments
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AK23 AJ23 AL24 AK24 AG22
Table 23.
USB pin mapping

I/O I O I O Voltage 3.3 USB 2.0 interface 1 3.3 3.3 USB 2.0 interface 2 3.3 Description Assignment PIO4[4], PIO12[5] PIO4[5], PIO12[6] PIO4[6]/PIO14[6] PIO4[7]/PIO14[7]
Mapping USB1_PRT_OVCUR USB1_PRT_PWR USB2_PRT_OVCUR USB2_PRT_PWR
Caution:
In case of USB signals, the usual naming convention is not used. In order to align with the STi7105 ballout names, this manual mentions two instances of USB as USB1 and USB2 rather than USB0 and USB1. Therefore, in this manual the first instance of USB is USB1 and the second instance is USB2.
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STi7105
Connections
6.16
6.16.1
Table 24.
Pin
Peripherals
DAA
DAA pins
Assignment DAA_C1A DAA_C2A I/O I/O I/O Voltage 3.3 3.3 Description DAA differential data(a) DAA differential data(b) Comments
J31 J30
a. ISO-Link capacitors C1 and C2, (33 pF) should be as close to the line-side device as possible.
6.16.2
Table 25.
Assignment
Asynchronous serial controller (ASC)

ASC / SCIF pins
I/O Voltage Description ASC0 Comments
UART0_RXD UART0_TXD UART0_CTS UART0_RTS UART0_NOT_OE
I O I O O
3.3 3.3 3.3 3.3 3.3
ASC 0 receive signal ASC 0 transmit signal ASC 0 clear to send signal ASC 0 request to send signal
PIO0[1] PIO0[0] PIO0[4] PIO0[3] PIO0[2]
ASC1 UART1_RXD UART1_TXD UART1_CTS UART1_RTS I O I O 3.3 3.3 3.3 3.3 ASC 1 receive signal ASC 1 transmit signal ASC 1 clear to send signal ASC 1 request to send signal ASC2 UART2_RXD UART2_TXD UART2_CTS UART2_RTS I O I O 3.3 3.3 3.3 3.3 ASC 2 receive signal ASC 2 transmit signal ASC 2 clear to send signal ASC 2 request to send signal ASC3 UART3_RXD UART3_TXD I O 3.3 3.3 ASC 3 receive signal ASC 3 transmit signal PIO5[1] PIO5[0] PIO12[1], PIO4[1] PIO12[0], PIO4[0] PIO12[2], PIO4[2] PIO12[3], PIO4[3] PIO1[1] PIO1[0] PIO1[4] PIO1[3]
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b. After satisfying the above, C1 and C2 should be as close to the embedded system-side DAA module as possible and no further than 6 inches away.
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Assignment UART3_CTS UART3_RTS
STi7105
ASC / SCIF pins (continued)

I/O I O Voltage 3.3 3.3 Description ASC 3 clear to send signal ASC 3 request to send signal Comments PIO5[3] PIO5[2]
6.16.3
Table 26.
Infrared transmitter/receiver
Infrared transmitter/receiver pins
I/O I I O O Voltage 3.3 3.3 3.3 3.3 Description IR data input UHF data input IR data output IR data output. It is open drain. Comments PIO3[0] PIO3[1] PIO3[2] PIO3[3]
Assignment IRB_IR_IN IRB_UHF_IN IRB_IR_DATAOUT IRB_IR_DATAOUT_OD
6.16.4
Modem analog front-end interface (MAFE)

MAFE pins
I/O O O I I I Voltage 3.3 3.3 3.3 3.3 3.3 Description Indicates a control/status exchange Line for serially transmitting samples Line for serially receiving samples Modem system clock Comments PIO1[2] PIO1[3] PIO1[0] PIO1[1]
Table 27.
Assignment MAFE_HC1 MAFE_DOUT MAFE_DIN MAFE_SCLK MAFE_FS
Start of a sampling period PIO1[5] latched on falling edges of SCLK
6.16.5
Table 28.
Pulse width modulator (PWM)

PWM pins
I/O Voltage PWM 0 Description Comments
Assignment
PWM_OUT0 PWM_CAPTURE_IN0
O I
3.3 PWM 0
PIO13[0], PIO4[4] PIO4[3]
PWM 1 PWM_OUT1 PWM_CAPTURE_IN1 PWM_COMPARE_OUT1 O I O 3.3 3.3 3.3 PWM 1 PIO13[1], PIO4[5] PIO4[7] PIO4[6]
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STi7105
Connections
6.16.6
Table 29.
Smartcard
Smartcard pins
I/O Voltage Smartcard 0 Description Comments
Assignment
SC0_EXTCLKIN SC0_CLKOUT SC0_DATAOUT SC0_DATAIN SC0_RESET SC0_COND_VCC SC0_COND_VPP SCO_DETECT
I O O I O O O I
3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3
External clock Clock for smartcard from 100 MHz system clock Serial data output Serial data input Serial data reset VCC control flag VPP control flag Detection flag Smartcard 1
PIO0[2] PIO0[3] PIO0[0] PIO0[1] PIO0[4] PIO0[5] PIO0[6] PIO0[7]
SC1_EXTCLKIN SC1_CLKOUT SC1_DATAOUT SC1_DATAIN SC1_RESET SC1_COND_VCC SC1_COND_VPP SC1_DETECT
I O O I O O O I
3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3
External clock Clock for smartcard from 100MHz system clock Serial data output Serial data input Serial data reset VCC control flag VPP control flag Detection flag
PIO1[2] PIO1[3] PIO1[0] PIO1[1] PIO1[4] PIO1[5] PIO1[6] PIO1[7]
6.16.7
Table 30.
Synchronous serial controller (SSC)

SSC pins
I/O Voltage SSC 0 Description Comments
Assignment
SSC0_SCL
I/O
3.3 3.3
SSC 0 serial clock SSC 0 data: master transmit, slave receive/master receive, slave transmit (half duplex mode for example I2C) SSC 0 data: master receive, slave transmit (full duplex mode) SSC 1
PIO2[2] PIO2[3]
SSC0_MTSR/SSC0_M I/O RST SSC0_MRST I/O
3.3
PIO2[4]
SSC1_SCL
I/O
3.3
SSC 1 serial clock
PIO2[5]
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Connections Table 30. SSC pins (continued)

I/O Voltage 3.3 Description SSC 1 data: master transmit, slave receive/master receive, slave transmit (half duplex mode for example I2C) SSC 1 data: master receive, slave transmit (full duplex mode) SSC 2 SSC2_SCL I/O 3.3 SSC 2 serial clock SSC 2 data: master transmit, slave receive/master receive, slave transmit (half duplex mode for example I2C) SSC 3 SSC3_SCL I/O 3.3 SSC 3 serial clock SSC3 data: master transmit, slave receive/master receive, slave transmit (half duplex mode for example I2C) PIO3[6], PIO13[2], PIO13[6] PIO2[1], PIO3[7], PIO13[3], PIO13[7] PIO3[4], PIO12[0], PIO13[4] PIO2[0], PIO3[5], PIO12[1], PIO13[5] Comments PIO2[6]
STi7105
Assignment
SSC1_MTSR/SSC1_M I/O RST SSC1_MRST I/O
3.3
PIO2[7]
SSC2_MTSR/SSC2_M I/O RST
3.3
SSC3_MTSR/SSC3_M I/O RST
3.3
6.16.8
Table 31.
Key Scanner (KS)

KS pins
I/O Voltage Description Comments PIO7[0], PIO5[0] PIO7[1], PIO5[1] O 3.3 Key Scanner outputs PIO7[2], PIO5[2] PIO7[3], PIO5[3] PIO5[4] PIO5[5] I 3.3 Key Scanner inputs PIO5[6] PIO5[7]
Assignment KEY_SCAN_OUT[0] KEY_SCAN_OUT[1] KEY_SCAN_OUT[2] KEY_SCAN_OUT[3] KEY_SCAN_IN[0] KEY_SCAN_IN[1] KEY_SCAN_IN[2] KEY_SCAN_IN[3]
6.17
Pad reset conditions

Table 32 describes the pad reset conditions.
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STi7105 Table 32. Pad reset conditions

Pad reset conditions Ball/Signal name Functional direction I/O System SYSCLKIN SYSCLKOSC NOTASEBRK TRIGGERIN TRIGGEROUT SYSITRQ[3:0] NMI WDOGRSTOUT SYSCLKOUT I I/O I/O I O I/O I O O I I/O I I I O I I O I I I I JTAG TDI TMS TCK NOTTRST TDO I I I I O I I I I O EMI NOTEMICSA NOTEMICSB NOTEMICSC NOTEMICSD NOTEMICSE NOTEMIBE[1:0] NOTEMIOE NOTEMILBA NOTEMIBAA EMIREADYORWAIT NANDWAIT EMIRDNOTWR I/O I/O I/O I/O I/O I/O O I/O I/O I/O I I/O I I I I I I O I I I I I 1 1 1 1 1 1 1 1 1 0 1 1 Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up 0 0 0 1 1 Pull-up Pull-up Pull-up Pull-up 1 0 1 0 0 0 0 1 1 0 0 1 Pull-up Reset value
Connections
Pull up/pull down
Pull-down Pull-down Pull-down Pull-down Pull-down Pull-down Pull-down
SYSCLKINALT FDMAREQ[3:0] NOTRESETIN
Pull-down Pull-up Pull-up
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Connections Table 32. Pad reset conditions (continued)

Pad reset conditions Ball/Signal name Functional direction I/O EMIDATA[15:0] EMIADDR[16:1] EMIADDR[25:17] EMIFLASHCLK EMIBUSREQ EMIBUSGNT I/O I/O I/O I/O I/O I/O I I I I I O PIO PIO0[7:0] PIO1[7:0] PIO2[7:0] I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I I I I I I I I I I I I I I I I O I I 1 1 1 1 1 1 1 x 1 x 1 x 0 x 1 x 1 1 1 1 1 0 0 1 Weak pull-up Weak pull-up Weak pull-up Weak pull-up Weak pull-up Weak pull-up Weak pull-up Weak pull-up Weak pull-up Weak pull-up Weak pull-up Weak pull-up Weak pull-up Weak pull-up Weak pull-up Weak pull-up Weak pull-up Weak pull-up Weak pull-up Weak pull-up Weak pull-up Weak pull-up Weak pull-up 0 1 1 0 0 0 Reset value
STi7105
Pull up/pull down Pull-down Pull-up Pull-up Pull-down
Pull-down
PIO3[7:0] PIO4[7:0] PIO5[7:0] PIO6[7:0] PIO7[7:4] PIO7[3:0] PIO8[7:6] PIO8[5] PIO8[4:0] PIO9[7] PIO9[6] PIO9[5:2] PIO9[1:0] PIO10[7:0] PIO11[7:0] PIO12[7:0] PIO13[7:0] PIO14[7:0] PIO15[3:0] PIO15[7:6] PIO15[5:4]
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STi7105 Table 32. Pad reset conditions (continued)

Pad reset conditions Ball/Signal name Functional direction I/O PIO16[7:5] PIO16[4:0] I/O I/O I I 1 x Reset value
Connections
Pull up/pull down
Weak pull-up
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Basic chip operating modes and multiplexing scenarios
STi7105

The STi7105 has one basic chip operating mode, however, other chip operating modes are supported through pad multiplexing. Following interfaces include ball multiplexing: Ethernet interface, which can support MII and ReduceMII(RMII) External memory interface (EMI), valid in several operating modes, attached to various types of devices Information classified Confidential - Do not copy (See last page for obligations)
7.1
Transport interfaces multiplexing

The PIO multiplexing used for transport interfaces can be configured in the following ways: serial transport stream inputs: up to four serial IN (mapping details in Table 33) parallel transport stream inputs/output: one parallel IN/OUT and two parallel IN (mapping details in Table 34)
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STi7105 Table 33.

Pin
Basic chip operating modes and multiplexing scenarios STi7105 Serial Transport Stream inputs mapping
Parameter Name Description PIO13[4] Direction Configuration Name Description Direction PIO13[5] Configuration Serial transport stream input 0 I No configuration is required TSIN0BYTECLK Transport stream0 data clock input/output Interface Details TSIN0SER/DATA[7] Transport stream0 serial data input
For OUTPUT selection: Config register: SYSTEM_CONFIG49[23:0] Config bus: PIO13_ALTFOP[2:0]_MUX_SEL_BUS[5]=0x000 For INPUT selection: No configuration is required TSIN0BYTECLKVALID Transport stream0 data valid input I No configuration is required TSIN0ERROR Transport stream0 data error input I No configuration is required TSIN0PACKETCLK Transport stream0 packet clock input I No configuration is required
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Name Description PIO13[6] Direction Configuration Name Description PIO13[7] Direction Configuration Name Description PIO14[0] Direction Configuration
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Basic chip operating modes and multiplexing scenarios Table 33.

Pin
STi7105
STi7105 Serial Transport Stream inputs mapping (continued)

Parameter Name Description Direction Interface Details TSIN1SER/DATA[7] Transport stream1 serial data input I For INPUT selection: Config register: SYSTEM_CONFIG4[31:0] Config bus: when PIO12[0], SYSTEM_CONFIG4[9] = 0 when PIO15[4], SYSTEM_CONFIG4[9] = 1 TSIN1BYTECLK Transport stream1 data clock input/output I For INPUT selection: Config register: SYSTEM_CONFIG4[31:0] Config bus: when PIO12[1], SYSTEM_CONFIG4[9] = 0 when PIO15[1], SYSTEM_CONFIG4[9] = 1 TSIN1BYTECLKVALID Transport stream1 data valid input Serial transport stream input 1 I For INPUT selection: Config register: SYSTEM_CONFIG4[31:0] Config bus: when PIO12[2], SYSTEM_CONFIG4[9] = 0 when PIO15[2], SYSTEM_CONFIG4[9] = 1 TSIN1ERROR Transport stream1 data error input I For INPUT selection: Config register: SYSTEM_CONFIG4[31:0] Config bus: when PIO12[3], SYSTEM_CONFIG4[9] = 0 when PIO15[3], SYSTEM_CONFIG4[9] = 1 TSIN1PACKETCLK Transport stream1 packet clock input I For INPUT selection: Config register: SYSTEM_CONFIG4[31:0] Config bus: when PIO12[4], SYSTEM_CONFIG4[9] = 0 when PIO15[0], SYSTEM_CONFIG4[9] = 1
PIO12[0]/ PIO15[4] Configuration
Name Description Direction PIO12[1]/ PIO15[1] Configuration
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STi7105 Table 33.

Pin
Basic chip operating modes and multiplexing scenarios STi7105 Serial Transport Stream inputs mapping (continued)
Parameter Name Description Direction PIO14[1]/ PIO6[0] Configuration Interface Details TSIN2SER/DATA[7] Transport stream2 serial data input I For INPUT selection: Config register: SYSTEM_CONFIG4[31:0] Config bus: when PIO6[0], SYSTEM_CONFIG4[10] = 0 when PIO14[1], SYSTEM_CONFIG4[10] = 1 TSIN2BYTECLK Transport stream2 data clock input I For INPUT selection: Config register: SYSTEM_CONFIG4[31:0] Config bus: when PIO6[1], SYSTEM_CONFIG4[10] = 0 when PIO14[2], SYSTEM_CONFIG4[10] = 1 TSIN2BYTECLKVALID Transport stream2 data valid input Serial transport stream input 2 I For INPUT selection: Config register: SYSTEM_CONFIG4[31:0] Config bus: when PIO6[2], SYSTEM_CONFIG4[10] = 0 when PIO14[3], SYSTEM_CONFIG4[10] = 1 TSIN2ERROR Transport stream2 data error input I For INPUT selection: Config register: SYSTEM_CONFIG4[31:0] Config bus: when PIO6[3], SYSTEM_CONFIG4[10] = 0 when PIO14[4], SYSTEM_CONFIG4[10] = 1 TSIN2PACKETCLK Transport stream2 packet clock input I For INPUT selection: Config register: SYSTEM_CONFIG4[31:0] Config bus: when PIO6[4], SYSTEM_CONFIG4[10] = 0 when PIO14[5], SYSTEM_CONFIG4[10] = 1
Name Description PIO14[3]/ PIO6[2] Direction
Configuration
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Pin
STi7105
STi7105 Serial Transport Stream inputs mapping (continued)

Parameter Name Description Interface Details TSIN3SER/DATA[7] Transport stream3 serial data input I No configuration is required TSIN3BYTECLK Transport stream3 data clock input/output
PIO12[5] Direction Configuration Name Description PIO12[6] Configuration Name Description PIO12[7] Direction Configuration Serial transport stream Input 3 No configuration is required TSIN3BYTECLKVALID Transport STREAM3 data valid input I No configuration is required TSIN3ERROR Transport stream3 data error input I No configuration is required TSIN3PACKETCLK Transport stream3 packet clock input I No configuration is required Direction
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Name Description PIO13[0] Direction Configuration Name Description PIO13[1] Direction Configuration
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STi7105 Table 34.

Pin
Basic chip operating modes and multiplexing scenarios STi7105 Parallel Transport Stream inputs/output mapping
Parameter Name Description PIO13[4] Direction Configuration Name Description Direction PIO13[5] Configuration Parallel transport stream input 0 I No configuration is required TSIN0BYTECLK Transport stream0 data clock input/output Interface Details TSIN0DATA[7] Transport stream0 parallel data input
For OUTPUT selection: Config register: SYSTEM_CONFIG49[23:0] Config bus: PIO13_ALTFOP[2:0]_MUX_SEL_BUS[5]=0x000 TSIN0BYTECLKVALID Transport stream0 data valid input I No configuration is required TSIN0ERROR Transport stream0 data error input I No configuration is required TSIN0PACKETCLK Transport stream0 packet clock input I No configuration is required
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Pin
STi7105
STi7105 Parallel Transport Stream inputs/output mapping (continued)

Parameter Name Description Interface Details TSIN0DATA[6] Transport stream0 parallel data input I No configuration is required TSIN0DATA[5] Transport stream0 parallel data input
PIO14[1] Direction Configuration Name Description PIO14[2] Configuration Name Description PIO14[3] Direction Configuration I No configuration is required TSIN0DATA[3] Parallel transport stream input 0 Transport stream0 parallel data input I No configuration is required TSIN0DATA[2] Transport stream0 parallel data input I No configuration is required TSIN0DATA[1] Transport stream0 parallel data input I No configuration is required TSIN0DATA[0] Transport stream0 parallel data input I No configuration is required No configuration is required TSIN0DATA[4] Transport stream0 parallel data input Direction
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Name Description PIO14[4] Direction Configuration Name Description PIO14[5] Direction Configuration Name Description PIO14[6] Direction Configuration Name Description PIO14[7] Direction Configuration
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STi7105 Table 34.

Pin
Basic chip operating modes and multiplexing scenarios STi7105 Parallel Transport Stream inputs/output mapping (continued)
Parameter Name Description Direction PIO12[0] Configuration Interface Details TSIN1DATA[7]/TSOUTDATA[7] Transport STREAM1 parallel data input/output B For OUTPUT selection: Config register: SYSTEM_CONFIG48[23:0] Config bus: PIO12_ALTFOP[2:0]_MUX_SEL_BUS[0]=0x000 PIO12_ALTFOP[2:0]_MUX_SEL_BUS[0]=0x001 TSIN1BYTECLK/TSOUTBYTECLK Transport stream1 data clock input/output B For OUTPUT selection: Config register: SYSTEM_CONFIG48[23:0] Config bus: PIO12_ALTFOP[2:0]_MUX_SEL_BUS[1]=0x000 PIO12_ALTFOP[2:0]_MUX_SEL_BUS[1]=0x001 Parallel transport stream input 1/ output 0 TSIN1BYTECLKVALID/TSOUTBYTECLKVALID Transport stream1 data valid input/output B For OUTPUT selection: Config register: SYSTEM_CONFIG48[23:0] Config bus: PIO12_ALTFOP[2:0]_MUX_SEL_BUS[2]=0x000 PIO12_ALTFOP[2:0]_MUX_SEL_BUS[2]=0x001 TSIN1ERROR/TSOUTERROR Transport stream1 data error input/output B For OUTPUT selection: Config register: SYSTEM_CONFIG48[23:0] Config bus: PIO12_ALTFOP[2:0]_MUX_SEL_BUS[3]=0x000 PIO12_ALTFOP[2:0]_MUX_SEL_BUS[3]=0x001 TSIN1PACKETCLK Transport stream1 packet clock input/output I No configuration is required
Name Description Direction PIO12[1] Configuration
Name Description PIO12[4] Direction Configuration
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Pin
STi7105

Parameter Name Description Direction Interface Details TSIN1DATA[6]/TSOUTDATA[6] Transport stream1 parallel data input/output B For OUTPUT selection: Config register: SYSTEM_CONFIG48[23:0] Config bus: PIO12_ALTFOP[2:0]_MUX_SEL_BUS[5]=0x000 PIO12_ALTFOP[2:0]_MUX_SEL_BUS[5]=0x001 TSIN1DATA[5]/TSOUTDATA[5] Transport stream1 serial data input/output B For OUTPUT selection: Config register: SYSTEM_CONFIG48[23:0] Config bus: PIO12_ALTFOP[2:0]_MUX_SEL_BUS[6]=0x000 PIO12_ALTFOP[2:0]_MUX_SEL_BUS[6]=0x001 TSIN1DATA[4]/TSOUTDATA[4] Transport stream1 parallel data input/output Parallel transport stream input 1/ output 0 B For OUTPUT selection: Config register: SYSTEM_CONFIG48[23:0] Config bus: PIO12_ALTFOP[2:0]_MUX_SEL_BUS[7]=0x000 PIO12_ALTFOP[2:0]_MUX_SEL_BUS[7]=0x001 TSIN1DATA[3]/TSOUTDATA[3] Transport STREAM1 parallel data input B For OUTPUT selection: Config register: SYSTEM_CONFIG49[23:0] Config bus: PIO13_ALTFOP[2:0]_MUX_SEL_BUS[0]=0x000 PIO13_ALTFOP[2:0]_MUX_SEL_BUS[0]=0x001 TSIN1DATA[2]/TSOUTDATA[2] Transport stream1 parallel data input B For OUTPUT selection: Config register: SYSTEM_CONFIG49[23:0] Config bus: PIO13_ALTFOP[2:0]_MUX_SEL_BUS[1]=0x000 PIO13_ALTFOP[2:0]_MUX_SEL_BUS[1]=0x001
PIO12[5] Configuration
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STi7105 Table 34.

Pin
Parameter Name Description Direction PIO13[2] Configuration Interface Details TSIN1DATA[1]/TSOUTDATA[1] Transport stream1 parallel data input B For OUTPUT selection: Config register: SYSTEM_CONFIG49[23:0] Config bus: PIO13_ALTFOP[2:0]_MUX_SEL_BUS[2]=0x000 PIO13_ALTFOP[2:0]_MUX_SEL_BUS[2]=0x001 TSIN1DATA[0]/TSOUTDATA[0] Transport stream1 parallel data input B For OUTPUT selection: Config register: SYSTEM_CONFIG49[23:0] Config bus: PIO13_ALTFOP[2:0]_MUX_SEL_BUS[3]=0x000 PIO13_ALTFOP[2:0]_MUX_SEL_BUS[3]=0x001
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Pin
STi7105

Parameter Name Description Direction Interface Details TSIN2SER/DATA[7] Transport stream2 parallel data input I For INPUT selection: Config register: SYSTEM_CONFIG4[31:0] Config bus: when PIO6[0], SYSTEM_CONFIG4[10] = 0 when PIO14[1], SYSTEM_CONFIG4[10] = 1 TSIN2BYTECLK Transport stream2 data clock input I For INPUT selection: Config register: SYSTEM_CONFIG4[31:0] Config bus: when PIO6[1], SYSTEM_CONFIG4[10] = 0 when PIO14[2], SYSTEM_CONFIG4[10] = 1 TSIN2BYTECLKVALID Transport stream2 data valid input Parallel transport stream input 2 I For INPUT selection: Config register: SYSTEM_CONFIG4[31:0] Config bus: when PIO6[2], SYSTEM_CONFIG4[10] = 0 when PIO14[3], SYSTEM_CONFIG4[10] = 1 TSIN2ERROR Transport stream2 data error input I For INPUT selection: Config register: SYSTEM_CONFIG4[31:0] Config bus: when PIO6[3], SYSTEM_CONFIG4[10] = 0 when PIO14[4], SYSTEM_CONFIG4[10] = 1 TSIN2PACKETCLK Transport stream2 packet clock input I For INPUT selection: Config register: SYSTEM_CONFIG4[31:0] Config bus: when PIO6[4], SYSTEM_CONFIG4[10] = 0 when PIO14[5], SYSTEM_CONFIG4[10] = 1
PIO14[1]/ PIO6[0] Configuration
Name Description PIO14[3]/ PIO6[2] Direction
Configuration
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STi7105 Table 34.

Pin
Parameter Name Description PIO6[5] Direction Configuration Name Description PIO6[6] Configuration Name Description PIO6[7] Direction Configuration I No configuration is required TSIN2DATA[3] Parallel transport stream input 2 Transport stream2 parallel data input I No configuration is required TSIN2DATA[2] Transport stream2 parallel data input I No configuration is required TSIN2DATA[1] Transport stream2 parallel data input I No configuration is required TSIN2DATA[0] Transport stream2 parallel data input I No configuration is required No configuration is required TSIN2DATA[4] Transport stream2 parallel data input Direction I No configuration is required TSIN2DATA[5] Transport stream2 parallel data input Interface Details TSIN2DATA[6] Transport stream2 parallel data input
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7.2
Ethernet interface multiplexing in standard mode

The Ethernet interface can be configured in the following ways: MII mode RMII mode The mapping is shown in Table 35.
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Pin
STi7105
STi7105 Ethernet muxing details (in standard mode)

Parameter Configuration0 Ethernet MII mode Configuration CONTROL_CONFIG7[16] =1 CONTROL_CONFIG7[18] =1 CONTROL_CONFIG7[26:25] =00 ETHMII_TXCLK Transmit clock I ETHMII_TXEN Transmit enable flag O ETHMII_TXD[3] Transmit data BIT3 O ETHMII_TXD[2] Transmit data BIT2 O ETHMII_TXD[1] Transmit data BIT1 O ETHMII_TXD[0] Transmit data BIT0 O ETHMII_RXCLK Receive clock I ETHMII_RXDV Receive data valid flag I ETHMII_RXER Receive data error flag I ETHMII_RXD[3] Receive data BIT3 I ETHMII_RXD[2] ETHRMII_CRS_DV Receive data valid flag I ETHRMII_RXER Receive data error flag I ETHRMII_TXD[1] Transmit data BIT1 O ETHRMII_TXD[0] Transmit data BIT0 O ETHRMII_TXEN Transmit enable flag O Configuration1 Ethernet RMII mode CONTROL_CONFIG7[16] =1 CONTROL_CONFIG7[18] =0 CONTROL_CONFIG7[26:25] =01
ETHMII_TXCLK
Name Description Direction
ETHMII_TXEN
ETHMII_TXD[3]
ETHMII_TXD[2]
ETHMII_TXD[1]
ETHMII_TXD[0]
ETHMII_RXCLK
ETHMII_RXDV
ETHMII_RXER
ETHMII_RXD[3]
ETHMII_RXD[2]
Name
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STi7105 Table 35.

Pin
Basic chip operating modes and multiplexing scenarios STi7105 Ethernet muxing details (in standard mode) (continued)
Parameter Description Direction Configuration0 Receive data BIT2 I ETHMII_RXD[1] Receive data BIT1 I ETHMII_RXD[0] Receive data BIT0 I ETHMII_CRS Carrier sense flag I ETHMII_COL Carrier collision detect flag I ETHMII_MDC Management data clock O ETHMII_MDIO Management data B ETHMII_MDINT Management data interrupt I ETHMII_PHYCLK PHY clock O ETHRMII_MDC Management data clock O ETHRMII_MDIO Management data B ETHRMII_MDINT Management data interrupt I ETHRMII_PHYCLK PHY clock O ETHRMII_RXD[1] Receive data BIT1 I ETHRMII_RXD[0] Configuration1
ETHMII_RXD[1]
ETHMII_RXD[0]
ETHMII_CRS
ETHMII_COL
ETHMII_MDC
ETHMII_MDIO
ETHMII_MDINT
ETHMII_PHYCLK
7.3
DVB common interface (DVB-CI) transport mode

In the DVB common interface mode, the transport stream is demodulated by the front-end subsystem, sent to the external DVB-CI decryption module through the transport interface (in parallel mode) and sent back again (in parallel mode) to the STi7105.
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Receive data BIT0
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Basic chip operating modes and multiplexing scenarios Figure 18. Chip operating modes multiplexing: DVB-CI mode
STi7105
STi7105 EMI
Control/configuration
Transport
TSIN0 parallel/serial TSIN0
parallel/serial
TSIN1
DVB-CI
TSIN2
parallel/serial
TSIN2
TSOUT
parallel/serial
TSOUT
Details of transport interface mapping on PIOs are provided in Section 7.1: Transport interfaces multiplexing and Table 34. Refer to Section 7.4.6: DVB-CI modes for DVB-CI mapping on EMI pads.
7.4
External memory interface (EMI) operating modes

The EMI can support the following device types, each one associated with different pin mappings: 1. Peripheral/SRAM on page 113 2. Asynchronous NOR-FLASH on page 113 3. Synchronous NOR-FLASH on page 114 4. NAND-FLASH on page 114 5. Serial FLASH on page 115 6. DVB-CI on page 115 7. ATAPI-PIO on page 116 8. PCI on page 116 9. Multi-Chip; independent from all other modes (except PCI) on page 117
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STi7105
7.4.1
Table 36.
Peripheral/SRAM mode
EMI peripheral/SRAM mode: pin mapping
Peripheral/SRAM mode assignment I/O Voltage Description NOTEMICSE,D,C,B,A NOTEMIBE[1:0] NOTEMIOE EMITREADYORWAIT O O O I 3.3 3.3 3.3 3.3 Peripheral chip select E,D,C,B,A External device databus byte enable External device output enable External memory device target ready indicator External read/write access indicator. Common to all devices. External common databus External common address bus
EMI assignment NOTEMICSE,D,C,B,A NOTEMIBE[1:0] NOTEMIOE EMITREADYORWAIT
EMIRDNOTWR EMIDATA[15:0] EMIADDR[25:1]
EMIRDNOTWR EMIDATA[0] EMIADDR[25:1]
3.3
I/O 3.3 O 3.3
Note:
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EMINOTLBA, EMINOTBAA, EMINANDREADYNOTBUSY, and EMIFLASHCLK are not used.
7.4.2
Table 37.
Asynchronous NOR-Flash mode

EMI asynchronous NOR-Flash mode: pin mapping
Asynchronous NOR-Flash mode assignment NOTEMICSE,D,C,B,A NOTEMIOE EMITREADYORWAIT I/O Voltage Description O O I 3.3 3.3 3.3 Chip select E,D,C,B,A External device output enable External memory device target ready indicator External read/write access indicator. Common to all devices. External common databus External common address bus
EMI assignment NOTEMICSE,D,C,B,A NOTEMIOE EMITREADYORWAIT
EMIRDNOTWR
EMIRDNOTWR
3.3
EMIDATA[15:0] EMIADDR[25:1]
EMIDATA[15:0] EMIADDR[24:0]
I/O 3.3 O 3.3
Note:
EMINOTLBA, EMINOTBAA, EMINANDREADYNOTBUSY, and EMIFLASHCLK are not used.
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7.4.3
Table 38.
Synchronous NOR-Flash mode

EMI synchronous NOR-Flash mode: pin mapping
Synchronous NOR-Flash mode assignment I/O NOTEMICSE,D,C,B,A NOTEMIOE NOTEMILBA NOTEMIBAA EMITREADYORWAIT O O O O I Voltage Description 3.3 3.3 3.3 3.3 3.3 Chip select E,D,C,B,A External device output enable Flash device load burst address
EMI assignment NOTEMICSE,D,C,B,A NOTEMIOE NOTEMILBA NOTEMIBAA EMITREADYORWAIT
External memory device target ready indicator External read/write access indicator. common to all devices. External common databus External common address bus Flash clock
EMIRDNOTWR
EMIRDNOTWR
3.3
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EMIDATA[15:0] EMIADDR[25:1] EMIFLASHCLK
EMIDATA[15:0] EMIADDR[24:0] EMIFLASHCLK
I/O O I/O
3.3 3.3 3.3
7.4.4
NAND-Flash mode
Features

Embeds a 1-bit error correcting code (ECC) hardware controller. Can support single level cell (SLC) NAND Flash devices from main Flash providers. Support of 16 Mbyte device per CS. Multiple Flash devices can be addressed, each EMI_CS being statically configured by software, such as EMI Flash CS. An external NOR is issued on READY_NOT_BUSY signals in that case.
Table 39.
EMI NAND-Flash mode: pin mapping

NAND-Flash mode assignment I/O NAND_CS0 NAND_CS1 NAND_CS2 NAND_CS3 NAND_CS4 NAND_REN NAND_WEN O O O O O O O Voltage Description 3.3 3.3 3.3 3.3 3.3 3.3 3.3 External device output enable External read/write access indicator Chip select E,D,C,B,A
EMI assignment NOTEMICSA NOTEMICSB NOTEMICSC NOTEMICSD NOTEMICSE NOTEMIOE EMIRDNOTWR
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STi7105 Table 39.
Basic chip operating modes and multiplexing scenarios EMI NAND-Flash mode: pin mapping (continued)
NAND-Flash mode assignment I/O NAND_AD[15:0] NAND_ALE NAND_CLE I/O O O Voltage Description 3.3 3.3 3.3 External common address/databus
EMI assignment EMIDATA[15:0] EMIADDR[18] EMIADDR[17]
Note:
NOTEMIBE[1:0], NOTEMILBA, NOTEMIBAA, EMITREADYORWAIT, EMIADDR[25:19], EMIADDR[16:1], and EMIFLASHCLK are not used. Information classified Confidential - Do not copy (See last page for obligations)
7.4.5
Table 40.
Assignment
Serial-Flash mode
EMI Serial-Flash pins as PIO alternates
I/O O O I O Voltage Description 3.3 3.3 3.3 3.3 Comments PIO15[0] PIO15[1] PIO15[3] PIO15[2]
SPIBOOT_CLOCK SPIBOOT_DATA_OUT
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SPIBOOT_DATA_IN SPIBOOT_CS
7.4.6
DVB-CI modes
The DVB-CI modes are only available on banks 2 and 3.
Table 41.
EMI DVB-CI mode: pin mapping

Peripheral/SRAM mode assignment DVBCI_NOTCEx DVBCI_NOTIOWR DVBCI_NOTOE DVBCI_NOTWE DVBCI_NOTIORD DVBCI_NOTWAIT DVBCI_DATA[7:0] DVBCI_A[15:1] I/O O O O O O I I/O O Voltage 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 Description Peripheral chip select D,C Write command Output enable Write enable DVBCI Read command Wait signal External common databus Address bus
EMI assignment NOTEMICSD,C NOTEMIBE[0] NOTEMIOE EMIRDNOTWR NOTEMIBAA EMITREADYORWAIT EMIDATA[7:0] EMIADDR[15:1]
Note:
EMI_NOTCSE/B/A, EMI_NOTBE[1], EMI_NOTLBA, EMI_NANDREADYNOTBUSY, EMI_DATA[15:8], EMI_ADDR[25:16], EMI_FLASHCLK are not used
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7.4.7
ATAPI-PIO modes
The ATAPI-PIO modes are only available on banks 2 and 3.
Table 42.
EMI ATAPI-PIO mode: pin mapping

Peripheral/SRAM mode assignment ATAPI_NOTCEx ATAPI_NOTDIOWR ATAPI_NOTDIORD ATAPI_IORDY ATAPI_DATA[15:0] ATAPI_CS[1:0] ATAPI_A[2:1] I/O O O O I I/O O O Voltage 3.3 3.3 3.3 3.3 3.3 3.3 3.3 Description Peripheral chip select D,C Write command Read command Wait signal External common databus Chip select Address bus
EMI assignment NOTEMICSD,C NOTEMIBE[0] NOTEMIBAA EMITREADYORWAIT EMIDATA[15:0] EMIADDR[20:19] EMIADDR[2:1]
Note:
NOTEMICSE/B/A, NOTEMIBE[1], NOTEMIOE, NOTEMILBA, EMIADDR[25:21], EMIADDR[18:3], EMIFLASHCLK are not used.
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7.4.8
Table 43.
PCI mode
EMI PCI mode: pin mapping
Peripheral/SRAM mode assignment I/O PCI_NOTFRAME PCI_CBE[1:0] PCI_NOTPERR PCI_AD[15:0] PCI_CBE[3:2] PCI_NOTDEVSEL PCI_NOTSTOP PCI_NOTIRDY PCI_NOTTRDY PCI_PAR PCI_AD[31:16] PCI_CLK PCI_REQ[0] PCI_GNT[0] I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Voltage 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 Description PCI frame PCI command/byte enable PCI parity error flag Common PCI address/data bus PCI command/byte enable PCI device select PCI target stop request PCI initiator ready flag PCI target ready flag PCI parity flag Common PCI address/data bus PCI clock PCI bus access request PCI bus access grant
EMI assignment NOTEMICSE NOTEMIBE[1:0] EMIRDNOTWR EMIDATA[15:0] EMIADDR[24:23] EMIADDR[22] EMIADDR[20] EMIADDR[19] EMIADDR[18] EMIADDR[17] EMIADDR[16:1] EMIFLASHCLK EMIBUSREQ EMIBUSGNT
Note: Caution:
NOTEMICSD/C/B/A, NOTEMIOE, EMIADDR[25], EMIADDR[21], NOTEMILBA, and EMITREADYORWAIT are not used. Memory read transfers from non-prefetchable memory are always signalled as 32 bits transfers (all byte enables active) by the STi7105. This should be taken into account when considering PCI devices to be used with STi7105.
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STi7105 Table 44.

Assignment PCI_BUS_REQ[1] PCI_BUS_REQ[2] PCI_BUS_GNT[1] PCI_BUS_GNT[2] PCI_LOCK_IN PCI_PME_IN PCI_INT_FROM_DEVICE[0] PCI_INT_FROM_DEVICE[1] PCI_INT_FROM_DEVICE[2] PCI_INT_TO_HOST
Basic chip operating modes and multiplexing scenarios EMI PCI pins as PIO alternates
I/O I I O O I I I I I O Voltage Description 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 PCI bus access request PCI bus access request PCI bus access grant PCI bus access grant PCI lock function PCI PME function PCI interrupt input (when host) PCI interrupt input (when host) PCI interrupt input (when host) Comments PIO6[5] PIO6[6] PIO7[1] PIO7[2] PIO7[0], PIO15[5] PIO15[6]
PIO6[1] PIO6[2]
PCI interrupt output (when device) PIO15[3], PIO6[0] PCI reset input (when host) PCI error flag PIO15[7] PIO15[4]
PCI_RESETN_FROM_HOST_TO_DEVI I CE
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PCI_SYSTEM_ERROR
7.4.9
Multi-chip mode
With the exception of PCI, this mode is independent from all other modes and uses dedicated balls.
Table 45.
EMI multi-chip mode: pin mapping

Peripheral/SRAM mode assignment EMIBUSREQ EMIBUSGNT I/O I/O I/O Voltage 3.3 3.3 Description Bus access request Bus access grant
EMI assignment EMIBUSREQ EMIBUSGNT
EMI multi-chip mode: pins as PIO alternates

Assignment EMI_SS_BUS_FREE_ACCESSPEND/ EMI_SS_BUS_FREE_OUT I/O I Voltage Description 3.3 Access pending flag Comments PIO15[2]
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PIO6[0]/PIO15[3]
Memory map
STi7105
Memory map
The STi7105 memory space is populated with non-volatile memories, with external peripherals (EMI) at base address 0 (ST40 boots at address 0), and with DDR2-SDRAM devices (LMI) at base address 0x0C00 0000 (128 Mbytes) in 29-bit mode or at base address 0x4000 0000 (1024 Mbytes) in 32-bit mode. The STi7105 on-chip peripherals are mapped in area 6 of the ST40 in 29-bit mode. The Figure 19 shows the STi7105 memory and peripheral mapping.
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STi7105 Figure 19. STi7105 memory and peripheral mapping

0x0000 0000 128 M 0x0800 0000 64 M 0x0C00 0000 256M 0 MB
Memory map
EMI PCI Master (29-bit) Reserved (32-bit)

128 MB 192 MB
ST40 29-bit addressing mode LMI #0 (29-bit) Reserved (32-bit)

384 MB 0x1C000 0000 448 MB 512 MB
64 M 0x2000 0000 0x3000 0000 0x4000 0000
Reserved Reserved
Reserved
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LMI #0 (32-bit) Reserved (29-bit)
1536 MB 0x8000 0000
ST40 32-bit addressing mode
1024M
Reserved (32-bit) Reserved (29-bit)
2560 MB 0xC000 0000
0xFC00 0000 960M
4032 MB ST40 core Debug 4048 MB On-chip Peripherals 4080 MB
PCI (32-bit) Reserved (29-bit)
16 MB 0xFD00 0000 32 MB
64M
0xFC00 0000 0xFFFF FFFF 4096 MB
0xFF00 0000 16 MB 0xFFFF FFFF
ST40 core Peripherals
4096 MB
Note:
In SE mode, the ST40 Core Peripherals (P4) appear twice in the STBUS address map. The LMI base address is programmable.
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Memory map
STi7105
8.1
Global Mapping
The internal peripherals addresses are located in ST40-300 P4 region. Grouping is done so that peripherals which belong to the same physical block have contiguous addresses, requiring only one address decoder in each physical block. The Table 46 gives the base address of the external interfaces and internal peripherals.
Table 46.
Target Name EMI
Internal peripheral base addresses

Start Offset 0x0000 0000 0x0800 0000 0x0C00 0000 0x0C00 0000 0x1C00 0000 0x4000 0000 0x4000 0000 0x8000 0000 0xC000 0000 0xFC00 0000 0xFD00 0000 0xFD10 0000 0xFD10 1000 0xFD10 1800 0xFD10 2000 0xFD10 3000 0xFD10 4000 0xFD10 6000 0xFD11 0000 0xFD11 8000 0xFD12 0000 0xFD12 8000 0xFE00 0000 0xFE00 1000 0xFE00 2000 End Offset 0x07FF FFFF 0x0BFF FFFF 0x1BFF FFFF 0x1BFF FFFF 0x3FFF FFFF 0x7FFF FFFF 0x7FFF FFFF 0xBFFF FFFF 0xFBFF FFFF 0xFCFF FFFF 0xFD0F FFFF 0xFD10 0FFF 0xFD10 17FF 0xFD10 1FFF 0xFD10 2FFF 0xFD10 3FFF 0xFD10 5FFF 0xFD10 FFFF 0xFD11 7FFF 0xFD11 FFFF 0xFD12 7FFF 0xFDFF FFFF 0xFE00 0FFF 0xFE00 1FFF 0xFE00 2FFF Size 128M 64M 256M 256M 576M 1024M 1024M 1024M 960M 16M 1M 4K 2K 4K 4K 4K 8K 44K 32K 32K 32K 15200K 4K 4K 4K Description EMI PCI Master, 29-bit mode LMI #0 - HP, 29-bit mode LMI #0 - LP, 29-bit mode Reserved LMI #0 - HP, 32-bit mode LMI #0 - LP, 32-bit mode Reserved PCI Master, 32-bit mode ST40 Core Debug Comms config registers (details in Table 47) Spare 0 plug Reserved PCM player 1 port & config registers PCM reader port & config registers CPXM registers TVOUT FDMA (HDMI, PCM_p1,SPDIF_p, TTxT) (details in Table 48) Reserved Ethernet 0 config registers Reserved Spare 1 plug Reserved Clock Generator B config registers System config registers (GP Registers) HD display config registers
PCI_MASTER_29B LMI0_HP_29B LMI0_LP_29B RESERVED LMI0_HP_32B
LMI0_LP_32B RESERVED PCI_MASTER_32B SH4 CORE DEBUG COMMs SPARE0_PLUG RESERVED PCMP1 PCMR0 CPXM TVOUT_FDMA RESERVED GMAC0 RESERVED SPARE1_PLUG RESERVED CLKGENB SYSC_A HD_DISPLAY
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STi7105 Table 46.

Target Name SD_DISPLAY RESERVED RESERVED T1_PIO KEY_SCAN RESERVED TVOUT_CPU RESERVED USB2_1
Memory map Internal peripheral base addresses (continued)

Start Offset 0xFE00 3000 0xFE00 4000 0xFE00 C000 0xFE01 0000 0xFE02 0000 0xFE02 0800 0xFE03 0000 0xFE03 8000 0xFE10 0000 0xFE20 0000 0xFE20 8000 0xFE20 9000 0xFE20 A000 0xFE20 B000 0xFE20 C000 0xFE20 D400 0xFE21 0000 0xFE21 1000 0xFE21 1800 0xFE21 2000 0xFE21 2800 0xFE21 3000 0xFE21 4000 0xFE22 0000 0xFE23 0000 0xFE24 0000 0xFE24 1000 0xFE24 2000 0xFE24 3000 0xFE25 0000 End Offset 0xFE00 3FFF 0xFE00 BFFF 0xFE00 FFFF 0xFE01 FFFF 0xFE02 07FF 0xFE02 FFFF 0xFE03 7FFF 0xFE0F FFFF 0xFE1F FFFF 0xFE20 7FFF 0xFE20 8FFF 0xFE20 9FFF 0xFE20 AFFF 0xFE20 BFFF 0xFE20 D3FF 0xFE20 FFFF 0xFE21 0FFF 0xFE21 17FF 0xFE21 1FFF 0xFE21 27FF 0xFE21 2FFF 0xFE21 3FFF 0xFE21 FFFF 0xFE22 FFFF 0xFE23 FFFF 0xFE24 0FFF 0xFE24 1FFF 0xFE24 2FFF 0xFE24 FFFF 0xFE25 0FFF Size 4K 32K 16K 64K 2K 62K 32K 800K 1M 32K 4K 4K 4K 4K 5K 11K 4K 2K 2K 2K 2K 4K 48K 64K 64K 4K 4K 4K 52K 4K Description SD display config registers Reserved Reserved T1 PIO - 10 Banks PIOs config registers
Reserved TVOUT Config Regs (Denc, VTGs, TVO_glue, FlexDVO, HD formatter, CEC) (details in Table 49) Reserved USB 2.0 #1 config registers Reserved Reserved SATA config registers Compositor config registers Blitter display config registers Reserved Reserved Audio config registers Mailbox #0 (LX Delta_Mu) config registers Reserved Mailbox #1 (LX Delta_Mu) config registers Reserved Clock Generator A config registers Reserved FDMA_0 memory and config registers PTI_0 config registers Reserved DVP config registers TSMerger config registers Reserved Reserved
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RESERVED RESERVED SATA COMPO BLITTER RESERVED RESERVED AUDIO_CONF MBX0 RESERVED MBX1 RESERVED CLKGENA RESERVED FDMA_0 PTI_0 RESERVED DVP TSMERGER RESERVED RESERVED
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Memory map Table 46.

Target Name RESERVED PTI_1 RESERVED EMISS RESERVED FDMA_1 FDMA_MUX RESERVED DMU PCI_MASTER_REGS
STi7105
Internal peripheral base addresses (continued)

Start Offset 0xFE25 1000 0xFE26 0000 0xFE27 0000 0xFE40 0000 0xFE40 8000 0xFE41 0000 0xFE42 0000 0xFE42 1000 0xFE54 0000 0xFE56 0000 0xFE56 1000 0xFE60 0000 0xFE70 0000 0xFE80 0000 0xFE90 0000 0xFE90 1000 0xFE90 2000 0xFEA0 0000 0xFEB0 0000 0xFF00 0000 End Offset 0xFE25 FFFF 0xFE26 FFFF 0xFE3F FFFF 0xFE40 7FFF 0xFE40 FFFF 0xFE41 FFFF 0xFE42 0FFF 0xFE53 FFFF 0xFE55 FFFF 0xFE56 0FFF 0xFE5F FFFF 0xFE6F FFFF 0xFE7F FFFF 0xFE8F FFFF 0xFE90 0FFF 0xFE90 1FFF 0xFE9F FFFF 0xFEAF FFFF 0xFEFF FFFF 0xFFFF FFFF Size 60K 64K 1600K 32K 32K 64K 4K 1148K 128K 4K 636K 1M 1M 1M 4K 4K 1016K 1M 4M 16M Description Reserved PTI_1 config registers Reserved EMISS config registers (EMISS) (details inTable 50)
FDMA_1 config registers FDMA Mux config registers Reserved Delta Mu configuration registers AHB-PCI config registers (on T3 I) Reserved ST231 Delta Mu peripherals EMI configuration registers (details inTable 50) ST231 audio peripherals TSMerger-Type2 space GPLMI0 control registers Reserved USB 2.0 #2 config registers Reserved ST40 core peripherals
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RESERVED LX_DMU EMIREG LX_AUD TSMERGER_T2 LMI0_REG RESERVED USB2_2 RESERVED SH4 CORE PERIPH
Table 47.
STi7105 Comms sub-blocks memory map (base address: 0xFD00 0000)

Start Offset End Offset Size (Bytes) Description
Region Name
ILC3 RESERVED LPC RESERVED PWM0 RESERVED IRB RESERVED
0x00000 0x01000 0x08000 0x09000 0x10000 0x11000 0x18000 0x19000
0x0FFF 0x07FFF 0x08FFF 0x0FFFF 0x10FFF 0x17FFF 0x18FFF 0x1FFFF
1K 7K 1K 7K 1K 7K 1K 7K
ILC Reserved LPC Reserved PWM0 Reserved IRB group Reserved
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STi7105 Table 47.
Memory map STi7105 Comms sub-blocks memory map (base address: 0xFD00 0000) (continued)
Start Offset 0x20000 0x21000 0x22000 0x23000 0x24000 0x25000 0x26000 0x0101 0000 0x0101 1000 0x0101 2000 0x0101 3000 0x0101 4000 0x0101 5000 0x0101 6000 0x0101 7000 0x0101 8000 0x0101 9000 0x27000 0x30000 0x31000 0x32000 0x33000 0x34000 0x40000 0x41000 0x42000 0x43000 0x44000 0x48000 0x49000 0x4A000 0x58000 0x59000 0x71000 End Offset 0x20FFF 0x21FFF 0x22FFF 0x23FFF 0x24FFF 0x25FFF 0x26FFF 0x0101 0FFF 0x0101 1FFF 0x0101 2FFF 0x0101 3FFF 0x0101 4FFF 0x0101 5FFF 0x0101 6FFF 0x0101 7FFF 0x0101 8FFF 0x0101 9FFF 0x2FFFF 0x30FFF 0x31FFF 0x32FFF 0x33FFF 0x3FFFF 0x40FFF 0x41FFF 0x42FFF 0x43FFF 0x47FFF 0x48FFF 0x49FFF 0x57FFF 0x58FFF 0x6FFFF 0xFFFFF Size (Bytes) 1K 1K 1K 1K PIO 1K 1K Description
Region Name PIO0 PIO1 PIO2 PIO3 PIO4 PIO5 PIO6 PIO7 PIO8 PIO9 PIO10 PIO11
1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 9K 1K 1K UART 1K 1K 12K 1K 1K Synchronous Serial Controller 1K 1K 4K 1K Reserved 1K 14K 1K 23K 143K Reserved MAFE Reserved Reserved Reserved Reserved Reserved PIO
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PIO12 PIO13 PIO14 PIO15 PIO16 RESERVED UART0 UART1 UART2 UART3 RESERVED SSC0 SSC1 SSC2 SSC3 RESERVED RESERVED RESERVED RESERVED MAFE RESERVED RESERVED
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1K
Memory map Table 48. STi7105 TVOUT_FDMA sub-blocks memory map (base address: 0xFD10 4000)
Start Offset End Offset Size (Bytes) 0x0000 0x0800 0x0C00 0x0E00 0x1000 0x1400 0x1800 0x1C00 0x4800 0x4D00 0x4E00 0x07FF 0x0BFF 0x0CFF 0x0FFF 0x13FF 0x17FF 0x1BFF 0x1FFF 0x48FF 0x4DFF 0x4EFF 512 256 64 128 256 Reserved Reserved Description
STi7105
Region Name HDMI_REG RESERVED SPDIFPLAYER_REG RESERVED I2S2SPDIF_1 I2S2SPDIF_2 I2S2SPDIF_3 I2S2SPDIF_4 HDCP PCMPLAYER0_REG TOP_GLUE_AUX
256 256 64 64 64
Table 49.
STi7105 TVOUT_CPU sub-blocks memory map (base address: 0xFE03 0000)

Start Offset End Offset 0x0000 0x0200 0x0300 0x0400 0x0600 0x0800 0x0900 0x0A00 0x0B00 0x0C00 0x1000 0x01FF 0x02FF 0x03FF 0x05FF 0x07FF 0x08FF 0x09FF 0x0AFF 0x0BFF 0x0CFC 0x2FFF Size (Bytes) 128 64 64 64 128 64 64 64 64 63 8K HD formatter 1 HD formatter 2 HD formatter 3 HD formatter 4 Description
Region Name DENC AUX_VTG MAIN_VTG HDTVOUT_TOP_GLUE_MAIN Flex-DVO0 HDTVOUT_HDF1 HDTVOUT_HDF2 HDTVOUT_HDF3 HDTVOUT_HDF4 CEC RESERVED
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STi7105 Table 50. STi7105 EMISS and EMI sub-blocks memory map
Start Offset 0xFE40 0000 + 0x1000 0xFE40 0000 + 0x1400 0xFE70 0000 + 0x0000 0xFE70 0000 + 0x1000 0xFE70 0000 + 0x2000 0xFE70 0000 + 0x3000 End Offset 0xFE40 0000 + 0x13FF 0xFE40 0000 + 0x17FF 0xFE70 0000 + 0x0FFF 0xFE70 0000 + 0x1FFF 0xFE70 0000 + 0x2FFF 0xFE70 0000 + 0xFFFF Size (Bytes) 256 256 1K 1K 1K 13K Description
Memory map
Region Name EMISS_ARBITER_REG EMISS_PCI_BRIDGE_REG EMI_CONF_REG EMI_NAND_REG EMI_SPI_REG RESERVED
EMI/PCI Arbiter registers PCI STbus Bridge registers EMI registers EMI Nand Controller registers EMI SPI Controller registers Reserved
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Interrupt networks
STi7105
9
9.1
Interrupt networks
Interrupt network organization
The STi7105 has two interrupt networks. One network is associated with the ST40 CPU and the other network is associated with the DeltaMu-ST231 CPU when used as as an application processor. The interrupt lines are routed to both ST40 and partially to DeltaMu-ST231. It is up to the software to handle the interrupts with ST40 or DeltaMu-ST231. Information classified Confidential - Do not copy (See last page for obligations) Figure 20. STi7105 interrupt network
Internal Interrupt sources Interrupt Expansion Bus
INTC2 (63-0)
NMI NMI IRL[3:0] VIDDIGOUTYC(15) MDINT Encode to 5 bits
INTC
ST40-300
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Mailbox 0
IRQ (63-3)
ST231 DeltaMu
Mailbox 1
IRQ (63-3)
ST231 Audio
LPC
WAKE_UP ILC_INT_LEVEL
[15:0]
Low power controller Wakeup interrupt
Low power mode UHF data IR data
ILC3
IRB wakeup
IRB wakeup interrupt
NMI MDINT
ILC3 EXT
ILC_EXT_OUT[8:0]
[8:4] left unconnected
IRQ(3:0)
ILC_EXT_OUT[3:0]
Output enable system_config (to be defined)
9.1.1
STi7105 interrupt network

ILC3 interrupt level controller
The STi7105 interrupt network includes an ILC3 interrupt level controller. The ILC3 accepts 96 synchronous interrupt inputs and eight asynchronous interrupt inputs. The external
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Interrupt networks interrupts can have up to five programmable triggering conditions (active high, active low, falling edge, rising edge, or any edge). The ILC3 maps any of these interrupts onto a group of 16 interrupt level outputs that are used in the STi7105 for internal and external interrupts and onto a group of four interrupt levels that are not used. The ILC3 mapping is described in Table 51 and Table 52.
Wake up by interrupt
The ILC3 also has an interrupt output dedicated to the wake-up process. A pulse stretcher receives a transition from the UHF and IR input pins and generates an interrupt connected to one of the external interrupt inputs.
Internal peripheral interrupts

Both the ST40 and the DeltaMu ST231 receive all the internal interrupt requests. It is up to the software to define the CPU that will serve each interrupt request. All the internal interrupts are routed to the INTC2, ST231 Interrupt controller and ILC3. All the internal interrupts are level sensitive and active HIGH.
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External interrupts inputs

The four external asynchronous interrupts and the MDINT interrupts (the Ethernet phy interrupt or fifth IRQ if the Ethernet/DVO pins are configured for Ethernet but the Ethernet phy is either not connected or does not use the MDINT) are routed to the ILC3 interrupt controller before reaching the ST40 and ST231 in order to synchronize and change the polarity if needed. The ST40 expects the interrupts to be active high. These interrupts are then output from the ILC3 to be routed toward the ST40 and DeltaMu ST231.
External interrupts outputs

The ILC3 has the capability to output a subset of the interrupts that are connected to it. Four of these interrupts are software selectable to be output externally for remote devices.
Control of the external interrupts direction

The direction of the external interrupts is controlled by the configuration register SYSTEM_CONFIG10. Table 51. ILC3 internal interrupt mapping
ILC3 mapping PIO0_INTERRUPT PIO1_INTERRUPT PIO2_INTERRUPT Comms/PIO PIO3_INTERRUPT PIO4_INTERRUPT PIO5_INTERRUPT PIO6_INTERRUPT 0 1 2 3 4 5 6
Interrupt source
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Interrupt networks Table 51. ILC3 internal interrupt mapping (continued)
STi7105
Interrupt source SSC0_INTERRUPT SSC1_INTERRUPT SSC SSC2_INTERRUPT SSC3_INTERRUPT UART0_INTERRUPT UART1_INTERRUPT Comms/UART UART3_INTERRUPT Comms/MAFE Comms/PWM Comms/IRB Comms/TTXT MAFE_INTERRUPT PWM_INTERRUPT IRB_INTERRUPT TTXT_INTERRUPT DAA_INTERRUPT DVP_INTERRUPT RESERVED DCXO_INTERRUPT PTI1_INTERRUPT ST40_LX_DELTAMU_INTERRUPT LX_DELTAMU_ST40_INTERRUPT MAILBOX ST40_AUDIO_INTERRUPT LX_AUDIO_ST40_INTERRUPT FDMA_1_MBOX_INTERRUPT FDMA0/1 FDMA_0_MBOX_INTERRUPT I2S2SPDIF_INTERRUPT0 SPDIFPLYR_INTERRUPT Audio PCMRDR_INTERRUPT PCMPLYR1_INTERRUPT PCMPLYR0_INTERRUPT Reserved RESERVED AUX_VTG_INTERRUPT (1) OR AUX_VTG_INTERRUPT (0) TVOUT/VTGs MAIN_VTG_INTERRUPT (1) OR MAIN_VTG_INTERRUPT (0) MAIN_VDP_END_PROCESSING_IRQ Main Video Display Pipe MAIN_VDP_FIFO_EMPTY_IRQ UART2_INTERRUPT
ILC3 mapping 7 8 9 10 11 12
14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
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Comms/DAA DVP Reserved ClockGen PTI1
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STi7105 Table 51. ILC3 internal interrupt mapping (continued)
Interrupt networks
Interrupt source HDCP_INTERRUPT HDMI_INTERRUPT HDMI/HDCP HDMI_CEC_IRQ HDMI_CEC_WAKEUP_INT Blitter display BDISP_AQ1_IRQP OR BDISP_AQ2_IRQP OR BDISP_AQ3_IRQP OR BDISP_AQ4_IRQP RESERVED RESERVED RESERVED RESERVED PTI0 RESERVED USBH PTI0_INTERRUPT RESERVED EHCI_INTERRUPT
ILC3 mapping 40 41 42 43 44
46 47 48 52 53 54 55 56 57 58 59 60 62 63
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OHCI_INTERRUPT RESERVED RESERVED RESERVED RESERVED TS Merger Ethernet GMAC PCI BLITTER DISPLAY RESERVED RESERVED TS_MERGER_INTERRUPT PMT_INT INT_PCI_DMA BDISP_CQ1_IRQP OR BDISP_CQ2_IRQP RESERVED
Table 52.
ILC3 external interrupt mapping table

ILC3 mapping EXT_INTERRUPT[0] 0 1 2 3 4 5 6 7 8
Interrupt source
External Interrupts from external devices
EXT_INTERRUPT[1] EXT_INTERRUPT[2] EXT_INTERRUPT[3]
From pins through pulse stretcher NMI Pin Ethernet PHY interrupt /SYSITRQ[4] From LPC timer
IRB_WAKEUP_INTERRUPT NMI_INTERRUPT MDINT LOWPOWEROUT_FROM_LPC
From Pads through PIO alt (PCI wake-up PCI_PME_IN interrupts) FDMA0 requests line
selected FDMA_REQ among 32 FDMA DREQ lines 9
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Interrupt networks Table 52. ILC3 external interrupt mapping table (continued)
STi7105
Interrupt source SATA_IINTRQ_DMAC_0 eSATA SATA_IINTRQ_HOSTC_0 Key Scanner Ethernet Gmac Standalone 10 banks PIOs KEY_SCANNER_INTERRUPT GMAC_MAC_INTR STANDALONE_10_BANKS_PIO (10 ORED INTERRUPTS) AUX_VDP_END_PROCESSING_IRQ VDP AUX AUX_VDP_FIFO_EMPTY_IRQ Compo Capture Compo Capture FDMA1 requests lines Reserved COMPO_CAP_BF COMPO_CAP_TF
ILC3 mapping 10 11 12 13 14 15 16 17 18
SELECTED FDMA_REQ AMONG 32 FDMA DREQ 19 LINES RESERVED IRQ_CLKOBS DELPHI_MBE_INTERRUPT 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 33
ClockGen A DeltaMu
DELPHI_PRE0_INTERRUPT NAND Controller INT_NAND IRQ_PCI_ERROR IRQ_PCI_FROM_DEVICE[0] PCI IRQ_PCI_FROM_DEVICE[1] IRQ_PCI_FROM_DEVICE[2] RESERVED I2S2SPDIF_INTERRUPT1 Audio I2S2SPDIF_INTERRUPT2 I2S2SPDIF_INTERRUPT3 RESERVED Reserved RESERVED RESERVED RESERVED RESERVED
95
9.1.2
ST40 interrupt network

Internal and external interrupts
The ST40-300 CPU has two types of interrupts.
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Interrupt networks
External interrupts

Non maskable interrupts (NMI)external interrupt source. Interrupt request level INTerrupts (IRLINT)four external interrupt sources IRL0 to IRL3 which can be configured as four independent interrupts or encoded to provide 15 external interrupt levels.
These interrupts are managed by the INTC interrupt controller integrated into the ST40-300 CPU core. The four external asynchronous interrupts and the MDINT interrupts (that is, the Ethernet phy interrupt or fifth IRQ if the Ethernet phy is either not connected or does not use the MDINT) are routed to the ILC3 interrupt controller before reaching the ST40 and ST231 in order to synchronize and change the polarity if needed.
Internal peripheral interrupts
On-chip peripherals interrupt sources.
These interrupts are managed by INTC and INTC2 which is an expansion to INTC. All interrupts (except NMI) are assigned a priority level between 0 and 15: level 15 is the highest and level 1 the lowest, level 0 means that the interrupt is masked. The NMI is defined to have a fixed priority level of 16. INTC controls the following interrupt sources: NMI, IRL[3...0] from external inputs ST40-P130 peripherals interrupts: user debug interface (UDI) timer unit (TMU0, 1) real time clock (RTC) serial controller interface (SCI) watch dog timer (WDT)
The INTC2 controls all the on-chip peripherals interrupts and is connected to the INTC through an interrupt expansion bus. The INTC2 accepts 16 groups of four interrupts (64 total), each group can be assigned a priority by software (INTPRIxx registers). Within each group (of four interrupts), there is a fixed priority, with interrupt four having the highest priority. All interrupts are synchronized in INTC2.
Interrupt service routine address

Whenever an interrupt occurs, the ST40 CPU branches to the interrupt handling vector address determined by adding the fixed offset 0x600 to the vector base address (VBR) register. Each interrupt type is assigned a code which is stored in the INTEVT (Interrupt Event) register when the interrupt occurs. This enables the interrupt service routine to identify the interrupt source type. The interrupt controller is responsible for mapping each interrupt to its code (INTEVT). Figure 21 displays the ST40-300 interrupt network, and Table 53 describes the internal interrupts with their INTEVT code.
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Interrupt networks Figure 21. ST40 interrupt network

ST40-300
ST40-C300 (CPU core) IRQ
STi7105
Interrupt status signals WDT TMU UDI INTC
NMI IRL[3:0]
External Interrupt Sources

GLOBAL_POWER_DOWN (refer to low power chapter)
Interrupt expansion bus
[4]
0000
5 bits Interrupt priority [15:0]
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Encode to WAKEUP_BY_INT (refer to low power chapter)
intreq_n intlevel[3:0] intevent[8:0] ext_intstb
ILC3
INTC2
16 groups of 4 interrupts Internal interrupts (x64)
External interrupts (x96)
On-chip peripherals
Table 53.
ST40-300 P130 interrupts

INTEVT code 0x1C0 IRL0 0x240 0x2A0 0x300 0x360 0x200~0x3C0 0x400 0x420 IPR (bit numbers) IPRD[15:12] IPRD[11:8] IPRD[7:4] IPRD[3:0] IPRA[15:12] IPRA[11:8] Interrupt priority (initial value) 16 15-0 (13) 15-0 (10) 15-0 (7) 15-0 (4) 1-15 15-0 (0) 15-0 (0)
Interrupt source NMI
IRL independent encoding
IRL1 IRL2 IRL3
IRL TMU0 TMU1
level encoding TUNI0 TUNI1
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STi7105 Table 53. ST40-300 P130 interrupts (continued)

INTEVT code TUNI2 TMU2 TICPI2 WDT UDI ITI H-UDI 0x460 0x560 0x600 IPRB[15:12] IPRC[3:0] 15-0 (0) 15-0 (0) 0x440 IPRA[7:4] 15-0 (0) IPR (bit numbers)
Interrupt networks
Interrupt source
Interrupt priority (initial value)
Table 54.
Group
ST40-300 on-chip peripheral interrupts Information classified Confidential - Do not copy (See last page for obligations)
Interrupt source I2S2SPDIF_INTERRUPT0 I2S2SPDIF_INTERRUPT1 AUDIO I2S2SPDIF_INTERRUPT2 I2S2SPDIF_INTERRUPT3 INTRQ_DMAC eSATA INTRQ_HOSTC DVP DVP_INTERRUPT 0xB00 0xB20 INTPRI00[7:4] INTREQ00[5] INTREQ00[6] INTREQ00[7] INTPRI00[11:8] INTREQ00[8] INTREQ00[9] INTREQ00[10] INTREQ00[11] INTPRI00[15:12] INTPRI00[19:16] INTPRI00[23:20] INTREQ00[12] INTREQ00[13] INTREQ00[14] INTREQ04[0] INTREQ04[1] INTPRI04[3:0] PIO4_INTERRUPT PIO3_INTERRUPT SSC0_INTERRUPT SSC1_INTERRUPT 0x1040 0x1060 0x10E0 0x10C0 INTPRI04[7:4] SSC2_INTERRUPT SSC3_INTERRUPT 0x10A0 0x1080 INTREQ04[5] INTREQ04[4] INTREQ04[2] INTREQ04[3] INTREQ04[7] INTREQ04[6] 0xA40 0xA60 0xA80 INTEVT code 0xA00 0xA20 INTPRI00[3:0] INTREQ00[2] INTREQ00[3] INTREQ00[4] IPR (bit numbers) INTREQ/INTMSK (bit number) INTREQ00[0] INTREQ00[1]
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group 0
Standalone 10 banks PIOs
STANDALONE_10_BANKS_PI 0xB40 O (10 ORED INTERRUPTS) AUX_VDP_END_PROCESSIN 0xB60 G_IRQ AUX_VDP_FIFO_EMPTY_IRQ 0xB80 COMPO_CAP_BF 0xBA0 0xBC0 0xC00 0xC80 0xD00 0x1000 0x1020
VDP AUX
Compo Capture COMPO_CAP_FF PIO0_INTERRUPT COMMs/PIO PIO1_INTERRUPT PIO2_INTERRUPT PIO6_INTERRUPT PIO5_INTERRUPT group1 COMMs/PIO
group2
SSC
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Interrupt networks Table 54.

Group
STi7105
ST40-300 on-chip peripheral interrupts (continued)

Interrupt source UART0_INTERRUPT UART1_INTERRUPT INTEVT code 0x1160 0x1140 INTPRI04[11:8] UART2_INTERRUPT UART3_INTERRUPT COMMs/MAFE COMMs/PWM MAFE_INTERRUPT PWM_INTERRUPT IRB_INTERRUPTS COMMs/IRB IRB_WAKEUP_INTERRUPT COMMs/TTXTDAA TTXT_INTERRUPT DAA_INTERRUPT BDISP_AQ1_IRQP OR BDISP_AQ2_IRQP OR BDISP_AQ3_IRQP OR BDISP_AQ4_IRQP RESERVED TS_MERGER_INTERRUPT PMT_INT 0x1180 0x1260 0x1240 INTPRI04[19:16] 0x1220 INTREQ04[17] INTREQ04[12] INTREQ04[19] INTREQ04[18] 0x1120 0x1100 0x11E0 0x11C0 INTPRI04[15:12] 0x11A0 INTREQ04[13] INTREQ04[9] INTREQ04[8] INTREQ04[15] INTREQ04[14] IPR (bit numbers) INTREQ/INTMSK (bit number) INTREQ04[11] INTREQ04[10]
group3
COMMs/UART
group5
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BLITTER DISPLAY RESERVED TS merger
0x1200 0x12E0 0x12A0 INTPRI04[23:20] 0x12C0 0x1280 0x1360 0x1340 0x1320 INTPRI04[27:24]
INTREQ04[16 INTREQ04[23] INTREQ04[21] INTREQ04[22] INTREQ04[20] INTREQ04[27] INTREQ04[26] INTREQ04[25] INTREQ04[24] INTREQ04[31] INTREQ04[30] INTPRI04[31:28] INTREQ04[29] INTREQ04[28] INTREQ08[3] INTREQ08[2] INTPRI08[3:0] INTREQ08[1] INTREQ08[0]
group 6
Ethernet GMAC GMAC_MAC_INTR PCI PTI1 ClockGen INT_PCI_DMA PTI1_INTERRUPT DCXO INTERRUPT LX_AUDIO_ST40_INTERRUP T MAILBOXes LX_DELTAMU_ST40_INTERR 0x1300 UPT EHCI1_INTERRUPT USB2 OHCI1_INTERRUPT 0x13C0 0x13E0
group7
group8 FDMA_1_MBOX_INTERRUPT 0x13A0 FDMA0/1 FDMA_0_MBOX_INTERRUPT 0x1380 SPDIFPLYR_INTERRUPT PCMRDR_INTERRUPT group9 Audio PCMPLYR1_INTERRUPT (AUDIO SS) PCMPLYR0_INTERRUPT (TVOUT SS) 0x1460 0x1440 0x1420 0x1400
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STi7105 Table 54.

Group
Interrupt networks ST40-300 on-chip peripheral interrupts (continued)

Interrupt source VIDEO DELTAMU DELTAMU_MBE_INTERRUPT DELTAMU_PP_INTERRUPT INTEVT code 0x14E0 0x14C0 INTPRI08[7:4] NAND Controller RESERVED INT_NAND RESERVED AUX_VTG_INTERRUPT (1) OR AUX_VTG_INTERRUPT (0) TVOUT/VTGs MAIN_VTG_INTERRUPT (1) OR MAIN_VTG_INTERRUPT (0) MAIN_VDP_END_PROCESSI NG_IRQ MAIN_VDP_FIFO_EMPTY_IR Q HDCP_INTERRUPT HDMI_INTERRUPT 0x14A0 0x1480 0x1560 INTREQ08[5] INTREQ08[4] INTREQ08[11] IPR (bit numbers) INTREQ/INTMSK (bit number) INTREQ08[7] INTREQ08[6]
group10
0x1540 INTPRI08[11:8] 0x1520 0x1500 0x15E0 0x15C0 INTPRI08[15:12] 0x15A0 0x1580 0x1660 0x1640 INTPRI08[19:16] 0x1620 0x1600 0x16E0 0x16C0 INTPRI08[23:20] 0x16A0 0x1680 0x1760 0x1740 0x1720 0x1700 0x17E0 INTPRI08[31:28] INTPRI08[27:24]
INTREQ08[10]
group11
INTREQ08[9] INTREQ08[8] INTREQ08[15] INTREQ08[14] INTREQ08[13] INTREQ08[12] INTREQ08[19] INTREQ08[18] INTREQ08[17] INTREQ08[16] INTREQ08[23] INTREQ08[22] INTREQ08[21] INTREQ08[20] INTREQ08[27] INTREQ08[26] INTREQ08[25] INTREQ08[24] INTREQ08[31] INTREQ08[30] INTREQ08[29] INTREQ08[28]
VDP MAIN DISPLAY PIPE
group12 HDMI/HDCP HDMI_CEC_INT HDMI_CEC_WAKEUP_INT RESERVED RESERVED group13 RESERVED PTI0 RESERVED RESERVED group14 RESERVED RESERVED BLITTER DISPLAY group15 RESERVED USB1 OHCI_INTERRUPT RESERVED Key Scanner group16 RESERVED RESERVED 0x17A0 0x1780 RESERVED RESERVED RESERVED BDISP_CQ1_IRQP OR BDISP_CQ2_IRQP RESERVED EHCI_INTERRUPT PTI0_INTERRUPT RESERVED RESERVED
KEY_SCANNER_INTERRUPT 0x17C0
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Interrupt networks
STi7105
9.1.3
DeltaMU and LX_AUDIO ST231 interrupt network

The ST231 accepts 60 external interrupts (from 63 to 3). Interrupts 0 to 2 are Reserved to the ST231 internal timers. All the interrupts are maskable but with a single level of priority. Multiple level priority must be implemented in the software. When used as an application processor, the DeltaMU ST231 processor receives a subset of the internal interrupts from the ST40 processor. The interrupts are active high and are re-synchronized in the ST231 clk_bus clock domain. When used as an application processor, the DeltaMU ST231 processor receives the same internal interrupts as ST40 processor except the interrupts generated by the DeltaMU coprocessors, the MES, ICAM3 interrupts, and Blitter Display interrupts. The DeltaMu ST231 also receives the external interrupts through the ILC3 interrupt controller. The AUDIO_LX receives audio peripherals and FDMA interrupts in order to manage audio applications without relying on the ST40 Host. Also, it executes soft modem (MAFE, DAA interrupts) Table 55 describes the mapping of the interrupts on the DeltaMU ST231 interrupt controller.
Table 55.
DeltaMU ST231 interrupts

INT number TIMER0_INTERRUPT TIMER1_INTERRUPT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
Interrupt source
ST231 Timers TIMER2_INTERRUPT RESERVED PIO0_INTERRUPT PIO1_INTERRUPT PIO2_INTERRUPT Comms/PIO PIO3_INTERRUPT PIO4_INTERRUPT PIO5_INTERRUPT SSC0_INTERRUPT SSC1_INTERRUPT SSC SSC2_INTERRUPT SSC3_INTERRUPT UART0_INTERRUPT UART1_INTERRUPT Comms/UART UART2_INTERRUPT UART3_INTERRUPT Comms/MAFE Comms/PWM MAFE_INTERRUPT PWM_INTERRUPT
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STi7105 Table 55. DeltaMU ST231 interrupts (continued)
Interrupt networks
Interrupt source IRB_INTERRUPT Comms/IRB IRB_WAKEUP_INTERRUPT Comms/TTXT Comms/DAA DVP TS Merger Ethernet GMAC PMT_INT ClockGen MAILBOX PTI1 FDMAs DCXO_INTERRUPT ST40_TX_DELTAMU_INTERRUPT PTI1_INTERRUPT FDMA_1_MBOX_INTERRUPT TTXT_INTERRUPT DAA_INTERRUPT DVP_INTERRUPT TS_MERGER_INTERRUPT GMAC_MAC_INTR
INT number 20 21 22 23 24 25
27 28 29 30 31 32
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FDMA_0_MBOX_INTERRUPT I2S2SPDIF_INTERRUPT0 OR I2S2SPDIF_INTERRUPT1 OR I2S2SPDIF_INTERRUPT2 OR I2S2SPDIF_INTERRUPT3 Audio SPDIFPLYR_INTERRUPT PCMRDR_INTERRUPT PCMPLYR1_INTERRUPT PCMPLYR0_INTERRUPT RESERVED RESERVED AUX_VTG_INTERRUPT (1) OR AUX_VTG_INTERRUPT (0) TVOUT/VTGS MAIN_VTG_INTERRUPT (1) OR MAIN_VTG_INTERRUPT (0) VDP_END_PROCESSING_IRQ MAIN VIDEO DISPLAY PIPE VDP_FIFO_EMPTY_IRQ HDCP_INTERRUPT HDMI_INTERRUPT HDMI/HDCP HDMI_CEC_IRQ HDMI_CEC_WAKEUP_IRQ BDISP_AQ1_IRQP OR BDISP_AQ2_IRQP OR BDISP_AQ3_IRQP OR BDISP_AQ4_IRQP
33
34 35 36 37 38 39 40 41 42 43 44 45 46
BLITTER DISPLAY
47
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Interrupt networks Table 55. DeltaMU ST231 interrupts (continued)

INT number RESERVED RESERVED RESERVED RESERVED PTI0 RESERVED RESERVED USB1 OHCI0_INTERRUPT NMI_INTERRUPT PADS RESERVED EXT_INTERRUPT[0] EXT_INTERRUPT[1] External interrupts 59 60 61 62 63 57 58 PTI0_INTERRUPT RESERVED RESERVED EHCI0_INTERRUPT 48 49 50 51 54 55
STi7105
Interrupt source
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EXT_INTERRUPT[2] EXT_INTERRUPT[3]
Caution:
In case of USB signals, the usual naming convention is not used. In order to align with the STi7105 ballout names, this manual mentions two instances of USB as USB1 and USB2 rather than USB0 and USB1. Therefore, in this manual the first instance of USB is USB1 and the second instance is USB2. The Table 56 describes the mapping of the interrupts on the LX_AUDIO ST231 interrupt controller. Table 56. LX_AUDIO ST231 interrupts
INT number TIMER0_INTERRUPT ST231 timers TIMER1_INTERRUPT TIMER2_INTERRUPT MAILBOX1 RESERVED Comms/MAFE RESERVED Comms/DAA RESERVED Audio I2S2SPDIF_INTERRUPT FDMA_1_MBOX_INTERRUPT FDMA FDMA_0_MBOX_INTERRUPT 34 32 33 ST40_LX_AUDIO_INTERRUPT RESERVED MAFE_INTERRUPT RESERVED DAA_INTERRUPT RESERVED RESERVED(CPXM_INTERRUPT) 0 1 2 3 17-4 18 22-19 23 30-24 31
Interrupt source
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STi7105 Table 56. LX_AUDIO ST231 interrupts (continued)
Interrupt networks
Interrupt source SPDIFPLYR_INTERRUPT0 SPDIFPLYR_INTERRUPT1 SPDIFPLYR_INTERRUPT2 Audio SPDIFPLYR_INTERRUPT3 PCMRDR_INTERRUPT PCMPLYR1_INTERRUPT PCMPLYR0_INTERRUPT RESERVED RESERVED RESERVED RESERVED Reserved RESERVED RESERVED RESERVED RESERVED
INT number 35 36 37 38 39 40
42-51 54 55 56-62 63
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FDMA
STi7105
10
10.1
FDMA
Overview
The STi7105 integrates two multiple-channel general purpose DMA engines, FDMA0 and FDMA1. Each FDMA engine is a general purpose direct memory access controller capable of supporting 16 independent DMA channels. Their purpose is to move data efficiently from memory to memory, memory to peripheral, and peripheral to peripheral. The FDMA supports free-running and paced transfers. The CPU sets up each DMA transfer by writing linked-lists of data structures in to main memory, then the CPU initializes the transfer by writing the pointer to the first node in the control word interface (CWI) of the FDMA. The FDMA then executes the necessary operations to complete the transfer and informs the CPU (through interrupts) after completion of the transfer. The FDMA1 includes video stream parsing functionalities: video PES parsing and start-code detection (PES/SCD) for H264, VC1, AVS, and MPEG2 dual PES parsing channel on same FDMA
10.1.1
FDMA0 and FDMA1 Partitioning

In STi7105, one FDMA is dedicated to serve real-time processes while the other FDMA handles the other processes, such as PES parsing, free-running, and non-critical paced channels. The partitioning between FDMA0 and FDMA1 is as follows: FDMA0real time paced channels: PCM players 0, 1, S/PDIF players, and SWTS (or playback) FDMA1free-running channels, PES parsing, and non-real-time paced channels (that is, COMMS and PCI) This partitioning is defined by software and is flexible. The Dreq crossbar-router, in front of the FDMAs, allows to route any paced peripheral Dreq signal to any FDMA Dreq input.
10.1.2
Peripheral and memory access

Each FDMA has two STBus Type-2 initiator ports. The Port0 (high priority port) has a direct connection to the paced peripherals. This direct connection minimizes the latency between the FDMA and peripherals. While defining the FDMA node, the Port0 is used to access the peripherals and Port1 (low priority port) is used to access the memory. LMI can be accessed by FDMA0 and FDMA1.
10.1.3
FDMA processing power

The FDMA slim core frequency is configurable up to 450 MHz.
10.1.4
FDMA firmware
FDMA0 uses real-time firmware, and FDMA1 uses non-real-time firmware.
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STi7105
FDMA
10.1.5
FDMA features
Following are the FDMA features: Support for 16 concurrent DMA channels Free-running transfer of aligned or unaligned data structure Single location (0D) Incrementing linear arrays (1D) Incrementing rectangular arrays (2D) Transfer units of 1-32 bytes Up to 128 bytes message support Programmable opcode for paced transfer, support for up to 30 request generating peripherals (Dreq)

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Linked-list control allowing complex transfer sequence Video PES parsing (VC1, H264, MPEG2, AVS) on channel 0 and 1 Audio compressed or PCM data output through S/PDIF player Hold off support per channel Secure/insecure transfer support NAND controller channel for AFM mode transfer to/from NAND devices
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FDMA
STi7105
10.2
Block diagram
Figure 22. FDMA block diagram
CLK_SLIM CLK_STBUS_T2_0 clk_stbus_t2_1
FDMA T2 STBus Initiator Data RAM

(8 Kbytes)
32
SLIM CPU
Register File
32
Instruction RAM
(12 Kbytes)
Byte Aligner
GPout(0)
O_MAILBOX_FLAG To Interrupt Controller
Each FDMA comprises a SLIM CPU, an instruction memory, a data memory, peripherals, an STBus T1 target interface, and a SLIM STBus initiator coprocessor. Each FDMA interfaces with the STBus interconnect through two STBus T2 initiator ports to execute the data transfers and through one STBus T1 target port to access the FDMA2 registers and memories. Each STBus port has its own separate asynchronous clock input.
10.3
DMA requests
The FDMA receives a number of requests where pacing is required for flow control in the system. This signal is a simple high-level sensitive signal used in conjunction with a hold-off counter. The blocks generating a request signal are the audio peripherals (PCM players, PCM reader, and S/PDIF player), transport TSMerger (software stream), UARTs, SSCs, PCI controller, NAND controller and external DMA requests.
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T2 STBus Initiator
T2 interface
System Interconnect
STBus T2 Initiator
T1 STBus Target
Coprocessor
T2 interface
STi7105 Figure 23. FDMA requests

FDMA_req[1:0] External IOs COMMs
FDMA
uart_tx_buf_half_empty<3:0> 4x UART uart_rx_buf_half_full<3:0>
SSC_TX_BUF_EMPTY<3:0> 4x SSC SSC_RX_BUF_FULL<3:0> DMA_REQ[31:0]
FDMA #0
AudioPeriph. PCM reader O_COUNTER_REQ
DREQ XBAR FDMA
PCM player 0,1 DMA_REQ[31:0]
S/PDIF player O_COUNTER_REQ Transport TS merger 3x swts req
FDMA #1
EMI Subsystem PCI control.
Nand control.
The FDMA accepts up to 30 DMA requests or events that are used to drive the paced channels of the FDMA. Requests 0 and 31 are reserved for the counter request and are internally connected to the FDMA counter to provide timed DMA channels. Request #0 has the lowest priority and request #31 has the highest priority.
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FDMA Table 57. FDMA request configuration

FDMA DREQ line Xbar Input Index Transfer Size
STi7105
FDMA #0
PCI controller
PCI_HALF_FULL NAND_AFM_DATA_REQ
52 50 49 46 45 42 40 39 37 34 32 31 30 29 28 27 3 4 26 25 24 23 22 21
x x x x x x x x x x x x x x x x x x x x x x x x
10 28 27 19 18 30 30 29 27 23 21 20 19 18 16 21 17 20 16 15 14 13 12 11
ST32 ST32 LD32 LD4 LD4 ST4 ST4 ST4 LD4 ST4 LD4 ST4 LD4 ST4 ST/LD32 ST/LD32 ST/LD32 ST/LD32 ST4 ST4 ST4 ST4 LD4 LD4
Opcode
Unit
PACING SIGNAL
FDMA #1
Comments
index
ST32 x4 ST32 x1 LD32 xn LD4 x1 IRB requests LD4 x1 ST4 x11 ST4 x4 ST4 x20 LD4 x2 ST4 x20 LD4 x32 ST4 x32 LD4 x32 ST4 x32 ST/LD32 x4 ST/LD32 x4 ST/LD32 x4 ST/LD32 x4 ST4 x1 ST4 x1 ST4 x1 ST4 x1 LD4 x1 LD4 x1 128 bytes fifo Ttxt FIFO is 2x48 bytes = 2 lines Includes a 24 bytes FIFO Includes a 160 bytes FIFO Includes a 8 bytes FIFO Includes a 160 bytes FIFO 128 bytes fifo Data request in Advanced Flex mode
NAND controller NAND_AFM_SEQ_REQ IRB_UHF_RX_BUFFER_FULL IRB/UHF IRB_UHF_RX_BUFFER_HALF 8FULL TELETEXT_DREQ HDMI_SPDIF_DREQ HDMI_PCM_DREQ PCMIN_DREQ PCMOUT1_DREQ CPXM_ENCRYPT_OUT_DRE Q CPXM_ENCRYPT_IN_DREQ CSS/CPxM decryption CPXM_DECRYPT_OUT_DRE Q CPXM_DECRYPT_IN_DREQ EXTDMAREQ1_DREQ EXTDMAREQ0_DREQ External DMA req EXTDMAREQ2_DREQ EXTDMAREQ3_DREQ UART#3 Tx UART#2 Tx UART#1 Tx UART#0 Tx UART#3 Rx UART#2 Rx UART3_TX_HALF_EMPTY UART2_TX_HALF_EMPTY UART1_TX_HALF_EMPTY UART0_TX_HALF_EMPTY UART3_RX_HALF_FULL UART2_RX_HALF_FULL
TeleText DENC #0
Confidential
HDMI S/PDIF Player HDMI PCM Player #0 PCM reader PCM Player #1
CSS/CPxM encryption
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STi7105 Table 57. FDMA request configuration (continued)

FDMA DREQ line Xbar Input Index Transfer Size
FDMA
FDMA #0
UART#1 Rx UART#0 Rx SSC#3 Tx SSC#2 Tx SSC#1 Tx SSC#0 Tx SSC#3 Rx SSC#2 Rx SSC#1 Rx
UART1_RX_HALF_FULL UART0_RX_HALF_FULL SSC3_TX_BUF_EMPTY SSC2_TX_BUF_EMPTY SSC1_TX_BUF_EMPTY SSC0_TX_BUF_EMPTY SSC3_RX_BUF_FULL SSC2_RX_BUF_FULL SSC1_RX_BUF_FULL SSC0_RX_BUF_FULL SWTS0_REQ
20 19 17 16 15 14 12 11 10 9 7 6 5 2 x x
x x x x x
10 9 7 6 5 15
LD4 LD4 ST4 ST4 ST4 ST4 LD4 LD4 LD4 LD4 ST32 ST32 ST32 ST4
Opcode
Unit
PACING SIGNAL
FDMA #1
Comments
index
LD4 x1 LD4 x1 ST4 x1 ST4 x1 ST4 x1 ST4 x1 LD4 x1 LD4 x1 LD4 x1 LD4 x1 ST32 x1 ST32 x1 ST32 x1 ST4 x1 Software Transport Stream play through PTI4L. Should be handled by Host CPU not FDMA Connects counter output to dreq #0 Connects counter output to dreq #0
x x x
3 2 1 14
Confidential
SSC#0 Rx
x x x x
24 23 22 26
TS Merger
SWTS1_REQ SWTS2_REQ
HDMI AVI buffer
AVI_BUFF_EMPTY
FDMA #1 counter FDMA #0 counter
FDMA1_COUNTER_REQ FDMA0_COUNTER_REQ
1 0 x
0 0
Table 58.
FDMA requests table

REQUEST SIGNAL O_COUNTER_REQ REQ_OUT[31:0] O_COUNTER_REQ 31:0 FDMA internal counter output, used for timed DMA-channel. Request index Description FDMA internal counter output, used for timed DMA-channel.
Request source FDMA# counter FDMA# cross-bar FDMA# counter
Note:
# in Table 58 is 0 or 1.
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FDMA
STi7105
10.4
Examples of DMA Data flow

The following figures describe various DMA data flows.
Figure 24. DMA data flows (I)
7105
7105
PTI4-lite
ST40-300
REQ
Comms
Setup FDMA-2 FDMA-2
PG
LMI
EMI
LMI
EMI
SDRAM
FLASH
SDRAM
FLASH
Video PES header and video start code detection
Comms DMA
Figure 25. DMA data flows (II)

7105
PTI4-lite
ST40-300
Setup FDMA-2
LMI
EMI
Memory to memory SDRAM FLASH DMA
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STi7105
Clocking
11
Clocking
The STi7105 includes four clock generator subsystems: ClockGen A: 2x PLLs main CPU, transport, and interconnect clocks ClockGen B: 2x FreqSynth: video, display, and peripheral clocks ClockGen C: 1x FreqSynth and audio clocks ClockGen D: 1x PLL memory clocks
The SYSCLKIN/SYSCLKOSC pair is a crystal interface, a part of the SATA analog interface, integrating an oscillator requiring 30 MHz crystal. In addition to driving the SATA and two USB interfaces, the clock can be used as a reference clock to generate the Group A, B, C, and D clocks. The SYSCLKINALT input provides an alternate reference clock for the Group A, B, C, and D clocks instead of using an oscillator clock inside the SATA Phy. The default state is to use the 30 MHz SATA clock, however, an alternate reference clock can be selected through a configuration register. The SYSCLKINALT pin is driven by either a 27 MHz fixed or voltage controllable oscillator or a fixed 30 MHz oscillator. A PWM output is provided as a part of an external VCXO configuration. The internal clocks can be observed:

ClockGen A through the TRIGGEROUT pad ClockGenB through the SYSCLKOUT pad ClockGen C frequency synthesizer #2 through the PIO10[3] pad ClockGen D through the LMICLKOUT pad
Encoder clock recovery

The STi7105 integrates a clock recovery module to recover the encoder clock. This module (DCXO) uses the digitally controllable frequency synthesizers and an integrated digital clock recovery module. This feature replaces the external VCXO functionality and allows the usage of a fixed oscillator. Nevertheless, the external VCXO functionality is still available. When the external VCXO functionality is used, the VCXO oscillator must be connected to the SYSCLKINALT, and the SYSCLKIN is connected either to a fixed oscillator or to the VCXO oscillator. When the DCXO is used the SYSCLKIN pin is connected to a fixed oscillator, and the SYSCLKINALT is connected either to the SYSCLKIN or left unconnected (in that case the SATA/USB 30 MHz clock is used). The system counter inside the programmable transport interface (PTI), which is used to compare the arriving PCRs, is clocked by the recovered 27 MHz clock generated by the Clock Generator B.
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11.1
Clock input/output pins
Confidential
Clocking Figure 26. STi7105 clocking scheme sources with optional external VCXO
STi7105
mode pin ckgA_src_lposc 27MHz fixed or VCXO oscillator
ClockGen A
SYSCLKINALT (optional)
PWM (optional)
ClockGen C
Confidential
ClockGen D
Internal 30 MHz clock
Ckg A mux is controlled by one bit mode pin Ckg B,C and D have sw controller source muxes
USB (2x) SATA
lposc 30 MHz
SYSCLKOSC SYSCLKIN 30 MHz Crystal
Sys config reg (default is lposc)
Table 59. ClockGen module

A B C D USB/SATA
STi7105 clocking scheme sources Reset default STi7105

Selection by modepin SATA/USB LP-Osc 30 MHz SATA/USB LP-Osc 30 MHz SATA/USB LP-Osc 30 MHz SATA/USB LP-Osc 30 MHz
Clock selection
STi7105 has mode pin to select default clock reference for ClockGen A ClockGen B config register Audio SS config register System config register System config register
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Clocking
11.2
Table 60.
Block
Clock domains
The Table 60 describes the clocking of the functional units integrated in STi7105. Column S is the clock source, indicating A, B, C, D for ClockGen, or T for Tap. Functional blocks clocking
Clock pin Clock signal TMC S Max frequency Comment
TMC
TCK
TCK
50 MHz
JTAG clock from pad
MAIN Interconnect and NOC
N_CPU N_PERIPH RESERVED N_DVP N_DISPLAY
CLK_IC_IF_200 CLK_IC_IF_100 RESERVED CLK_IC_DISP_200 CLK_IC_DISP_200 CLK_IC_COMPO_200 CLK_BLIT_PROC CLK_EMI_MASTER CLK_IC_TS_200 CLK_IC_TS_200 CLK_IC_IF_100 CLK_IC_BDISP_200 CLK_IC_IF_100 SYSTEM
A A
200 MHz 100 MHz
A A A A A A A A A A 266 MHz
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N_COMPO N_DMU N_PCI N_PCI_TS N_TS N_IF N_BDISP N_CPU_REG
SYSCLKINALT
pad
SYSCLKINALT IN
30 MHz
LPOSC
ZI
CLK_LPOSC_30
30 MHz
These are the clock sources, from the two possible inputs Clock from pad Clock from SATA/USB osc
CLK_STBUS CLK_OSC_A ClockGenA CLK_OSC_B CLK_OSC_C CLK_OSC_D
CLK_IC_IF_100 NOT USED CLK_LPOSC_30 SYSCLKINALT NOT USED
100 MHz
30 MHz 27/30 MHz
from SATA/USB oscillator direct from pad crystal
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STNoC
CLK_IC_STNOC
400 MHz
CPU processing clock
Clocking Table 60.

Block
STi7105 Functional blocks clocking (continued)

Clock pin CLK_IC CLK_OSC_A Clock signal CLK_IC_IF_100 NOT USED CLK_LPOSC_30 SYSCLKINALT NOT USED NOT USED CLK_LPOSC_30 SYSCLKINALT NOT USED NOT USED CLK_LPOSC_30 SYSCLKINALT NOT USED MAIN CPU CLK_ST40_IC K CLK_SH4_ICK CLK_IC_IF_100 CLK_IC_IF_100 DMA IC_CK CLK_IC_BDISP_200 CLK_IC_IF_100 CLK_BLIT_PROC CLK_FDMA0 CLK_IC_IF_100 CLK_IC_TS_200 CLK_IC_IF_100 A A A A A A A 200 MHz 100 MHz 266 MHz 450 MHz 100 MHz 200 MHz 100 MHz Type 3 interconnect clock Type 1 interconnect clock Bdisp processing clock SLIM Processing clock High priority FDMA port Low priority FDMA port Type 1 interconnect clock A A A 450 MHz 100 MHz 100 MHz CPU processing clock Interface clock Type 1 interconnect clock 30 MHz 27/30 MHz from SATA/USB oscillator direct from pad crystal 30 MHz 27/30 MHz from SATA/USB oscillator direct from pad crystal 30 MHz 27/30 MHz from SATA/USB oscillator direct from pad crystal S A Max frequency Comment STBus clock
ClockGenB
CLK_OSC_B CLK_OSC_C CLK_OSC_D CLK_OSC_A CLK_OSC_B
ClockGen C CLK_OSC_C CLK_OSC_D CLK_OSC_A CLK_OSC_B
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ClockGenD CLK_OSC_C CLK_OSC_D
SH4-300 CLK_ST40_PC K Mailbox CLK
BlitterDisplay
CPU_CK BDISP_CK CLK_SLIM CLK_STBUS_ T2_0
FDMA0
CLK_STBUS_ T2_1 CLK_STBUS_ T1
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STi7105 Table 60.

Block
Clocking Functional blocks clocking (continued)

Clock pin CLK_SLIM CLK_STBUS_ T2_0 Clock signal CLK_FDMA1 CLK_IC_IF_100 CLK_IC_TS_200 CLK_IC_IF_100 S A A A A Max frequency 450 MHz 100 MHz 200 MHz 100 MHz Comment SLIM Processing clock High priority FDMA port Low priority FDMA port Type 1 interconnect clock
FDMA1
CLK_STBUS_ T2_1 CLK_STBUS_ T1
CLK_PROC CLK_SYS HD Display CLK_PIX
CLK_DISP_PIPE_200 CLK_IC_DISP_200 CLK_DISP_HD CLK_IC_DISP_200 CLK_DISP_PIPE_200 CLK_IC_DISP_200 CLK_DISP_ID or CLK_DISP_HD CLK_IC_DISP_200 CLK_IC_COMPO_200 CLK_DISP_HD CLK_DISP_ID CLK_DISP_ID CLK_DISP_HD or CLK_DISP_ID (CLK_GDP3)
A A B A A A B A A B B B
200 MHz 200 MHz 148.5 MHz 200 MHz 200 MHz 200 MHz
Display pipeline processing clock Type 3 interconnect clock Display-to-Compositor pixel clock Type 1 interconnect clock Display pipeline processing clock Type 3 interconnect clock
CLK_REG CLK_DISP CLK_IC SD Display CLK_PIXEL CLK_REG ST_CK MAIN_CK AUX_CK VP2_CK
13.5 MHz in SD and Display-to-Compositor 148.5 MHz in HD (PIP) pixel clock 200 MHz 200 MHz 148.5 MHz Max 108 MHz Max 108 MHz Max Type 1 interconnect clock Type 3 Interconnect clock Main mixer (HD) pixel clock Aux mixer (SD) pixel clock Video2 pixel clock (SD or HD) GDP3 pixel clock (HD or SD)
Compositor
GDP3_CK
148.5 MHz
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Clocking Table 60.

Block

Clock pin Clock signal S Max frequency Comment
VIDEO OUTPUT STAGE CLK_IC PIX_CLK DENC PIX_CLK_FRO M_PAD RGB-to-YCbCr

601/709/240M
CLK_IC_IF_100 CLK_PIX_SD
A B
100 MHz 27MHz Max
Type 1 interconnect clock DENC processing clock This clock is used by DVP in functional mode. Used for testing also. HD Display Clock Type 1 interconnect clock SD pixel input clock HD pixel input clock SD pixel input clock Pixel output clock HD display clock ID display clock HD Video DAC sampling clock SD Video DAC sampling clock
VIDINCLK FROM PAD
27 MHz
CLK_DISP_HD CLK_IC
CLK_DISP_HD CLK_IC_IF_100 CLK_PIX_SD CLK_DISP_HD CLK_PIX_SD CLK_PIX_HD CLK_DISP_HD CLK_DISP_SD CLK_PIX_HD CLK_PIX_SD
B A B B B B B B B B
148.5 MHz 100 MHz 27MHz 148.5 MHz 27 MHz 148.5 MHz 148.5 MHz 13.5 MHz 148.5 MHz 108 MHz
DWCS AWG CLK_PIX CLK_DISP_HD
UpSampler
CLK_PIXEL_S D CLK_PIXEL_H D
VTG0 VTG1 HD Video DAC SD Video DAC
CLK_DISP CLK_DISP CLK CLK
AUDIO DECODING CLK_CPU LX- Audio CLK_BUS CLK_IC_100 A 100 MHz CLK_LX_AUD_CPU A 450 MHz Max LX processing clock Peripheral Interconnect clock Peripheral Interconnect clock in audio peripherals Interconnect clock PCM oversampling clock (256xFs) = 256x 192kHz Interconnect clock PCM input serial clock
Audio Glue
CLK_IC CLK_STBUS
CLK_IC_IF_100 CLK_IC_IF_100 CLK_PCM1 CLK_IC_IF_100 I2S_SCLK
A A C A C
100 MHz 100 MHz 50 MHz Max 100 MHz 5 MHz
PCM player 1 see audio clocking scheme PCM reader see audio clocking scheme
CLK_PCM CLK_STBUS CLK_I2S
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STi7105 Table 60.

Block Audio DAC see audio clocking scheme

Clock pin Clock signal S Max frequency Comment Oversampling clock (Fs = 48 kHz Max)
MCLK
CLK_PCM1
C 256 x Fs, 15 MHz Max
VIDEO DECODING CLK_CPU DeltaMu ST231 CLK_BUS CLK_VID CLK_BUS (CLK_IC_DELT A_200 ON SS) CLK_PP CLK_IC_IF_100 CLK_VID A A 100 MHz 225 MHz (clk_lx_dh_cpu/2) 266 MHz CLK_LX_DMU_CPU A 450 MHz LX Processing clock Peripheral Interconnect clock
DeltaMu Hdw
CLK_BLIT_PROC
DeltaMu STBus initiator and target port clock DeltaMu Hdw Preprocessor clock
CLK_PP
150 MHz
Confidential
TRANSPORT CLK_SYSTEM TSMerger CLK_27MHZ CLK_PIX_SD B 27 MHz CLK_IC_TS_200 A 200 MHz Interconnect clock For free running and programmable counters (timestamp) 200 MHzType 1 & 2 Interconnect clock PCR Timer clock for AV services -
CLK_SYSTEM PTI CLK_TIMER RESERVED RESERVED
CLK_IC_TS_200 CLK_PIX_SD RESERVED
A B
200 MHz 27 MHz Max -
CONNECTIVITY CLK100 PAD PHY_TX_CLK PHY_TX_CLK_ PS GMAC PHY_RX_CLK PHY_RX_CLK _PS CLK_IC_IF_100 CLK_ETHERNET A A 100 MHz 75 MHz Type 1 and 2 interconnect clock potential clock for Ethernet interface Timing reference for MII RX interface (_ps is inverted clock) Timing reference for MII TX interface (_ps is inverted clock) Clock to PHY in MII mode (output through PIOX(Y) pad) REF clock in RMII mode (input or output through PIOX(Y) pad)
PAD
75 MHz
PAD
75 MHz
PHY_RMII_CL K
CLK_ETHERNET (VIA PAD)
50 MHz
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DeltaMu Hdw processing clock
Clocking Table 60.

Block

Clock pin STBUS_CLOC K CLOCK48 Clock signal CLK_IC_IF_100 S A Max frequency 100 MHz Comment Type 1 & 2 Interconnect clock From USB FSyn pending confirmation that PHY will supply From USB PLL From USB2.0 Phy From USB PLL From pad for test Type-1 interconnect clock Pixel clock TMDS clock is 1x or 2x pixel clock BCH clock is 2x or 4x TMDS clock PCM oversampling clock (256xFs, Fs = 192 kHz Max) S/PDIF clock 256xFs = 256 x 48 kHz From rejection PLL From ClockGen B Type 1 & 2 interconnect clock
CLK_USB48 CLK_USB60 CLK_PHY_USB60 CLK_USB60 TST_CLK_USB60 CLK_IC_IF_100 CLK_DISP_HD CLK_TMDS_HDMI CLK_BCH_HDMI
48 MHz 60 MHz 60 MHz 60 MHz 60 MHz
USB2.0 Host PHY_CLK_I UTMI_PHY_CL K_I REFCLK_CUS T USB2.0 Phy REFCLKBYPA SS_CUST STBUS_CLOC K PIX_CLOCK
A B B B
100 MHz 148.5 MHz Max 148.5 MHz Max 148.5 MHz Max
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HDMI Frame formatter
TMDS_CLOCK BCH_CLOCK
PCM player 0
CLK_PCM
CLK_PCM0
50 MHz Max
S/PDIF player
SPDIF_CLOCK CKPXDLL
CLK_PCM2 CLK_PLL_HDMI_PHY CLK_TMDS_HDMI CLK_IC_IF_200
C B B A
15 MHz Max 148.5 MHz 74.25 MHz 200 MHz
HDMI Analog CKPX ST_CK
DVP DVP_PIX2_CK
CLK_DVP
D1 video stream clock provided by ClockGen B 148.5 MHz in HD mode B when in compositor capture mode B 148.5 MHz in HD mode D1 video stream clock
VidInClk from pad
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STi7105 Table 60.

Block

Clock pin CLK_STBUS Clock signal CLK_IC_IF_100 S A Max frequency 100 MHz Comment Type 1 & 2 interconnect clock Recovery clock, synchronous with received data (75 MHz) (provided by SATA PHY) Used into transport and link layer blocks (75 MHz) (provided by SATA PHY) Used to OOB detection and also used as possible reference clock for ClockGen B and C (provided by SATA PHY)
CLK_RBC0
CLK_RBC0
75 MHz
CLK_ASIC
CLK_ASIC
75 MHz
CLK_RXOOB
CLK_SATA
30 MHz
MEMORY INTERFACES SYSTEM_CLO CK EMI-PCI Subsystem PCI_CLOCK CLK_EMI_MASTER CLK_PCI A A 100 MHz 33/66 MHz EMI & PCI can also be clocked from external pads, STBus side will be synchronized to SYSTEM_CLOCK EMI SS clock when in EMI clock slave mode or PCI clock when in PCI clock slave mode. From GPLMI0 padlogic after divider and DLL From PLL
DEVICE_CLK_ IN
EMI_FLASHCLK (PAD)
50 MHz
GPLMI0 GPLMI0PL RESERVED
MCLK LMI_PL_MCLK RESERVED
MCLK LMI_PL_MCLK RESERVED COMMS D
400 MHz 800 MHz
CLK_IC COMMs LP_CLOCK CLK_DAA CLK_DSS
CLK_IC_IF_100 CLK_LPC CLK_DAA CLK_DSS
A B B B
100 MHz 46.875 kHz 32.768 MHz 36.864 MHz
Type 1 & 2 interconnect clock Low power clock DAA clock Smart card clock
11.3
CPUs and interconnect clock generation (ClockGen A)

The reference clock can be either an internal 30 MHz clock signal or a clock connected to the SYSCLKINALT pin. The reset value is defined by mode pin[0] value. This ClockGen is responsible for clocking the following units.
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Clocking Table 61.

Channel div# CLK_DIV_HS[0] CLK_DIV_HS[1] CLK_DIV_HS[2] CLK_DIV_HS[3] CLK_DIV_LS[4] CLK_DIV_LS[5] CLK_DIV_LS[6] CLK_DIV_LS[7] CLK_DIV_LS[8] STi7105 Clk name CLK_IC_STNOC CLK_FDMA0 /3=300 CLK_FDMA1 NOT USED CLK_SH4_ICK CLK_IC_IF_100 CLK_LX_DMU_CPU CLK_LX_AUD_CPU CLK_IC_DISP_200 CLK_IC_BDISP_200 CLK_IC_TS_200 CLK_DISP_PIPE_200 CLK_BLIT_PROC /6=75 /9=50 /18=25 /12=66 /24=33 /1=450 /1=450 /32=0.95 /1=450 /8=100 /2=400 /2=400 /4=200 /4=200 /4=200 /4=200 /3=266
STi7105 ClockGen A mapping

30 OSC 900 450 800 Comment
PLL0 HS PLL0 LS PLL1 /3=300 /3=266 /2=400 /3=266 /2=400 /3=266 /4=200
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CLK_DIV_LS[9] CLK_DIV_LS[10] CLK_DIV_LS[11] CLK_DIV_LS[12]
DeltaMu IC at 266 MHz
CLK_DIV_LS[13]
CLK_ETHERNET_PHY
CLK_DIV_LS[14] CLK_DIV_LS[15] CLK_DIV_LS[16] CLK_DIV_LS[17] CLK_IC_LS
CLK_PCI CLK_EMI_MASTER CLK_IC_COMPO_200 CLK_IC_IF_200 not used
two outputs; full speed and half speed
11.3.1
Block diagram
At POR, all clocks are output at 30 MHz (x1 from USB/SATA osc). The Figure 27 shows the STi7105 ClockGen A block diagram.
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STi7105 Figure 27. STi7105 ClockGen A block diagram

PLL0 (1600) HS (900) LS (450) DIVO_HS DIVO_1 DIVO_OSC x4 PLL1 (800) DIVO_HS DIVO_1 clk_osc_a clk_osc_b clk_osc_c clk_osc_d CLK_OSC Optional Pre divider by 16 DIV_OSC Matrix OR source selection 14 Matrix OR source selection
4
Clocking
CLK_DIV_HS[3:0]
CLK_DIV_LS[17:4]
CLK_DIV_LS[17] x14 Obs Counter div2 div4 Obs Mux1
CLK_IC_LS
CLKGENA_CLOCKOBS_MUX_1_CFG Internal/interface ClockGenA clocks CLK OP source switch control divider control internal/interface clockgenA clocks
CLK_FUNCOBS
Confidential
div2 div4
Obs Mux2
CLK_FUNCOBS2
T1 target interface CLK_STBUS STBus interface registers
CLKGENA_CLOCKOBS_MUX_2_CFG
11.3.2
Clockoff and reduced power

Clocks in group A can be slowed to less than 1MHz, through register programming or low power signal from LPC, or stopped.
11.3.3
Clock observability
All the clocks of the ClockGen A can be observed on the TRIGGEROUT pad.
The CLOCK_OUT_SEL[5:0] bits of the CLKGNA_CLKOBS_MUX_X_CFG (where X = 1 and 2) configuration register is provided to select the clock which will be routed to the
pad.
11.4
Video decoder, display, and Comms clock generation (ClockGen B)

This ClockGen is mainly responsible for generating the clocks used by the video display pipeline. This includes the following units: SD and HD displays compositor video output stage (formatters, HDMI, and DENC) HD and SD video DACs In addition, ClockGen B also generates some processing clocks for the following units: commsLPC/PWM
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DIV2 gated
Clocking
STi7105 ClockGen B comprises two digitally controlled frequency synthesizers (FS0 and FS1). The reference clock can be either an internal 30 MHz clock (USB) signal or a clock connected to the SYSCLKINALT pin. The reset value is the SATA Phy clock. The ClockGen B also includes a digital clock recovery module to recover the encoder clock. The block diagram of ClockGen B is shown in Figure 29.
11.4.1
Clock signals
The Table 62 lists the group B clocks with their maximum frequency.
Table 62.
Clock generator B Maximum frequency (MHz) Description

148.5 148.5 148.5 13.5 148.5 148.5 150 32.768 36.864 46.875 27 148.5 148.5 148.5 148.5 HD pixel clock SD pixel clock (support HD format) HD display clock SD display clock GDP3 pixel clock (HD or SD) DVO0 pixel clock Delta Preprocessors DAA clock DSS clock Low Power Controller clock Teletext clock HDMI serializer clock HDMI BCH clock HDMI TMDS clock DVO1 pixel clock
Clock name
CLK_PIX_HD CLK_PIX_SD CLK_DISP_HD CLK_DISP_ID
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CLK_GDP3 CLK_656 CLK_PP CLK_DAA CLK_DSS CLK_LPC CLK_TTXT CLK_SERLZR_HDMI CLK_BCH_HDMI CLK_TMDS_HDMI CLK_656_1
The frequency of all the clocks is programmable. Especially, the video clocks must be set up with respect to the display standard in use. The Table 63 gives some programming examples with respect to the targeted application. Table 63. Video clock domains by applications
CLK_PIXEL_HD CLK_DISP_HD CLK_PIXEL_SD CLK_DISP_ID CLK_656 CLK_TMDS_HDMI CLK_GDP3
Application
Main (1080p60) & Aux
Main 1080p/60Hz or 720p/60Hz (HD) Aux: 480i / 576i (SD)
GDP3 on main 148.5 148.5 27 GDP3 on aux 148.5 148.5 27
13.5 13.5
148.5 148.5 148.5 148.5 NA 13.5
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STi7105 Table 63. Video clock domains by applications

CLK_PIXEL_HD CLK_DISP_HD CLK_PIXEL_SD CLK_DISP_ID CLK_656
Clocking
CLK_TMDS_HDMI
CLK_GDP3
Application
Main (HD) & Aux (HD)
Main & Aux
Main 1080i/30Hz or 720p/60Hz (HD) Aux: 480i / 576i (SD) Main 480p/576p (ED) Aux: 480i / 576i (SD) Main 480i/576i (SD) Aux: 480i / 576i (SD) Main 1080i/30Hz or 720p/60Hz (HD) Aux: 480i / 576i (SD)
GDP3 on main 148.5 74.25 27 GDP3 on aux 148.5 74.25 27 27 27 13.5 27 27 27
13.5 13.5 13.5 13.5 NA
148.5 74.25 74.25 148.5 NA 54 54 27 27 NA 27 13.5 27 13.5 13.5
GDP3 on main 108 GDP3 on aux 108
Main & Aux Alternate (main to denc)
GDP3 on main 108
Main & Aux SCART
108 GDP3 on main (from 74.25 27 FS0) GDP3 on aux 148.5 74.25 27 13.6 13.5 27 27
13.5 13.5 13.6 13.5
148.5 74.25 74.25 148.5 NA NA NA NA NA 13.5 13.5 13.5
Main & Aux pseudoSCART
Main 480i/ 576i (SD) - GDP3 on main 108 TV (video + gfx) Aux: 480i / 576i (SD) - GDP3 on aux 108 VCR (video only)
11.4.2
Clock generator B startup configuration

After the reset phase, the ClockGen B is by default configured with a 13.5 MHz display clock on both the Main and Auxiliary video outputs.
Table 64.
Clock name
Clock generator B default configuration

Frequency (MHz) 148.5 148.5 13.5 13.5 148.5 148.5 27 32.768 36.864 Description HD pixel clock SD pixel clock HD display clock SD display clock GDP3 pixel clock (HD or SD) DVO pixel clock DVP clock DAA clock DSS clock
CLK_PIX_HD CLK_PIX_SD CLK_DISP_HD CLK_DISP_ID CLK_GDP3 CLK_656 CLK_DVP CLK_DAA CLK_DSS
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GDP3 on main 148.5 74.25 27
13.5
148.5 74.25 74.25
GDP3 on aux
148.5 148.5 148.5 74.25 148.5 NA
74.25
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Clocking Table 64.

Clock name CLK_LPC CLK_PP CLK_FSO_CHAN0 CLK_TMDS_HDMI CLK_656_1
STi7105 Clock generator B default configuration (continued)

Frequency (MHz) 46.875 27 108 27 13.5 Description Low Power Controller clock DeltaMu Preprocessor clock must be re-programmed for 150 MHz frequency. Clock to HDMI PII rejection HDMI TMDS clock DVO1 pixel clock
11.4.3
Clock frequency change

The clock generator always starts with the default configuration as defined in Table 64. Nevertheless, the frequency synthesizers FS0 and FS1 can be re-configured to produce different frequencies.
Clock generator programminglock/unlock
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To prevent any unwanted ClockGen reprogramming, a protection mechanism is provided using the CKGB_LOCK register. This register must be written first with the keyword 0xC0DE to authorize any ClockGen registers update. Writing another data to the CKGB_LOCK register locks all the ClockGen registers.
Clock ratio change without changing FS0 and FS1 programming

The clocks CLK_BCH_HDMI, CLK_TMDS_HDMI, Clk_656_1, CLK_PIX_HD, CLK_DISP_HD, CLK_656, CLK_GDP2, CLK_DISP_ID, and CLK_PIX_SD are generated from a master clock (from FS0 and FS1), which is then divided by programmable dividers (by 2, 4, 8, or 1024). These dividers can be redefined using the register CKGB_DISP_CFG without changing the FS0 and FS1 setup. The clock generator design ensures a glitch-free frequency change.
FS0 and FS1 frequency definition

The frequencies generated by FS0 and FS1 are defined by the registers CKGB_FS0/1_MDx, CKGB_FS0/1_PEx and CKGB_FS0/1_SDIVx and is given by the formula:
F out
2 F PLL = -------------------------------------------------------------------------------------------------------------------------------------------------15 md +1 sdiv pe 1 + ------- ( pe 2 ) 1 + md ----------------- 32 32
15
with FPLL = 216 MHz, if the reference clock is 27 MHz or with FPLL = 240 MHz, if the reference clock is 30 MHz. To avoid glitches at the frequency synthesizer output, only the MD, PE, and EN_PRG parameters can be changed. The other parameters can be changed but glitches will occur.
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Clocking
11.4.4
Clock frequency reduction

Most of the group B clocks can be divided to reduce the power consumption with the register CKGB_CLK_DIV without stopping the clocks.
11.4.5
Clocks observation
Any group B clock can be routed and observed on the SYSCLKOUT pad. The configuration register CKGB_CLKOUT_SEL is provided to select the clock which will be routed to the pad. Information classified Confidential - Do not copy (See last page for obligations)
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Clocking Figure 28. FS0 and FS1 clocks observation

CKGB_CLOCKOUT0_SEL[3:0] RESERVED CLK_TMDS_HDMI RESERVED CLK_PIX_HD CLK_DISP_HD CLK_656 CLK_GDP3 CLK_DISP_ID CLK_PIX_SD CLK_DSS CLK_DAA RESERVED 0 1 2 3 4 5 6 7 8 9 10 11 12 CLK_LPC RESERVED RESERVED 13 14 15 CKGB_CLOCKOUT1_SEL[3:0] CLKB_OBS (SYSCLKOUT pad)
STi7105
RESERVED CLK_TMDS_HDMI RESERVED CLK_PIX_HD CLK_DISP_HD CLK_656 CLK_GDP3 CLK_DISP_ID CLK_PIX_SD CLK_DSS CLK_DAA CLK_PP FS0_CHAN3 CLK_LPC RESERVED RESERVED
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CKGB_CLKOUT1
Note: SYSCLKOUT pad is rated to operate up to 100 MHz.
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STi7105 Figure 29. ClockGen B block diagram

CLK_FS0_CHAN0 Rejection PLL To HDMI line driver CLK_DLL_HDMI
Clocking
(148.5 MHz Max)

Rejection Div by: 1, 2, 1024 PLL
Reserved
CLK_TMDS_HDMI CLOCK_OFF
CKGB_DISPLAY_CFG_TBUF(16)
Rejection Div by: 1, 2,4, 1024 PLL Rejection Div by: 1, 2,4,8,1024 PLL Rejection Div by: 1,PLL 1024 Rejection Div by: 1, 2,4,8,1024 PLL
(148.5 MHz Max)

CLK_656_1 (7105)
(148.5 MHz Max)

CLK_PIX_HD
(148.5 MHz Max)

CLK_DISP_HD CLOCK_OFF
Rejection Div by: 1,2,4,8,1024 PLL
(148.5 MHz Max)
Freq. Synth #0 (HD)
CLK_DSS (36.864 MHz) CLK_DAA (32.768 MHz)
Rejection Div by: 1,2,4, 1024 PLL
CLK_656
(148.5 MHz Max)

CLK_GDP3
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CLK_LPOSC_30 SYSCLKINALT
ref ref
Rejection Div by: 2,4,8,1024 PLL
(148.5 MHz Max)

CLK_DISP_ID
(74.5 MHz Max)

ref
Rejection Div by: 1,2,4,8, PLL1024
(148.5 MHz Max)
CLK_PIX_SD
Freq. Synth #1 (SD)

Pixel clock from DVP
Rejection Div by: 1,PLL 1024
CLK_DVP CLK_PP
(148.5 MHz Max)
ref
Rejection Div by: 1024 PLL
CLK_LPC (46.875 kHz)
11.4.6
Frequency synthesizers reference clock

The reference clock of two frequency synthesizers is selectable and can be chosen between the 30 MHz clock coming from the SATA Phy or from the pad SYSCLKINALT.
11.5
Audio clock generation (ClockGen C)

The ClockGen C is responsible for clocking the following units: multichannel PCM Player 0 (CLK_PCM0) connected to HDMI or external DACs (stereo) stereo PCM Player 1 (CLK_PCM1) connected to internal audio DACs and to HDMI stereo channels

S/PDIF Player stereo audio DAC
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Clocking
STi7105 The audio clock generator is a quad-frequency synthesizer which generates the 256 x Fs (audio sampling frequency) from which the I2S serial clock, left-right clock and DAC oversampling clocks are derived. Typical audio sampling frequencies are: 32 kHz, 44.1 kHz, and 48 kHz for Set-top box applications, and can be up to 192 or 96 kHz for DVD applications. The three audio players have independent clock generators issued from the same quadfrequency synthesizer. The frequency synthesizer channel#0 clocks the PCM player#0, the channel#1 clocks the PCM player#1, and the channel#2 clocks the S/PDIF player. Refer to Section 3.12: Audio subsystem on page 28 for a full overview of the Audio system clocking. The Figure 30 shows the block diagram of ClockGen C. Figure 30. ClockGen C block diagram
30 MHz ref clock from SYSCLKINALT fs0 CLK_PCM0 (256 x Fs) (12.288 MHz Max) Frequency synthesizer fs1 #2 CLK_PCM1 (256 x Fs) (12.288 MHz Max) fs2 CLK_SPDIF (256 x Fs) (12.288 MHz Max) fs3 CLK_PCM2 (256 x Fs) (12.288 MHz Max) Audio configuration registers PAD_CLK_PCM (PCM clock from pad)
SYSCLKIN 30 MHz ref clock from SATA Phy
(Audio)
11.5.1
Frequency synthesizer reference clock

The reference clock of the frequency synthesizer is selectable and can be chosen between the 30 MHz clock coming from the SATA Phy or from the pad SYSCLKINALT. The reset value is the SATA Phy clock.
11.6
LMI memory clocks (ClockGen D)

The ClockGen D supplies clocks to the LMI memory interface(s). This is a simple ClockGen with a PLL only, the dividing function, to generate the GPLMI IP Mclk, is done inside the LMI padlogic.
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Clocking
11.6.1
Clock signals
The Table 65 lists group D clocks with their maximum and reset frequency.
Table 65.
Clock name
Clock Generator D
Maximum frequency Reset (MHz) frequency (MHz) 0 0 Phase altered and divided by 2 version of CLK_LMI_PL Description
CLK_LMI_PL 800 CLK_LMI 400
11.6.2
Reference clock
The reference clock can be either an internal 30 MHz clock signal or a clock connected to the SYSCLKINALT pin. The reset value is SYSCLKALTIN.
11.6.3
Clock frequency reduction

Flexible, CPU can reprogram the PLL controls.
11.7
MPEG clock recovery

The MPEG clock recovery is a mechanism to adjust the locally generated clocks with the encoder clock referenced in the program counter reference (PCR) located in the adaptation field of the incoming transport stream. The STi7105 generates three local clocks from internal frequency synthesizers using a fixed and stable 27 MHz reference clock produced by a crystal. These three clocks are: CLK_PIX_SD used for standard definition display CLK_PIX_HD used for high definition display CLK_PCM (256 x Fs, where Fs can take several possible values, such as 32 kHz, 44.1 kHz, and 48 kHz) used for audio output
11.7.1
Clock recovery principle

The mechanism assumes that these three clocks are related to each other. The recovery is done as usual for the CLK_PIX_SD (generated by the frequency synthesizer FS#0) by comparing the 42 bits PCR value located in the adaptation field of the stream with the local system timer counter (STC) value when a packet arrives. This generates a potential correction that is applied to the CLK_PIX_SD frequency synthesizer. The frequency synthesizer is programmed with new setup values to slow or accelerate the clock. Regarding the Audio PCM clock recovery, two counters are used.

A PCM free-running counter, clocked by the PCM Audio frequency synthesizer FS#2. A reference counter, clocked by the SD video frequency synthesizer FS#0. The maximum value of this counter is programmable defining the time interval between two consecutive resets. This counter is used as a time-base.
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Clocking
STi7105 When the reference counter resets, the values of the free-running counter clocked off CLK_PCM is captured into a readable register. This event generates an interrupt to the CPU (CRU_IRQ). The CPU reads the value and compares it with the previously captured value. The difference between two adjacent values gives an indication of the correction to apply to the PCM audio frequency synthesizer FS#2. The decision to correct the frequency synthesizers setup is under the control of the software. The same principle applies for the recovery of the CLK_PIX_HD. A free-running counter is clocked with the HD video frequency synthesizer FS#1. The same reference counter is used. When this counter resets then the output of the free-running counter clocked at CLK_PIX_HD is captured into a readable register. The Figure 31 shows the block diagram of clock recovery unit (CRU). Information classified Confidential - Do not copy (See last page for obligations)
Figure 31. CRU block diagram

27 MHz Crystal
FS#0 Counter max value
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SD Video Frequency synthesizer
CLK_PIX SD
DIN Reference counter RST/ID Zero detect
IRQ Cut Down STBus 32-bit Type 1 Target Plug
CRU_IRQ
Cut Down 32-bit STBus T1 I/F
Command register Resync FS#2 PCM Audio Frequency synthesizer
CLK_PCM
RST Free-running PCM counter
ld PCM capture register
CLK_IC_100
FS#1 HD Video Frequency synthesizer
CLK_PIX_HD
RST free-running HD counter
ld HD capture register
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Power-On-Reset and system reset
12
12.1
Power-On-Reset and system reset

Reset sources
The different reset sources are: Power-On-Reset (POR) signal, which is applied on the RESETN pad (with glitch suppression using a Schmitt type pad) watchdog reset generated by the ST40 internal Watchdog Timer (WDT) UDI reset sent through the ST40 debug port software reset from the ST40 to the ST231 CPU through the ST231 reset filters smartcard insertion long time-out reset (front-panel reset button) The ST40 manual reset is not used, only the PMU_PRESET_N POR reset is used.
12.2
POR reset (cold reset) vs. system reset (warm reset)

In the POR sequence (cold reset), everything is reset including the clock generators and captured mode pins values. In the system reset (warm reset) sequence, everything is reset except clock generators and a part of system configuration. The system reset sequence is executed when the reset source is watchdog, UDI, long-time-out reset, or smart card insertion. The long-time-out reset can be performed with an interrupt generated from a PIO. The CPU can use this interrupt to identify a long-time-out reset, and then use the WDT to generate a system reset.
12.3
Reset test mode

The reset generator includes a test mode that allows to bypass all the stretchers, and to directly apply a reset signal simultaneously to all the units.
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Mode pins
STi7105
13
Mode pins
The mode pins are a group of pads configured in the input mode, and are dedicated to capture values during the power-on-reset sequence that are used to configure certain defined functionalities. The captured values are viewed in the SYSTEM_STATUS1 register. The mode pins are captured at the rising-edge of the RST_N signal during the reset phase, and are made available to the system to define operating modes, such as ClockGen boot configuration. The Table 66 describes the mapping of the mode pins on PIO pads.
Table 66.
Bit
Mode pins mapping

Bit field Ref clock selection for Clockgen A 0: SYSCLKINALT (Ext) 1: Osc (SATA) PLL0 startup configuration(1) 00: Fin/Fout27/900 MHz 01: Fin/Fout27/604.8 MHz 10: Fin/Fout30/900 MHz 11: Fin/Fout30/600 MHz PLL1 startup configuration(1) 00: Fin/Fout27/799.2 MHz 01: Fin/Fout27/399.6 MHz 10: Fin/Fout30/800 MHz 11: Fin/Fout30/400 MHz Reset bypasses(2) CPU_RST_OUT_BYPASS[1]: bypass of (LX_Audio+LXDelphi) reset loop back CPU_RST_OUT_BYPASS[0]: bypass of (SH4+LX_Audio+LXDelphi) reset loop back Resetout mode (see SYSTEM_CONFIG9, long_reset_mode bit)(3) BOOT mode selection: 00: SH4-300 boot first 01: ST231 DeltaMu boot first 10: ST231 Audio boot first Reserved (Do not connect) nand_addr_short_not_long(4) Serial Flash usage: 0: ATMEL 1: ST Flash Boot device port size at boot: (4) 0: 16 bits 1: 8 bits Controlled unit Controlling Pad
MODE[0]
ClockGen A
MIIMDIO [PIO8(3)]
MODE[2:1]
ClockGen A
[PIO16(1,0)]
MODE[4:3]
ClockGen A
MIIMDINT: MIIMDC [PIO9(6):PIO8(4)]
MODE[6:5]
Reset generator
[PIO16(3:2)]
MODE[7]
Reset generator ST40, ST231 Audio, ST231 DeltaMu, request filtering Reserved Nand Controller EMI4
MIITX_EN [PIO8(2)]
MODE[9:8]
MIIRXD[3:2] [PIO9(1:0)]
MODE[10] MODE[11] MODE[12]
MIIRX_DV [PIO7(4)] MIIRX_ER [PIO7(5)] MIIRXD[0] PIO8(6)
MODE[13]
EMI4 and Nand Controller
[PIO16(4)]
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STi7105 Table 66.

Bit MODE[14]
Mode pins Mode pins mapping (continued)

Bit field emiss_slave_not_master Boot Device: 00: NOR Flash (EMI controller) 01: Nand Flash (Nand Controller) 10: Serial Flash (SPI controller) 11: Reserved emiss_clock_slave_not_master nand_page_large_not_small(4) Controlled unit EMI subsystem Controlling Pad MIIRXD[1] [PIO8(7)]
MODE[16:15]
EMI subsystem
MIITXD[1:0] [PIO7(7:6)]
MODE[17] MODE[18]
EMI subsystem Nand Controller
MIITXD[2] [PIO8(0)]
1. It allows to setup ClockGen A PLL0 and PLL1 configurations (freq input /freq output) without relying on software. The ClockGen A registers CLKGENA_CLKOPSRC_SWITCH_CFG/CFG2 have to be configured to switch the source of STi7105 clocks from oscillator (default mode after reset) to PLL. The usage of mode pins allows to speed-up the ClockGen A configuration. By the time the software changes the CLKGENA_CLKOPSRC_SWITCH_CFG/CFG2 setting, the PLL may already be locked (so normally that allows to mask the PLL lock time). For more details, please contact your local ST representative to access ClockGen A functional specifications. 2. Allows to bypass the CPUs handshake in the chain of the reset generator. After boot, the modepin value can be bypassed by using the SYSTEM_CONFIG9[28:27] register (this register is not reset in case of watchdog reset, also it takes the value of the two modepins at reset). A typical usage of this system config bit is to bypass the ST231 resetout. Infact, the ST40 may change the boot address of the ST231 (by default 0x0). To allow the ST231 to take into account this new boot address it must be reset again through a config register (SYSTEM_CONFIG29). In that case, you do not propagate the resetout of the ST231 to the others IPs which may have already been configured. 3. It selects the resetout mode (SYS_WDOGRSTOUT pin): In Long ResetOut mode, the reset value guarantees a 200 ms reset out for the resetout. In Short ResetOut mode, resetout lasts 100 us. The resetout period is loaded during reset (RST_CONF) on the SYSTEM_CONFIG9[25:0] register (being the resetout period value depending on the mode pin 7 value). This register is not reset in case of watchdog reset and it can be reprogrammed after reset to allow for a resetout period of 2.48 s. 4. The Nand controller selects among the different memory types based on the three input signals: nand_page_large_not_small, nand_add_short_not_long, and nand_data_8_not_16. Refer Table 67.
Table 67.
Memory type based on static input pins Type select signal
nand_page_lar nand_add_shor nand_data_8_n ge_not_small t_not_long ot_16

0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 3 4 1 2 7 8 5 6
Type
Comment
small page devices
large page devices
System configuration registers reset

Some System configuration registers are not affected by a system reset. They keep the value which was written either during the POR reset or by the software.
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MIITXD[3] [PIO8(1)]
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Mode pins These registers are: mode pins value captured during the POR sequence reset generator configurationresetout duration, CPUresetout bypass(1:0) boot mode boot sizeboot Flash bus width (8 or 16 bits)
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Low power control
14
Low power control

Power down mode in the STi7105 consists of having some or almost all clocks running 1024 times as slow as their normal speed. This reduces power consumption dramatically and still enables some software to be running, also, it enables the chip to be woken up fairly quickly without having to reboot the application.
Note:
Additionally, a standby mode is provided whereby some clocks can be completely switched off. This can be a power saving feature for applications where functionalities clocked by a dedicated clock will never be needed. The standby mode includes different mechanisms: switch-off clocks by programming the ClockGen or some bits of the system configuration module (for the EMI and DDR selfrefresh), standby, and sleep modes in the ST40. The ST40 also supports two main low power modes: sleep and standby (see ST40 sleep and standby modes overview on page 175). The EMI clock cannot be switched off with the ClockGen. Both IPs support the powerdown protocol: this is managed by a simple hand-shake between the system configuration register (under control of the CPU) and the two IPs. This mechanism allows the EMI clock to be switched off selectively. The same mechanism is used to send the DDR into self-refresh mode (powerdown protocol between the LMI Core and the system config module).
14.1
Entering low power modes

Method 1.1: by programming configuration bits in the ClockGen
Using configuration bits of the ClockGen, some clocks can selectively be slowed down (divided by 1024) to enter power down mode whilst others keep their nominal speed. Refer to the ClockGen specifications.
Note:
Standby mode (clocks halted) is also controllable through configuration bits of the ClockGen.
Method 1.2: using the low power controller (LPC) module

A global power down command can be issued by using the low power alarm (LPA) timer of the LPC module (part of STi7105 COMMs). Refer to Figure 32 on page 174.
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Certain precautions must be taken to achieve this: In particular, the DDR SDRAM must be put into self-refresh mode prior to entering this mode, and at wake up there must be no access to DDR until the DDR and associated PadLogic have been restored to their normal mode of operation. If the LMI clock is slowed down (to less than 100 MHz), the DDL of the LMI padlogic will no longer be operational. It will also be necessary to update the refresh interval.
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Low power control
STi7105
All clocks, for which the 1024 divider ratio is available inside the two ClockGens, will be slowed down: the 1024 division is not currently implemented for the following clocks: In the ClockGen A: CLK_EMI_MASTER_A (EMI clock @ 100 MHz) CLK_ETHERNET_A (Ethernet clock @ 100 MHz) In the ClockGen B: CLK_DSS (DSS clock @ 36.768 MHz) CLK_DAA (DAA clock @ 32.768 MHz) CLK_EMI_MASTER_B (EMI clock @ 100 MHz) CLK_ETHERNET_B (Ethernet clock @ 100 MHz) Power Down mode is entered upon programming of the LPA timer. Note: 1 2 3 The usage of the LPA Counter is not compatible with use as a WatchDog Timer. Refer to the LPC specification for details. Standby mode (clocks completely switched off) cannot be entered through the LPC. The only way to slow down the clocks for which the 1024 divider ratio is not implemented inside the ClockGen, is to bypass the PLL (By doing this it is possible to reach frequencies in the range of a few MHz), or to use the clockgen configuration registers to reduce the clock frequency generated by the PLL. Refer to clockgen specifications for details. Information classified Confidential - Do not copy (See last page for obligations)
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Method 1.3: using a global power down control bit

A global power down command (all clocks slowed down) can be issued by setting the appropriate configuration bit located in the CONF block register (refer to the System Configuration bit SYSTEM_CONFIG7[23]). Global standby mode (clocks completely switched off) cannot be entered this way.
14.2
Exiting low power modes

Method 2.1: through configuration bits in the ClockGen
If power down is entered by Method 1.1 above, it can clear the bits that are already set in ClockGen while exiting.
Note:
This is also valid for standby mode (that is, when clocks were halted through ClockGen configuration).
Method 2.2: through the LPC

If power down is entered by Method 1.2 above: when the LPA counter reaches zero, the LPC releases the global power down command and the ClockGen exits power down mode. The duration of the countdown is user programmable, and can be programmed from a few milliseconds to up to 271 days after LPA has been programmed (LPA counter is 40 bits clocked at 46.87 kHz).
Method 2.3: upon detection of activity on the UHF or IRB inputs

This generates an interrupt (IRB_WAKEUP_INTERRUPT) to the ILC3, which, assuming it has first been programmed accordingly, treats it as a wake up request that it routes to the LPC and also to the CONF module (to clear the global powerdown bit). Refer to Figure 32 on page 174.
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Low power control IMPORTANT: the IRB_WAKE_UP interrupt routed to the ILC3 will be generated only if the global power down command is received by the wake-up interrupt generator module. This implies that the LPC must be programmed (METH 1.2). Of course this has also the effect of slow down by 1024 the frequency clocks. If power down is entered by method 1.2: the LPC, when it receives the wake up request from the ILC, clears the global power down command that goes to the ClockGen and normal speed is restored. If power down is entered by method 1.3: the global powerdown control bit in the CONF block, when it receives the wake up request from the ILC, clears the global power down command that goes to the ClockGen and normal speed is restored. Information classified Confidential - Do not copy (See last page for obligations) If power down is entered by method 1.1: the configuration bits in the ClockGen must be set back to their normal value. This can be done by an interrupt routine. However, if DDR is not operational (because it was sent in self-refresh) this means the interrupt servicing routine is stored in the ST40 cache or stored in external Flash, if EMI is not switched off. In the case that the interrupt going to the ILC3 upon detection of IRB/UHF activity can be treated as a normal interrupt, servicing it then consists of restoring the ClockGen configuration bits.
Note:
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The same interrupt can be also used to wake-up the ST40 from sleep or standby mode since four interrupt levels provided by the ILC3 are connected to the ST40 IRL.
Method 2.4: upon firing of any selected interrupt

This is just an extension of the latter case. In fact if the condition that the relevant interrupt handler is not located in DDR is fulfilled, then any source can be programmed to trigger the interrupt routine that will clear configuration bits in the ClockGen if power down was entered in that way (method 1.1), or clear the LPA counter to restore normal operation if power down was controlled from the LPC (method 1.2).
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Low power control Figure 32. Low power mode control hardware
WAKE-UP_PULSE_RC_IRDA/UHF/IRD_ASC 3
STi7105
Wake-up Int. generator
IRB2 Rx processor (IRB/UHF inputs)_ To ClockGen GLOBAL_POWER_DOWN
PIOs
IRB_WAKEUP_INTERRUPT
IRQ_EXT[4]
Interrupt level controller (ILC3)
wakeup
4
CLK_IC_100 GLOBAL_POWER_DOWN_REG
Clear
ILC_EXT_OUT[7:4]
R/W uC
Low power controller 4 Interrupt levels to ST40 IRL
LOWPOWEROUT_FROM_LPC WAKEUP_BY_INT
LOW_POWER_IN
To ILC3 ext interrupt [7]
14.3
DDR self-refresh
To send the DDR in self-refresh the CPU needs to write a bit in the system config register: SYSTEM_CONFIG11: GP-LMI / LMI padlogic config control register bit[12] LMIPL_PLL_POWERDOWN: PLL power down This write operation activates the powerdown protocol for the LMI Core (a powerdown request is received by the LMI). The LMI core completes all of the outstanding operations, it
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Low power control puts the DDR in self-refresh mode and then answers with a powerdown grant. This can be monitored by means of a status bit in the system conf register: SYSTEM_STATUS4: LMI padlogic status register, bit[0] LMI_PWRD_ACK: LMI power
acknowledge
As soon the acknowledge is received the LMI clock can be switched off or slowed down using the methods described before. After exiting from low power mode the DLLs inside the LMI padlogic must be reset by means of a soft reset using the sys conf bit and the lock condition must be reached: SYSTEM_CONFIG11: GP-LMI / LMI padlogic config control register Information classified Confidential - Do not copy (See last page for obligations) bit[27] RST_N_LMI: LMI sub system reset. Active Low Note: This procedure has the effect of resetting the LMI core. This implies that the LMI core configuration must be re-done. The software needs to guarantee that no access is performed to the LMI during powerdown and until LMI and padlogic are restored to the normal mode of operation.
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14.4
EMI and PCI clocks stopping

The clocks of these three IPs can be switched off with the same mechanism used to put the DDR into self-refresh (that is, by means of the powerdown protocol executed between the system config and the two IPs). For that case the system config bits to be used are:
SYSTEM_CONFIG32: Power down config register bit[1] EMI_POWER_DOWN_REQ: Power down request for EMI module bit[2] PCI_POWER_DOWN_REQ: Power down request for PCI module SYSTEM_STATUS15: Power down status register bit[1] POWER_DOWN_ACK_EMI: EMI power down acknowledge bit[2] POWER_DOWN_ACK_PCI: PCI power down acknowledge
14.5
ST40 sleep and standby modes overview

The ST40-300 ISA includes a sleep instruction that can be used to suspend operation of the core to the point where the clocks can be stopped. The ST40-300 top also provides signals to inform an SoC level power or clock controller when it is safe to remove the clock and to determine whether the CSP clock should be stopped or not.
Note:
The STi7105 ClockGenA does not allow the ST40 clocks to be switched off because of the missing hand-shake with the ST40. ST40 clocks can only be slowed-down.
Sleep mode
On executing the sleep instruction the ST40-300 core will flush the instructions in the pipeline and complete all outstanding STBus transactions on the initiator port. Once this has been completed the CPU will assert the EXT_ST40_CORE_PDACK signal to indicate that the clock to the core can be removed.
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Low power control
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The actual gating of the clock provided to the core is expected to be performed at the SoC level from the clock controller itself in response to the EXT_ST40_CORE_PDACK signal being asserted. This is done to allow the entire clock tree to be stopped and therefore to maximize the dynamic power-saving. Note: The STi7105 ClockGenA does not allow the ST40_ICK clock to be switched off because of the missing hand-shake with the ST40. The CSP also provides a mechanism to enter sleep mode as directed by a system level clock or power controller. In this case the CSP is instructed to enter sleep mode by the system level assertion of the EXT_ST40_CSP_PDREQ signal. At this point the CSP will complete all outstanding STBus requests that it has received. Once the CSP is idle it will internally switch the relevant wake-up control signals to operate correctly with the CSP clock removed and will then assert EXT_ST40_CSP_PDACK to indicate that it is safe to stop the clock to the CSP. The actual gating of the clock provided to the CSP is expected to be performed at the SoC level from the clock controller itself in response to the EXT_ST40_CSP_PDACK signal being asserted. This is done to allow the entire clock tree to be stopped and therefore to maximize the dynamic power-saving. Note: 1 Neither the core nor the CSP will signal readiness to have their clocks removed until all outstanding transactions are completed. Consequently, a pending access to a nonresponding peripheral will prevent the ST40-300 entering sleep mode. The system designer must ensure that other initiators and targets in the system are shut down in a manner that ensures all transactions can be completed safely. The STi7105 ClockGenA does not allow the ST40_PCK clock to be switched off because of the missing hand-shake with the ST40. Exiting sleep mode Two conditions will cause the ST40 core to exit sleep mode.

An interrupt on the NMI, IRL, through the interrupt expansion interface or generated by one of the CSP peripherals (if the CSP is still being clocked). Either a manual or power-on reset. This can be applied either through the relevant pins on the core, the UDI, or by the watchdog timer.
De-asserting EXT_ST40_CSP_PDREQ will not cause the CSP or core to resume from sleep and will be ignored. When a return from sleep mode is requested the CSP will deassert the EXT_ST40_CSP_PDACK signal to indicate to the system level clock controller that it is ready for its clock to be started. Note: Before starting the CSP clock the system level clock controller should de-assert EXT_ST40_CSP_PDREQ to prevent the CSP from re-entering sleep mode. Once it has started to receive a clock the CSP will return to functional mode and will assert the STBus default grant signal to indicate it can start to accept transactions from the STBus. The CSP will also internally signal to the core that it is to wake-up from sleep mode, at which point the core will de-assert its EXT_ST40_CORE_PDACK and wait until the core clock is re-started by the clock controller therefore allowing the core to continue with execution of instructions. Note: There is no mechanism in place to prevent the CSP from transitioning into sleep even if the CPU is in functional mode. An operation where the core is being clocked and the CSP is powered down is not supported and should be avoided except during the transition to and from sleep mode.
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STi7105
System config module
15
15.1

Brief overview
The System Config is a module that holds general purpose configuration registers. It can also be used to read back some system configurations. Register addresses are shown as SystemConfigBaseAddress + Offset The SystemConfigBaseAddress is: 0xFE00 1000 Information classified Confidential - Do not copy (See last page for obligations)
15.1.1
Table 68.
Address offset 0x0000 0x0004
Register summary
Register summary
Register DEVICE_ID EXTRA_DEVICE_ID Device identifier Reserved Status registers Description Reference on page 180 on page 180
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0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x002C 0x0030 0x0034 0x0038 0x003C 0x0040 0x0044
SYSTEM_STATUS0 SYSTEM_STATUS1 SYSTEM_STATUS2 SYSTEM_STATUS3 SYSTEM_STATUS4 SYSTEM_STATUS5 SYSTEM_STATUS6 SYSTEM_STATUS7 SYSTEM_STATUS8 SYSTEM_STATUS9 SYSTEM_STATUS10 SYSTEM_STATUS11 SYSTEM_STATUS12 SYSTEM_STATUS13 SYSTEM_STATUS14 SYSTEM_STATUS15
USB/SATA PHY status register Mode pin status captured during power-onreset OSC status register LMI-PADLOGIC (LMI_SYS) status register LMI-PADLOGIC (LMI_SYS) status register ClockGen D Jitter estimator capture pattern monitor ClockGen D Jitter estimator beat edge monitor Compensation status registers ClockGenD Jitter estimator beat edge counter monitor HDMI PLL status register USB/LMI PLI Bist counter status register Reserved Thermal sensor status register Reserved Reserved Power down status register Configuration registers
on page 181 on page 181 on page 182 on page 182 on page 183 on page 183 on page 184 on page 184 on page 185 on page 185 on page 186 on page 186 on page 187 on page 187 on page 188 on page 188
0x0100 0x0104
SYSTEM_CONFIG0 SYSTEM_CONFIG1
Transport config register HDMI PHY compensation code register
on page 189 on page 190
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Address offset 0x0108 0x010C 0x0110 0x0114 0x0118 0x011C 0x0120 0x0124 0x0128 0x012C 0x0130 0x0134
Register SYSTEM_CONFIG2 SYSTEM_CONFIG3 SYSTEM_CONFIG4 SYSTEM_CONFIG5 SYSTEM_CONFIG6 SYSTEM_CONFIG7 SYSTEM_CONFIG8 SYSTEM_CONFIG9 SYSTEM_CONFIG10 SYSTEM_CONFIG11 SYSTEM_CONFIG12 SYSTEM_CONFIG13 SYSTEM_CONFIG14 SYSTEM_CONFIG15 SYSTEM_CONFIG16 SYSTEM_CONFIG17 SYSTEM_CONFIG18 SYSTEM_CONFIG19 SYSTEM_CONFIG20 SYSTEM_CONFIG21 SYSTEM_CONFIG22 SYSTEM_CONFIG23 SYSTEM_CONFIG24 SYSTEM_CONFIG25 SYSTEM_CONFIG26 SYSTEM_CONFIG27 SYSTEM_CONFIG28 SYSTEM_CONFIG29 SYSTEM_CONFIG30 SYSTEM_CONFIG31 SYSTEM_CONFIG32 SYSTEM_CONFIG33
Description HDMI PHY configuration register DAC /HDMI config register USB / Delta -Mu config register EMI/PCI config register Vidout config register COMMS /Ethernet config register SH4 boot control config register ResetGen config register (only sensitive to preset) ITRQ pads control pin config register LMI padlogic config register LMI padlogic config register LMI padlogic config register LMI padlogic config register Key scan / FDMA config register Comms SSC configuration register CPXM config control register pad state config control register PIO 0 alternate function control register PIO 1 alternate function control register PIO 2 alternate function control register Compensation config registers Compensation config registers Osc config register PIO 3 alternate function control register ST230 Lx - AUDIO boot ST230 Lx - AUDIO reset control and periph address ST230 DELTA - MU boot ST230 DELTA -MU reset control and periph address Reserved EMI config register Power Down config register SOFT_JTAG register for the USB2.0 tap controller
Reference on page 191 on page 192 on page 193 on page 194 on page 195 on page 196
on page 199 on page 200 on page 200 on page 201 on page 203 on page 204 on page 204 on page 205 on page 206 on page 207 on page 207 on page 208 on page 208 on page 209 on page 210 on page 211 on page 211 on page 212 on page 212 on page 213 on page 213 on page 214 on page 214 on page 215 on page 216
0x0138 0x13C 0x0140 0x0144 0x0148 0x014C 0x0150 0x0154 0x0158 0x015C 0x0160 0x0164 0x0168 0x016C 0x0170 0x0174 0x0178 0x017C 0x0180 0x0184
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STi7105
Address offset 0x0188 0x018C 0x0190 0x0194 0x0198 0x019C 0x01A0 0x01A4 0x01A8 0x01AC 0x01B0 0x01B4
Register SYSTEM_CONFIG34 SYSTEM_CONFIG35 SYSTEM_CONFIG36 SYSTEM_CONFIG37 SYSTEM_CONFIG38 SYSTEM_CONFIG39 SYSTEM_CONFIG40 SYSTEM_CONFIG41 SYSTEM_CONFIG42 SYSTEM_CONFIG43 SYSTEM_CONFIG44 SYSTEM_CONFIG45 SYSTEM_CONFIG46 SYSTEM_CONFIG47 SYSTEM_CONFIG48 SYSTEM_CONFIG49 SYSTEM_CONFIG50 SYSTEM_CONFIG51 SYSTEM_CONFIG52 SYSTEM_CONFIG53 SYSTEM_CONFIG54 SYSTEM_CONFIG55
Description PIO 4 alternate function control register PIO 5 alternate function control register PIO 6 alternate function control register PIO 7 alternate function control register LMI config register Reserved Clock select config register Thermal sensor config register LMI config register LMI config register Reserved Reserved PIO 8 alternate function control register PIO 9 alternate function control register PIO 12 alternate function control register PIO 13 alternate function control register PIO 15 alternate function control register LMI config register LMI config register Reserved Reserved LMI config INTC2 registers
Reference on page 216 on page 217 on page 217 on page 218 on page 218 on page 219
on page 220 on page 220 on page 221 on page 221 on page 222 on page 222 on page 223 on page 223 on page 224 on page 224 on page 225 on page 226 on page 226 on page 227 on page 227
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0x01B8 0x01BC 0x01C0 0x01C4 0x01C8 0x01CC 0x01D0 0x01D4 0x01D8 0x01DC
0x0300 0x0304 0x0308 0x0320 0x0324 0x0328 0x0340 0x0344 0x0348 0x0360 0x0364
INTC2_PRIORITY00 INTC2_PRIORITY04 INTC2_PRIORITY08 INTC2_REQUEST00 INTC2_REQUEST04 INTC2_REQUEST08 INTC2_MASK00 INTC2_MASK04 INTC2_MASK08 INTC2_MASK_CLEAR00 INTC2_MASK_CLEAR04
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
on page 228 on page 228 on page 229 on page 229 on page 229 on page 230 on page 230 on page 230 on page 231 on page 231 on page 231
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Address offset 0x0368 0x0380
Register INTC2_MASK_CLEAR08 INTC2_MODE Reserved Reserved
Description
Reference on page 232 on page 232
15.1.2
Device ID register descriptions Device ID register

9 8 7 6 MANUFACTURER_ID 5 4 3 2 1 0
DEVICE_ID
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Address:
SystemConfigBaseAddress + 0x0000 R 0x2D43E041(1) JTAG deviceID
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Type: Reset: Description:
[31:28] VERSION [27:22] GROUP_ID [21:12] DEVICE_ID [11:1] MANUFACTURER_ID [0] JTAG_BIT
EXTRA_DEVICE_ID
Reserved
9 8 7 6 5 4 3 2 1 0 RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Address: Type: Reset: Description:
SystemConfigBaseAddress + 0x0004 R 0xXXXX Reserved
[31:0] RESERVED
1. This reset value is for cut 3.0. The reset value is 0x1D43E041 for cut 2.0 and 0x0D43E041 for cut 1.0.
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DEVICE_ID
GROUP_ID
JTAG_BIT
VERSION
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15.1.3
System status register description USB/SATA PHY status register

9 8 7 6 5 4 3 BISTOK 2 TDO_USB 1 TDO_SATA 0 RESERVED RESERVED
SYSTEM_STATUS0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SystemConfigBaseAddress + 0x0008 R 0x0000 USB/SATA Phy status Information classified Confidential - Do not copy (See last page for obligations)
[31:4] RESERVED [3] BISTOK: High level means that bist is running into USB PHY device and no error is detected. [2] TDO_USB: USB2 PHY TDO signal.
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[1] TDO_SATA: SATA PHY TDO signal. [0] RESERVED
SYSTEM_STATUS1
RESERVED
Mode pins values register

9 MODE_PIN 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SystemConfigBaseAddress + 0x000C R Undefined(1) Mode pins values
[31:19] RESERVED [18:0] MODE_PIN: Mode pins are captured during the power-on-reset period.
1. Reset value depends on modepins value
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SYSTEM_STATUS2
OSC status register

9 8 7 6 5 4 3 2 1 0 OSCI30_OSCIOK
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED
SystemConfigBaseAddress + 0x0010 R Information classified Confidential - Do not copy (See last page for obligations) 0x00000000 OSC status
[31:1] RESERVED [0] OSCI30_OSCIOK: 1: OSCI 30 MHz oscillation stable (ZI output enabled) 0: OSCI 30 MHz oscillation unstable
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SYSTEM_STATUS3
LMIPL_IOREF_NASRC[6:0]
LMI status register

9 8 7 6 5 LMIPL_DLL1_COMMAND[8:0] 4 3 2 1 0 LMIPL_DLL2_COMMAND[8:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 LMIPL_IOREF_COMPOK
LMIPL_DLL2_LOCK
LMIPL_DLL1_LOCK
SystemConfigBaseAddress + 0x0014 R 0xXXXX(1) LMI status
[31:29] RESERVED [28] LMIPL_IOREF_COMPOK: Can be high only in normal mode and when a new measured code is available on the ASRC lines. When macrocell turns from any other mode to normal mode, delay constraints are applied to COMPOK signal. [27:21] LMIPL_IOREF_NASRC[6:0]: Input code to be copied on the AxSRC lines by the compensation cell in Read mode. [20] LMIPL_DLL2_LOCK: DLL2 lock. 1: DDL2 is locked 0: DDL2 is unlocked
1. From LMI Padlogic
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LMIPL_PLL_LOCK
RESERVED
STi7105
[19:11] LMIPL_DLL2_COMMAND[8:0]: DLL2 command. Reports the command currently being generated by DLL2. [10] LMIPL_DLL1_LOCK: DLL1 lock. 1: DDL1 is locked 0: DDL1 is unlocked
[9:1] LMIPL_DLL1_COMMAND[8:0]: DLL1 command. Reports the command currently being generated by DLL1. [0] LMIPL_PLL_LOCK: LMIPL PLL lock signal. 1: LMI PLL is locked 0: LMI PLL is unlocked
SYSTEM_STATUS4
LMI padlogic status register

9 8 7 6 5 4 DDR2_DIAG_MONITOR[4:0] 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SystemConfigBaseAddress + 0x0018 R 0x00000000 LMI padlogic config status
[31:7] RESERVED [6:2] DDR2_DIAG_MONITOR[4:0]: For future development. [1] LMI_DQS_FAIL: 1: Notification for DQS spurious/missing behavior [0] LMI_PWRD_ACK: 1: LMI power acknowledge
SYSTEM_STATUS5
Clockgen D Jitter estimator capture pattern monitor

9 8 7 6 5 4 3 2 1 0 JITTER_CAPTURE_PATTERN
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 JITTER_CAPTURE_NOT_PATTERN
SystemConfigBaseAddress + 0x001C R 0x00000000 ClockGenD Jitter estimator capture pattern monitor
[31:16] JITTER_CAPTURE_NOT_PATTERN [15:0] JITTER_CAPTURE_PATTERN
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LMI_PWRD_ACK
LMI_DQS_FAIL
RESERVED
STi7105
SYSTEM_STATUS6
RESERVED
Clockgen D Jitter estimator beat edge monitor

9 8 7 6 5 4 3 2 1 0 JITTER_BEAT_EDGE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SystemConfigBaseAddress + 0x0020 R 0x00000000 ClockGenD Jitter estimator beat edge monitor Information classified Confidential - Do not copy (See last page for obligations)
[31:21] RESERVED [20:0] JITTER_BEAT_EDGE
SYSTEM_STATUS7
Compensation status register

9 8 CONF_3V3COMP1_COMPOK 7 6 5 4 CONF_3V3COMP0_NASRC 3 2 1 0 CONF_3V3COMP0_COMPOK CONF_3V3COMP2_COMPOK
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 CONF_3V3COMP2_NASRC CONF_3V3COMP1_NASRC
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RESERVED
SystemConfigBaseAddress + 0x0024 R 0x00000000 Compensation status
[31:24] RESERVED [23:17] CONF_3V3COMP2_NASRC: 3V3 compensation 2: NASRC code [16] CONF_3V3COMP2_COMPOK: 3V3 compensation 2: COMPOK signal [15:9] CONF_3V3COMP1_NASRC: 3V3 compensation 1: NASRC code [8] CONF_3V3COMP1_COMPOK: 3V3 compensation 1: COMPOK signal [7:1] CONF_3V3COMP0_NASRC: 3V3 compensation 0: NASRC code [0] CONF_3V3COMP0_COMPOK: 3V3 compensation 0: COMPOK signal
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System config module ClockGenD Jitter estimator beat edge counter monitor
9 8 JITTER_BEAT_EDGE_COUNTER 7 6 5 4 3 2 1 0
SYSTEM_STATUS8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 CONF_3V3COMP3_COMPOK CONF_3V3COMP3_NASRC
RESERVED

[31:24]
SystemConfigBaseAddress + 0x0028 R 0x00000000 ClockGenD Jitter estimator beat edge pattern monitor
RESERVED
[23:17] CONF_3V3COMP3_NASRC: 3V3 compensation 3: nasrc code [16] CONF_3V3COMP3_COMPOK: 3V3 compensation 3: compok signal [15:0] JITTER_BEAT_EDGE_COUNTER
SYSTEM_STATUS9
HDMI PLL status register

9 8 7 6 5 4 3 2 1 0 HDMI_PLL_LOCK
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED
SystemConfigBaseAddress + 0x002C R 0x00000000 HDMI PLL status
[31:1] RESERVED [0] HDMI_PLL_LOCK: Used to check lock condition of HDMI rejection PLL. 1: HDMI rejection PLL is locked 0: HDMI rejection PLL is unlocked
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STi7105 USB/LMI PLI Bist counter status register

9 8 7 6 5 4 LMI_PLL_BIST_COUNT 3 2 1 0 USB2_PLL_BIST_COUNT USB1_PLL_BIST_COUNT
SYSTEM_STATUS10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
SystemConfigBaseAddress + 0x0030 R 0x00000000 Reserved Information classified Confidential - Do not copy (See last page for obligations)
[31:27] RESERVED [26:18] USB2_PLL_BIST_COUNT: Value of USB2 PLL Bist counter value
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[17:9] USB1_PLL_BIST_COUNT: Value of USB1 PLL Bist counter value [8:0] LMI_PLL_BIST_COUNT: Value of LMI PLL Bist counter value
Caution:
In case of USB signals, the usual naming convention is not used. In order to align with the STi7105 ballout names, this manual mentions two instances of USB as USB1 and USB2 rather than USB0 and USB1. Therefore, in this manual the first instance of USB is USB1 and the second instance is USB2. Reserved
9 8 7 6 5 4 3 2 1 0 RESERVED
SYSTEM_STATUS11
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SystemConfigBaseAddress + 0x0034 R 0xXXXX Reserved
[31:0] RESERVED
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System config module Thermal sensor status register

9 DATAREADY 8 OVERFLOW 7 6 5 4 INTREG 3 2 1 0 COMPOUT
SYSTEM_STATUS12
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 VOBS DATA
SystemConfigBaseAddress + 0x0038 R 0x00000000 Information classified Confidential - Do not copy (See last page for obligations) Thermal sensor status
[31:18] RESERVED [17] VOBS: Reserved to debug - not connected in application. [16:10] DATA: Output data. [9] DATAREADY: Set to 1 every 32 clock cycles when conversion is over, valid for 1 clock period, held at 0 as long as the bandgap has not started.
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[8] OVERFLOW: Overflow of digital adder, corresponds to the upper limit of the temperature range after calibration. [7:1] INTREG: Reserved to debug - not connected in application. [0] COMPOUT: Reserved to debug - not connected in application.
SYSTEM_STATUS13
Reserved
9 8 7 6 5 4 3 2 1 0 RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SystemConfigBaseAddress + 0x003C R 0x00000000 Reserved
[31:0] RESERVED
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9 8 7 6 5 4 3 2 1 0 RESERVED
SYSTEM_STATUS14
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SystemConfigBaseAddress + 0x0040 R 0x00000000 Reserved Information classified Confidential - Do not copy (See last page for obligations)
[31:0] RESERVED
SYSTEM_STATUS15
Power down status register

9 8 7 POWER_DOWN_ACK_SATA1 6 5 POWER_DOWN_ACK_USB2 4 POWER_DOWN_ACK_USB1 3 POWER_DOWN_ACK_KEY_SCAN 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
POWER_DOWN_ACK_EMI
POWER_DOWN_ACK_PCI
RESERVED
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SystemConfigBaseAddress + 0x0044 R 0x00000000 Power down status
[31:8] RESERVED [7] POWER_DOWN_ACK_SATA1: 1: SATA host power down acknowledge [6] RESERVED [5] POWER_DOWN_ACK_USB2: 1: USB2 host power down acknowledge. [4] POWER_DOWN_ACK_USB1: 1: USB1 host power down acknowledge [3] POWER_DOWN_ACK_KEY_SCAN: 1: Key scanner power down acknowledge [2] POWER_DOWN_ACK_PCI: 1: PCI power down acknowledge [1] POWER_DOWN_ACK_EMI: 1: EMI power down acknowledge [0] RESERVED
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RESERVED
RESERVED
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15.1.4
System configuration register description

Transport stream config register
9 8 7 6 5 4 CFG_TSIN3_PARALLEL_NOT_SERIAL 3 2 1 0
SYSTEM_CONFIG0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CFG_TSIN0_TSIN1_SELECT
CFG_TSIN2_NOTSELECT
CFG_TSIN3_SELECT
RESERVED
RESERVED
Address: Type: Reset:
SystemConfigBaseAddress + 0x0100 RW 0x00000000 Transport stream config register
Description:
[31:5] RESERVED [4] CFG_TSIN3_PARALLEL_NOT_SERIAL: 1: TSIN3 is in parallel mode 0: TSIN3 is in serial mode
[3] CFG_TSIN3_SELECT: 1: TSIN3 of TS_Merger receives TSIN3 0: TSIN3 of TS_Merger receives output of mux_1 (that is, TSIN0, TSIN1, OR TSIN2 depending upon CFG_TSIN0_TSIN1_SELECT and CFG_TSIN2_NOTSELECT) [2] CFG_TSIN2_NOTSELECT: 1: input TSIN2 of TSMerger receives output of mux_0 (i.e. TSIN0 or TSIN1 depending of CFG_TSIN0_TSIN1_SELECT) 0: input TSIN2 of TSMerger recieves TSIN2 [1] CFG_TSIN0_TSIN1_SELECT: 1: TSIN1 routed through mux_0 to input 1 of mux_1 0: TSIN0 routed through mux_0 to input 1 of mux_1 [0] RESERVED
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System config module Figure 33. Transport stream routing to TSMerger

CFG_TSIN0_TSIN1_SELECT CFG_TSIN1_SRC_SELECT TSIN0 PIO13(7: 4), PIO14(7:0) PIO15(4:0), PIO12(4:0) TSIN1 CFG_TSIN2_NOTSELECT CFG_TSIN3_SELECT
STi7105
TSin0 parallel TSin1 0 0 1

mux_0
TSin0
parallel / serial TSin1 1
PIO12(7: 0), PIO13(3:0) parallel / serial TSIN2 PIO14(5:1) PIO6(7: 0), PIO7(3:0) PIO14(5: 1), PIO7(3:0) TSIN3
TSin1
TSin2 serial/parallel
0 1
0
mux_1
TSin3
1
mux_2
TSin3 serial
CFG_TSIN2_SRC_SELECT
PIO12(7:5) PIO13 (1:0)
TSOUT
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0
TSIN1 or TSout1394 (1394 interface)
TS1394
PIO12
mux_4
PIO12_ALTFOPJ_MUX_SEL_BUS(7:0) & PIO13_ALTFOPJ_MUX_SEL_BUS(3:0) = MUX4_SELECT
Transport subsystem
Note:
CFG_TSIN3_PARALLEL_NOT_SERIAL is an extra programming required to select parallel mode. On reset, the TSIN3 stream by default is in serial mode. Since, on PIO TSIN3 can be selected both in parallel and serial mode, therefore, to receive TSIN3 in parallel mode this bit must be first programmed to 1. Then, serial not parallel configuration inside TSmerger will also be required to process TSIN3 in serial/parallel mode. HDMI PHY compensation config register
9 8 7 6 5 4 3 2 1 0 USER_COMP
SYSTEM_CONFIG1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SystemConfigBaseAddress + 0x0104 RW 0x00000000 HDMI PHY compensation config register
[31:0] USER_COMP: External compensation code command to be applied to the HDMI phy.
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mux_5 mux_3
TSMerger TSin2
STi7105
System config module HDMI / HDMI phy config register

9 8 7 6 5 4 3 2 1 0 HDMI_PHY_PREEMPWDTH[2:0]
SYSTEM_CONFIG2
HDMI_PHY_PREEMPWDTHEXT HDMI_PHY_PREEMPSTR[1:0] HDMI_HOT_PLUG_ENABLE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 COMPENSATION_BYPASS CLK_BCH_HDMI_DIVSEL HDMI_CEC_RX_ENABLE HDMI_PHY_PREEMPON
HDMI_AUDIO_SRC_SEL
HDMI_POFF_ENABLE
USER_COMP[47:32]
RESERVED
PROG[1:0]
SystemConfigBaseAddress + 0x0108 RW 0x0000 HDMI PHY config register
[31] RESERVED
[30] HDMI_AUDIO_SRC_SEL: 1: Audio SRC is 8-channel PCM out [29] HDMI_CEC_RX_ENABLE: 1: Indicates usage of HDMI_CEC_RX is enabled [28] CLK_BCH_HDMI_DIVSEL [27] HDMI_HOT_PLUG_ENABLE: 1: Enables mapping of HDMI_HOT_PLUG_IN on PIO [26] HDMI_POFF_ENABLE: 1: Enables power off on HDMI [25] HDMI_PHY_PREEMPWDTHEXT [24:22] HDMI_PHY_PREEMPWDTH[2:0] [21:20] HDMI_PHY_PREEMPSTR[1:0] [19] HDMI_PHY_PREEMPON
0: Audio SRC is 2-channel stereo 0: Indicates disabled
0: Disables POFF
[18:17] PROG[1:0]: Programs the output buffer speed for PROGB/PROGA. x0: Speed set up to 1.6 Gbps 01: Speed set up to 800 Mbps 1: Speed set up to 400 Mbps [16] COMPENSATION_BYPASS: Selects internally generated compensation bits or external compensation code. 1: Provides compensation bits generated by Pivot compensation cell 0: Provides external bits generated by USER_COMP to compensation cell [15:0] USER_COMP[47:32]: External compensation command bit.
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STi7105 Video DAC / HDMI config register

9 TST_DAC_HD_CMDR 8 TST_DAC_HD_CMDS 7 TST_DAC_SD_CMDR 6 TST_DAC_SD_CMDS 5 4 3 2 1 0 DVONOTPAD_DVP_MAIN
SYSTEM_CONFIG3
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PLL_S_HDMI_ENABLE PLL_S_HDMI_MDIV PLL_S_HDMI_NDIV PLL_S_HDMI_PDIV
S_HDMI_RST_N
DAC_HD_HZW
SystemConfigBaseAddress + 0x010C RW 0x32644000 DAC config
DAC_SD_HZW
DAC_HD_HZU
DAC_HD_HZV
DAC_SD_HZU
DAC_SD_HZV
[31:24] PLL_S_HDMI_MDIV[7:0]: Sets the dividing factor of the 8-bit programmable input divider. [23:16] PLL_S_HDMI_NDIV[7:0]: Sets the dividing factor of the 8-bit programmable loop divider. [15:13] PLL_S_HDMI_PDIV[2:0]: Sets the dividing factor of the 3-bit programmable output divider.
[12] PLL_S_HDMI_ENABLE: This signal determines the mode of operation of the rejection PLL. 0: PLL is powered down 1: Rejection PLL is powered up [11] S_HDMI_RST_N: 0: HDMI serializer reset is asserted [10] DVONOTPAD_DVP_MAIN: 0: DVP video input coming from pads 1: HDMI serializer is de-asserted 1: DVP video input coming from DVO
[9] TST_DAC_HD_CMDR: Functions with CMDR signals. Can be used to force DAC HD O/P. [8] TST_DAC_HD_CMDS: Functions with CMDS signal. Can be used to force DAC HD O/P. [7] TST_DAC_SD_CMDR: Functions with CMDR signals. Can be used to force DAC SD O/P. [6] TST_DAC_SD_CMDS: Functions with CMDS signal. Can be used to force DAC SD O/P. [5] DAC_HD_HZU: 1: Disables the DAC HD output current and puts the O/P in high impedance mode, but leaves the reference circuitry powered for fast recovery to active mode. [4] DAC_HD_HZV: 1: Disables the DAC HD output current and puts the O/P in high impedance mode, but leaves the reference circuitry powered for fast recovery to active mode. [3] DAC_HD_HZW: 1: Disables the DAC HD output current and puts the O/P in high impedance mode, but leaves the reference circuitry powered for fast recovery to active mode. [2] DAC_SD_HZU: 1: Disables the DAC SD output current and puts the O/P in high impedance mode, but leaves the reference circuitry powered for fast recovery to active mode. [1] DAC_SD_HZV: 1: Disables the DAC SD output current and puts the O/P in high impedance mode, but leaves the reference circuitry powered for fast recovery to active mode. [0] DAC_SD_HZW: 1: Disables the DAC SD output current and puts the O/P in high impedance mode, but leaves the reference circuitry powered for fast recovery to active mode.
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STi7105
System config module STBus / USB config control register

9 8 7 6 5 4 3 2 1 USB_HOST_SOFT_RESET_ENABLE 0
SYSTEM_CONFIG4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 CFG_USB2_OVRCURR_ENABLE CFG_USB1_OVRCURR_ENABLE
USB2_PRT_OVCURR_POL
USB1_PRT_OVCURR_POL
USB2_PRT_OVCURR_SEL
USB1_PRT_OVCURR_SEL
USBPHY_INEDGECTRL2
USBPHY_INEDGECTRL1
ENABLE_TID_DELTAMU
USB_PHY_XTAL_VALID
PLI_CLOCK_STOP
USB_INDCSHIFT2
USB_INDCSHIFT1
RESERVED
RESERVED
SystemConfigBaseAddress + 0x0110 RW 0x00000126 STBus/ USB Config
[31:17] RESERVED [16] USBPHY_INEDGECTRL2: 1: USBPHY_INEDGECTRL2 is active [15] USB_INDCSHIFT2 1: USBPHY_INDCSHIFT2 is active [14] USBPHY_INEDGECTRL1: 1: USBPHY_INEDGECTRL1 is active [13] USB_INDCSHIFT1: 1: USBPHY_INDCSHIFT1 is active [12] CFG_USB2_OVRCURR_ENABLE: 1: USB2_overcurrent is enabled [11] CFG_USB1_OVRCURR_ENABLE: 1: USB1_overcurrent is enabled [10] CFG_TSIN2_SRC_SELECT: 1: TSin2 is from PIO14 [9] CFG_TSIN1_SRC_SELECT: 1: TSin1 is selected from PIO15 [8] RESERVED [7] USB_PHY_XTAL_VALID: 1: OSC input to USB PHY is stable [6] USB2_PRT_OVCURR_SEL: 1: USB2_PRT_OVCURR_IN is from PIO14[6] [5] USB1_PRT_OVCURR_SEL: 1: USB1_PRT_OVCURR_IN is from PIO12[5] 0: OSC input is invalid 0: From PIO4[6] 0: From PIO4[4] 0: USBPHY_INEDGECTRL2 is inactive 0: USBPHY_INDCSHIFT2 is inactive 0: USBPHY_INEDGECTRL1 is inactive 0: USBPHY_INDCSHIFT1 is inactive 0: Disabled 0: Disabled 0: TSin2 is from PIO6 0: TSin1 is from PIO12
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Confidential
STi7105
[4] USB2_PRT_OVCURR_POL: 1: USB2_PRT_OVCURR is active high [3] USB1_PRT_OVCURR_POL: 1: USB1_PRT_OVCURR is active high
0: USB2_PRT_OVCURR is sensed active low 0: USB1_PRT_OVCURR is sensed active low
[2] PLI_CLOCK_STOP: 1: Stops the PLL1600 clock output to LMI padlogic [1] USB_HOST_SOFT_RESET_ENABLE: 1: Allows soft reset of USB host (active low) [0] ENABLE_TID_DELTAMU: 1: Enables TID[3:0] generation for DeltaMu Rasta STBUS plug2
SYSTEM_CONFIG5
PCI_CLOCK_MASTER_NOT_SLAVE PCI_DEVICE_NOT_HOST_ENABLE
EMI / PCI config register

9 8 7 6 FMI_BUSFREE_ACCESS_ENABLE 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PCI_INT_TO_HOST_ENABLE
SystemConfigBaseAddress + 0x0114 RW 0x04000040 EMI / PCI config
[31:30] RESERVED [29] PCI_DEVICE_NOT_HOST_ENABLE: 1: PCI is a device [28] PCI_CLOCK_MASTER_NOT_SLAVE: 1: PCI clock is master [27:26] RESERVED [25] PCI_LOCK_IN_SEL: 1: PCI_LOCK_IN is from PIO15[5] [24] PCI_SYS_ERROR_ENABLE: 1: Indicates PCI_SYSTEM_ERROR enabled 0: PCI_LOCK_IN is from PIO7[0] 0: ISs disabled 0: PCI is a host 0: PCI clock is slave
[23] PCI_RESETN_ENABLE: 1: Indicates PCI_RESETN_FROM_HOST_TO_DEVICE is enabled 0: Indicates PCI_RESETN_FROM_HOST_TO_DEVICE is disabled
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FMI_PULLUP_DISABLE[1:0]
PCI_SYS_ERROR_ENABLE
PCI_INT0_FROM_DEVICE
Confidential
DVBCI_MODE_ENABLE
PCI_LOCK_IN_ENABLE
PCI_RESETN_ENABLE
FMI_GEN_CFG[1:0]
PCI_LOCK_IN_SEL
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
STi7105
[22] PCI_INT_TO_HOST_ENABLE: 1: Indicates INT_PCI_TO_HOST enabled [21] PCI_INT0_FROM_DEVICE: 1: Indicates PCI_INT_FROM_DEVICE[0] is enabled [20] PCI_INT1_FROM_DEVICE: 1: Indicates PCI_INT_FROM_DEVICE[1] is enabled [19] PCI_INT2_FROM_DEVICE: 1: Indicates PCI_INT_FROM_DEVICE[2] is enabled [18] RESERVED [17] PCI_LOCK_IN_ENABLE: 1: Indicates usage of PCI_LOCK_IN is enabled [16:12] RESERVED [11:10] FMI_PULLUP_DISABLE[1:0]: 1: Pullup is disabled
0: Indicates INT_PCI_TO_HOST is disabled 0: Indicates disabled 0: Indicates disabled 0: Indicates disabled
0: indicates disabled
0: Pullup is enabled
[9:8] FMI_GEN_CFG[1:0]: Decides whether re-timing stages are used or not in FMI padlogic
Confidential
[7] RESERVED [6] FMI_BUSFREE_ACCESS_ENABLE: 1: EMI_BUS_FREE_ACCESSPENDING_IN enabled [5:4] RESERVED [3] RESERVED [2] RESERVED [1] RESERVED [0] DVBCI_MODE_ENABLE: 1: Indicates DVB-CI mode is enabled 0: DVBCI mode is disabled 0: Indicates disabled
SYSTEM_CONFIG6
Video-out config control register

9 8 7 6 OLD_FASHIONED_DVO0 5 4 REF_NO_SYNCH_DVO0 3 2 BOT_NOT_TOP_INVERSION 1 AUDIO_SYNC_MAIN_NOT_AUX 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 OLD_FASHIONED_DVO1 REF_NO_SYNCH_DVO1
AUX_NOT_MAIN_DVO1
AUX_NOT_MAIN_DVO0
SPDIF_CHANNEL_SEL
PCMPLYR0_OUT_SEL
H_NOT_V_DVO1
H_NOT_V_DVO0
RESERVED
SystemConfigBaseAddress + 0x0118 RW 0x0000 Video-out config
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PIP_MODE
STi7105
[31:16] RESERVED [15] OLD_FASHIONED_DVO1: 1: H/V reference and synch are from main [14] AUX_NOT_MAIN_DVO1: 1: H/V reference is taken from AUX channel [13] REF_NO_SYNCH_DVO1: 1: Input from pad is H/V reference [12] H_NOT_V_DVO1: 1: H ref/sync is selected [11:10] SPDIF_CHANNEL_SEL: 00: SPDIF_CH0 is selected 10: SPDIF_CH2 is selected 0: H/V reference and synch are from VTG1 0: H/V reference is taken from main channel 0: Input is H/V sync for DVO1 0: V ref/sync is selected for DVO1 01: SPDIF_CH1 is selected 11: SPDIF_CH3 is selected
[9:7] PCMPLYR0_OUT_SEL: 000: PCM channel 0 is routed to PCM_READER [6] OLD_FASHIONED_DVO0: 1: H/V reference and synch are from main 0: H/V reference and synch are from VTG0 0: H/V reference is taken from main channel 0: Input is H/V sync for DVO0 0: V ref/sync is selected for DVO0 0: Inversion is disabled 0: Audio synch is taken from VTG_AUX
Confidential
[5] AUX_NOT_MAIN_DVO0: 1: H/V reference is taken from AUX channel [4] REF_NO_SYNCH_DVO0: 1: Input from pad is H/V reference [3] H_NOT_V_DVO0: 1: H ref/sync is selected [2] BOT_NOT_TOP_INVERSION: 1: Inversion is enabled [1] AUDIO_SYNC_MAIN_NOT_AUX: 1: Audio synch is taken from VTG_MAIN
[0] PIP_MODE: 1: Video2 plug of compositor is routed to main mixer else on AUX mixer
SYSTEM_CONFIG7
GLOBAL_POWER_DOWN
Comms/Ethernet config control register

9 IRB_DATA_OUT_POL_OD 8 SC0_DETECT_VCC_POL 7 SC0_COND_VCC_ENABLE 6 SC0_NOT_SC1_SELECT 5 SCCLK1_NOT_CLKDSS 4 SCCLK0_NOT_CLKDSS 3 SC1_DETECT_VCC_POL 2 UART2_CTS_SRC_SELECT 1 UART2_RXD_SRC_SELECT 0 ETHERNET_INTERFACE_ON
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 SC1_COND_VCC_ENABLE SC_DETECT_VPP_POL
DAA_SERIAL_MODE
DAA_CONFIG_CTRL
PHY_INTF_SELECT
MIIM_DIO_SELECT
SystemConfigBaseAddress + 0x011C RW 0x08081000 COMMS/Ethernet config
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SCIF_PIO_OUTEN
MAC_SPEED_SEL
RMII_MODE
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
ENMII
STi7105
[31:28] RESERVED [27] ENMII: 1: MII mode 0: Reverse MII mode
[26:25] PHY_INTF_SELECT: Selects the type of Ethernet mode 00: MII mode (Default) 01: Reserved 1x: Reserved [24] RESERVED [23] GLOBAL_POWER_DOWN: 1: Activate low power 0: Normal mode
[22] DAA_CONFIG_CTRL: DAA configuration control [21] RESERVED [20] MAC_SPEED_SEL: 1: Indicates that the MAC is running at 100 Mbps speed 0: Indicates that the MAC is running at 10 Mbps speed Remark: Useless if RMII interface is not activated (SYSTEM_CONFIG7[18]). MAC speed does not need to be specified in MII mode.
[19] RESERVED [18] RMII_MODE: 1: RMII interface activated 0: MII interface activated
[17] MIIM_DIO_SELECT: 1: MIIM_DIO from external input, else from GMAC [16] ETHERNET_INTERFACE_ON: 1: Ethernet on (pads enables controlled by MAC) [15:13] RESERVED [12] DAA_SERIAL_MODE: DAA serial interface mode select pin 1: Sets a start pulse on FSYNC at the beginning of the transition 0: Sets a low level on FSYNC at the beginning of the transition [11] SC1_COND_VCC_ENABLE: Enables control of smart card VCC upon detection of smart card removal or insertion.This bit is overridden by PDES_SC_MUXOUT, which is driven by a configuration bit in the PDES. 1: Alternate PIO output pin SC_NOT_SETVCC is controlled according to input SC_DETECT 0: Alternate PIO output pin SC_NOT_SETVCC is driven permanently low [10] SC_DETECT_VPP_POL: 1: Output pin SC_NOT_SETVPP is inverted of PDES_SC_SETVPP 0: Output pin SC_NOT_SETVPP is PDES_SC_SETVPP [9] IRB_DATA_OUT_POL_OD: Selection of polarity of IRB output signal routed as alternate function IRB_DATA_OUT_OD to PIO_3[6] (normally configured as open-drain) 0: IRB_DATA_OUT_OD has same polarity as IRB_DATA_OUT 1: Polarity of IRB_DATA_OUT_OD is inverted [8] SC0_DETECT_VCC_POL: 1: Output pin SC_NOT_SETVPP is inverted 0: Output pin SC_NOT_SETVPP is not inverted 0: All MII pads in input mode
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STi7105
[7] SC0_COND_VCC_ENABLE: Enables control of smart card VCC upon detection of smart card removal or insertion.This bit is overridden by PDES_SC_MUXOUT, which is driven by a configuration bit in the PDES. 1: Alternate PIO output pin SC_NOT_SETVCC is controlled according to input SC_DETECT 0: Alternate PIO output pin SC_NOT_SETVCC is driven permanently low [6] SC0_NOT_SC1_SELECT: 1: Smartcard 0 is selected 0: Smartcard1 is selected
[5] SCCLK1_NOT_CLKDSS: Smartcard clock muxing selection. 1: Smart card clock sourced from smart card clock generator (COMMS): SCCLKGEN1_CLK_OUT 0: Smart card clock sourced from CLK_DSS (CLKgen B) [4] SCCLK0_NOT_CLKDSS: Smartcard clock muxing selection. 1: Smart card clock sourced from smart card clock generator (COMMS): SCCLKGEN0_CLK_OUT 0: Smart card clock sourced from CLK_DSS (CLKgen B) [3] SC1_DETECT_VCC_POL: 1: Output pin SC1_NOT_SETVCC is inverted 0: Output pin SC1_NOT_SETVCC is un-inverted [2] UART2_CTS_SRC_SELECT: 1: UART2_CTS is from PIO12[2] [1] UART2_RXD_SRC_SELECT: 1: UART2_RXD is from PIO12[1] [0] SCIF_PIO_OUTEN: 1: SCIF output enable 0: From PIO4[2] 0: From PIO4[1] 0: Used as regular PIO
SYSTEM_CONFIG8
SH4 boot config control register

9 8 7 6 5 4 3 2 1 0 SH4_RESET_ADDRESS[27:2]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SystemConfigBaseAddress + 0x0120 RW 0x01(1) This register configures the ST40 boot process. Bit 0 controls the ST40 boot request upon reset. Its value depends on the mode_pins (9:8) captured during the reset period.
[31:6] SH4_RESET_ADDRESS[27:2]: NDS compliance.
1. 0x01 when MODE[9:8]=00; ST40 boots, 0x00 for other values of MODE[9:8]
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SH4_ALLOW_BOOT
RESERVED
STi7105
[5:1] RESERVED [0] SH4_ALLOW_BOOT: SH4 request filter control. 1: Request enabled 0: Request bypassed
SYSTEM_CONFIG9
Reset Gen config control register

9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 CPU_RST_OUT_BYPASS[1:0] LONG_RESET_MODE
RESETOUT_PERIOD
Address:
SystemConfigBaseAddress + 0x0124 RW 0xXXXX(1) Reset Gen config
Confidential
[31:30] RESERVED [29] LONG_RESET_MODE: ResetOut mode. Reset value from mode pin (7) [28:27] CPU_RST_OUT_BYPASS[1:0]: CPU_RST_OUT_BYPASS (1): bypass of (LX_Audio+LXDelphi) reset loop back CPU_RST_OUT_BYPASS (0): bypass of (SH4+LX_Audio+LXDelphi) reset loop back Reset value from mode pin (6:5). [26] RESERVED [25:0] RESETOUT_PERIOD: Period of ResetOut in 27MHz cycles. In Long ResetOut mode, the reset value guarantees a 200 ms reset out. In short ResetOut mode, reset out lasts 100 us. This dynamic of this register allows for a max reset out of 2.48 s. Reset value: 0x5265C0 in long ResetOut mode(a), 0x000A8C in short ResetOut mode
a. Long ResetOut mode is selected when the CONF input mode_pin(7) is set to 1.
1. Depends on mode pin
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RESERVED
RESERVED
STi7105 ITRQ pins config control register

9 8 7 6 5 4 3 ITRQ3_DIR 2 ITRQ2_DIR 1 ITRQ1_DIR 0 ITRQ0_DIR RESERVED
SYSTEM_CONFIG10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SystemConfigBaseAddress + 0x0128 RW 0x000F Information classified Confidential - Do not copy (See last page for obligations) ITRQ pins config
[31:4] RESERVED [3] ITRQ3_DIR: 1: ITRQ3 is configured as input [2] ITRQ2_DIR: 1: ITRQ2 is configured as input 0: ITRQ3 is configured as output 0: ITRQ2 is configured as output 0: ITRQ1 is configured as output 1: ITRQ0 configured as input
Confidential
[1] ITRQ1_DIR: 1: ITRQ1 is configured as input [0] ITRQ0_DIR: ITRQ0 pin direction: 0: ITRQ0 configured as output
SYSTEM_CONFIG11
CMOS_MODE_LMI_POWERDWNACK_ENB
GP-LMI / LMI padlogic config control register

9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
LMIPL_BYPASS_PAD_DQS_VALID
LMI_GLUE_RETIME_LMI_TO_PLI
LMIPL_BYPASS_PDL_DQSEN
LMI_SINGLE_RANK_SELECT
LMIPL_PLL_POWERDOWN
LMIPL_DQS270_DEL_OPZ
SINGLE_RANK_SELECT
LMIPL_ENABLE_ENZI
LMIPL_PLLDIV_R[2:0]
LMIPL_PLLDIV_D[7:0]
CLK1_ENABLE
SystemConfigBaseAddress + 0x012C RW 0x00000D28 LMI padlogic config
[31:30] RESERVED [29] CMOS_MODE_LMI_POWERDWNACK_ENB 1: CMOS mode power mode is enabled 0: CMOS mode power mode is disabled
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RST_N_LMIPL
RST_N_LMI
RESERVED
RESERVED
STi7105
[28] LMIPL_DQS270_DEL_OPZ: Selects dqs270_del as 3T/4 or T/2 (1=T/2) [27] RST_N_LMI: 1: LMI sub system reset. Active Low. [26:20] RESERVED [19] LMI_GLUE_RETIME_LMI_TO_PLI: 1: Re-time is done [18] CLK1_ENABLE: 1: clk1 is enabled [17] SINGLE_RANK_SELECT: 1: Single rank is selected 0: No re-time 0: clk1 is disabled 0: Dual rank (default)
[16] LMIPL_BYPASS_PDL_DQSEN: 1: Bypasses PDL component of DQS_EN_DEL timing. [15] LMIPL_BYPASS_PAD_DQS_VALID: 1: Bypasses dummy pad component of DQS_EN_DEL timing. [14] LMI_SINGLE_RANK_SELECT: 1: Single rank is selected 0: Dual rank is selected
[13] LMIPL_ENABLE_ENZI: 1: Overrides ENZI disable when MODEZI = 0 (differential input mode). [12] LMIPL_PLL_POWERDOWN: PLL power down 0: Normal mode 1: Power down mode [11:9] LMIPL_PLLDIV_R[2:0]: Default values for PLL output clock at 666 MHz Values for PLL output clock at 800 MHz: LMIPL0_PLLDIV_R(2:0) = 100 [8:1] LMIPL_PLLDIV_D[7:0]: Default values for PLL output clock at 666 MHz Values for PLL output clock at 800 MHz: LMIPL0_PLLDIV_R[2:0] = 100 [0] RST_N_LMIPL: LMISYS_PL reset. Active low.
SYSTEM_CONFIG12
CONF_LMIPL_FUNC_CMDDQSNCKN_PD CONF_LMIPL_FUNC_CMDDQSNCKN_PU

9 LMIPL_FUNC_ZOUTPROGA_CMD 8 7 LMIPL_FUNC_ZOUTPROGA_DQDQSDM 6 5 4 LMIPL_FUNC_PROGB_DQDQSDM 3 2 1 LMIPL_FUNC_PROGA_DQDQSDM 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 CONF_LMIPL_FUNC_OTHERS_PD CONF_LMIPL_FUNC_OTHERS_PU
LMIPL_FUNC_ZOUTPROGA_CK
LMIPL_FUNC_USEPAD_VREF
LMIPL_FUNC_PROGB_CMD
LMIPL_FUNC_PROGA_CMD
LMIPL_IOREF_DDR_COMP
LMIPL_IOREF_RASRC[6:0]
LMIPL_IOREF_ACCURATE
LMIPL_FUNC_PROGB_CK
LMIPL_FUNC_PROGA_CK
LMIPL_IOREF_COMPEN
LMIPL_IOREF_COMPTQ
LMIPL_FUNC_TQ_VREF
LMIPL_IOREF_FREEZE
LMIPL_FUNC_MODEZI
LMIPL_FUNC_ODTB
LMIPL_FUNC_ODTA
Address:
SystemConfigBaseAddress + 0x0130
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LMIPL_FUNC_DDR
LMIPL_IOREF_TQ
Confidential
System config module Type: Reset: Description: RW 0xA200180F GP-LMI / LMI padlogic config
STi7105
[31] CONF_LMIPL_FUNC_OTHERS_PD (func_pdn_active_hi): Other pads than CMD, DQSN, CKN pulldown command. [30] CONF_LMIPL_FUNC_OTHERS_PU (func_pu_active_high): Other pads than CMD, DQSN, CKN pullup command. [29] CONF_LMIPL_FUNC_CMDDQSNCKN_PD (func_pdn_active_lo): CMD, DQSN, CKN pad pulldown command. [28] CONF_LMIPL_FUNC_CMDDQSNCKN_PU (func_pu_active_lo): CMD, DQSN, CKN pad pullup command. [27] LMIPL_IOREF_TQ: 1: IDDQ mode select. [26] LMIPL_IOREF_DDR_COMP: 1: Controls PSW compensation signal.
Confidential
[25] LMIPL_IOREF_ACCURATE: 1: Accurate mode select. [24] LMIPL_IOREF_FREEZE: 1: Freezes compensation code. [23] LMIPL_IOREF_COMPTQ: Operating mode. [22] LMIPL_IOREF_COMPEN: Operating mode. [21:15] LMIPL_IOREF_RASRC[6:0]: Input code. [14] LMIPL_FUNC_TQ_VREF: TQ setting for VREFIN pad control. [13] LMIPL_FUNC_USEPAD_VREF: Use PAD setting for VREFIN pad. [12] LMIPL_FUNC_ODTB: [11] LMIPL_FUNC_ODTA: ODTA / ODTB controlling On Die Termination 00: Disabled 01: RTT2 = 150 10: RTT2 = 150 11: RTT1 = 75 [10] LMIPL_FUNC_MODEZI: Receiver mode select (I/O MODEZI) 0: Differential 2.5V receiver for DDR1 or Differential 1.8V receiver for DDR2 1: 2.5V Digital CMOS receiver for DDR1 or 1.8V Digital CMOS receiver for DDR2 [9] LMIPL_FUNC_ZOUTPROGA_CMD (func_zoutproga_abc): Outputs buffer impedance (I/O ZOUTPROGA). [8] LMIPL_FUNC_ZOUTPROGA_CK (func_zoutproga_k): Outputs buffer impedance (I/O ZOUTPROGA). [7] LMIPL_FUNC_ZOUTPROGA_DQDQSDM (func_zoutproga_d): Outputs buffer impedance(I/O ZOUTPROGA). 0: 25 (Strong SSTL2) 1: 40 (Weak SSTL2) [6] LMIPL_FUNC_PROGB_CMD (func_progb_abc): PROGB for CMD pads. [5] LMIPL_FUNC_PROGB_CK (func_progb_k): PROGB for CK/CKN pads.
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[4] LMIPL_FUNC_PROGB_DQDQSDM (func_progb_d): PROGB for DQ/DQS/DQSN/DM pads. [3] LMIPL_FUNC_PROGA_CMD (func_proga_abc): PROGA for CMD pads. [2] LMIPL_FUNC_PROGA_CK (func_proga_k): PROGA for CK/CKN pads. [1] LMIPL_FUNC_PROGA_DQDQSDM (func_proga_d): PROGA for DQ/DQS/DQSN/DM pads. [0] LMIPL_FUNC_DDR: DDR mode 0: DDR1 operation mode (2.5V) 1: DDR2 operation mode (1.8V)
SYSTEM_CONFIG13
LMIPL_FORCE_DQS_VALID_MINUS_HALF LMIPL_FORCE_ODT_INT_MINUS_HALF

9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SystemConfigBaseAddress + 0x0134 RW 0x00000000 LMI padlogic config
[31:23] RESERVED [22] LMIPL_FORCE_DQS_VALID_MINUS_HALF: Utilizes negative shift of DDR 0.5 CAS latency in DDR2 mode for dqs270_valid timing. 0: Aligned 1: T/2 [21] LMIPL_FORCE_ODT_INT_MINUS_HALF: Utilizes negative shift of DDR 0.5 CAS latency in DDR2 mode for odt_int timing. 0: Aligned 1: T/2 [20:18] RESERVED [17] LMIPL0_SEL_OEN_DEL: DATA/DM output enable timing options (T/4 resolution). [16:8] LMIPL0_DLL1_USR_CMD[8:0]: Allows user control of DLL1 delay. [7:4] LMIPL0_DLL1_LOCK_CON[3:0]: Defines lock condition for DLL1. [3] LMIPL0_DLL1_INT_CMD_CON: Controls which internal delay command is used for DLL1. [2] LMIPL0_DLL1_EXT_CMD_CON: Controls which external delay command is used for DLL1. [1] LMIPL0_PDL_CLK_OPZ_DLL1: Selects CLK_COMMAND inputs for DLL1 PDLs (LOW = PDL output, HIGH = DLL output). [0] LMIPL0_DLL1_SOFT_RST: DLL1 soft reset.
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LMIPL0_DLL1_EXT_CMD_CON
LMIPL0_DLL1_LOCK_CON[3:0]
LMIPL0_DLL1_INT_CMD_CON
LMIPL0_PDL_CLK_OPZ_DLL1
LMIPL0_DLL1_USR_CMD[8:0]
Confidential
LMIPL0_DLL1_SOFT_RST
LMIPL0_SEL_OEN_DEL
RESERVED
RESERVED
STi7105 LMI padlogic config control register

9 8 7 6 LMIPL_DLL2_LOCK_CON 5 4 3 LMIPL_DLL2_INT_CMD_CON 2 LMIPL_DLL2_EXT_CMD_CON 1 LMIPL_PDL_CLK_OPZ_DLL2 0 LMIPL_DLL2_SOFT_RST
SYSTEM_CONFIG14
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 LMIPL_DLL2_USR_CMD
RESERVED
SystemConfigBaseAddress + 0x0138 RW 0x0000 LMI Padlogic config
[31:17] RESERVED
[16:8] LMIPL_DLL2_USR_CMD: Allows user control of DLL2 delay. [7:4] LMIPL_DLL2_LOCK_CON: Defines lock condition for DLL2. [3] LMIPL_DLL2_INT_CMD_CON: Controls which internal delay command is used for DLL2. [2] LMIPL_DLL2_EXT_CMD_CON: Controls which external delay command is used for DLL2. [1] LMIPL_PDL_CLK_OPZ_DLL2: Selects CLK_COMMAND inputs for DLL2 PDLs (LOW = PDL output, HIGH = DLL output). [0] LMIPL_DLL2_SOFT_RST: DLL2 soft reset. 1: DLL2 soft reset is active 0: DLL2 soft reset is inactive
SYSTEM_CONFIG15
FDMA_REQ3_ENABLE FDMA_REQ2_ENABLE FDMA_REQ1_ENABLE FDMA_REQ0_ENABLE
FDMA and key scan config register

9 8 7 6 5 4 3 KEY_SCANIN3_ENABLE 2 KEY_SCANIN2_ENABLE 1 KEY_SCANIN1_ENABLE 0 KEY_SCANIN0_ENABLE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SystemConfigBaseAddress + 0x013C RW 0x000000 FDMA and key scan config

[31] FDMA_REQ3: Internal FDMA req 3 ORed with external FDMA req 3 [30] FDMA_REQ2: Internal FDMA req 2 ORed with external FDMA req 2
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Confidential
FDMA_REQ3
FDMA_REQ2
FDMA_REQ1
FDMA_REQ0
RESERVED
STi7105
[29] FDMA_REQ1: Internal FDMA req 1ORed with external FDMA req 1 [28] FDMA_REQ0: Internal FDMA req 0 ORed with external FDMA req 0 [27] FDMA_REQ3_ENABLE: External FDMA req 3 enable [26] FDMA_REQ2_ENABLE: External FDMA req 2 enable [25] FDMA_REQ1_ENABLE: External FDMA req 1 enable [24] FDMA_REQ0_ENABLE: External FDMA req 0 enable [23: 4] RESERVED [3] KEY_SCANIN3_ENABLE: 1: Indicates key_scanin3 enabled [2] KEY_SCANIN2_ENABLE: 1: Indicates key_scanin2 enabled [1] KEY_SCANIN1_ENABLE: 1: Indicates key_scanin1 enabled [0] KEY_SCANIN0_ENABLE: 1: Indicates key_scanin0 enabled 0: Indicates key_scanin3 disabled 0: Indicates key_scanin2 disabled 0: Indicates key_scanin1 disabled 0: Indicates key_scanin0 disabled
SYSTEM_CONFIG16
Comms SSC configuration register

9 SSC2_MTSR_IN_SEL[1:0] 8 SSC2_MRST_IN_SEL[1:0] 7 6 5 4 3 SSC1_MRST_IN_SEL 2 1 0 SSC0_MRST_IN_SEL SSC3_MRST_IN_SEL[1:0] SSC3_MTSR_IN_SEL[1:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 SSC2_SCLK_IN[1:0]
SystemConfigBaseAddress + 0x0140 RW 0x000000 Comms SSC config
[31:20] RESERVED [19:18] SSC3_SCLK_IN: 00: Invalid 10: ssc3_sclk_in from PIO13[2] [17:16] SSC3_MTSR_IN_SEL[1:0]: 00: ssc3_mtsr_in from PIO2[1] 10: ssc3_mtsr_in from PIO13[3] [15:14] SSC3_MRST_IN_SEL[1:0]: 00: ssc3_mrst_in from PIO2[1] 10: ssc3_mrst_in from PIO13[3] [13] RESERVED 01: ssc3_sclk_in from PIO3[6] 11: ssc3_sclk_in from PIO13(6) 01: ssc3_mtsr_in from PIO3[7] 11: ssc3_mtsr_in from PIO13[7] 01: ssc3_mrst_in from PIO3(7) 11: ssc3_mrst_in from PIO13(7)
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Confidential
SSC3_SCLK_IN
RESERVED
RESERVED
RESERVED
RESERVED
STi7105
[12:11] SSC2_SCLK_IN[1:0]: 0x: ssc2_sclk_in from PIO3[4] 11: ssc2_sclk_in from PIO13[4] [10:9] SSC2_MTSR_IN_SEL[1:0]: 00: ssc2_mtsr_in from PIO2[0] 10: ssc2_mtsr_in from PIO12[1] [8:7] SSC2_MRST_IN_SEL[1:0]: 00: ssc2_mrst_in from PIO2[0] 10: ssc2_mrst_in from PIO12[1] [6:4] RESERVED [3] SSC1_MRST_IN_SEL: 1: ssc1_mrst_in is from PIO2[7] [2:1] RESERVED [0] SSC0_MRST_IN_SEL: 1: ssc0_mrst_in is from PIO2[4]
10: ssc2_sclk_in from PIO12[0]
01: ssc2_mtsr_in from PIO3[5] 11: ssc2_mtsr_in from PIO13[5] 01: ssc2_mrst_in from PIO3[5] 11: ssc2_mrst_in from PIO13[5]
0: ssc1_mrst_in is from PIO2[6]
0: ssc0_mrst_in is from PIO2[3]
Confidential
SYSTEM_CONFIG17
CPXM CPRM enable configuration register

9 8 7 6 5 4 3 2 1 CPXM_ENCRYPT_DISABLE 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SystemConfigBaseAddress + 0x0144 RW 0x00000002 CPXM CPRM encode enable config
[31:2] RESERVED [1] CPXM_ENCRYPT_DISABLE: 1: CPXM_ENCRYPT is disabled [0] RESERVED 0: Enabled only if CPXM feature is enabled
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RESERVED
RESERVED
STi7105
System config module PAD State control register

9 8 7 6 5 4 3 2 1 PULL_UP_ENABLE 0 SLEEP_MODE_ON
SYSTEM_CONFIG18
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED
SystemConfigBaseAddress + 0x0148 RW 0x0000 Pad state config Information classified Confidential - Do not copy (See last page for obligations)
[31:2] RESERVED [1] PULL_UP_ENABLE: 1: Indicates pad pullup is active 0: Indicates pull up is de-active 0: Indicates switched off
Confidential
[0] SLEEP_MODE_ON: 1: Indicates sleep mode control switched on
SYSTEM_CONFIG19
RESERVED
Alternate function output control for PIO 0

9 8 7 6 5 4 3 2 1 0 PIO0_ALTFOP1_MUX_SEL_BUS PIO0_ALTFOP0_MUX_SEL_BUS
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SystemConfigBaseAddress + 0x014C RW 0x0000 PIO0 alternate function output config
[31:16] RESERVED [15:8] PIO0_ALTFOP1_MUX_SEL_BUS [7:0] PIO0_ALTFOP0_MUX_SEL_BUS
Note: Alternate 1: PIO0_ALTFOPJ_MUX_SEL_BUS(n) = 00 [( j = 0,1); (n = 0,1,2,3,4,5,6,7)] Alternate 2: PIO0_ALTFOPJ_MUX_SEL_BUS(n) = 01 [( j = 0,1); (n = 0,1,2,3,4,5,6,7)] Alternate 3: PIO0_ALTFOPJ_MUX_SEL_BUS(n) = 10 [( j = 0,1); (n = 0,1,2,3,4,5,6,7)] Alternate 4: PIO0_ALTFOPJ_MUX_SEL_BUS(n) = 11 [( j = 0,1); (n = 0,1,2,3,4,5,6,7)]
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STi7105 Alternate function output control for PIO 1

SYSTEM_CONFIG20
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SystemConfigBaseAddress + 0x0150 RW 0x00000000 Alternate Function PIO1 Output Control Information classified Confidential - Do not copy (See last page for obligations)
Note: Alternate 1: PIO1_ALTFOPj_MUX_SEL_BUS(n) = 00 [( j = 0,1); (n = 0,1,2,3,4,5,6,7)] Alternate 2: PIO1_ALTFOPj_MUX_SEL_BUS(n) = 01 [( j = 0,1); (n = 0,1,2,3,4,5,6,7)]
Confidential
Alternate 3: PIO1_ALTFOPj_MUX_SEL_BUS(n) = 10 [( j = 0,1); (n = 0,1,2,3,4,5,6,7)] Alternate 4: PIO1_ALTFOPj_MUX_SEL_BUS(n) = 11 [( j = 0,1); (n = 0)]
SYSTEM_CONFIG21
RESERVED

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SystemConfigBaseAddress + 0x0154 RW 0x00000000 PIO2 alternate function output config
Note: Alternate 1: PIO2_ALTFOPj_MUX_SEL_BUS(n) = 00 [( j = 0,1); (n = 0,1,2,3,4,5,6,7)] Alternate 2: PIO2_ALTFOPj_MUX_SEL_BUS(n) = 01 [( j = 0,1); (n = 0,1,2,3,4,5,6,7)] Alternate 3: PIO2_ALTFOPj_MUX_SEL_BUS(n) = 10 [( j = 0,1); (n = 0,1,2,3,4,5,6,7)] Alternate 4: PIO2_ALTFOPj_MUX_SEL_BUS(n) = 11 [( j = 0,1); (n = 0,1,2,3,4,5,6,7)]
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STi7105
System config module Compensation config register

9 8 7 6 CONF_3V3COMP0_RASRC 5 4 3 2 CONF_3V3COMP0_FREEZE 1 CONF_3V3COMP0_COMPTQ 0 CONF_3V3COMP0_COMPEN CONF_3V3COMP2_COMPTQ CONF_3V3COMP1_COMPTQ CONF_3V3COMP2_COMPEN CONF_3V3COMP1_COMPEN CONF_3V3COMP2_FREEZE CONF_3V3COMP1_FREEZE
SYSTEM_CONFIG22
CONF_3V3COMP2_RASRC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 CONF_3V3COMP1_RASRC
RESERVED
SystemConfigBaseAddress + 0x0158 RW 0x00000000 Compensation config
[31:30] RESERVED
Confidential
[29:23] CONF_3V3COMP2_RASRC: 3V3 COMPENSATION 2: Input code [22] CONF_3V3COMP2_FREEZE: 3V3 COMPENSATION 2: Freezes ASRC code to its last value [21] CONF_3V3COMP2_COMPTQ: [20] CONF_3V3COMP2_COMPEN: 3V3 COMPENSATION 2: Operating mode (comptq/compen) 00: Normal mode 01: HZ mode 11: Read mode [19:13] CONF_3V3COMP1_RASRC: 3V3 COMPENSATION 1: Input code [12] CONF_3V3COMP1_FREEZE: 3V3 COMPENSATION 1: Freezes ASRC code to its last value [11] CONF_3V3COMP1_COMPTQ: [10] CONF_3V3COMP1_COMPEN: 3V3 COMPENSATION 1: Operating mode (comptq/compen) 00: Normal mode 01: HZ mode 11: Read mode [9:3] CONF_3V3COMP0_RASRC: 3V3 COMPENSATION 0: Input code [2] CONF_3V3COMP0_FREEZE: 3V3 COMPENSATION 0: Freezes ASRC code to its last value [1] CONF_3V3COMP0_COMPTQ: [0] CONF_3V3COMP0_COMPEN: 3V3 COMPENSATION 0: Operating mode (comptq/compen) 00: Normal mode 01: HZ mode 11: Read mode
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STi7105 Compensation config register

9 8 7 6 CONF_3V3COMP3_RASRC 5 4 3 2 CONF_3V3COMP3_FREEZE 1 CONF_3V3COMP3_COMPTQ 0 CONF_3V3COMP3_COMPEN CONF_3V3COMP4_COMPTQ CONF_3V3COMP4_COMPEN CONF_3V3COMP4_FREEZE
SYSTEM_CONFIG23
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 CONF_3V3COMP4_RASRC CONF4_3V3COMP_TQ CONF3_3V3COMP_TQ
RESERVED
SystemConfigBaseAddress + 0x015C RW 0x00000000 Compensation config
[31:25] RESERVED
Confidential
[24] CONF4_3V3COMP_TQ: Drives the 4 compensations TQ pin 1 to put the cells in IDDQ mode [23] CONF_3V3COMP4_FREEZE: 3V3 COMPENSATION 4: Freezes ASRC code to its last value [22] CONF_3V3COMP4_COMPTQ: [21:20] CONF_3V3COMP4_COMPEN: 3V3 COMPENSATION 4: Operating mode (comptq/compen) 00: Normal mode 01: HZ mode 11: Read mode [19:11] CONF_3V3COMP4_RASRC: 3V3 COMPENSATION 4: Input code [10] CONF3_3V3COMP_TQ: Drives the 4 compensations TQ pin 1: Puts the cells in IDDQ mode [9:3] CONF_3V3COMP3_RASRC: 3V3 COMPENSATION 3: Input code [2] CONF_3V3COMP3_FREEZE: 3V3 COMPENSATION 3: Freeze ASRC code to its last value [1] CONF_3V3COMP3_COMPTQ: [0] CONF_3V3COMP3_COMPEN: 3V3 COMPENSATION 3: Operating mode (comptq/compen) 00: Normal mode 01: HZ mode 11: Read mode
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STi7105
System config module OSC config register

9 8 7 6 5 CLKGENA_OBSCLK_ENABLE 4 SYSCLKOUT_ENABLE 3 2 1 0
SYSTEM_CONFIG24
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
OSCI_BYPASS
RESERVED
RESERVED
RESERVED
SystemConfigBaseAddress + 0x0160 RW 0x0000000C Oscillator config
[31:6] RESERVED
[5] CLKGENA_OBSCLK_ENABLE: 1: ClockGenA clk output is enabled [4] SYSCLKOUT_ENABLE: 1: ClockGenB clk output is enabled [3] RESERVED [2] OSCI_BYPASS: 1: OSC is not bypassed [1:0] RESERVED
0: Disabled 0: Disabled
0: OSC is bypassed
SYSTEM_CONFIG25
RESERVED

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SystemConfigBaseAddress + 0x0164 RW 0x0000 PIO3 alternate function output register
Note:
Alternate 1: PIO3_ALTFOPj_MUX_SEL_BUS(n) = 00 [( j = 0,1); (n = 0,1,2,3,4,5,6,7)] Alternate 2: PIO3_ALTFOPj_MUX_SEL_BUS(n) = 01 [( j = 0,1); (n = 0,1,2,3,4,5,6,7)] Alternate 3: PIO3_ALTFOPj_MUX_SEL_BUS(n) = 10 [( j = 0,1); (n = 0,1,2,3,4,5,6,7)] Alternate 4: PIO3_ALTFOPj_MUX_SEL_BUS(n) = 11 [( j = 0,1); (n = 0,1,2,3,4,5,6,7)]
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Confidential
STi7105 LX audio config register

9 8 7 6 5 4 3 2 1 LX_AUD_GNT_FILTER_DISABLE 0
SYSTEM_CONFIG26
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 LX_AUD_BOOT_ADDR[29:6]
LX_AUD_ALLOW_BOOT
RESERVED
SystemConfigBaseAddress + 0x0168 RW 0xXXXX(1) LX Audio config
Confidential
[31:8] LX_AUD_BOOT_ADDR[29:6]: ST230 AUDIO boot address. [7:2] RESERVED [1] LX_AUD_GNT_FILTER_DISABLE: 1: Filter is disabled [0] LX_AUD_ALLOW_BOOT: ST230 AUDIO request filter. 1: Request enabled 0: Request bypassed
SYSTEM_CONFIG27
LX audio config register

9 8 7 LX_AUD_PERIPH_ADDR 6 5 4 3 2 1 0 LX_AUD_RST_N_CTRL
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SystemConfigBaseAddress + 0x016C RW 0x1FD0 LX Audio config
[31:13] RESERVED [12:1] LX_AUD_PERIPH_ADDR: ST230 AUDIO peripheral address.
1. Depends on mode pins; Reset value is 1, when MODE[9:8]=10 AND LX_AUDIO_BOOT_ENABLE=1, and reset value is 0, For other values of MODE[9:8] and LX_AUDIO_BOOT_ENABLE
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RESERVED
STi7105
[0] LX_AUD_RST_N_CTRL: ST230 AUDIO reset active low control bit. 0: Reset of ST230 driven by hardware reset 1: Reset of ST230 fixed to active state
SYSTEM_CONFIG28
LX Delta Rasta config register

9 8 7 6 5 4 3 2 1 0 LX_DH_ALLOW_BOOT LX_DH_BOOT_ADDR[29:6]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
SystemConfigBaseAddress + 0x0170 RW 0xXXXX(1) LX Delta Rasta config
[31:8] LX_DH_BOOT_ADDR[29:6]: ST230 DELPHI boot address. [7:1] RESERVED [0] LX_DH_ALLOW_BOOT: ST230 DELPHI request filter: 1: Request enabled
0: Request bypassed
SYSTEM_CONFIG29
LX Delta Rasta config register

9 8 7 LX_DH_PERIPH_ADDR 6 5 4 3 2 1 0 LX_DH_RST_N_CTRL
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SystemConfigBaseAddress + 0x0174 RW 0x1FCC LX Delta Rasta config
[31:13] RESERVED
1. Depends on Mode pins. Reset value is: 1: When MODE[9:8]=01 AND LX_DELTA_BOOT_ENABLE=1 0: For other values of MODE[9:8] and LX_DELTA_BOOT_ENABLE
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Confidential
RESERVED
STi7105
[12:1] LX_DH_PERIPH_ADDR: ST230 DELPHI peripheral address. [0] LX_DH_RST_N_CTRL: ST230 DELPHI reset active low control bit. 0: Reset of ST230 driven by hardware reset 1: Reset of ST230 fixed to active state
SYSTEM_CONFIG30
Reserved
9 8 7 6 5 4 3 2 1 0 RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SystemConfigBaseAddress + 0x0178 Information classified Confidential - Do not copy (See last page for obligations) RW 0x0000 Reserved
[31:0] RESERVED
SYSTEM_CONFIG31
EMI config register

9 8 7 6 5 4 3 2 DMA_SRC_ID[3:0] 1 0
Confidential
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 EMI_PAD_MODE RESERVED RESERVED
SystemConfigBaseAddress + 0x017C RW 0x0000 EMI config
[31:21] RESERVED [20] EMI_PAD_MODE: 0: TTL bi-directional mode (EMI) [19:4] RESERVED [3:0] DMA_SRC_ID[3:0]: DMA source ID. 1: PCI mode
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STi7105
System config module Power down config register

9 SATA_PHY_POWER_DOWN_REQ 8 7 USB2_PHY_POWER_DOWN_REQ 6 USB1_PHY_POWER_DOWN_REQ 5 USB2_HC_POWER_DOWN_REQ 4 USB1_HC_POWER_DOWN_REQ 3 KEY_SCAN_POWER_DOWN_REQ 2 1 0
SYSTEM_CONFIG32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 SATA_HC_POWER_DOWN_REQ
EMI_POWER_DOWN_REQ
PCI_POWER_DOWN_REQ
RESERVED
RESERVED
RESERVED
RESERVED

fig
SystemConfigBaseAddress + 0x0180 RW 0x0B35 Power down config
Confidential
[31:12] RESERVED [11] SATA_HC_POWER_DOWN_REQ: 1: SATA host power down [10] RESERVED [9] SATA_PHY_POWER_DOWN_REQ: 1: Power down request for SATA PHY module [8] RESERVED [7] USB2_PHY_POWER_DOWN_REQ: 1: USB2 phy is in power down [6] USB1_PHY_POWER_DOWN_REQ: 1: USB1 phy is in power down [5] USB2_HC_POWER_DOWN_REQ: 1: Power down request for USB2 HC module [4] USB1_HC_POWER_DOWN_REQ: 1: Power down request for USB1 HC module [3] KEY_SCAN_POWER_DOWN_REQ: 1: Power down request for Key scanner module [2] PCI_POWER_DOWN_REQ: 1: Power down request for PCI module is active [1] EMI_POWER_DOWN_REQ: 1: Power down request for EMI module is active [0] RESERVED 0: USB2 phy is power up 0: USB1 phy is power up 0: SATA host power up
Note:
1 2
Due to the reset value of bit 0, 2 ,4,5,9, and 11 the PCI and USB PHYs and SATA HC+PHY are switched off by default. USB PHYs power down are active low.
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STi7105 SOFT_JTAG register (USB ) config register

9 8 7 6 SOFT_JTAG_EN 5 4 3 2 1 0
SYSTEM_CONFIG33
EXTERNAL_DAA_SEL
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
TRSTN_SATA
TRSTN_USB
RESERVED
TMS_SATA
TMS_USB
SystemConfigBaseAddress + 0x0184 Information classified Confidential - Do not copy (See last page for obligations) RW 0x00000000 SOFT_JTAG register (USB ) config
[31] EXTERNAL_DAA_SEL [30:7] RESERVED
Confidential
[6] SOFT_JTAG_EN: High level means that USB2.0 or SATA TAP is managed by SOFT_JTAG register; Low level means JTAG is through PAD. [5] TMS_SATA: TEST mode select for SATA TAP only [4] TRSTN_SATA: Asynchronous reset for SATA TAP only. [3] TMS_USB: Test mode select USB2.0 TAP only. [2] TRSTN_USB: Asynchronous reset USB2.0 TAP only. [1] TDI: Test data input for the USB2.0 TAP or SATA TAP. [0] TCK: Test clock for the USB2.0 TAP or SATA TAP.
SYSTEM_CONFIG34
RESERVED
Alternate function PIO output control for PIO 4

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Note:
Alternate 1 : PIO4_ALTFOPj_MUX_SEL_BUS(n) = 00 [( j = 0,1); (n = 0,1,2,3,4,5,6,7)] Alternate 2 : PIO4_ALTFOPj_MUX_SEL_BUS(n) = 01 [( j = 0,1); (n = 0,1,2,3,4,5,6,7)] Alternate 3 : PIO4_ALTFOPj_MUX_SEL_BUS(n) = 10 [( j = 0,1); (n = 0,1,2,3,4,5,6,7)] Alternate 4 : PIO4_ALTFOPj_MUX_SEL_BUS(n) = 11 [( j = 0,1); (n = 0,1,2,3,4,5,6,7)]
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TCK
TDI
STi7105
System config module Alternate function PIO output control for PIO 5
SYSTEM_CONFIG35
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SystemConfigBaseAddress + 0x018C RW 0x0000 PIO5 alternate function output config Information classified Confidential - Do not copy (See last page for obligations)
Alternate 1 : PIO5_ALTFOPj_MUX_SEL_BUS(n) = 00 [( j = 0,1); (n = 0,1,2,3,4,5,6,7)] Alternate 2 : PIO5_ALTFOPj_MUX_SEL_BUS(n) = 01 [( j = 0,1); (n = 0,1,2,3,4,5,6,7)] Alternate 3 : PIO5_ALTFOPj_MUX_SEL_BUS(n) = 10 [( j = 0,1); (n = 0,1,2,3,4,5,6,7)]
Confidential
Alternate 4 : PIO5_ALTFOPj_MUX_SEL_BUS(n) = 11 [( j = 0,1); (n = 0,1,2,3,4,5,6,7)]
SYSTEM_CONFIG36
RESERVED
Alternate Function PIO Output Control for PIO 6

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Note: Alternate 1 : PIO6_ALTFOPj_MUX_SEL_BUS(n) = 00 [( j = 0,1); (n = 0,1,2,3,4,5,6,7)] Alternate 2 : PIO6_ALTFOPj_MUX_SEL_BUS(n) = 01 [( j = 0,1); (n = 0,1,2,3,4,5,6,7)] Alternate 3 : PIO6_ALTFOPj_MUX_SEL_BUS(n) = 10 [( j = 0,1); (n = 0,1,2,3,4,5,6,7)] Alternate 4 : PIO6_ALTFOPj_MUX_SEL_BUS(n) = 11 [( j = 0,1); (n = 0,1,2,3,4,5,6,7)]
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STi7105 Alternate function PIO output control for PIO 7

SYSTEM_CONFIG37
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SystemConfigBaseAddress + 0x0194 RW 0x00000000 PIO7 alternate function output config Information classified Confidential - Do not copy (See last page for obligations)
Alternate 1 : PIO7_ALTFOPj_MUX_SEL_BUS(n) = 00 [( j = 0,1); (n = 0,1,2,3,4,5,6,7)] Alternate 2 : PIO7_ALTFOPj_MUX_SEL_BUS(n) = 01 [( j = 0,1); (n = 0,1,2,3,4,5,6,7)] Alternate 3 : PIO7_ALTFOPj_MUX_SEL_BUS(n) = 10 [( j = 0,1); (n = 0,1,2,3,4,5,6,7)]
Confidential
Alternate 4 : PIO7_ALTFOPj_MUX_SEL_BUS(n) = 11 [( j = 0,1); (n = 0,1,2,3,4,5,6,7)]
SYSTEM_CONFIG38
CONF_LMI_SEL_SYNC_FLOP_NB[1:0] CONF_LMI_SEL_SYNC_FLOP_HALF
LMI / LMI padlogic config register

9 8 7 6 5 4 CONF_LMI_MEM_BASE_ADDR[7:0] 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CONF_LMI_SEL_CLK_PHASE
CONF_LMI_HP_EN_AP[1:0]
CONF_LMI_LP_EN_AP[1:0]
CONF_LMI_PWRD_REQ
RESERVED
SystemConfigBaseAddress + 0x0198 RW 0x0000000C LMI / LMI padlogic config
[31:25] RESERVED [24:23] CONF_LMI_SEL_SYNC_FLOP_NB[1:0]: Selection of the number of flops used in the synchronizer to prevent metastability. 00: two flops are used 01: three flops are used 10 : four flops are used 11: one flop is used; For test/characterization only
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RESERVED
STi7105
[22] CONF_LMI_SEL_SYNC_FLOP_HALF: Selection of the clk_m clock or clk_m180 used for the first resync. flop used to prevent metastability : 0: both rising and falling edges of clk_m are used 1: only rising edge of clk_m is used [21] CONF_LMI_SEL_CLK_PHASE: Selection of the clock edges used in FIFO control: 0: both rising and falling edges of clk_m are used 1: only rising edges of clk_m is used [20] CONF_LMI_PWRD_REQ: LMI power down request. [19:18] CONF_LMI_HP_EN_AP[1:0]: Enables read with autoprecharge on lmi0 high priority port.
[15:8] RESERVED [7:0] CONF_LMI_MEM_BASE_ADDR[7:0]: LMI memory base address. 29-bit LMI base address : 0x0C 32-bit LMI base address : 0x40
SYSTEM_CONFIG39
Reserved
9 8 7 6 5 4 3 2 1 0 RESERVED
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SystemConfigBaseAddress + 0x019C RW 0x0000 Reserved
[31:0] RESERVED
SYSTEM_CONFIG40
Clock select config register

9 8 7 6 5 4 3 2 USB_PHY_CLOCK_SELECT 1 0 LMI_PLL_CLOCK_SELECT
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SystemConfigBaseAddress + 0x01A0 RW 0x00000004 Clock select config
[31:3] RESERVED
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[17:16] CONF_LMI_LP_EN_AP[1:0]: Enables read with autoprecharge on lmi0 low priority port.
RESERVED
RESERVED
STi7105
[2] USB_PHY_CLOCK_SELECT: Select clock for USB PHY. 0: Clock from SATA OSC 1: Clock from alternate pad [1] RESERVED [0] LMI_PLL_CLOCK_SELECT: Select clock for LMI Pll imput. 0: Clock from alternate pad 1: Clock from SATA OSC
SYSTEM_CONFIG41
RESERVED
Thermal sensor config register

9 8 7 DCORRECT 6 5 4 PDN 3 CMDTCO 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
OBS
SystemConfigBaseAddress + 0x01A4 RW 0x00000008 Thermal sensor config
[31:10] RESERVED [9:5] DCORRECT: Digital code to correct systematic offset by addition to the digital output. [4] PDN: Power Down 0: Power down mode 1: Normal mode; asynchronous
[3:2] CMDTCO: Reserved to debug. To be fixed to 10 in application. [1:0] OBS: Reserved to debug. To be fixed to 00 in application.
SYSTEM_CONFIG42
LMIPL_SEL_DQS_VALID_DEL[3:0]
LMI / LMI padlogic config register

9 8 7 6 5 4 LMIPL_DSQ0_OFFSET[8:0] 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 LMIPL_DSQ2_OFFSET[8:0] LMIPL_DSQ1_OFFSET[8:0]
SystemConfigBaseAddress + 0x01A8 RW 0x0000 LMI padlogic config register
[31] RESERVED
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RESERVED
STi7105
[30:27] LMIPL_SEL_DQS_VALID_DEL[3:0]: dqs_valid timing options (T/4 resolution). [26:18] LMIPL_DSQ2_OFFSET[8:0]: Offset command for DQS[2] PDL. [17:9] LMIPL_DSQ1_OFFSET[8:0]: Offset command for DQS[1] PDL. [8:0] LMIPL_DSQ0_OFFSET[8:0]: Offset command for DQS[0] PDL.
SYSTEM_CONFIG43
LMIPL_DQS_VALID_OFFSET[8:0] LMIPL_SEL_ODT_INT_DEL[3:0]
LMI / LMI Padlogic config register

9 8 7 6 5 4 LMIPL_DSQ3_OFFSET[8:0] 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 LMIPL_DISABLE_ODTINT
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SystemConfigBaseAddress + 0x01AC RW 0x0000 LMI / LMI Padlogic config
[31] LMIPL_DISABLE_ODTINT: Disables Internal ODT function (as in DDR1 mode). [30:27] LMIPL_SEL_ODT_INT_DEL[3:0]: Internal odt timing options (T/4 resolution). [26:18] LMIPL_DQS_VALID_OFFSET[8:0]: Offset command for dqs_en_del PDL. [17:9] RESERVED [8:0] LMIPL_DSQ3_OFFSET[8:0]: Offset command for DQS[3] PDL.
SYSTEM_CONFIG44
ClockgenD Jitter estimator

9 8 7 6 5 4 3 2 1 0 TST_SEL_JITTER_PATTERN
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 TST_PLL_BIST_RUN
RESERVED
SystemConfigBaseAddress + 0x01B0 RW 0x00000000 ClockGen D Jitter estimator config
TST_PLL
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RESERVED
STi7105
[31:26] RESERVED [25] TST_PLL [24] TST_PLL_BIST_RUN [23:0] TST_SEL_JITTER_PATTERN
SYSTEM_CONFIG45
Reserved
9 8 7 6 5 4 3 2 1 0 RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RW 0x00000000 Reserved
[31:0] RESERVED
SYSTEM_CONFIG46
RESERVED

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SystemConfigBaseAddress + 0x01B8 RW 0x0000 PIO8 alternate function output config
Note: Alternate 1 : PIO8_ALTFOPj_MUX_SEL_BUS(n) = 00 [( j = 0,1); (n = 0,1,2,3,4,5,6,7)] Alternate 2 : PIO8_ALTFOPj_MUX_SEL_BUS(n) = 01 [( j = 0,1); (n = 0,1,2,3,4,5,6,7)] Alternate 3 : PIO8_ALTFOPj_MUX_SEL_BUS(n) = 1x [( j = 0,1); (n = 0,1,2,3,4,5,6,7)]
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Address:
SystemConfigBaseAddress + 0x01B4
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STi7105
System config module Alternate function PIO output control for PIO 9
SYSTEM_CONFIG47
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SystemConfigBaseAddress + 0x01BC RW 0x0000 PIO9 alternate function output config Information classified Confidential - Do not copy (See last page for obligations)
Note: Alternate 1 : PIO9_ALTFOPj_MUX_SEL_BUS(n) = 00 [( j = 0,1); (n = 0,1,2,3,4,5,6,7)] Alternate 2 : PIO9_ALTFOPj_MUX_SEL_BUS(n) = 01 [( j = 0,1); (n = 0,1,2,3,4,5,6,7)]
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Alternate 3 : PIO9_ALTFOPj_MUX_SEL_BUS(n) = 1x [( j = 0,1); (n = 0,1,2,3,4,5,6,7)]
SYSTEM_CONFIG48
RESERVED

9 8 7 6 5 4 3 2 1 0 PIO12_ALTFOP2_MUX_SEL_BUS PIO12_ALTFOP1_MUX_SEL_BUS PIO12_ALTFOP0_MUX_SEL_BUS
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SystemConfigBaseAddress + 0x01C0 RW 0x0000 PIO12 alternate function output config
[31: 24] RESERVED [23 : 16] PIO12_ALTFOP2_MUX_SEL_BUS [15 : 8] PIO12_ALTFOP1_MUX_SEL_BUS [7 : 0] PIO12_ALTFOP0_MUX_SEL_BUS
Note: Alternate 1 : PIO12_ALTFOPj_MUX_SEL_BUS(n) = 000 [( j = 0,1,2); (n = 0,1,2,3,4,5,6,7)] Alternate 2 : PIO12_ALTFOPj_MUX_SEL_BUS(n) = 001 [( j = 0,1,2); (n = 0,1,2,3,4,5,6,7)] Alternate 3 : PIO12_ALTFOPj_MUX_SEL_BUS(n) = 010 [( j = 0,1,2); (n = 0,1,2,3,4,5,6,7)] Alternate 4 : PIO12_ALTFOPj_MUX_SEL_BUS(n) = 011 [( j = 0,1,2); (n = 0,1,2,3,4,5,6,7)] Alternate 5 : PIO12_ALTFOPj_MUX_SEL_BUS(n) = 1xx [( j = 0,1,2); (n = 0,1,2,3,4,5,6,7)]
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STi7105 Alternate function PIO output control for PIO 13

9 8 7 6 5 4 3 2 1 0 PIO13_ALTFOP2_MUX_SEL_BUS PIO13_ALTFOP1_MUX_SEL_BUS PIO13_ALTFOP0_MUX_SEL_BUS
SYSTEM_CONFIG49
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SystemConfigBaseAddress + 0x01C4 RW 0x0000 PIO13 alternate function output config Information classified Confidential - Do not copy (See last page for obligations)
[31: 24] RESERVED [23 : 16] PIO13_ALTFOP2_MUX_SEL_BUS [15 : 8] PIO13_ALTFOP1_MUX_SEL_BUS [7 : 0] PIO13_ALTFOP0_MUX_SEL_BUS
Note: Alternate 1 : PIO13_ALTFOPj_MUX_SEL_BUS(n) = 000 [( j = 0,1,2); (n = 0,1,2,3,4,5,6,7)]
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Alternate 2 : PIO13_ALTFOPj_MUX_SEL_BUS(n) = 001 [( j = 0,1,2); (n = 0,1,2,3,4,5,6,7)] Alternate 3 : PIO13_ALTFOPj_MUX_SEL_BUS(n) = 010 [( j = 0,1,2); (n = 0,1,2,3,4,5,6,7)] Alternate 4 : PIO13_ALTFOPj_MUX_SEL_BUS(n) = 011 [( j = 0,1,2); (n = 0,1,2,3,4,5,6,7)] Alternate 5 : PIO13_ALTFOPj_MUX_SEL_BUS(n) = 1xx [( j = 0,1,2); (n = 0,1,2,3,4,5,6,7)]
SYSTEM_CONFIG50

9 8 7 6 5 4 PIO15_ALTFOP0_MUX_SEL_BUS 3 2 1 0 PIO15_ALTFOP1_MUX_SEL_BUS
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SystemConfigBaseAddress + 0x01C8 RW 0x00000400 PIO15 alternate function output config
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RESERVED
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STi7105 Note:
Alternate 1 : PIO15_ALTFOPj_MUX_SEL_BUS(n) = 00 [( j = 0,1); (n = 0,1,2,3,4,5,6,7)] Alternate 2 : PIO15_ALTFOPj_MUX_SEL_BUS(n) = 01 [( j = 0,1); (n = 0,1,2,3,4,5,6,7)] Alternate 3 : PIO15_ALTFOPj_MUX_SEL_BUS(n) = 1x [( j = 0,1); (n = 0,1,2,3,4,5,6,7)] Note: PIO10, PIO11 and PIO14 do not require any alternate function output muxing as they are dedicated. LMI / LMI Padlogic config register
9 8 7 6 5 4 LCONF_MIPL0_DQS270_DEL0_OFFSET[8:0] 3 2 1 0 LCONF_MIPL0_DQS270_DEL1_OFFSET[8:0]
SYSTEM_CONFIG51
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SystemConfigBaseAddress + 0x01CC RW 0x0000 LMI / LMI Padlogic config
[31:25] RESERVED [24:16] LCONF_MIPL0_DQS270_DEL1_OFFSET[8:0]: Offset command for dqs270_del1 PDL. [15:9] RESERVED [8:0] LCONF_MIPL0_DQS270_DEL0_OFFSET[8:0]: Offset command for dqs270_del0 PDL.
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RESERVED
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RESERVED
STi7105 LMI / LMI Padlogic config register

9 8 7 6 5 4 LCONF_MIPL0_DQS270_DEL2_OFFSET[8:0] 3 2 1 0 LCONF_MIPL0_DQS270_DEL3_OFFSET[8:0]
SYSTEM_CONFIG52
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
RESERVED
Address: Type: Reset:
SystemConfigBaseAddress + 0x01D0 RW 0x0000 LMI / LMI Padlogic config
Description:
[31:25] RESERVED [24:16] LCONF_MIPL0_DQS270_DEL3_OFFSET[8:0]: Offset command for dqs270_del1 PDL. [15:9] RESERVED [8:0] LCONF_MIPL0_DQS270_DEL2_OFFSET[8:0]: Offset command for dqs270_del0 PDL.
SYSTEM_CONFIG53
Reserved
9 8 7 6 5 4 3 2 1 0 RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SystemConfigBaseAddress + 0x01D4 RW 0x00000000 Reserved
[31:0] RESERVED
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System config module Reserved

9 8 7 6 5 4 3 2 1 0 RESERVED
SYSTEM_CONFIG54
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SystemConfigBaseAddress + 0x01D8 RW 0x00000000 Reserved Information classified Confidential - Do not copy (See last page for obligations)
[31:0] RESERVED
SYSTEM_CONFIG55
LMIPL_USERMODE_PDL_DQS270_DEL LMIPL_USER_COMMAND_DQS_VALID LMIPL_USERMODE_PDL_DQS_VALID
LMI / LMI Padlogic config register

9 8 LMIPL_FILTER_SHIFT_PARAM[2:0] 7 6 5 4 3 2 LMIPL_DDR2_DIAG_CONTROL[4:0] 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
LMIPL_USERMODE_PDL_DQS
LMIPL_DUMMY_PCB_TRACE
LMIPL_LOWER_16BIT_ONLY
LMIPL_PHASE_SHIFT[1:0]
LMIPL_RETIME_PLI_LMI
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SystemConfigBaseAddress + 0x01DC RW 0x00002000 LMI / LMI Padlogic config
[31:30] RESERVED [29] LMIPL_USERMODE_PDL_DQS_VALID: 0: T/4 DLL1 command routed to dqs_valid PDL 1: user_command_dqs_valid<8:0> routed to dqs_valid PDL [28] LMIPL_USERMODE_PDL_DQS270_DEL: 0: 3T/4 (or T/2) DLL2 command routed to dqs270_del<3:0> PDLs 1: dll2_usr_cmd<8:0> routed to dqs270_del<3:0> PDLs [27] LMIPL_USERMODE_PDL_DQS: 0: T/4 DLL command routed to dqs<3:0> PDLs 1: dll1_usr_cmd<8:0> routed to dqs<3:0> PDLs [26:18] LMIPL_USER_COMMAND_DQS_VALID: User command for forcing delay of dqs_valid PDL(also diagnostics). [17:14] RESERVED [13] LMIPL_RETIME_PLI_LMI: Active high retiming stage enable for lmisys_pl.
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RESERVED
RESERVED
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STi7105
[12:11] LMIPL_PHASE_SHIFT[1:0] : Shift padlogic clock in T/4 increments; needs clk_pll stopped when rst_n released. [10] LMIPL_LOWER_16BIT_ONLY: 16/32-bit mode switch; High = 16-bit mode. [9:7] LMIPL_FILTER_SHIFT_PARAM[2:0]: Programmable filter characteristic. [6] LMIPL_DUMMY_PCB_TRACE: Active high to enable dummy PCB trace option. [5] LMIPL_DOUBLE_WIDTH: Enable half speed LMI-PLI interface. [4:0] LMIPL_DDR2_DIAG_CONTROL[4:0]: For future development. Tied off.
15.1.5
INTC2 registers description

INTC2 priority 00 register
9 8 7 6 5 4 3 2 1 0 RESERVED
INTC2_PRIORITY00
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Address: Type:
SystemConfigBaseAddress + 0x0300 RW 0 INTC2 priority 00 register
Reset: Description:
[31:0] RESERVED
INTC2_PRIORITY04
INTC2 priority 04 register

9 8 7 6 5 4 3 2 1 0 RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SystemConfigBaseAddress + 0x0304 RW 0 INTC2 priority 04 register
[31:0] RESERVED
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STi7105
System config module INTC2 priority 08 register

9 8 7 6 5 4 3 2 1 0 RESERVED
INTC2_PRIORITY08
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SystemConfigBaseAddress + 0x0308 RW 0 INTC2 priority 08 register Information classified Confidential - Do not copy (See last page for obligations)
[31:0] RESERVED
INTC2_REQUEST00
INTC2 request 00 register

9 8 7 6 5 4 3 2 1 0 RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Address:
SystemConfigBaseAddress + 0x0320 RW 0 INTC2 request 00 register
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[31:0] RESERVED
INTC2_REQUEST04
INTC2 request 04 register

9 8 7 6 5 4 3 2 1 0 RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SystemConfigBaseAddress + 0x0324 RW 0 INTC2 request 04 register
[31:0] RESERVED
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STi7105 INTC2 request 08 register

9 8 7 6 5 4 3 2 1 0 RESERVED
INTC2_REQUEST08
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SystemConfigBaseAddress + 0x0328 RW 0 INTC2 request 08 register Information classified Confidential - Do not copy (See last page for obligations)
[31:0] RESERVED
INTC2_MASK00
INTC2 mask 00 register

9 8 7 6 5 4 3 2 1 0 RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Address:
SystemConfigBaseAddress + 0x0340 RW 0 INTC2 mask 00 register
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[31:0] RESERVED
INTC2_MASK04
INTC2 mask 04 register

9 8 7 6 5 4 3 2 1 0 RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SystemConfigBaseAddress + 0x0344 RW 0 INTC2 mask 04 register
[31:0] RESERVED
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System config module INTC2 mask 08 register

9 8 7 6 5 4 3 2 1 0 RESERVED
NTC2_MASK08
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SystemConfigBaseAddress + 0x0348 RW 0 INTC2 mask 08 register Information classified Confidential - Do not copy (See last page for obligations)
[31:0] RESERVED
INTC2_MASK_CLEAR00
INTC2 mask clear 00 register

9 8 7 6 5 4 3 2 1 0 RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Address:
SystemConfigBaseAddress + 0x0360 RW 0 INTC2 mask clear 00 register
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[31:0] RESERVED
INTC2_MASK_CLEAR04
INTC2 mask clear 04 register

9 8 7 6 5 4 3 2 1 0 RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SystemConfigBaseAddress + 0x0364 RW 0 INTC2 mask clear 04 register
[31:0] RESERVED
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STi7105 INTC2 mask clear 08 register

9 8 7 6 5 4 3 2 1 0 RESERVED
INTC2_MASK_CLEAR08
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SystemConfigBaseAddress + 0x0368 RW 0 INTC2 mask clear 08 register Information classified Confidential - Do not copy (See last page for obligations)
[31:0] RESERVED
INTC2_MODE
INTC2 mode register

9 8 7 6 5 4 3 2 1 0 RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Address:
SystemConfigBaseAddress + 0x0380 RW 0 INTC2 mode register
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[31:0] RESERVED
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External circuitry recommendations
16
16.1
16.1.1

Power supplies
Decoupling recommendations
It is recommended to: 1. connect all balls of the same group (with the same names) together 2. add decoupling capacitors between each VDD and GND group, respectively: VDD3V3 group and GND3V3 group AVDD2V5 group and AGND2V5 group VDD1V8_2V5 group and LMI_GND1V8 group DVDD1V2 group and DGND1V2 group The decoupling capacitor values must be carefully considered and fully simulated prior to the board design cycle.
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16.1.2
Power-up recommendations
There is no specific recommendation for power-up sequence.
16.2
System
The SYS oscillator recommended external circuitry is shown in Figure 34. Figure 34. Oscillator recommended external circuitry
CL2 SYSCLKIN
STi7105
SYSCLKOSC CL1 RD
Two differential signals (VDDSENSE and GNDSENSE) are used to provide loopback information on the core supply voltage to an external voltage regulator. Most of the signals have internal pull-up or pull-down, and do not require an external resistor when not in use. Refer to the I/O value field of the Table 32 for details. For the electrical specifications, please contact your local ST representative to access SATA application notes describing oscillators electrical specifications.
16.3
JTAG
The JTAG recommended connections are shown in Figure 35.
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External circuitry recommendations Figure 35. Recommended connections

VCC 3.3 V
STi7105
Host device
TDI TDO TMS TCK NOT_TRST TRIGOUT0 TRIGIN NOT_RST
10k
22
STi7105
TDO TDI TMS TCK NOTTRST TRIGGERIN TRIGGEROUT NOTRESETIN
Board power-on reset
10k
Target board
Note:
Confidential
If there is a lot of noise on the clock line, a capacitor in the range 10 to 100 pF can be fitted between TCK and ground near the target STi7105, however, this may limit the maximum TAP clock rate.
16.4
16.4.1
Display analog output interface

Video DACs description
There are two identical sets of triple video DACs for HD and SD output. Both are triple high performance 10-bit digital to analog converters, and consist of three 10-bit DAC modules joined together. A reference circuit controlled by one external resistor sets the full-scale output for each DAC set. Each DAC is able to drive 10 mA. The blocks are powered by 2.5 V analog and 1.2 V digital supplies, with separate analog and digital grounds. The blocks require an external precision resistor (Rref) to provide a bandgap reference. The Rref optimum value is 7.81 k +/- 1%. The blocks analog current sources provide a voltage output range of 1.4 V with an optimum linearity through an external precision resistor (Rload). The Rload optimum value is 140 +/- 1%. The exact calculation for the voltage output range is: Vout = Din * 0.0625 * [(Rext-Mass_quiet)/Rref]*Rload where:

DinCode value in decimal Rext-Mass_quietVbandGap(=1.2214 V) Rrefreference resistor; optimum value is 7.81 k Rloadload resistor (=140 )
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16.4.2
Power mode
Each DAC has two power modesnormal mode and high-impedance modethat are controlled by the SYSTEM_CONFIG3 system configuration register. The high impedance mode allows fast recovery from the low power consumption state, and can be used to reduce power during line and frame refresh. Each DAC takes 100 ns time interval to switch from normal mode to high-impedance mode, and vice-versa.
16.4.3
Video DACs output-stage adaptation and amplification

Information classified Confidential - Do not copy (See last page for obligations) Please contact your local ST representative to access application notes describing video DACs output stage adaptation and amplification.
16.5
HDMI interface
Please contact your local ST representative to access application notes describing HDMI PCB design guidelines.
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16.6
Audio digital interface

Please contact your local ST representative to access application notes describing audio digital interface.
16.7
Audio analog interface

The audio DAC provides differential current source outputs for each channel. The use of a differential mode interface circuit is recommended to achieve the best signal to noise ratio performance. A single-ended mode interface circuit can be used, by grounding pins AUDA_LEFTOUTN and AUDA_RIGHTOUTN, but this is not recommended as the resulting signal to noise ratio is less than 90 dB. An external 1% resistor RREF should be connected between AUDA_IREF and AUDA_GND2V5. A typical value for RREF is 575 , to get proper band gap functionality. An external 10 F capacitance should be connected between AUDA_VREF and AUDA_GND2V5. Figure 36 describes an audio output stage to deliver a 2 VRMS signal.
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External circuitry recommendations Figure 36. VRMS external audio analog schematic with +9V power supply
STi7105
20.5 1k
3.3 nF
AUDA_RIGHTOUTn
2 VRMS
AUDA_RIGHT
Audio right
AUDA_IREF
AUDA_RIGHTOUTp
3.3 nF 1 k . 20.5 4.5 V
575
AUDA_GND2V5
1F
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AUDA_VREF
20.5
1k
100 nF 5.36 k
3.3 nF
AUDA_lefTOUTp
1.96 k Audio left
AUDA_lefTOUTn
3.3 nF 1k 20.5
AUDA_LEFT
2 VRMS
16.8
Programmable inputs/outputs
There is no specific external circuitry recommendations for this interface.
16.9

The EMI is designed to be connected to up to: 1 PCI/33 MHz slot + 4 TTL/100 MHz/40 pF slots 1 PCI/66 MHz slot + 3 TTL/100 MHz/30 pF slots
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16.10
Local memory interface

Apart from the direct signal connections between the LMI and the DDR memories (refer to Figure 37 and Figure 38 for details), several extra connections are required. An external resistor of 121 K +/- 1% is to be connected between LMI_COMP_REF AND LMI_COMP_GND to enable the internal pad drive compensation mechanism. The two voltage reference signals LMIVREF[0]/LMIVREF[1] are to be connected together to the memories VREF signals and to a resistor pair whose pedestal is connected to VDD1V8_2V5 and LMI_GND1V8. The LMIDUMMY[0]/LMIDUMMY[1] signals act as a PCB track delay estimator, and have to be connected through a dummy PCB trace. If all signal lengths are equal to an ideal TLsignal, TLdummy is also equal to this TLsignal. If this is not the case, the ideal TLdummy length is defined by the following equation: TLdummy =
0.5 { ( TLLMICLK [ 0 ] + TLNOTLMICLK [ 0 ] + TL LMICLK [ 1 ] + TL NOTLMICLK [ 1 ] ) 4 + ( TL LMIDQS [ 0 ] + TL LMIDQSN [ 0 ]
+ TL LMIDQS [ 1 ] + TL LMIDQSN [ 1 ] + TL LMIDQS [ 2 ] + TL LMIDQSN [ 2 ] + TL LMIDQS [ 3 ] + TL LMIDQSN [ 3 ] ) 8}
For further information on LMI PCB design guidelines, please contact your local ST representative.
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External circuitry recommendations Figure 37. LMI: connections to a (single rank/2 x16 devices) DDR 32-bit configuration
In red: ballout optimized for TOP pcb routing
STi7105
In blue: ballout optimized for BOTTOM pcb routing
STi7105
LMICLK[0]/ NOTLMICLK[0] LMIDATA[7:0] LMIDATAMASK[0] LMIDQS[0]/ LMIDQSN[0] LMIDATA[15:8] LMIDATAMASK[1] LMIDQS[1]/ LMIDQSN[1] LMIADDR[13:0] NOTLMICS[0] LMICLKEN[0]
CK/CKN DQ[7:0] LDM
DDR0 x16
LDQS/LDQSN
DQ[15:8]
UDQS/UDQSN A[n:0] BA[m:0] CSN CASN/RASN/WEN CKE ODT VREF

vdd1v8
ODT[0] LMIVREF[0] NOTLMICS[1] LMIVREF[1] ODT1 NOTLMICAS/ NOTLMIRAS/ NOTLMIWE LMIBA[2:0] LMICLKEN[1] LMIDATA[31:24] LMIDATAMASK[3] LMIDQS[3]/ LMIDQSN[3] LMIDATA[23:16] LMIDATAMASK[2] LMIDQS[2]/ LMI_DQSN[2] LMICLK[1]/ LMI NOTLMIClK[1] LMIDUMMY[0] LMIDUMMY[1] LMI_COMP_REF LMI_COMP_GND
R R gnd1v8
VREF ODT CKE
DDR1 x16
CASN/RASN/WEN CSN BA[m:0] A[n:0] UDQS/UDQSN UDM DQ[15:8]
LDQS/LDQSN LDM DQ[7:0] CK/CKN
pcb track with similar length as other signals
Note: series resistances not shown
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Figure 38. LMI: connections to a (single rank/1 x16 devices) DDR 16-bit configuration
In red: ballout optimized for TOP pcb routing In blue: ballout optimized for BOTTOM pcb routing
STi7105
LMIClK[0]/ NOTLMICLK[0] LMIDATA[7:0] LMIDATAMASK[0] LMIDQS[0]/ LMIDQSN[0] LMIDATA[15:8] LMIDATAMASK[1] LMIDQS[1] LMIDQSN[1] LMIADDR[13:0] NOTLMICS[0] LMICLKEN[0] ODT[0] LMIVREF[0]
vdd1v8
CK/CKN DQ[7:0] LDM
DDR x16
LDQS/LDQSN
DQ[15:8]
UDQS/UDQSN A[n:0] BA[m:0] CSN CASN/RASN/WEN CKE ODT VREF
NOTLMICS[1] LMIVREF[1] ODT[1] NOTLMICAS/ NOTLMIRAS/ NOTLMIWE LMIBA[2:0] LMICLKEN[1] LMIDATA[31:24] LMIDATAMASK[3] LMIDQS[3]/ LMIDQSN[3] LMIDATA[23:16] LMIDATAMASK[2] LMIDQS[2]/ LMIDQSN[2] LMICLK[1]/ NOTLMICLK[1] LMIDUMMY[0] LMIDUMMY[1] LMI_COMP_REF LMI_COMP_GND
R gnd1v8
pcb track with similar length as other signals
Note: series resistances not shown
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16.11
Ethernet interface
Some mode pins are mapped on some Ethernet interface signals. Pull-up or pull-down resistors have to be added depending upon the chosen reset configuration. Refer to Mode pins for details.
16.12
USB interface
The USB external recommended connections are shown in Figure 39.
Figure 39. USB 2.0 application circuit

+5 V STi7105 USB_PRT_PWR 4.7 k +3.3V USB_PRT_OVRCUR Power switch Input EN1 EN2 GND OUT1 NOC1 OUT2 NOC2
USB USBDM USBDP USBREF 400 mV (High speed), 3.3 V (Low speed and full speed) 400 mV (High speed), 3.3 V (Low speed and full speed) 1.5 k VBUS DM DP GND SHIELD SHIELD
Shield
For PCB design guidelines, refer to the USB PCB design guidelines specific document (ADCS #7991152). For access to this ST internal document please contact your local ST representative.
16.13
SATA
Please contact your local ST representative to access application notes describing SATA PCB design guidelines.
16.14
Peripherals
The DAA external recommended connections are shown in Figure 40.
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STi7105 Figure 40. Example of DAA application circuit

No ground plane in DAA section
R10
Q1
R3 R1 R2
R11 Q4 Q5 R4
R5 Q2 C10
Si307x
C4 STi7105 DAA_C1A DAA_C2A R13 C2 R9 C6 C5 C1 DCT2 QE IGND DCT DCT3 RX QB IB QE2 C1B SC C2B VREG2 VREG Reserved Reserved
R12
R10 Q3
R6
R14
C7
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C3 R8 FB1 D2 C8 R7 D1 FB2 Tip RV1 C9 Ring
Note:
The ISO-Link capacitors C1 and C2, (33 pF) should be as close to the line-side device as possible.They should also be as close to the embedded system-side DAA module as possible and no further than 6 inches away.
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Electrical specifications
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17
Values in this chapter are provisional and may change after characterization
17.1
Table 69. Symbol
VDD3V3max VDD2V5max
Absolute maximum ratings

Absolute maximum ratings Parameter
Digital 3.3 V maximum voltage Analog 2.5 V maximum voltage Digital 1.8 V maximum voltage Digital 1.2 V maximum voltage Electrostatic discharge voltage (HBM modem) Electrostatic discharge voltage (CDM modem) Storage temperature - 60
Min
-0.6 -0.5 -0.5 -0.5
Typ
Max
3.9 3.3 3.3 1.4 1000 250 150
Units Information classified Confidential - Do not copy (See last page for obligations)
V V V V V V C
VDD1V8_2V5max VDD1V2max VESD_HBM
Confidential
VESD_CDM TSTG
17.2
Table 70. Symbol
VDD3V3 VDD2V5 VDD1V8 VDD1V2 I3V3 I2V5 I1V8 I1V2 CL TA PDFP PDLP RTHJAa
Operating conditions
Operating conditions Parameter
Digital 3.3 V operating voltage Analog 2.5 V operating voltage Digital 1.8 V operating voltage Digital 1.2 V operating voltage Digital 3.3 V current Analog 2.5 V current Digital 1.8 V current Digital 1.2 core current Load capacitance per pin Operating ambient temperature Full-Power consumption Low-Power consumption Junction-to-ambient thermal resistance 0 TBD TBD TBD
Min
3.0 2.25 1.7 1.14
Typ
3.3 2.5 1.8 1.2
Max
3.6 2.75 1.9 1.26 TBD TBD TBD TBD 100 70
Units
V V V V A A A A pF C W W C/W
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17.3
17.3.1
Audio DAC
Electrical characteristics
The Table 71 describes absolute maximum ratings for audio DAC. Table 71. Symbol
ANA1_VDD2V5 AUDA_DVDD1V2 Tstg
Absolute maximum ratings Parameter

Analog power supply Digital power supply Storage temperature - 60
Min
Typ
Max
4 2 150
Units Information classified Confidential - Do not copy (See last page for obligations)
V V C
The Table 72 describes operating conditions for audio DAC. Table 72. Operating conditions Parameter
Digital power supply Operating Temperature Digital Supply Current Analog power supply 2.5 Analog Supply Current Supply Current in Power Down Mode 2.25
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Symbol
AUDA_DVDD1V2 Toper ID ANA1_VDD2V5 IA IPD
Min
1 -40
Typ
1.2 27 2 2.5
Max
1.4 125
Units
V C mA
2.75 TBD 10
V mA A
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Output current
In case of no input data, the DAC provides a common mode output current (Icom), as shown in Figure 41. Figure 41. Current output
The output current is fixed by internal reference current or can be fixed externally. Table 73. Parameter Audio DAC output current Imin Icom Imax Unit
Output current
0.8 -----------Rext
1.613 -------------Rext
17.4
Triple HD video DACs

The Table 74 describes absolute maximum ratings for triple video DACs. Table 74. Symbol Absolute maximum rating Parameter Min Typ Max
2.75 2.75 -60 150
Unit
V V degrees
VIDA1_VCCA1/ Analog power supply for current VIDA2_VCCA1 matrix & bias blocks 2.75 V VIDA1_VCCA2/ Analog power supply for level shifters VIDA2_VCCA2 Tstg Storage temperature
The Table 75 describes operating conditions for triple video DACs.
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STi7105 Table 75. Symbol Operating conditions Parameter Min

2.25 2.25 -40
Typ
2.5 2.5 25
Max
Unit
2.75 V 2.75 V 125 degrees
VIDA1_VCCA1/ Analog power supply for current VIDA2_VCCA1 matrix & bias blocks 2.75 V VIDA1_VCCA2/ Analog power supply for level shifters VIDA2_VCCA2 Top Operating junction temperature
Table 76.
Symbol Nb PonAnalog PonDigital
Static electrical performance Rref = 7.81 k; Rload = 140

Parameter DAC resolution Power consumption analog/ active(1) Power consumption digital/ active(2) Power consumption / HZ Power consumption / Off Integral non linearity Differential non linearity DAC to DAC matching(5) Output compliance 0 V < Vout < 1.4 V DAC output current Full scale gain error (6) DAC output resistance @ DC 100 0 (code min) mode(3) mode(4) Min Typ 10 110 3.0 12.7 2.5 +/- 0.4 +/- 0.2 +/- 0.5 133 3.9 15.6 102.0 +/- 1.0 +/- 0.5 +/- 3 0.03 10.0 (code max) +/7 LSB mA % k Max Unit bits mW mW mW W LSB LSB
PHZ POFF INL DNL DAC to DAC matching Compliance Iout Rref = 7.81 k Full scale Gain Error Rout
1. Typical consumption at 2.5 V/1.2 V supply; and Max. at 2.75 V/1.32 V supply 2. Typical consumption at 2.5 V/1.2 V supply; and Max. at 2.75 V/1.32 V supply 3. Independent of dk activity 4. Transistor off-stage leakage only 5. Under ideal supply conditions 6. This value includes the 1% variation of reference resistor (Rref) and 1% of load resistor (Rload)
The Table 77 describes dynamic electrical performance of video DACs.
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The Table 76 describes static electrical performance of TriDAC.
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Electrical specifications Table 77.

Symbol F_CLK BDW THD
STi7105
Dynamic electrical performance Rref = 7.81 k; Rload = 140

Parameter Clock speed Output 3 dB bandwidth @ Fclk=160 MHz Total harmonic distortion Fin =4 MHz, F_clk =160 MHz Spurious free dynamic range Fin=4 MHz, Fclk=160 MHz Output full scale Power supply rejection ratio @ 1 Hz (full scale) Power supply rejection ratio @1 MHz(full scale) DC to 30 -44.27 -46.47 Min Typ Max 160 Unit MHz MHz dB
SFDR PSRR (dVout/dVvcca)
-44.88
-47.79
dB
-50 -22
-55 -25
dB dB
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17.5
Table 78. Symbol
V1
DAA electrical characteristics

The Table 78 describes absolute maximum ratings for DAA. Absolute maximum ratings Parameter
Input voltage on IO pin with respect to GND
Conditions
Min
Max
3.6
Units
V
17.6.1
Limiting values
The Table 79 describes the limiting values for DDR.
Table 79.
Symbol
DDR limiting values

Parameter 1.8 V pad supply voltage Conditions DDR II mode DDR I mode Min 1.7 2.25 (0.49 * VDDE) VREF 0.04 Typ 1.8 2.5 (0.5 * VDDE) VREF Max 1.9 2.75 (0.51 * VDDE) VREF +0.04 Unit V V V
VDDE Input reference voltage connected on REFSSTL (corresponding to supply VDDE) Termination voltage
VREF(DC)
(1)
VTT
(2)
1. The value of VREF is expected to be (0.49-0.51) x VDDE of the transmitting device and VREF is expected to track variations in VDDE. 2. Peak to peak AC noise on VREF may not exceed +/-2% of VREF(DC). VTT of transmitting device must track VREF of receiving device.
17.6.2
Table 80.
Symbol Iol
Output buffer DC characteristics

Output buffer DC characteristics
Mode of I/O buffer Parameter Output minimum DC current sink DDRI Output minimum DC current source Output minimum DC current sink DDRII Output minimum DC current source Conditions Vol = 0.36V(1) Voh = VDDE 0.36V Vol = 0.28V Voh = VDDE 0.28V(2) Min 16.2 -16.2 13.4 -13.4 Typ Max Unit mA mA mA mA
Ioh Iol Ioh
1. SSTL2 classII specification with ZOUTPROGA set low. 2. SSTL_18 specification with ZOUTPROGA set low.
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17.6
DDR electrical characteristics
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17.6.3
Table 81.
Symbol VREF Vil (DC) Vih (DC) Vil (AC) Vih(AC)
Input buffer DC specifications

Input buffer DC characteristics for DDRI
Parameter Voltage reference DC input logic low DC input logic high AC input logic low AC input logic high Conditions Min Typ Max Unit V V V V V
0.49 * VDDE = 1.1 0.5 * VDDE = 1.25 0.51 * VDDE = 1.4 -0.3 VREF + 0.15 VREF + 0.31 VREF - 0.15 VDDE + 0.3 VREF - 0.31 -
Table 82.
Symbol VREF
Input buffer DC characteristics for DDRII

Parameter Voltage reference Conditions Min 0.49 * VDDE = 0.833 -0.3 VREF + 0.125 VREF - 0.04 VREF + 0.25 Typ 0.5 * VDDE = 0.9 Max 0.51 * VDDE = 0.969 VREF - 0.125 VDDE + 0.3 VREF + 0.04 VREF - 0.25 Unit V V V V V V
Vil (DC) DC input logic low
Vih (DC) VTT (DC) Vil (AC)
DC input logic high Termination voltage AC input logic low
Vih(AC) AC input logic high
17.7
17.7.1
SATA PHY electrical characteristics

Table 83 describes the absolute maximum ratings.
Table 83.

Parameter Min Max Unit
Symbol SATAVDDR SATAVDDT SATAVDD_PLL SATAVDD2_PLL VINL VINH1 VINH2
Supply Voltage (1.2 V nom.)
1.35
Supply Voltage (2.5 V) Input low level Input high level (oscillator and pll 2v5 inputs) Input high level (all other inputs) TBD
2.75
V V
2.75 1.35
V V
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17.7.2
Table 84 describes the operating conditions.
Table 84.
Parameter Min Typ Max Units
Symbol SATAVDDR SATAVDDT SATAVDD_PLL SATAVDD2_PLL
1v2 supply voltage range
1.08
1.20
1.32
Supply Voltage (2.5 V) Supply ripple (1MHz to 3GHz)
2.25
2.50
2.75 50
V mV(pk-pk) C
TJ
Operating junction temperature
-40
125
17.7.3
General electrical specifications

Table 85 describes the general electrical specifications.
Confidential
Table 85.
Symbol Rref TUISATASAS1 FSSC SSCTOL Vcm,ac Zdiff tsettle,cm Vtrans
General electrical specifications

Parameter External reference resistor (from refers pin to the vdd_pll pin) Unit Interval for SATA/SAS gen1 (1.5 Gbps) Spread spectrum modulation frequency Spread spectrum modulation deviation AC coupled common mode voltage Nominal differential impedance Common mode transient settle time (SATA gen1 only) Sequencing transient voltage -2.0 30 -5000 0 100 10 2.0 ns V Min -1% Typ 475 666.67 33 +0 2000 Max +1% Unit Ohm ps kHz ppm mV
17.8

The EMI pads are TTL/PCI dual-mode. TTL electrical specifications are shown in Table 86 and PCI electrical specifications in Table 87.
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Electrical specifications Table 86.

Symbol VIH VIL VOH VOL RPU RPD IIN CIN
STi7105
TTL-mode 3V3 EMI pads DC specifications

Parameter Input logic 1 voltage Input logic 0 voltage Output logic 1 voltage Output logic 0 voltage Equivalent pull-up resistance Equivalent pull-down resistance Input leakage current (input pin) Input capacitance 50 50 4 10 Min 2.0 -0.5 VDD3V3 0.2 0.2 Typical Max VDD3V3 + 0.5 0.8 Units V V V V k k A pF
(3) (1) (2)
Notes
1. IOUT = -8 mA 2. IOUT = 8 mA 3. 0 Vin VDD3V3
Table 87.
Symbol VIH VIL VOH VOL RPU RPD IIN CIN
PCI-mode 3V3 EMI pads DC specifications

Parameter Input logic 1 voltage Input logic 0 voltage Output logic 1 voltage Output logic 0 voltage Equivalent pull-up resistance Equivalent pull-down resistance Input leakage current (input pin) Input capacitance 50 50 4 10 Min 0.5*VDD3V3 -0.5 0.9*VDD3V3 0.1*VDD3V3 Typical Max VDD3V3 + 0.5 0.3*VDD3V3 Units V V V V k k A pF
(3) (1) (2)
Notes
1. IOUT = -0.5 mA 2. IOUT = 1.5 mA 3. 0 Vin VDD3V3
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17.9
Table 88.
Symbol
USB
Table 88 describes the operating conditions of USB. USB operating conditions
Parameter Analog supply voltage Min 3.0 1.1 2.3 800 -50 -50 100 400 200 Typ 3.3 1.2 2.5 Max 3.6 1.3 2.7 2500 500 600 1100 Unit V V
USB1_VDD3V3 USB2_VDD3V3 USB_VDD1V2 USB_VDD2V5 VLFS-cm VHS-cm Vchirp-cm Digital supply voltage Analog supply voltage Low and full speed mode input common mode level High speed mode input common mode level Chirp mode input common mode level Differential input signal amplitude
mV mV mV mV
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Vdiff
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18
18.1
18.1.1
Timing interfaces
Digital audio interface Digital PCM reader input interface
Digital PCM Player timing waveform
The Figure 42 shows the timing waveforms of the digital Audio PCM input to the PCM reader. Figure 42. Digital PCM audio input timing waveforms
tpcmi_sclkl tpcmi_sclkh
PCMI_SCLK PCMI_DATA
tpcmidSH PCMI_LRCLK
tpcmidHD
Table 89.
Symbol fpcmi_sclk tpcmi_sclkl tpcmi_sclkh tpcmidSH tpcmidHD
Digital audio PCM input timing parameters

Parameter PCMI_SCLK max frequency PCMI_SCLK low pulse PCMI_SCLK high pulse PCMI_data setup time to PCMI_SCLK rising edge PCMI_data hold time from PCMI_SCLK rising edge Min -12 12 5 5 Max 32 ----Units MHz ns ns ns ns
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18.2
18.2.1
Digital PCM player output interface

PCM player output timing waveform
The Figure 43 shows the timing waveforms of the PCM player output interface.
Figure 43. PCM player timing output waveforms

tSCLPD SCLK INV_SCLK = 0 PCMDATA tSCLLR
LRCLK
tSCHPD
tSCHLR
SCLK INV_SCLK = 1 PCMDATA
LRCLK
Table 90.
Symbol tSCLPD tSCLLR tSCHPD tSCHLR PCMjitter
PCM player output timing parameters

Parameter SCLK low to PCMDATA valid SCLK low to LRCLK SCLK high to PCMDATA valid SCLK high to LRCLK Dedicated PCMCLK pin jitter Min ----Max 10 10 50 50 Units ns ns ns ns
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18.3
18.3.1
Transport stream input AC specification

Parallel transport stream input interface
The Figure 44 shows the timing waveforms of parallel transport stream input interface. Figure 44. Parallel transport stream input timing waveform
tLCLLCL TSnINBYTECLK
tLCLLCL
tLCHLCH
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TSnINBYTECLKVALID TSnINDATA[7:0] TSnINERROR TSnINPACKETCLK
tLDVLCH
tLCHLDX
Table 91.
Symbol tLCLLCL tLCHLCH tLCLLCL tLDVLCH tLCHLDX
Parallel transport stream input timing parameter

Parameter TSnINBYTECLK period TSnINBYTECLK pulse width high TSnINBYTECLK pulse width low TSnIN signals valid to TSnINBYTECLK high TSnIN signals hold after TSnINBYTECLK high Min 37 10 10 4 0 Mon -----Max -----Units ns ns ns ns ns
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18.3.2
Serial transport stream input interface

The Figure 45 shows the timing waveforms of serial transport stream input interface. Figure 45. Serial transport stream input timing waveform
tLCLLCL
TSnINBITCLK tLCLLCL tLCHLCH
TSnINBITCLKVALID TSnINDATA TSnINERROR TSnINPACKETCLK
tLDVLCH
tLCHLDX
Table 92.
Symbol tLCLLCL tLCHLCH tLCLLCL tLDVLCH tLCHLDX
Serial transport stream input timing parameter

Parameter TSnINBITCLK period TSnINBITCLK pulse width high TSnINBITCLK pulse width low TSnIN signals valid to TSnINBITCLK high TSnIN signals hold after TSnINBITCLK high Min 10 3 3 3 0 Mon -----Max -----Units ns ns ns ns ns
18.4
Transport stream output AC specification

The Figure 46 shows the timing waveforms of transport stream output interface. Figure 46. Transport stream output timing
tTSIN2BYTECLK
TSINBYTECLK
tTSBYTECLK
Outputs
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Timing interfaces Table 93.

Symbol tTSINBYTECLK tTSBYTECLK tACHACH tACLLAL
STi7105 Transport stream output port timings

Parameter TSINBYTECLK clock period Output delay to TSINBYTECLK TSnINOUTBYTECLK pulse width high TSnINOUTBYTECLK pulse width low 40 40 Min 10 0 Max Units ns ns ns ns
18.5
JTAG interfaces AC specification

Input clocks: TCK (rising edge) Inputs: TDI, TMS Figure 47. JTAG interface timing Information classified Confidential - Do not copy (See last page for obligations)
tTAPCLK
Confidential
TCK
tTAPHCLK
Inputs
tTAPSCLK tPTAPCLK
TDO
Table 94.
Symbol Input clock tTAPHCLK tTAPSCLK tPTAPCLK
JTAG input/output port timings

Parameter TCK period Inputs setup to TCK rising edge Inputs hold to TCK rising sdge Output delay to TCK falling edge Min 20 5 5 15 Max Units ns ns ns ns
18.6
EMI timings
All of the outputs come from a multiplexer controlled by the clock. It is assumed that the EMI will be programmed so that all the outputs will be changed on the falling edge of the clock. Following tables assume an external load of 25 pF on every EMI pad.
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18.6.1
Synchronous devices
All synchronous transactions originate and terminate at flip flops within the padlogics. Outputs are generated with respect to the falling edge of the bus clock, and inputs are sampled with respect to the rising edge. EMI-Clock: EMISFLASH EMI-outputs: EMIADDR[*], EMIDATA[*], NOTEMICS*, NOTEMIBE, NOTEMIOE, NOTEMILBA, NOTEMIBAA, EMIRDNOTWR EMI-inputs: EMIDATA[*], EMIREADYORWAIT Information classified Confidential - Do not copy (See last page for obligations) Figure 48. EMI synchronous device timing
tEMI-clock
EMI-clock
tECHEOV
Confidential
EMI-outputs
tEIVECH
EMI-inputs
tECHEIX
tECHEOZ
EMI-tristate Outputs
tECHEON
Table 95.
Symbol Input clock tECHEOV tEIVECH tECHEIX tECHEON tECHEOZ
EMI / SFLASH synchronous interface parameters

Parameter EMISFLASHCLK period Bus clock falling edge to valid data Input valid to rising clock edge (input setup time) Rising clock edge to input invalid (input hold time) Falling clock edge to data valid (after tristate output) Falling clock edge to data valid (before tri-state output) Min 33 0 5.5 0 2 -3 4 Max Units ns ns ns ns ns ns
These values are static offsets within a bus cycle, they should be read in conjunction with the waveforms in external memory interface (EMI), which are cycle accurate only.
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Asynchronous memory/peripherals
The EMI strobes are programmed in terms of internal clock phases, that is to say with half cycle resolution. The clock to output delay for all outputs (address, data, strobes) are closely matched with a skew tolerance of -3 ns / +3 ns (assuming an external load of 25 pF on pads). The input latch point for a read access is determined by the number of programmed EMI subsystem clock cycles for the latch point. The correction allows the latch point to be measured from the edge of an active chip select, that has been programmed to rise at the programmed read latch point. Information classified Confidential - Do not copy (See last page for obligations) Time between the address bus switching and a chip select or data bus output switching is n programmed phases +/- 3 ns. That is, worst case, the chip select or data is maximum of 3 ns after the address, or worst case the chip select or data is 3 ns before the address. For a read cycle, the data is latched by the STi7105 at the programmed number of EMI subsystem clock cycles from the end of the access plus a latch point correction time, which is effectively the read setup time. The latch point correction time (read setup time) is a minimum of 5 ns + skew tolerance correction of the output signal used as a reference. This is 5 +/- 3 ns, thus the minimum read setup time relative to a strobe is 8 ns. This ensures the read hold time is always a minimum of 0 ns, guaranteed by design.
Confidential
Asynchronous access - READ

Figure 49. EMI asynchronous read timing
Nominal access time (+ any wait states) Actual latch point Programmed latch point
EMIADDR
tAVSV
EMISTROBE
tAVSV
tRDVSV
EMIDATA
tSVRDX
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Asynchronous access - WRITE

Figure 50. EMI asynchronous write timing
Nominal access time (+ any wait states)
EMIADDR
tAVSV
EMISTROBE
tAVSV
tAVWDON
EMIDATA
tAVWDOZ
tAVWDV
EMIDATA
Table 96.
Symbol tAVSV tRDVSV tSVRDX tAVWDON tAVWDOZ tAVWDV
EMI / Asynchronous memory/peripherals interface parameters

Parameter Address valid to output strobe valid Read data valid to strobe valid (read setup time) Read data hold time after strobe valid (read hold time) Address valid to write data valid (after tristate output) Address valid to write data valid (before tristate output) Address valid to write data valid -2 Min -1.5 8 0 3 -4.5 2 Max 3 Units Note ns ns ns ns ns ns
(1) (2) (3) (4)
1. Skew plus nominal N programmed EMI subsystem clock cycles of strobe delay. 2. Skew from nominal programmed read latch point. 3. Minimum values are guaranteed by design. 4. Skew from nominal programmed phases of data drive delay.
Table 96 assumes an external load of 25 pF on EMI pads.
18.7
LMI DDR2-SDRAM timings

The DDR2 interface is compliant to the Jedec DDR2 specs (DDR2-800 grade).
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18.8
Note:
PIO output AC specification

Reference clock in this case means the last transition of any PIO signal. There are two different sets of PIO timings, one for the SSC (I2C) outputs and one for all other PIO outputs. Figure 51. PIO timing
PIO reference clock
tPCHPOV
PIOOUT
tPCHWDZ
PIOOUT
Table 97.
Symbol tPCHPOV tPCHWDZ tPIOr tPIOf
PIO timings: SSC (I2C bus)

Parameter PIO_REFCLOCK high to PIO output valid PIO tristate after PIO_REFCLOCK high Output rise time Output fall time Min -20.0 -20.0 3.0 3.0 Max 0.0 5.0 30.0 30.0 Units ns ns ns ns
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18.9
18.9.1
Ethernet interface
MII interface
MII receive interface
The Figure 52 shows the timing waveform for the Receive MII interface. Figure 52. Receive signal timing relationship at the MII PHY interface
10 ns min RX_DV RX_ER RX_D*
10 ns min
MII transmit interface

The Figure 53 shows the timing waveform for the Transmit MII interface. Figure 53. Transmit signal timing relationship at the MII PHY interface
TX_CLK
10 ns min TX_EN TX_D*
0 ns min, 25 ns max
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RX_CLK
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Timing interfaces
STi7105
MII control interface

The Figure 54 shows the timing waveform for the MII control interface. Figure 54. Control signal timing relationship at the MII PHY interface
MDC
0 ns min, 300 ns max
MDIO (Input)
MDC
10 ns min
10 ns min
MDIO (Output)
18.9.2
RMII interface
RMII timing parameters
The Table 98 describes RMII timings parameters. Table 98.
Parameter REF_CLK Frequency REF_CLK Duty Cycle TXD[1:0], TX_EN,RXD[1:0], CRS_DV, RX_ER (Data Setup to REF_CLK rising edge) TXD[1:0], TX_EN,RXD[1:0], CRS_DV, RX_ER (Data hold from REF_CLK rising edge) 35 4 2
RMII timing parameters

Min Typ 50 65 Max Units MHz % ns ns
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19
19.1
Alternate functions on PIO

Alternate functions
To improve flexibility and to allow the STi7105 to fit into different set-top box application architectures, the input and output signals from some of the peripherals and functions are not directly connected to the pins of the device. Instead, they are assigned to the alternate function inputs and outputs of a PIO port bit, or an I/O pin. This allows the pins to be configured with their default function if the associated input or output is not required in that particular application. Some pins have several alternate functions, for inputs and outputs, or both. Table 99 to Table 115 list the different alternate functions. Inputs connected to the alternate function input are permanently connected to the input pin. The output signal from a peripheral is only connected when the PIO bit is configured into either push-pull or open drain driver alternate function mode. Some alternate function signals are available on more than one PIO port. The STi7105 uses 7 PIO banks (PIO#0 to PIO#6) that are controlled by the COMMS IP and 10 banks that are driven by a standalone PIO module called STD_PIO. The STi7105 embeds two types of PIOs alternate functions. Functions that are enabled by a register located inside the COMMS (or STD_PIO module). Functions that are enabled by a register located inside the system config module. This configuration is required for the pins where the alternate functions are enabled already at reset (by default the pins controlled by the COMMS are in the PIO mode and not alternate).
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In addition to the multiplexing on the PIO pins, the STi7105 uses other pin multiplexing to provide different signal options depending upon the device application. For these other multiplexing options see Section 7: Basic chip operating modes and multiplexing scenarios on page 98. Alternate functions on PIO
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Figure 55. I/O port pins (alternate functions controlled by COMMS or STD_PIO)
Pin
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Push-pull tri-state open drain weak pull-up
Alternate function
1
Alternate function output
Alternate function input
Output latch
Input latch
COMMS
STi7105
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Figure 56. I/O port pins (alternate functions controlled by the System Config bit)
Pin Pad enable from alternate function
STi7105
1
Pad enable from PIO
Alternate function
1
Alternate function output
Alternate function 1 Alternate function output 0
Alternate function input
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Output latch
Input latch
COMMS
Note:
In case of alternate functions controlled by the System Config bit, the enabling of the pad is driven by the alternate function itself when in the alternate mode or by the COMMS (or STD_PIO) signals when in the PIO mode. Alternate functions on PIO
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19.2 PIO0 alternate functions
PIO0 is on COMMS block. It provides: first digital video output extension (8 to 16-bit) DVO0 second digital video output (24-bit) DVO1 smartcard interfaces SC0 and SC1 UART0 interfaces Table 99.
PIO0 Config bus: PIO0_ALTFOP[1:0]_MUX_SEL_BUS[7:0] PIN Parameter Alternate 1 Digital video output 1 Alternate 2 Digital video output 0
DVO0[16] First DVO output O SYSTEM_CONFIG19[8,0]=01 DVO0[17] First DVO output O SYSTEM_CONFIG19[9,1]=01 DVO0[18] First DVO output O SYSTEM_CONFIG19[10,2]=01 DVO0[19] First DVO output O SYSTEM_CONFIG19[11,3]=01
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PIO0 alternate functions
Config register: SYSTEM_CONFIG19[15:0]
Alternate 3 Smart card 0

SC0_DATAOUT Smartcard 0 O SYSTEM_CONFIG19[8,0]=10 SC0_DATAIN Smartcard 0 I Not required SC0_EXTCLKIN Smartcard 0 I Not required SC0_CLKOUT Smartcard 0 O SYSTEM_CONFIG19[11,3]=10
Alternate 4 UART 0
UART0_TXD UART 0 O SYSTEM_CONFIG19[8,0]=11 UART0_RXD UART 0 I Not required UART0_NOT_OE UART 0 O SYSTEM_CONFIG19[10,2]=11 UART0_RTS UART 0 O SYSTEM_CONFIG19[11,3]=11
Alternate 5 Reserved
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
DVO1[0] Second DVO output O SYSTEM_CONFIG19[8,0]=00 DVO1[1] Second DVO output O SYSTEM_CONFIG19[9,1]=00 DVO1[2] Second DVO output O SYSTEM_CONFIG19[10,2]=00 DVO1[3] Second DVO output O SYSTEM_CONFIG19[11,3]=00
STi7105
RESERVED RESERVED
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Table 99.
PIO0 Config bus: PIO0_ALTFOP[1:0]_MUX_SEL_BUS[7:0] PIN Parameter Alternate 1 Digital video output 1 Name Description PIO0[4] Direction Configuration Name Description PIO0[5] Direction
O SYSTEM_CONFIG19[13,5]=00 DVO1[6] Second DVO output O SYSTEM_CONFIG19[14,6]=00 DVO1[7] Second DVO output O SYSTEM_CONFIG19[15,7]=00 O SYSTEM_CONFIG19[13,5]=01 DVO0[22] First DVO output O SYSTEM_CONFIG19[14,6]=01 DVO0[23] First DVO output O SYSTEM_CONFIG19[15,7]=01 O SYSTEM_CONFIG19[13,5]=10 SC0_COND_VPP Smartcard 0 O SYSTEM_CONFIG19[14,6]=10 SC0_DETECT Smartcard 0 I Not required RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED O SYSTEM_CONFIG19[12,4]=00 DVO1[5] Second DVO output O SYSTEM_CONFIG19[12,4]=01 DVO0[21] First DVO output O SYSTEM_CONFIG19[12,4]=10 SC0_COND_VCC Smartcard 0 I Not required RESERVED RESERVED RESERVED RESERVED DVO1[4] Second DVO output
PIO0 alternate functions (continued)
STi7105
Config register: SYSTEM_CONFIG19[15:0]
Alternate 2 Digital video output 0

DVO0[20] First DVO output
Alternate 3 Smart card 0

SC0_RESET Smartcard 0
Alternate 4 UART 0
UART0_CTS UART 0
Alternate 5 Reserved
RESERVED RESERVED
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Configuration Name Description PIO0[6] Direction Configuration Name Description PIO0[7] Direction Configuration
RESERVED
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PIO1 is on COMMS block. It provides: second Digital Video Output (24-bit) DVO1 smart card interface SC1 MAFE interface UART interfaces Table 100. PIO1 alternate functions
Config register: SYSTEM_CONFIG20[15:0] PIO1 Config bus: PIO0_ALTFOP[1:0]_MUX_SEL_BUS[7:0] PIN Parameter Alternate 1 Digital video output 1 Alternate 2 MAFE I/F
MAFE_DIN MAFE I Not required MAFE_SCLK MAFE I Not required MAFE_HC1 MAFE O SYSTEM_CONFIG20[10,2]=01 MAFE_DOUT MAFE O SYSTEM_CONFIG20[11,3]=01
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Alternate 3 Smartcard 1
SC1_DATAOUT Smartcard 1 O SYSTEM_CONFIG20[8,0]=10 SC1_DATAIN Smartcard 1 I Not required SC1_EXTCLKIN Smartcard 1 I Not required SC1_CLKOUT Smartcard 1 O SYSTEM_CONFIG20[11,3]=10
Alternate 4 UART 1
UART1_TXD UART 1 O SYSTEM_CONFIG20[8,0]=11 UART1_RXD UART 1 I Not required
DVO1[8] Second DVO output O SYSTEM_CONFIG20[8,0]=00 DVO1[9] Second DVO output O SYSTEM_CONFIG20[9,1]=00 DVO1[10] Second DVO output O SYSTEM_CONFIG20[10,2]=00 DVO1[11] Second DVO output O SYSTEM_CONFIG20[11,3]=00
UART1_RTS UART 1
STi7105
O SYSTEM_CONFIG20[11,3]=11
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Table 100. PIO1 alternate functions (continued)
Config register: SYSTEM_CONFIG20[15:0] PIO1 Config bus: PIO0_ALTFOP[1:0]_MUX_SEL_BUS[7:0] PIN Parameter Alternate 1 Digital video output 1 Name Description PIO1[4] Direction Configuration Name Description PIO1[5] Direction
O SYSTEM_CONFIG20[13,5]=00 DVO1[14] Second DVO output O SYSTEM_CONFIG20[14,6]=00 DVO1[15] Second DVO output O SYSTEM_CONFIG20[15,7]=00 I Not required O SYSTEM_CONFIG20[13,5]=00 SC1_COND_VPP Smartcard 1 O SYSTEM_CONFIG20[14,6]=10 SC1_DETECT Smartcard 1 I O SYSTEM_CONFIG20[12,4]=00 DVO1[13] Second DVO output MAFE_FS MAFE O SYSTEM_CONFIG20[12,4]=10 SC1_COND_VCC Smartcard 1 I Not required DVO1[12] Second DVO output
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Alternate 2 MAFE I/F
Alternate 3 Smartcard 1
SC1_RESET Smartcard 1
Alternate 4 UART 1
UART1_CTS UART 1
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Not required
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PIO2 is on COMMS block. It provides: second Digital Video Output (24-bit) DVO1 SSC0 and SSC1 interfaces with I2C half-duplex/full-duplex modes selectable by the ssc0_mux_sel and ssc1_mux_sel bits SSC2 and SSC3 interfaces with I2C half-duplex modes selectable Table 101. PIO2 alternate functions
Config register: SYSTEM_CONFIG21[15:0] PIO2 Config bus: PIO2_ALTFOP[1:0]_MUX_SEL_BUS[7:0] PIN Parameter Alternate 1 Digital video output 1 Name
DVO1[16] Second DVO output O
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Alternate 2 SSC2, SSC3
Alternate 3 SSC 0,1,2,3

SSC2_MTSR SSC2 Data bit: master transmit/slave receive, full duplex I/O In: SYSTEM_CONFIG16[10,9]=00 Out: SYSTEM_CONFIG21[8,0]=10 SSC3_MTSR SSC3 Data bit: master transmit/slave receive, full duplex I/O In: SYSTEM_CONFIG16[17:16]=00 Out: SYSTEM_CONFIG21[9,1]=10 SSC0_SCL SSC0 serial clock in/out I/O In: Not required Out: SYSTEM_CONFIG21[10,2]=10

SSC2_MRST SSC2 Data bit: master receive/slave transmit, full duplex I/O In: SYSTEM_CONFIG16[8,7]=00 Out: SYSTEM_CONFIG21[8,0]=11 SSC3_MRST SSC3 Data bit: master receive/slave transmit, full duplex I/O In: SYSTEM_CONFIG16[15,14]=00 Out: SYSTEM_CONFIG21[9,1]=11 SSC0_SCL SSC0 serial clock in/out I/O In: Not required Out: SYSTEM_CONFIG21[10,2]=11
Description PIO2[0] Direction
Configuration
SYSTEM_CONFIG21[8,0]=00
Name Description PIO2[1]

Direction
Configuration
Name Description PIO2[2] Direction
STi7105
Configuration
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Config register: SYSTEM_CONFIG21[15:0] PIO2 Config bus: PIO2_ALTFOP[1:0]_MUX_SEL_BUS[7:0] PIN Parameter Alternate 1 Digital video output 1 Name Description PIO2[3] Direction
STi7105

SSC0_MTSR SSC0 Data bit: master transmit/slave receive, full duplex I/O In: Not required Out: SYSTEM_CONFIG21[11,3]=10 SSC0_MRST SSC0 Data bit: master receive/slave transmit, full duplex I/O In: SYSTEM_CONFIG16[0]=1 Out: SYSTEM_CONFIG21[12,4]=10 SSC1_SCL SSC1 Serial Clock I/O In: Not required Out: SYSTEM_CONFIG21[13,5]=10 SSC1_MTSR SSC1 Data bit: master transmit/slave receive, full duplex I/O In: Not required Out: SYSTEM_CONFIG21[14,6]=10

SSC0_MRST SSC0 Data bit: master receive/slave transmit, full duplex I/O In: SYSTEM_CONFIG16[0]=0 Out: SYSTEM_CONFIG21[11,3]=11 SSC0_MRST SSC0 Data bit: master receive/slave transmit, full duplex I/O In: SYSTEM_CONFIG16[0]=1 Out: SYSTEM_CONFIG21[12,4]=11 SSC1_SCL SSC1 Serial Clock I/O In: Not required Out: SYSTEM_CONFIG21[13,5]=11 SSC1_MRST SSC1 Data bit: master receive/slave transmit, full duplex I/O In: SYSTEM_CONFIG16[3]=0 Out: SYSTEM_CONFIG21[14,6]=11
Configuration
Name
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Description PIO2[4] Direction
Configuration
Configuration
Configuration
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SSC1_MRST SSC1 Data bit: master receive/slave transmit, full duplex I/O In: SYSTEM_CONFIG16[3]=1 Out: SYSTEM_CONFIG21[15,7]=10

SSC1_MRST SSC1 Data bit: master receive/slave transmit, full duplex I/O In: SYSTEM_CONFIG16[3]=1 Out: SYSTEM_CONFIG21[15,7]=11
Configuration
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PIO3 is on COMMS block. It provides: first digital video output (16-bit) DVO0 second digital video output (24-bit) DVO1 digital video port extension(16-bit) DVP0 SSC2 and SSC3 interfaces with I2C half-duplex modes selectable infra red blaster interface IRB auxiliary VTG synchronizations Table 102. PIO3 alternate functions
Config register: SYSTEM_CONFIG25[15:0] PIO3 Config bus: PIO3_ALTFOP[1:0]_MUX_SEL_BUS[7:0] PIN Parameter Alternate 1 Digital video output 1 Name Description PIO3[0] Direction Configuration Name Description PIO3[1] Direction Configuration Name Description PIO3[2] Direction Configuration
O SYSTEM_CONFIG25[10,2]=00 O SYSTEM_CONFIG25[10,2]=01 O SYSTEM_CONFIG25[10,2]=10 O SYSTEM_CONFIG25[10,2]=11 O SYSTEM_CONFIG25[9,1]=00 DVO1VS DVO vertical sync IRB_IR_DATA_OUT IRB IR data output I Not required IRB_IR_DATA_OUT IRB IR data output VTG_AUX_VS Aux video O SYSTEM_CONFIG25[8,0]=00 DVO1_CLK DVO clock I Not required IRB_UHF_IN IRB UHF data input O SYSTEM_CONFIG25[8,0]=11 DVO1HS DVO horizontal sync
STi7105
Alternate 2 Digital video input 0, ssc 2,3
Alternate 3 Infra-red blaster, ssc 2,3

IRB_IR_IN IRB IR data input
Alternate 4 AUX video timing h/v refs

VTG_AUX_HS Aux video
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Config register: SYSTEM_CONFIG25[15:0] PIO3 Config bus: PIO3_ALTFOP[1:0]_MUX_SEL_BUS[7:0] PIN Parameter Alternate 1 Digital video output 1 Name Description PIO3[3] Direction Configuration Name Description
O SYSTEM_CONFIG25[11,3]=00 DVO0[0] First DVO output O O SYSTEM_CONFIG25[11,3]=01 DVP0[8]/SSC2_SCL DVP input/SSC2 SCL out I/O In: Not required Out: SYSTEM_CONFIG25[12,4]=01 DVP0[9]/SSC2_MTSR DVP input/SSC2 Data bit: master transmit/slave receive, full duplex I/O In: Not required Out: SYSTEM_CONFIG25[13,5]=01 DVP0[10]/SSC3_SCL DVP input/SSC3 SCL out I/O In: Not required Out: SYSTEM_CONFIG25[14,6]=01 O SYSTEM_CONFIG25[11,3]=10 SSC2_SCL SSC2 SCL out I/O In: SYSTEM_CONFIG16[12,11]=00/01 Out: SYSTEM_CONFIG25[12,4]=10 SSC2_MTSR SSC2 Data bit: master transmit/slave receive, full duplex I SYSTEM_CONFIG16[10,9]= 01 SSC3_SCL SSC3 SCL in/SSC3 SCL out I/O In: SYSTEM_CONFIG16[19,18]=01 Out: SYSTEM_CONFIG25[14,6]=10 SSC2_MRST SSC2 Data bit: master receive/slave transmit, full duplex I/O In: SYSTEM_CONFIG16[8,7]=01 Out: SYSTEM_CONFIG25[13,5]=10 O SYSTEM_CONFIG25[11,3]=11 DVO1DE Second DVO output
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IRB_DATA_OUT_OD IRB data output open drain

IRB_DATA_OUT_OD IRB data output open drain

VTG_AUX_BOTNOTTOP Aux video
PIO3[4]
Direction
Configuration
DVO0[1] First DVO output O
Configuration
Configuration
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DVP0[11]/SSC3_MTSR DVP input/ SSC3 Data bit: master transmit/slave receive, full duplex I/O In: Not required Out: SYSTEM_CONFIG25[15,7]=01

SSC3_MTSR SSC3 Data bit: master transmit/slave receive, full duplex I In: SYSTEM_CONFIG16[17,16] =01 SSC3_MRST SSC3 Data bit: master receive/slave transmit, full duplex I/O In: SYSTEM_CONFIG16[15,14]=0 1 Out: SYSTEM_CONFIG25[15,7]=10
Configuration
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PIO4 is on COMMS block. It provides: first digital video output (16-bit) DVO0 digital video port extension(16-bit) DVP0 UART2 interface pulse width modulator interface PWM USB power control Table 103. PIO4 alternate functions
Config register: SYSTEM_CONFIG34[15:0] PIO4 Config bus: PIO4_ALTFOP[1:0]_MUX_SEL_BUS[7:0] PIN Parameter Alternate 1 Digital video output 0 Name Description PIO4[0] Direction Configuration Name Description PIO4[1] Direction Configuration Name Description PIO4[2] Direction Configuration
O SYSTEM_CONFIG34[10,2]=00 I Not required I Not required O SYSTEM_CONFIG34[9,1]=00 DVO0[6] First DVO output I Not required DVP0[14] DVP input I Not required UART2_CTS UART O SYSTEM_CONFIG34[8,0]=00 DVO0[5] First DVO output I Not required DVP0[13] DVP input O SYSTEM_CONFIG34[8,0]=10 UART2_RXD UART DVO0[4] First DVO output
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Alternate 2 Digital video input 0

DVP0[12] DVP input
Alternate 3 UART 2, PWM 0,1

UART2_TXD UART
Alternate 4 PWM 0, USB 1,2 Power ctrl
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Alternate 2 Digital video input 0

DVP0[15] DVP input I
Alternate 3 UART 2, PWM 0,1

PWM_CAPTURE_IN0/UART2_RTS PWM 0 capture input/UART I/O In: Not required Out: SYSTEM_CONFIG34[11,3]=10 PWM_OUT0 PWM 0 output O SYSTEM_CONFIG34[12,4]=10 PWM_OUT1 PWM 1 output O SYSTEM_CONFIG34[13,5]=10 PWM_COMPARE_OUT1 PWM 1 compare output O SYSTEM_CONFIG34[14,6]=10 PWM_CAPTURE_IN1 PWM 1 compare output I Not required
Alternate 4 PWM 0, USB 1,2 Power ctrl
Configuration
Not required
DVO0[8] First DVO output O SYSTEM_CONFIG34[12,4]=00 DVO0[9] First DVO output O SYSTEM_CONFIG34[13,5]=00 DVO0[10] First DVO output O SYSTEM_CONFIG34[14,6]=00 DVO0[11] First DVO output O SYSTEM_CONFIG34[15,7]=00
USB1_PRT_OVCUR USB 1 PRT overcurrent I SYSTEM_CONFIG4[5]=0 USB1_PRT_PWR USB 1 PRT power O SYSTEM_CONFIG34[13,5]=11 USB2_PRT_OVCUR USB 2 PRT overcurrent
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I SYSTEM_CONFIG4[6]=0 USB2_PRT_PWR USB 2 PRT power O SYSTEM_CONFIG34[15,7]=11
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Caution: In case of USB signals, the usual naming convention is not used. In order to align with the STi7105 ballout names, this manual mentions two instances of USB as USB1 and USB2 rather than USB0 and USB1. Therefore, in this manual the first instance of USB is USB1 and the second instance is USB2.
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19.7
PIO5 alternate functions

PIO5 is on COMMS block. It provides: first digital video output (16-bit) DVO0 key scanner interface KEY SCAN UART3 interface main VTG synchronization signals
Table 104. PIO5 alternate functions

O SYSTEM_CONFIG35[8,0]=00 DVO0[13] First DVO output O O SYSTEM_CONFIG35[8,0]=01 O SYSTEM_CONFIG35[8,0]=10 UART3_RXD/KEY_SCAN_OUT[1] UART 3/Key scanning I/O In: Not required Out: SYSTEM_CONFIG35[9,1]=10 DVO0[12] First DVO output
Alternate 2 Key scanning I/F, UART 3

UART3_TXD UART 3
Alternate 3 UART 3, Key scanning

KEY_SCAN_OUT[0] Key scanning
Alternate 4 Main video timing h/v refs
Configuration
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O SYSTEM_CONFIG35[10,2]=00 DVO0[15] First DVO output O O SYSTEM_CONFIG35[10,2]=01 O SYSTEM_CONFIG35[10,2]=10 UART3_CTS/KEY_SCAN_OUT[3] UART 3/Key scanning I/O In: Not required Out: SYSTEM_CONFIG35[11,3]=10 KEY_SCAN_IN[0] Key scanning I Not required KEY_SCAN_IN[1] Key scanning VTG_MAIN_HS VTG main O SYSTEM_CONFIG35[12,4]=11 DVO0[14] First DVO output
STi7105

UART3_RTS UART 3

KEY_SCAN_OUT[2] Key scanning
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Configuration
DVO0_HSYNC First DVO output O SYSTEM_CONFIG35[12,4]=00 DVO0CLK First DVO output O SYSTEM_CONFIG35[13,5]=00 DVO0_VSYNC First DVO output O SYSTEM_CONFIG35[14,6]=00
I Not required KEY_SCAN_IN[2] Key scanning I Not required VTG_MAIN_VS VTG main O SYSTEM_CONFIG35[14,6]=11
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Config register: SYSTEM_CONFIG35[15:0] PIO5 Config bus: PIO5_ALTFOP[1:0]_MUX_SEL_BUS[7:0] PIN Parameter Alternate 1 Digital video output 0 Name Description PIO5[7] Direction Configuration
O SYSTEM_CONFIG35[15,7]=00 I Not required O SYSTEM_CONFIG35[15,7]=11 DVO0_DATA_EN First DVO output
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KEY_SCAN_IN[3] Key scanning

VTG_MAIN_BOTNOTTOP VTG main
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PIO6 is on COMMS block. It provides: digital video port (8-bit) DVP0 third transport input interface TSIN2 second PCMCIA interface input VTG synchronization signals EMI SS arbiter signals/PCI support EMI SS arbiter signals Table 105. PIO6 alternate functions
Config register: SYSTEM_CONFIG36[15:0] PIO6 Config bus: PIO6_ALTFOP[1:0]_MUX_SEL_BUS[7:0] PIN Parameter Alternate 1 Alternate 2 Alternate 3 PCI I/F, PCMCIA 2 i/F, Video input timing h/v refs
PCI_INT_TO_HOST PCI host O SYSTEM_CONFIG36[16,8,0]=0 10
STi7105
Alternate 4
Alternate 5 PCI I/F, EMI I/F

PCI_INT_FROM_DEVICE[0] PCI device I
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Digital video input 0, PCMCIA 2 Transport stream input 2 I/F Name Description PIO6[0] Direction
DVP0[0]/PCMCIA2_OE DVP input/ PCMCIA 2 I/F I/O In: Not required Out: SYSTEM_CONFIG36[16,8,0]=000 DVP0[1]/PCMCIA2_WE DVP input/ PCMCIA 2 I/F I/O In: Not required Out: SYSTEM_CONFIG36[17,9,1]=000 TSIN2SER/DATA[7] TS2 input I
Configuration
SYSTEM_CONFIG4[10]=0
TSIN2BYTECLK TS2 input I
PCI_INT_FROM_DEVICE[1] PCI device I
Configuration
Not required
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Config register: SYSTEM_CONFIG36[15:0] PIO6 Config bus: PIO6_ALTFOP[1:0]_MUX_SEL_BUS[7:0] PIN Parameter Alternate 1 Alternate 2 Alternate 3 PCI I/F, PCMCIA 2 i/F, Video input timing h/v refs Alternate 4 Alternate 5 PCI I/F, EMI I/F
PCI_INT_FROM_DEVICE[2] PCI Host/device I
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Digital video input 0, PCMCIA 2 Transport stream input 2 I/F Name Description PIO6[2] Direction
DVP0[2]/PCMCIA2_IORD DVP input/PCMCIA 2 i/F I/O In: Not required Out: SYSTEM_CONFIG36[18,10,2]=000 DVP0[3]/PCMCIA2_IOWR DVP input/PCMCIA 2 I/F I/O In: Not required Out: SYSTEM_CONFIG36[19,11,3]=000 DVP0[4] DVP input I Not required DVP0[5] DVP input I Not required TSIN2BYTECLKVALID TS2 input I
Configuration
Not required
TSIN2ERROR TS2 input I
Configuration
Name Description PIO6[4] Direction Configuration Name Description PIO6[5] Direction Configuration
TSIN2PACKETCLK TS2 input I In: SYSTEM_CONFIG4[10]=0 TSIN2DATA[6] TS2 input I In: SYSTEM_CONFIG4[10]=0
PCMCIA2_WAIT PCMCIA 2 I/F I Not required PCMCIA_INT PCMCIA 2 I/F I Not required PCI_BUS_REQ[1] PCI Host/device I Not required
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Config register: SYSTEM_CONFIG36[15:0] PIO6 Config bus: PIO6_ALTFOP[1:0]_MUX_SEL_BUS[7:0] PIN Parameter Alternate 1 Alternate 2 Alternate 3 PCI I/F, PCMCIA 2 i/F, Video input timing h/v refs
VTG_IN_HS VTG input lock I Not required VTG_IN_VS VTG I Not required
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Alternate 4

PCI_BUS_REQ[2] PCI Host/device I Not required
Digital video input 0, PCMCIA 2 Transport stream input 2 I/F Name Description PIO6[6] Direction Configuration Name Description PIO6[7] Direction Configuration
DVP0[6] DVP input I Not Required DVP0[7] DVP input I Not required TSIN2DATA[5] TS2 input I In: SYSTEM_CONFIG4[10]=0 TSIN2DATA[4] TS2 input I In: SYSTEM_CONFIG4[10]=0
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PIO7 is PIO0 on GPIO standalone block. It provides: digital video port (8-bit) DVP0 third transport input interface TSIN2 MII and RMII interfaces key scanner interface KEY SCAN EMI SS arbiter signals/PCI support EMI SS arbiter signals Note: During reset PIO7[7:4] are in input mode for mode pin capture.
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Config register: SYSTEM_CONFIG37[15:0] PIO7 Config bus: PIO7_ALTFOP[1:0]_MUX_SEL_BUS[7:0] PIN Parameter Alternate 1 Digital video input 0 Name Description PIO7[0] Direction
DVP0_HSYNC DVP input I
Alternate 2 Transport stream input 2

TSIN2DATA[3] TS2 input I SYSTEM_CONFIG4[10]=0 TSIN2DATA[2] TS2 input I SYSTEM_CONFIG4[10]=0
Alternate 3 Key scanning

KEY_SCAN_OUT[0] Key scanning O SYSTEM_CONFIG37[16,8,0]=01 0 KEY_SCAN_OUT[1] Key scanning O
Alternate 4 PCI I/F

PCI_LOCK_IN PCI Host/device I SYSTEM_CONFIG5[25]=0
Configuration Not required Name Description PIO7[1] Direction

DVP0_VSYNC DVP input I
PCI_BUS_GNT[1] PCI Host/device O
PCI_BUS_GNT[1] PCI host/device O SYSTEM_CONFIG37[17,9,1]=1 00
Configuration Not required
Out: SYSTEM_CONFIG37[17,9,1]=01 SYSTEM_CONFIG37[17,9,1]= 0 011
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Config register: SYSTEM_CONFIG37[15:0] PIO7 Config bus: PIO7_ALTFOP[1:0]_MUX_SEL_BUS[7:0] PIN Parameter Alternate 1 Digital video input 0 Name Description PIO7[2] Direction
DVP0_CLK DVP input I
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TSIN2DATA[1] TS2 input I SYSTEM_CONFIG4[10]=0 TSIN2DATA[0] TS2 input I SYSTEM_CONFIG4[10]=0

KEY_SCAN_OUT[2] Key scanning O
Alternate 4 PCI I/F

PCI_BUS_GNT[2] PCI Host/device O

PCI_BUS_GNT[2] PCI Host/device O SYSTEM_CONFIG37[18,10,2]= 101
Configuration Not required Name Description
Out: SYSTEM_CONFIG37[18,10,2]=0 SYSTEM_CONFIG37[18,10,2] 10 =011 KEY_SCAN_OUT[3] Key scanning O SYSTEM_CONFIG37[19,11,3]=0 10
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PIO7[3]
Direction Configuration Name Description Direction

MIIRX_DV/MII_EXCRS MII receive data valid I/O In: Not required Out: SYSTEM_CONFIG37[20,12,4]=0 00 MIIRX_ER/MII_EXCOL MII receive error I/O In: Not required Out: SYSTEM_CONFIG37[21,13,5]=0 00
RMIICRS_DV RMII receive data valid I
PIO7[4] Configuration
RMIIRX_ER RMII receive error I
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Config register: SYSTEM_CONFIG37[15:0] PIO7 Config bus: PIO7_ALTFOP[1:0]_MUX_SEL_BUS[7:0] PIN Parameter Alternate 1 Digital video input 0 Name Description PIO7[6] Direction Configuration Name Description PIO7[7] Direction Configuration
MIITXD[0] MII transmit data O SYSTEM_CONFIG37[22,14,6]=0 00 MIITXD[1] MII transmit data O SYSTEM_CONFIG37[23,15,7]=0 00
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RMIITXD[0] RMII transmit data O SYSTEM_CONFIG37[22,14,6]= 001 RMIITXD[1] RMII transmit data O SYSTEM_CONFIG37[23,15,7]= 001
Alternate 4 PCI I/F
STi7105
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PIO8 is PIO1 on GPIO standalone block. It provides: MII and RMII interfaces DVO1 ALPHA coefficient output Note: During reset PIO8[7:0] are in input mode for mode pin capture. STi7105

Config register: SYSTEM_CONFIG46[15:0] PIO8 Config bus: PIO8_ALTFOP[1:0]_MUX_SEL_BUS[7:0] PIN Parameter Alternate 1 MII I/F Name
MIITXD[2] MII transmit data O SYSTEM_CONFIG46[8,0]=00 MIITXD[3] MII transmit data O SYSTEM_CONFIG46[9,1]=00 MIITX_EN MII TX Enable O SYSTEM_CONFIG46[10,2]=00
Alternate 2 RMII I/F, Digital video output 1

DVO1_ALPHA[0] Second DVO/Alpha output O SYSTEM_CONFIG46[8,0]=01 DVO1_ALPHA[1] Second DVO/Alpha output O SYSTEM_CONFIG46[9,1]=01 RMIITX_EN
Alternate 3
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Description PIO8[0] Direction Configuration Name Description PIO8[1] Direction Configuration Name Description PIO8[2] Direction Configuration
RMII TX Enable O SYSTEM_CONFIG46[10,2]=01
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Config register: SYSTEM_CONFIG46[15:0] PIO8 Config bus: PIO8_ALTFOP[1:0]_MUX_SEL_BUS[7:0] PIN Parameter Alternate 1 MII I/F Name Description PIO8[3] Direction
MIIMDIO MII mgmt data I/O In: Not required Out: SYSTEM_CONFIG46[11,3]=00 MIIMDCI/MIIMDCO MII Mgmg Clock input/output I/O In: Not required Out: SYSTEM_CONFIG46[12,4]=00 MIIRXCLK MII receive clock for RXD I Not required MIIRXD[0] MII receive data I Not required MIIRXD[1] MII receive data I Not required
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RMIIMDIO RMII mgmt data I/O In: Not required Out: SYSTEM_CONFIG46[11,3]=01 RMIIMDC RMII Mgmg Clock O
Alternate 3
Configuration
Configuration
DVO1_ALPHA[2] Second DVO/Alpha output O SYSTEM_CONFIG46[13,5]=01 RMIIRXD[0] RMII receive data I Not required RMIIRXD[1] RMII receive data
STi7105
I Not required
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PIO9 is PIO2 on GPIO standalone block. It provides: MII and RMII interfaces DVO1 ALPHA coefficient output Note: During reset PIO9[6, 1:0] are in input mode for mode pin capture. STi7105

Config register: SYSTEM_CONFIG47[15:0] PIO9 Config bus: PIO9_ALTFOP[1:0]_MUX_SEL_BUS[7:0] PIN Parameter Alternate 1 MII I/F Name
MIIRXD[2] MII receive data I Not required MIIRXD[3] MII receive data I Not required MIITXCLK MII Transmit clock for TXD I Not required MIICOL MII collision detected I Not required

DVO1_ALPHA[3] Second DVO/Alpha output O SYSTEM_CONFIG47[8,0]=01 DVO1_ALPHA[4] Second DVO/Alpha output O SYSTEM_CONFIG47[9,1]=01 DVO1_ALPHA[5]
Alternate 3
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Description PIO9[0] Direction Configuration Name Description PIO9[1] Direction Configuration Name Description PIO9[2] Direction Configuration Name Description PIO9[3] Direction Configuration
Second DVO/Alpha output O SYSTEM_CONFIG47[10,2]=01 DVO1_ALPHA[6] Second DVO/Alpha output O SYSTEM_CONFIG47[11,3]=01
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Config register: SYSTEM_CONFIG47[15:0] PIO9 Config bus: PIO9_ALTFOP[1:0]_MUX_SEL_BUS[7:0] PIN Parameter Alternate 1 MII I/F Name Description PIO9[4] Direction Configuration Name Description PIO9[5] Direction
I Not required MIIPHYCLK Clock to PHY O O SYSTEM_CONFIG47[12,4]=01 RMIIREF_CLK RMII REF CLOCK I/O In: Not required Out: SYSTEM_CONFIG47[13,5]=01 RMIIMDINT RMII Mgmt data interrupt I Not required MIICRS MII carrier sense detected
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DVO1_ALPHA[7] Second DVO/Alpha output
Alternate 3
Configuration
Name Description PIO9[6] Direction Configuration Name Description PIO9[7] Direction
MIIMDINT Mgmt data interrupt I Not required HDMI_PLUGIN/MDO_EN HDMI, MDO I/O In: Not required Out: SYSTEM_CONFIG47[15,7]=00
Configuration
STi7105
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PIO10 is PIO3 on GPIO standalone block. It provides: multichannel digital audio PCM output AUDDIG1PCMOUT audio S/PDIF output S/PDIF stereo digital Audio PCM input AUDDIG Table 109. PIO10 alternate functions
Config register: Not required PIO10 Config bus: Not required PIN Parameter Alternate 1 Digital audio output 0, SPDIF I/F, Audio digital input 0 Name
AUDDIG0_PCM_OUT_DATA0 PCMOUT 0 - data 0 O Not required AUDDIG0_PCM_OUT_DATA1 PCMOUT 0 - data 1 O Not required PCI_IDSEL/AUDDIG0_PCM_OUT_DATA2 PCI, PCMOUT 0 - data 2 I/O Not required AUDDIG0_PCM_OUT_CLKIN/CLK PCMOUT 0 - clock I/O Not required
STi7105
Alternate 2
Alternate 3
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Config register: Not required PIO10 Config bus: Not required PIN Parameter Alternate 1 Digital audio output 0, SPDIF I/F, Audio digital input 0 Name Description PIO10[4] Direction Configuration Name Description PIO10[5] Direction
O Not required AUD_SPDIF_OUT SPDIF out O Not required AUDDIG0_PCM_DATAIN/AUDDIG1_PCM_OUT_DATA0 PCMIN0/PCMOUT1 - data I/O Not required O Not required AUDDIG0_PCM_OUT_SCLK PCMOUT0 - SCLK AUDDIG0_PCM_OUT_LRCLK PCMOUT0 - LRCLK
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Alternate 2
Alternate 3
STi7105
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PIO11 is PIO4 on GPIO standalone block. It provides: stereo digital audio PCM input AUD0PCMIN stereo digital audio PCM output AUD1PCMOUT Note: PIO11 alternate function is controlled by SYS_CFG5[29] STi7105

Config register: Not required PIO11 Config bus: Not required PIN Parameter Alternate 1 Digital audio input 0 Name
AUDDIG0_PCM_STRBIN/AUDDIG1_PCM_OUT_LRCLK PCMIN0 - SCLK/PCMOUT1 - LRCLK I/O Not required AUDDIG0_PCM_LRCLKIN/AUDDIG1_PCM_OUT_SCLK PCMIN0 - LRCLK/PCMOUT1 - SCLK I/O Not required
Alternate 2 Genlock
Alternate 3
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Config register: Not required PIO11 Config bus: Not required PIN Parameter Alternate 1 Digital audio input 0 Name Description PIO11[4] Direction Configuration Name Description PIO11[5] Direction
I Not required VSYNC_FROM_PAD Genlock I Not required HSYNC_FROM_PAD Genlock I Not required PIXCLK_FROM_PAD Genlock
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Alternate 2 Genlock
Alternate 3
STi7105
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PIO12 is PIO5 on GPIO standalone block. It provides: second transport input TSIN1 transport output TSOUT SSC2 interface with I2C half-duplex modes selectable UART2 interface USB1 power control fourth transport input TSIN3 (serial only) Table 111. PIO12 alternate functions
Config register: SYSTEM_CONFIG48[23:0] PIO12 Config bus: PIO12_ALTFOP[2:0]_MUX_SEL_BUS[7:0] PIN Parameter Alternate 1 Transport stream input 1 Name Description PIO12[0] Direction
TSIN1SER/DATA[7] TS1 input I
STi7105
Alternate 2 Transport stream input

TSOUTSER/DATA[7] TS output O
Alternate 3 SSC 2, USB 1 power ctrl

SSC2_SCL SSC2 serial clock in/out I/O In: SYSTEM_CONFIG16[12,11]=10 Out: SYSTEM_CONFIG48[16,8,0]=010 SSC2_MTSR SSC2_MRST
Alternate 4 Transport stream input 3, UART2, SSC2

SSC2_SCL SSC2 serial clock out O SYSTEM_CONFIG48[16,8,0] =011 UART2_RXD
Alternate 5 UART2
UART2_TXD UART O SYSTEM_CONFIG48[16,8,0]= 100
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Configuration
SYSTEM_CONFIG4[9]=0 SYSTEM_CONFIG48[16,8,0]=001
Name
TSIN1BYTECLK
TSOUTBYTECLK
Description
TS1 input
TS output
SSC2 Data bit: SSC2 Data bit: master master receive/slave transmit/slave transmit, full receive, full duplex duplex I/O In: SYSTEM_CONFI G16[10,9]=10 Out: SYSTEM_CONFI G48[17,9,1]=010 I
UART
PIO12[1]
Direction
I/O
Configuration
In: Not required SYSTEM_CONFIG4[9]=0 Out: SYSTEM_CONFIG48[17,9,1]=001
SYSTEM_CONFI G16[8,7]=10
Not required
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Config register: SYSTEM_CONFIG48[23:0] PIO12 Config bus: PIO12_ALTFOP[2:0]_MUX_SEL_BUS[7:0] PIN Parameter Alternate 1 Transport stream input 1 Name Description PIO12[2] Direction Configuration Name Description PIO12[3]
I O I Not required UART2_RTS UART O SYSTEM_CONFIG48[19,11,3] =100 SYSTEM_CONFIG4[9]=0 SYSTEM_CONFIG48[18,10,2]=001 TSIN1ERROR TS1 input I TSOUTERROR TS output O TSIN1BYECLKVALID TS1 input
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TSOUTBYTECLKVALID TS output

UART2_CTS UART
Alternate 5 UART2
Direction Configuration Name Description
SYSTEM_CONFIG4[9]=0 SYSTEM_CONFIG48[19,11,3]=001 TSIN1PACKETCLK TS1 input I TSOUTPACKETCLK TS output O
PIO12[4] Direction Configuration Name Description PIO12[5] Direction Configuration Name Description PIO12[6] Direction Configuration
I O O I Not required SYSTEM_CONFIG4[9]=0 SYSTEM_CONFIG48[22,14,6]=001 SYSTEM_CONFIG48[22,14,6]=010 I O I I Not required TSIN3BYTECLK TS3 input SYSTEM_CONFIG4[9]=0 SYSTEM_CONFIG48[21,13,5]=001 SYSTEM_CONFIG4[5]=1 TSIN1DATA[5] TS1 input TSOUTDATA[5] TS output USB1_PRT_PWR USB 1 PRT power SYSTEM_CONFIG4[9]=0 SYSTEM_CONFIG48[20,12,4]=001 TSIN1DATA[6] TS1 input TSOUTDATA[6] TS output USB1_PRT_OVCUR USB 1 PRT overcurrent TSIN3SER/DATA[7] TS3 input
STi7105
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Config register: SYSTEM_CONFIG48[23:0] PIO12 Config bus: PIO12_ALTFOP[2:0]_MUX_SEL_BUS[7:0] PIN Parameter Alternate 1 Transport stream input 1 Name Description PIO12[7] Direction Configuration
I O I Not required SYSTEM_CONFIG4[9]=0 SYSTEM_CONFIG48[23,15,7]=001 TSIN1DATA[4] TS1 input
STi7105

TSOUTDATA[4] TS output

TSIN3BYTECLKVALID TS3 input
Alternate 5 UART2
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PIO13 is PIO6 on GPIO standalone block. It provides: second transport input TSIN1 first transport input TSIN0 fourth transport input TSIN3 (serial only) transport output TSOUT pulse width modulator interface PWM SSC2 and SSC3 interfaces with I2C half-duplex modes selectable Table 112. PIO13 alternate functions
Config register: SYSTEM_CONFIG49[23:0] PIO13 Config bus: PIO13_ALTFOP[2:0]_MUX_SEL_BUS[7:0] PIN Parameter Alternate 1 Transport stream input 0,1 Name Description PIO13[0] Direction Configuration Name Description PIO13[1] Direction Configuration
TSIN1DATA[3] TS1 input I
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Alternate 2 Transport stream output, ssc 2,3

TSOUTDATA[3] TS output O
Alternate 3 Transport stream output, ssc 3

Alternate 4 Transport stream input 3, PWM 0,1

TSIN3ERROR/PWM_OUT0 TS3 input/PWM out I/O
Alternate 5 PWM 0,1, SSC3

PWM_OUT0 PWM out O
Not required
SYSTEM_CONFIG49[16,8,0]=001
In: Not required SYSTEM_CONFIG49[16,8,0]= SYSTEM_CONFIG49[16,8,0]=010 Out: 100 SYSTEM_CONFIG49[16,8,0]=011 TSOUTDATA[2] TS output O TSIN3PACKETCLK/PWM_OUT1 TS3 input I/O PWM_OUT1 PWM out O
Not required
In: SYSTEM_CONFIG49[17,9,1]= Not required 100 Out: SYSTEM_CONFIG49[17,9,1]=011
STi7105
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Config register: SYSTEM_CONFIG49[23:0] PIO13 Config bus: PIO13_ALTFOP[2:0]_MUX_SEL_BUS[7:0] PIN Parameter Alternate 1 Transport stream input 0,1 Name Description PIO13[2] Direction
STi7105


SSC3_SCL/TSOUTDATA[1] SSC3 input/TS output I/O

SSC3_SCL SSC3 output O

SSC3_SCL SSC3 output O
Configuration
Not required
In: SYSTEM_CONFIG16[19:18]=10 SYSTEM_CONFIG49[18,10,2]=01 SYSTEM_CONFIG49[18,10,2] Out: 1 =100 SYSTEM_CONFIG49[18,10,2]=01 0 SSC3_MTSR/SSC3_MRST/TSOU SSC3_MTSR TDATA[0] SSC3 Data bit: master transmit/slave receive, full duplex/TS output I/O SSC3 Data bit: master receive/slave transmit, full duplex O O SSC3_MTSR
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TSIN1DATA[0]
TSOUTDATA[0]
TS1 input I
TS output O
Configuration
Not required
In: SYSTEM_CONFIG16[17,16]=10/ SYSTEM_CONFIG16[15,14]=10 SYSTEM_CONFIG49[19,11,3]=01 SYSTEM_CONFIG49[19,11,3] Out: 1 =100 SYSTEM_CONFIG49[19,11,3]=01 0 SSC2_SCL
Name Description PIO13[4] Direction Configuration
SSC2_SCL SSC2 serial clock in/out I/O In: SYSTEM_CONFIG16[12,11]=11 Out: SYSTEM_CONFIG49[20,12,4]=001
SSC2 serial clock out O SYSTEM_CONFIG49[20,12,4]=01 0
Not required
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Config register: SYSTEM_CONFIG49[23:0] PIO13 Config bus: PIO13_ALTFOP[2:0]_MUX_SEL_BUS[7:0] PIN Parameter Alternate 1 Transport stream input 0,1 Name
TSIN0BYTECLK
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SSC2_MTSR SSC2 Data bit: master transmit/slave receive, full duplex I/O In SYSTEM_CONFI G16[10,9]=11 Out: SYSTEM_CONFI G49[21,13,5]=001 SSC3_SCL SSC3 serial clock in/out I/O In: SYSTEM_CONFI G16[19,18]=11 Out: SYSTEM_CONFI G49[22,14,6]=001 SSC2_MRST SSC2 Data bit: master receive/slave transmit, full duplex I

SSC2_MRST
Description PIO13[5]
TS input
Direction
I/O In: Not required Out: SYSTEM_CONFIG49[ 21,13,5]=000 TSIN0BYTECLKVALID TS0 input I
Configuration
SYSTEM_CONFIG49[21,13,5]=01 0
SSC3_SCL SSC3 serial clock out O
Not required
STi7105
Confidential
Config register: SYSTEM_CONFIG49[23:0] PIO13 Config bus: PIO13_ALTFOP[2:0]_MUX_SEL_BUS[7:0] PIN Parameter Alternate 1 Transport stream input 0,1 Name
TSIN0ERROR
STi7105

SSC3_MTSR SSC3 Data bit: master transmit/slave receive, full duplex I/O In: SYSTEM_CONFI G16[17,16]=11 Out: SYSTEM_CONFI G49[23,15,7]=001 SSC3_MRST SSC3 Data bit: master receive/slave transmit, full duplex I

SSC3_MRST
Description PIO13[7]
TS0 input
SSC3 Data bit: master receive/slave transmit, full duplex
Direction
Configuration
Not required
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PIO14 is PIO7 on GPIO standalone block. It provides: first transport input TSIN0 third transport input in serial mode only TSIN2 (serial only) USB2 power control Table 113. PIO14 alternate functions
Config register: Not required PIO14 Config bus: Not required PIN Parameter Alternate 1 Transport stream input 0 Name Description PIO14[0] Direction Configuration Name Description PIO14[1] Direction Configuration Name Description PIO14[2] Direction Configuration Name Description PIO14[3] Direction Configuration
I Not required I SYSTEM_CONFIG4[10]=1 I Not required TSIN0DATA[5] TS 0 input I Not required TSIN0DATA[4] TS 0 input I SYSTEM_CONFIG4[10]=1 TSIN2BYTECLK TS 2 input I In: SYSTEM_CONFIG4[10]=1 TSIN2BYTECLKVALID TS 2 input I Not required TSIN0DATA[6] TS 0 input TSIN2SER/DATA[7] TS 2 input TSIN0PACKETCLK TS 0 input
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Alternate 2 Transport stream input 2, USB 2 power ctrl
Alternate 3
Alternate 4
Alternate 5
STi7105
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Config register: Not required PIO14 Config bus: Not required PIN Parameter Alternate 1 Transport stream input 0 Name Description PIO14[4] Direction Configuration Name Description PIO14[5] Direction Configuration Name Description PIO14[6] Direction Configuration Name Description PIO14[7] Direction Configuration
I Not required O Not required I Not required TSIN0DATA[0] TS 0 input I SYSTEM_CONFIG4[10]=1 USB2_PRT_PWR USB2 PRT power I Not required TSIN0DATA[1] TS 0 input I SYSTEM_CONFIG4[10]=1 USB2_PRT_OVCUR USB2 PRT overcurrent I Not required TSIN0DATA[2] TS 0 input I SYSTEM_CONFIG4[10]=1 TSIN2PACKETCLK TS 2 input TSIN0DATA[3] TS 0 input
STi7105
Alternate 2 Transport stream input 2, USB 2 power ctrl

TSIN2ERROR TS 2 input
Alternate 3
Alternate 4
Alternate 5
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PIO15 is PIO8 on GPIO standalone block. It provides: SPI boot interface EMI SS arbiter signals/PCI support PCI interface Table 114. PIO15 alternate functions
Config register: SYSTEM_CONFIG50[15:0] PIO15 Config bus: PIO15_ALTFOP[1:0]_MUX_SEL_BUS[7:0] PIN Parameter Alternate 1 Serial peripheral I/F Name
SPIBOOT_CLOCK SPI O SYSTEM_CONFIG50[8,0]=00 SPIBOOT_DATA_OUT SPI O SYSTEM_CONFIG50[9,1]=00 SPIBOOT_CS SPI O
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TSIN1PACKETCLK TS1 input I SYSTEM_CONFIG4[9]=1 TSIN1BYTECLK TS1 input I SYSTEM_CONFIG4[9]=1 TSIN1BYTECLKVALID TS1 input I
Alternate 4
Description PIO15[0] Direction Configuration Name Description PIO15[1] Direction Configuration Name Description PIO15[2] Direction
EMI_SS_BUS_FREE_ACCESSPEND/EMI_SS_BU S_FREE_OUT EMI I/F I/O In: Not required Out: SYSTEM_CONFIG50[10,2]=10
EMI_SS_BUS_FREE_OUT EMI I/F O
Configuration
SYSTEM_CONFIG4[9]=1
STi7105
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Config register: SYSTEM_CONFIG50[15:0] PIO15 Config bus: PIO15_ALTFOP[1:0]_MUX_SEL_BUS[7:0] PIN Parameter Alternate 1 Serial peripheral I/F Name Description PIO15[3] Direction
SPIBOOT_DATA_IN SPI I
STi7105

TSIN1ERROR TS1 input I

PCI_INT_FROM_DEVICE[0]/PCI_INT_TO_HOST PCI host/device I/O In: SYSTEM_CONFIG5[27]=1 Out: SYSTEM_CONFIG50[11,3]=10 PCI_SYSTEM_ERROR PCI Host/device I/O In: Not required Out: SYSTEM_CONFIG50[12,4]=10 PCI_LOCK_IN PCI Host/device I SYSTEM_CONFIG5[25]=1 PCI_PME_IN PCI Host/device I Not required PCI_RESETN_FROM_HOST_TO_DEVICE PCI Host/device I Not required
Alternate 4
PCI_INT_TO_HOST PCI Host O
Configuration
Not required
SYSTEM_CONFIG4[9]=1
PCI_SYSTEM_ERROR PCI Host/device O
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Configuration
SYSTEM_CONFIG4[9]=1
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PIO16 is PIO9 on GPIO standalone block. It provides: MPEG recovered clock Note: During reset PIO16[6:0] is in input mode for mode pin capture. Table 115. PIO16 alternate functions
Config register:Not required PIO16 Config bus:Not required Alternate 1 Name PIO16[0] Description Direction Configuration RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED Alternate 2
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Name PIO16[1] Description Direction Configuration Name PIO16[2] Description Direction Configuration Name PIO16[3] Description Direction Configuration Name PIO16[4] Description Direction Configuration
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Config register:Not required PIO16 Config bus:Not required Alternate 1 Name PIO16[5] Description Direction Configuration Name PIO16[6] Description Direction Configuration Name PIO16[7] Description Direction Configuration RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED MPEG_RECOVERED_CLOCK MPEG recovered clock O Not required RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED Alternate 2
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Licenses
STi7105
20
Licenses
Supply of this product does not convey a license under the relevant intellectual property of the companies mentioned in this chapter nor imply any right to use this intellectual property in any finished end-user or ready to use final product. An independent license for such use is required and can be obtained by contacting the company or companies concerned. Once the license is obtained, a copy must be sent to STMicroelectronics. The details of all the features requiring licenses are not provided within the datasheet and register manual. They are provided only after a copy of the license has been received by STMicroelectronics. The features requiring licenses include:
CSS
CSS DVD Copy Protection is intellectual property of Matsushita Electronics Industrial Co. The CSS DVD Copy Protection license allows the use of the CSS decryption cell embedded in the STi7105.
Confidential
For all details, contact Matsushita at: Matsushita Electronics Industrial Co. LTD, CSS Interim License Organization, 1006 Kadoma, Kadoma-Shi, Osaka 571-8503 JAPAN
Dolby Digital EX, Pro Logic II, MLP Lossless

Dolby Digital, Pro Logic and MLP Lossless are intellectual properties of Dolby Labs. The Dolby Digital, Pro Logic or MLP Lossless license allows the use of the corresponding decoder embedded in the STi7105. Two types of license exist: S license must be obtained for samples (up to 25 units). P license must be obtained for production. For all details, contact Dolby Labs at: Dolby Labs, 100 Potrero Avenue, San Francisco, CA 94103, USA
Macrovision
Macrovision Anti-Copy System for DVD is intellectual property of Macrovision Corporation. The Macrovision license allows the use of the Macrovision feature embedded in STi7105. For all details, contact Macrovision at: Macrovision Corp., 1341 Orlean Drive, Sunnyvale, CA 94089 USA
Dwight Cavendish
The STi7105 is enabled with the Dwight Cavendish copy protection process. Activation of the Dwight Cavendish copy protection is subject to Dwight Cavendish Intellectual Property Rights and is not permitted otherwise than with an express written licence from Dwight Cavendish. For more details, click www.dwightcav.com
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Licenses
TruSurround XT, CircleSurround II

The CircleSurround II, TruSurround XT and SRS technology rights incorporated in this chip are owned by SRS Labs, a U.S. corporation and licensed to ST Microelectronics. Purchasers of this chip, who use the SRS technology incorporated herein, must sign a license for use of the chip and display of the SRS trademarks. Any product using the SRS technology incorporated in this chip must be sent to SRS Labs for review. Circle Surround II, TruSurround XT and SRS are protected under U.S. and foreign patents issued and/or pending. Neither the purchase of this chip, nor the corresponding sale of audio enhancement equipment conveys the right to sell commercialized recordings made with any SRS technology. SRS requires all set makers to comply with all rules and regulations as outlined in the SRS Trademark Usage Manual. For all details, contact SRS Labs at: SRS Labs Inc., 2909 Daimler Street, Santa Ana, CA 92705 USA
DTS (ES, 96/24, Neo)

DTS ES, DTS 96/24 and DTS Neo are intellectual properties of Digital Theater Systems Inc. The DTS licenses allow the use of the corresponding decoder executed in the STi7105.
For all details, contact Digital Theater Systems Inc at: DTS, 5171 Clareton Drive, Agoura Hills, CA 91301, USA
CPRM/CPPM
CPRM/CPPM technology is intellectual property of 4C Entity. The CPRM/CPPM license allows the use of the CPRM/CPPM technology embedded in the STi7105. For all details, contact 4C Entity at: 4C Entity, LLC, 225 B Cochrane Circle, Morgan Hill, CA 95037, USA
Windows Media (audio [WMA] and video [WMV])

Windows Media is intellectual property of Microsoft Corporation. The Windows Media license allows the use of the Windows Media audio and video decoders executed in the STi7105. For all details, contact Microsoft at: Microsoft Corporation, One Microsoft Way, Redmond, WA 98052-6399, USA
USB (Universal Serial Bus)

USB is intellectual property of USB-IF. The USB license gives the right to display the certified USB logo with a product when the product has passed USB-IF compliance testing for product quality. For all details, contact USB-IF: USB Implementers Forum, Inc., 5440 SW Westgate Drive, Suite 217, Portland, OR 97221, USA
HDMI (High-definition multimedia interface)

HDMI and High-definition multimedia interface are intellectual properties of HDMI Licensing, LLC. The HDMI license allows the use of HDMI in the STi7105.
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Licenses For all details, contact HDMI Licensing, LLC at: 1060 E. Arques Avenue, Suite 100, Sunnyvale, CA 94085, USA
STi7105
HDCP
HDCP is an intellectual property of Digital Content Protection, LLC. The HDCP license allows the use of HDCP in the STi7105. For all details, contact Digital Content Protection, LLC at: C/O Intel Corporation, Stephen Balogh, JF2-55, 2111 NE 25th Ave, Hillsboro, OR 97124
AACS
Information classified Confidential - Do not copy (See last page for obligations) AACS is an intellectual property of Koninklijke Philips Electronics N.V. For all details, contact AACS LA, LLC at: c/o AACS Administration, 5440 SW Westgate Drive, Suite 217, Portland, Oregon 97221
AAC
AAC is an intellectual property of Fraunhofer Institut Integrierte Schaltungen. For all details, contact Fraunhofer Institute IIS, Am Wolfsmantel 33, 91058 Erlangen, Germany.
Confidential
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Revision history
21
Revision history
Table 116. Document revision history

Date Revision Changes
Changes: -- The Figure 1 is updated. -- In Figure 3, STV6440AJ replaces the devices TSH94 & TSH110. -- In Figure 33, mux_2 is moved from TSIN2 path to TSIN3 path. -- The ClockGen B block diagram (Figure 29) is updated. -- The SYSTEM_CONFIG5(16) bit is made reserved. -- Pins and signal names with prefix USB0 and USB1 are changed to USB1 and USB2 respectively throughout in the datasheet. -- The DEVICE_ID register is updated for the reset value. -- The de-ringing feature is removed from the corresponding sections. -- The SYSTEM_CONFIG16 register definition is updated. -- PIO tables for SSC2/SSc3 input configuration are updated. -- The Figure 34: Oscillator recommended external circuitry is updated. -- The Table 32.: Pad reset conditions is updated. Changes: --PIO tables in Chapter 19: Alternate functions on PIO are updated. --References to TSOUT1 and TSOUT2 are removed from PIO tables. --The value of external resistors for VIDA0_REXT and VID1_REXT is changed to 7.81 kohm in Section 6.5: Display analog output interface. --Mention of DVO1HS/DVO1VS is swapped in Chapter 19: Alternate functions on PIO. Now, PIO3[0]=DVO1HS and PIO3[2]=DVO1VS --Mode pin 13 functionality to select 8/16 bits is chnaged to0: 16 bits and 1: 8 bitsin Chapter 13: Mode pins. --Bit field description for Mode pin 0 is changed to 0: SYSCLKINALT (Ext) and 1: Osc (SATA)in Chapter 13: Mode pins. --16 H/W perfect match MAC address filters in Chapter 3.14.2: Ethernet controller is changed to 32 H/W perfect match MAC address filters. --SYSCLKIN and SYSCLKOSC pins are changed to 2.5 V in Table 5. -- Updated electrostatic discharge voltage VESD_HBM (HBM modem) in Section 17.1: Absolute maximum ratings on page 242.
20-Feb-2009
Rev D
01-Dec-2008
Rev C
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Revision history Table 116. Document revision history (continued)

Date Revision Changes
Major changes: --Added Interrupt network, FDMA, system config, Low power mode, and Clocking chapters. --Renamed AF22 ball to GNDSATA instead of USB_GND1V2 in Figure 17.: Bottom-right quadrant, Table 3.: Pin list, and Table 4.: Power/ground pins. --Mentioned Dwight Cavendish for HDTV video output in 3.10.1: Main HDTV video output section. --Output Enable column is removed from 6.17: Pad reset conditions section of the connection chapter. --In Figure 34.: Oscillator recommended external circuitry of 16.2: System section, CL1 and CL2 are connected to GND not vdd2v5. --In 11.6.2: Reference clock, the reset value is sysclkaltin. --SBAG I/F information is removed from the datasheet due to security constraints. --The Chapter 16.1.2: Power-up recommendations section is updated by deleting the power-up sequence, and specifying no specific power-up sequence in STi7105. Initial release
STi7105
22-Aug-2008
Rev B
01-Jul-2008
Rev A
312/313
8065505 Rev D
Confidential
STi7105
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STi7105

Advanced HD decoding IC for STB

DDR1 DDR2 SDRAM

Serial ATA HDD, int/ext

Dual USB 2.0 hosts

Line side DAA

16/32 ST40-300 core 450 MHz UDI TMUs/INTC MMU LMI

Key Scan USB 2.0 USB 2.0 2x I/F SmCard

System side DAA

Clock gen and system services

Aux video display

TS TS TS TS IN0 IN2 IN3 IN1/OUT0

Resets/ clocks/ modes

Analog video output (HD/SD)

Digital Digital video video output 0 output 1

FLASH NOR/NAND SFLASH

System on chip subsystem overview . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.6 3.7 3.8 3.9

2D blitter display engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.12 3.13 3.14

Clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 System services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

BGA footprint and pin lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Pad reset conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Basic chip operating modes and multiplexing scenarios . . . . . . . . . . 98

Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Interrupt networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

10.2 10.3 10.4

Video decoder, display, and Comms clock generation (ClockGen B) 157

Audio clock generation (ClockGen C) . . . . . . . . . . . . . . . . . . . . . . . . . . 163

LMI memory clocks (ClockGen D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

MPEG clock recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Power-On-Reset and system reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Mode pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Low power control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

System config module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

External circuitry recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . 233

16.2 16.3 16.4

16.5 16.6 16.7 16.8 16.9

Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

SATA PHY electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

External memory interface (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

Timing interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

Digital PCM player output interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253

Transport stream input AC specification . . . . . . . . . . . . . . . . . . . . . . . . . 254

18.4 18.5 18.6

STi7105 Synchronous devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

18.7 18.8 18.9

Alternate functions on PIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

19.6 19.7 19.8 19.9

Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311

STi7105 programming manual

Graphics and display

Processors and memory

STi7105 Figure 1. Typical DVR cable STB with DOCSIS

MII USB ST8024 SMARTCARD

Cable tuner 2 x TSin Cable tuner

I2C 30 MHz I2C LMI

Description Figure 2. IP client

MII PHY TMDS/I2C HDMI