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1.8 - MOSFET MODELS

INTRODUCTION Objective The objective of this presentation is: 1.) Understand how the MOS transistor works 2.) Understand and apply the simple large signal model 3.) Understand and apply the small-signal model Outline MOS Structure and Operation Large Signal Model Small-Signal Model Capacitance Short Channel Large Signal Model Subthreshold Large Signal Model Summary

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MOS STRUCTURE AND OPERATION

Metal-Oxide-Semiconductor Structure
Bulk/Substrate

Source

p+

n+

,,, ,,,
Gate Drain
Polysilicon

Thin Oxide (10-100nm 100-1000)

n+

p- substrate

Heavily Doped p

Lightly Doped p

Intrinsic Doping

Lightly Doped n

Heavily Metal Doped n Fig1.8-1

Terminals: Bulk - Used to make an ohmic contact to the substrate Gate - The gate voltage is applied in such a manner as to invert the doping of the material directly beneath the gate to form a channel between the source and drain. Source - Source of the carriers flowing in the channel Drain - Collects the carriers flowing in the channel

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Formation of the Channel for an Enhancement MOS Transistor

Subthreshold (VG<VT) VB = 0

VS = 0

p+ p- substrate Threshold (VG=VT) VB = 0

n+

VS = 0

p+ p- substrate

n+

Strong Threshold (VG>VT) VB = 0 VS = 0

p+ p- substrate

n+

,,, ,,, ,,, ,,,

VG < VT
Polysilicon

VD = 0

n+

VG =VT

VD = 0

Polysilicon

n+

Inverted Region

VG >VT

VD = 0

Polysilicon

n+

Inverted Region

Fig1.8-2

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MOS Models (5/23/00)

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The MOSFET Threshold Voltage When the gate voltage reaches a value called the threshold voltage (VT), the substrate beneath the gate becomes inverted (it changes from p-type to n-type).
Qb QSS V T = MS + -2 F + Cox Cox

where

MS = F(substrate) - F(gate) F = Equilibrium electrostatic potential (Femi potential)

kT F(PMOS) = - q ln(NA/ni) = -Vt ln(NA/ni) kT F(NMOS) = q ln(ND/ni) = Vt ln(ND/ni) Qb 2qNAsi(|-2F+vSB|)

QSS = undesired positive charge present in the interface between the oxide and the bulk silicon Rewriting the threshold voltage expression gives, Q b0 QSS Q b - Q b 0 = VT0 + V T = MS -2 F - C - C |-2 F + v S B | Cox ox ox where Q b0 Q SS 2qsiNA V T 0 = MS - 2 F and = Cox - Cox Cox

|-2 F |

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Signs for the Quantities in the Threshold Voltage Expression

Parameter Substrate MS Metal n+ Si Gate p+ Si Gate F Qb0,Qb Qss VSB

N-Channel p-type + + + +

P-Channel n-type + + + +

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Example 1 - Calculation of the Threshold Voltage Find the threshold voltage and body factor for an n-channel transistor with an n+ silicon gate if tox = 200 , NA = 3 1016 cm -3, gate doping, ND = 4 1019 cm -3, and if the positively-charged ions at the oxide-silicon interface per area is 10 10 cm-2. Solution From above, F(substrate) is given as

F(substrate) = 0.0259 ln

3 10 16 = 0.377 V 1 0 1.45 1 0

The equilibrium electrostatic potential for the n+ polysilicon gate is found from as

F(gate) = 0.0259 ln

4 10 1 9 = 0.563 V 1.45 10 1 0

Therefore, the potential MS is found to be

F(substrate) F(gate) = 0.940 V.

The oxide capacitance is given as C ox = ox /tox = 3.9 8.854 10 -14 = 1.727 10-7 F/cm2 8 200 10

The fixed charge in the depletion region, Qb0, is given as Qb0 = [2 1.6 10-19 11.7 8.854 10-14 2 0.377 3 1016]1/2 = 8.66 10-8 C/cm2.

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Example 1 - Continued Dividing Qb0 by Cox gives 0.501 V. Finally, Qss/Cox is given as Qss 10 10 1.60 10 -19 = = 9.3 10-3 V -7 Cox 1.727 10 Substituting these values for VT0 gives V T0 = - 0.940 + 0.754 + 0.501 - 9.3 x 10-3 = 0.306 V The body factor is found as
-19 11.7 8.854 10 -14 3 10 1 6 2 1.6 10 1/2

1.727 10

-7

= 0.577 V1/2

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SIMPLE LARGE SIGNAL MOSFET MODEL Large Signal Model Derivation Derivation1.) Let the charge per unit area in the channel inversion layer be Q I(y) = -C ox[vGS - v(y) - VT] (coulombs/cm2) 2.) Define sheet conductivity of the inversion layer per square as amps 1 cm2 coulombs S = oQ I(y) vs cm2 = volt = /sq. 3.) Ohm's Law for current in a sheet is iD -iD -iDdy dv JS = = E = dv = dy = S y S dy o Q I(y )W W SW 4.) Integrating along the channel for 0 to L gives
vD S vD S L iD dy = - W oQ I(y)dv = W o C ox [ v GS - v ( y )- V T ] dv 0 0 0 pn+ Source 0 v(y) dy y y+dy + vGS iD n+ Drain L + v - DS

iD dy = -W oQ I(y)dv

5.) Evaluating the limits gives WoCox v 2 ( y ) vD S iD = ( v GS - V T ) v ( y ) L 2 0 W oC o x v DS 2 ( v - V ) v iD = - 2 L GS T DS

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Saturation Voltage - V D S(sat) Interpretation of the large signal model:

iD vDS = vGS - VT

Active Region

Saturation Region

Increasing values of vGS vDS

The saturation voltage for MOSFETs is the value of drain-source voltage at the peak of the inverted parabolas. diD oCoxW [(vGS -V T ) - vDS ] = 0 v D S (sat) = v G S - V T dvDS = L Useful definitions: oCoxW KW = L = L

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Complete Large Signal Model Regions of Operation of the MOS Transistor: 1.) Cutoff Region: iD = 0, v GS - V T < 0 (Ignores subthreshold currents) 2.) Active Region oCoxW 0 < v DS < v GS - V T iD = 2 L [ 2( v G S - V T ) - v D S] v DS , 3.) Saturation Region oCoxW v - VT) 2 , 0 < v GS - V T < v D S iD = 2L ( G S Output Characteristics of the MOSFET:
iD /ID0 vDS = vGS - VT 1.0 0.75 Channel modulation effects 0.5 0.25 Cutoff Region 0 0 0.5 1.0 1.5 2.0 Active Region Saturation Region vGS-VT = 1.0 VGS0 - VT vGS-VT = 0.867 VGS0 - VT vGS-VT = 0.707 VGS0 - VT vGS-VT = 0.5 VGS0 - VT vGS-VT = 0 VGS0 - VT vDS VGS0 - VT 2.5

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Influence of VD S on the Output Characteristics Channel modulation effect: As the value of vDS increases, it causes the effective L to decrease which causes the current to increase. Illustration:

p+

,,, ,,,,,,,
VG > VT VD > VDS(sat)
S

,,,,,,,
n+ n+ Leff Xd

Polysilicon

Depletion Region

p- substrate

Fig1.8-3

Note that Leff = L - Xd Therefore the model in saturation becomes, diD dL eff iD dX d KW KW 2 2 iD = 2L (v GS - V T ) dvDS = - 2Leff2 (v GS - V T ) dvDS = Leff dvDS iD eff Therefore, a good approximation to the influence of vDS on iD is diD KW iD iD(vDS=0) + dv vDS = iD (vDS=0)(1 + vDS) = 2 L (v GS -V T )2(1+ v DS ) DS

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Influence of the Bulk Voltage on the Large Signal MOSFET Model Illustration of the influence of the bulk: V SB0 = 0V:
Bulk p+ pSubstrate/Bulk VSB1 + Bulk p+ pSubstrate/Bulk Source n+ Gate VGS>VT
Poly

VSB0 =0V + Source n+

Gate VGS>VT
Poly

Drain VDS>0

n+

V SB 1>0V:

Drain VDS>0

n+

V SB 2 > V SB 1 :
Bulk p+ p-

VSB2

Gate VGS>VT
Poly

Drain VDS>0

Source n+

n+

Substrate/Bulk

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MOS Models (5/23/00)

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Influence of the Bulk Voltage on the Large Signal MOSFET Model - Continued Bulk-Source (vBS) influence on the transconductance characteristicsiD Decreasing values of bulk-source voltage VBS = 0 vDS vGS - VT

vGS VT0 VT1 VT2 VT3

In general, the simple model incorporates the bulk effect into VT by the following empirically developed equationV T ( v BS ) = V T0 + 2| f | + | v BS | - 2| f |

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MOSFET Schematic Symbols Enhancement:

VBS 0V D NMOS G S D PMOS G S B G S B G S D G S
Fig1.8-4

VBS=0V D G

Simple D

S D

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Summary of the Simple Large Signal MOSFET Model N-channel reference convention:
G + vGS D iD + + B vDS

Non-saturationWoCox vDS2 ( v - V T ) v D S - 2 (1 + vDS ) iD = L GS SaturationWoCox v DS (sat) 2 W oC ox 2 ( v GS - V T ) v DS (sat) (1 + v DS ) = iD = L 2 2 L (v GS - V T ) (1 + v DS ) where: o = zero field mobility (cm2/voltsec) Cox = gate oxide capacitance per unit area (F/cm2) = channel-length modulation parameter (volts-1) V T = V T0 + 2| f | + | v B S | - 2| f | VT0 = zero bias threshold voltage = bulk threshold parameter (volts-0.5) 2|f| = strong inversion surface potential (volts) For p-channel MOSFETs, use n-channel equations with p-channel parameters and invert current.

vBS - -S

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MOSFET Constants for Silicon:

Constant Symbol VG k ni Constant Description Silicon bandgap (27C) Boltzmanns constant Intrinsic carrier concentration (27C) Permittivity of free space Permittivity of silicon Permittivity of SiO2 Value 1.205 1.381x10-23 1.45x1010 8.854x10-14 11.7 0 3.9 0 Units V J/K cm-3 f/cm F/cm F/cm

0 si ox

Model Parameters for a Typical CMOS Bulk Process (0.8m CMOS n-well):
Parameter Parameter Symbol Description Threshold Voltage VT0 (VBS = 0) K' Transconductance Parameter (in saturation) Bulk threshold parameter Channel length modulation parameter Surface potential at 2|F| strong inversion Typical Parameter Value N-Channel P-Channel 0.7 0.15 0.7 0.15 110.0 10% 50.0 10% Units V

A/V2

0.4 0.04 (L=1 m) 0.01 (L=2 m) 0.7

0.57 0.05 (L = 1 m) 0.01 (L = 2 m) 0.8

(V)1/2 (V)-1

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MOSFET SMALL SIGNAL MODEL Small-Signal Model Complete schematic model:

D D

id G B + vgs B + vbs rds

G S

G S

gmvgs

gmbsvbs

+D vds S
Fig. 4.2-4

where diD | = (V -V ) = gm dv GS T GS Q and 2 ID diD iD | gds dv = iD DS Q 1 + v D S gm i D vT = vTvBSQ 2 2| F | - V B S = gm

id D G S G S D G + vgs rds

D iD vGS gmbs = v = = BS Q vGS vBS Q

Simplified schematic model:

+D vds S Fig. 4.2-2

gmvgs

Extremely important assumption: g m 10 g m b s 100 g ds

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Illustration of the Small-Signal Model Application DC resistor: v V DC resistance = i = Q I Useful for biasing - creating current from voltage and vice versa
ID

i AC Resistance DC Resistance

Small-Signal Load (AC resistance):

D D

VT

VDS

v
Fig. 4-2-2B

id G B + vgs B + vbs rds

G S

G S

gmvgs

gmbsvbs

+D vds S
Fig. 4.2-4

vds 1 1 AC resistance = i = g + g g d m ds m

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Example 2 - Small-Signal Load Resistance Find the small signal resistance of the MOS diode shown using the parameters of Table 3.2-1. Assume that the W/L ratio is 10m/1m. Solution If we are going to include the bulk effect, we must first find the dc value of the bulk-source voltage. Unfortunately, we do not know the threshold voltage because the bulk-source voltage is unknown. The best approach is to ignore the bulk-source voltage, find the gate-source voltage and then iterate if necessary. VGS =

VDD = 5V

rac

100A
Fig. 4.2-5

2I 2100 + V = + 0.7 = 1.126V T 0 11010 Thus let us guess at a gate-source voltage of 1.3V (to account for the bulk effect) and calculate the resulting gate-source voltage. V T = V T 0 + 2| F | - (-3.7) - 2|F| = 0.7 + 0.4 0.7+3.7 - 0.4 0.7 = 1.20V VGS = 1.63V Now refine our guess at VGS as 1.6V and repeat the above to get VT = 1.175V which gives VGS = 1.60V. Therefore, V BS = -3.4V.

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Example 2 - Continued The small signal model for this example is shown. The ac input resistance is found by, iac = gdsvac - gmvgs - gmbsvbs = gdsvac + gmvs + gmbsvs = vac(gm+gmbs+gds) vac 1 rac = i = g +g +g ac m mbs ds Now we must find the parameters which are,

G,D,B gmvgs
rds

id + vds = vgs -

rac vac iac Fig. 4.2-6

gmbsvbs S

2ID = 211010100 S = 469S, gds = 0.04V-1100A = 4S, 469S0.4 = 0.0987469S = 46.33S and gmbs = 2 0.7+3.4 Finally, gm = 106 rac = 469 + 46.33 + 4 = 1926 If we had used the previous approximations of gm 10gmbs 100gds, then we could have simply let 1 1 rac g = 469 = 2132 m Probably the most important result of this approximation is that we would not have to find VBS which took a lot of effort for little return.

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Small-Signal Model for the Active Region

iD | KWV DS KW gm = = (1+ V ) VD S DS v GS Q L L iD | KW V D S gmbs = v Q = BS 2L 2 F - V B S iD | ID KW = L ( V GS - V T - V DS )(1+ V DS ) + 1+V gds = v Q DS DS

KW L (V GS - V T - V DS )

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MOSFET CAPACITANCES Types of Capacitance Physical Picture:

SiO2

Gate Source C1 FOX C4 CBS Bulk CBD

Fig1.8-5

Drain C2 C3 FOX

MOSFET Capacitances consist of: Depletion capacitance Charge storage or parallel plate capacitance

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MOSFET Depletion Capacitors

Polysilicon gate

Model:
H G C

CJAS CJSWPS C BS = + MJ MJSW, v BS FC PB v B S v B S 1 1 PB PB and V B S 1 (1+ MJ ) FC + MJ C BS = 1+MJ PB ( 1- F C) CJAS CJSWPS

D Source E A SiO2 Bulk Drain F B

Fig1.8-6

Drain bottom = ABCD Drain sidewall = ABFE + BCGF + DCGH + ADHE

V B S , + 1 (1+ MJSW ) FC + MJSW 1+MJSW PB ( 1 - F C) vBS> FC PB where AS = area of the source PS = perimeter of the source CJSW = zero bias, bulk source sidewall capacitance MJSW = bulk-source sidewall grading coefficient For the bulk-drain depletion capacitance replace "S" by "D" in the above.
vBS FCPB

CBS

vBS FCPB PB vBS FCPB

Fig1.8-6B

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Charge Storage (Parallel Plate) MOSFET Capacitances - C1 , C2 , C3 and C4

Mask L Actual L (Leff) LD Oxide encroachment

Mask W

Actual W (Weff)

Gate Source-gate overlap capacitance CGS (C1) Gate FOX Source Gate-Channel Capacitance (C2) FOX Drain Channel-Bulk Capacitance (C4)
Fig1.8-7

Drain-gate overlap capacitance CGD (C3)

Bulk

Overlap capacitances: C1 = C3 = LDWeffCox = CGSO or CGDO

(LD 0.015 m for LDD structures)

Channel capacitances: C2 = gate-to-channel = CoxW eff(L-2LD) = CoxW effLeff C4 = voltage dependent channel-bulk/substrate capacitance

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Charge Storage (Parallel Plate) MOSFET Capacitances - C5 View looking down the channel from source to drain
Overlap Overlap

FOX C5

Gate Source/Drain Bulk

C5 FOX

Fig1.8-8

C5 = CGBO Capacitance values and coefficients based on an oxide thickness of 140 or Cox=24.7 104 F/m2:
Type CGSO CGDO CGBO CJ CJSW MJ MJSW P-Channel 220 1012 220 1012 700 1012 560 106 350 1012 0.5 0.35 N-Channel 220 1012 220 1012 700 1012 770 106 380 1012 0.5 0.38 Units F/m F/m F/m F/m2 F/m

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Expressions for CGD, CG S and CG B Cutoff Region: CGB = C2 + 2 C 5 = Cox(Weff)(Leff) + 2CGBO(Leff) CGS = C1 Cox(LD)Weff) = CGSO(Weff) CGD = C3 Cox(LD)Weff) = CGDO(Weff) Saturation Region: CGB = 2C5 = CGBO(Leff) CGS = C1 +(2/3)C2 = Cox(LD+0.67Leff)(Weff) = CGSO(Weff) + 0.67Cox(Weff)(Leff) CGD = C3 Cox(LD)Weff) = CGDO(Weff) Active Region: CGB = 2 C 5 = 2CGBO(Leff) CGS = C1 + 0.5C2 = Cox(LD+0.5Leff)(Weff) = (CGSO + 0.5CoxLeff)Weff CGD = C3 + 0.5C2 = Cox(LD+0.5Leff)(Weff) = (CGDO + 0.5CoxLeff)Weff

Cutoff VB = 0

CGS p+ p- substrate Saturated VB = 0

VS = 0

n+

VS = 0 CGS n+

p+ p- substrate Active VB = 0

VS = 0 CGS n+

p+ p- substrate

,,, ,,, ,,, ,,,

VG < VT
Polysilicon

VD > 0 CGD n+

CGB

VG >VT

Polysilicon

VD >VG -VT CGD n+

Inverted Region

VG >VT

Polysilicon

VD <VG -VT CGD n+

Inverted Region

Fig1.8-9

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Illustration of CGD, CG S and CG B

Capacitance C4 Large C2 + 2 C5 C1+ 0.67C2 C1+ 0.5C2 C1, C3 2C5 0 CGS, CGD CGS CGS, CGD CGD CGB Saturation VT vDS = constant vBS = 0 C4 Small NonSaturation vDS +VT vGS
Fig1.8-10

Off

Comments on the variation of CBG in the cutoff region: 1 CBG = 1 1 + 2C 5 + C C2 4 For vGS 0, C GB C 2 + 2C 5 (C4 is large because of the thin inversion layer in weak inversion where VGS is slightly less than VT)) For 0<vGS V T, C GB 2C 5 (C4 is small because of the thicker inversion layer in strong inversion)

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Small-Signal Frequency Dependent Model

Cgd

id
rds

+ vgs S -

Cgs gmvgs

gmbsvbs vbs + B
Cbs

+ vds S

Cgb

Cbd

Fig1.8-15

The depletion capacitors are found by evaluating the large signal capacitors at the DC operating point. The charge storage capacitors are constant for a specific region of operation. Gainbandwidth of the MOSFET: Assume VSB = 0 and the MOSFET is in saturation, gm 1 1 gm f T = 2 C + C 2 C gs gd gs Recalling that 2 and Cgs 3 C ox WL gives 3 o fT = 4 2 (V GS - V T ) L

gm = oCox

W ( V GS - V T ) L

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Summary of the MOSFET Large Signal Model

D CGD rD CBD

vBD + rG iD iBD vBS + iBS

CBS

rB B

CGS

CGB

rS S

where, rG, rS, rB, and rD are vBD iBD = Is exp Vt

ohmic and contact resistances vBS 1 and iBS = Is exp V - 1 t

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SHORT-CHANNEL MOSFET MODEL Velocity Saturation The most important short-channel effect in MOSFETs is the velocity saturation of carriers in the channel. A plot of electron drift velocity versus electric field is shown below.
Electron Drift Velocity (m/s) 105 5x104 2x104 104 5x103 105 106 Electric Field (V/m) 107
Fig1.8-11

An expression for the electron drift velocity as a function of the electric field is, nE v d 1 + E/E c where vd = electron drift velocity (m/s) n = low-field mobility ( 0.07m2/Vs) Ec = critical electrical field at which velocity saturation occurs

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Short-Channel Model Derivation As before, iD WQ I(y) nE JD = JS = W = Q I(y)vd(y) iD = W QI(y)vd(y) = 1 + E/E c Replacing E by dv/dy gives, 1 d v dv iD 1 + E dy= WQ I(y)n dy C Integrating along the channel gives,
L vD S 1 d v iD 1 + dy = WQ I(y) ndv Ec dy 0 0

E iD 1 + E = WQ I(y)nE C

The result of this integration is, nCox W K W 2] = [2( v V ) v v [2(vGS - V T )vDS - vDS 2] iD = GS T DS DS L 2[1 + ( v V )] L v GS T 1 D S 2 1 + E L c where = 1/LEc with dimensions of V-1. The saturation voltage has not changed so substituting for vDS by vGS-VT gives, K W iD = 2[1 + ( v - V )] L [ vGS - V T ]2 GS T Note that the transistor will enter the saturation region for vDS < vGS - VT in the presence of velocity saturation.

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The Influence of Velocity Saturation on the Transconductance Characteristics The following plot was made for K = 110A/V2 and W/L = 1:
1000 800 iD/W (A/m) 600 = 0.6 400 200 0 0.5 = 1.0 = 0.8 =0 = 0.2 = 0.4

1.5 vGS (V)

2.5

3
Fig1.8-12

Note as the velocity saturation effect becomes stronger, that the drain current-gate voltage relationship becomes linear.

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Circuit Model for Velocity Saturation A simple circuit model to include the influence of velocity saturation is the following:
G + vGS

D iD + vGS' RSX - S

We know that KW iD = 2 L (v GS -V T )2 and v GS = v GS + iD RSX Substituting vGS into the current relationship gives, KW iD = 2 L (v GS - iD R SX -V T )2 Solving for iD results in, iD = K W 21 + K L R SX ( v GS - V T ) W (v GS - V T )2 L

Fig1.8-13

or

v GS = v GS - iD R XS

Comparing with the previous result, we see that W 1 L = K L R SX R SX = = E KW KW c Therefore for K = 110A/V2, W = 1m and Ec = 1.5x106V/m, we get RXS = 6.06k .

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Output Characteristics of Short-Channel MOSFETs IBM, 1998, tox = 3.5nm

800 700 Drain Current (A/m) 600 500 400 300 200 100 0 -1.8 -1.2 -0.6 0.6 0.0 Drain Voltage (V) 1.2 1.8
Fig1.8-14

PFET Leff = 0.11m

NFET VGS=1.8V Leff = 0.08m VGS=1.4V

VGS=-1.8V VGS=1.0V VGS=-1.4V VGS=-1.0V VGS=-0.6V VGS=0.6V

Su, L., et.al., A High Performance Sub-0.25m CMOS Technology with Multiple Thresholds and Copper Interconnects, 1998 Symposium on VLSI Technology Digest of Technical Papers, pp. 18-19.

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SUBTHRESHOLD MOSFET MODEL Weak inversion operation occurs when the applied gate voltage is below V T and pertains to when the surface of the substrate beneath the gate is weakly inverted.

Diffusion Current p-substrate/well

,,, zz

,, y y
VGS
n+
n-channel

n+

Regions of operation according to the surface potential, S. S < F : Substrate not inverted

F < S < 2 F : Channel is weakly inverted (diffusion current) 2F < S : Strong inversion (drift current)
Drift current versus diffusion current in a MOSFET:
log iD Diffusion Current 10-6 Drift Current

10-12

VT

VGS

ECE 4430 - Analog Integrated Circuits and Systems

Phillip E. Allen 2000

MOS Models (5/23/00)

Page 36

Large-Signal Model for Subthreshold Model: W iD = K x L evGS/nVt(1 - e-vDS/Vt)(1 + vDS) where Kx is dependent on process parameters and the bulk-source voltage n 1.5 - 3 and kT Vt = q If vDS > 0, then W iD = K x L evGS/nVt (1 + vDS) Small-signal model:
iD 1A VGS=VT

VGS<VT

iD | qID = nkT gm = v Q GS iD | gds = v Q DS

ID VA

1V

vDS
Fig1.8-18

ECE 4430 - Analog Integrated Circuits and Systems

Phillip E. Allen 2000

MOS Models (5/23/00)

Page 37

SUBSTRATE CURRENT FLOW IN MOSFETS Impact Ionization Impact Ionization: Occurs because high electric fields cause an impact which generates a hole-electron pair. The electrons flow out the drain and the holes flow into the substrate causing a substrate current flow. Illustration:
B

p+

,,, ,,,,,,,,
VG > VT
S

VD > VDS(sat)

p- substrate

,,,,,,,, ,,,,,,,,
n+
A

Polysilicon

Depletion Region

Fixed Atom

Free n+ electron

Free hole

Fig1.8-16

ECE 4430 - Analog Integrated Circuits and Systems

Phillip E. Allen 2000

MOS Models (5/23/00)

Page 38

Model of Substrate Current Flow Substrate current: iDB = K1(vDS - vDS(sat))iDe-[K2/(vDS-vDS(sat))] where K1 and K2 are process-dependent parameters (typical values are K1 = 5V-1 and K2 = 30V) Schematic model:
D

iDB G B S
Fig1.8-17

Small-signal model: IDB iDB gdb = v = K 2 V DB DS - V DS (sat) This conductance will have a negative influence on high-output resistance current sinks/sources.

ECE 4430 - Analog Integrated Circuits and Systems

Phillip E. Allen 2000

MOS Models (5/23/00)

Page 39

SUMMARY Simple Large-Signal Model Non-saturationWoCox vDS2 ( v - V T ) v D S - 2 (1 + vDS ) iD = L GS SaturationW oC ox 2 iD = 2 L (v GS - V T ) (1 + v DS ) Small-Signal Model diD diD iD | | = (V GS -V T ) = 2 ID g ds dv = iD gm dv GS Q DS Q 1 + v D S Capacitances
Capacitance C4 Large C2 + 2C5 C1+ 0.67C2 C1+ 0.5C2 C1, C3 2C5 0 CGS, CGD CGS CGS, CGD CGD CGB Saturation VT vDS = constant vBS = 0 C4 Small NonSaturation vDS +VT vGS
Fig1.8-10

g mbs =

gm 2 2| F | - V B S

Off

ECE 4430 - Analog Integrated Circuits and Systems

Phillip E. Allen 2000