Sandeepalani Course of 16 Weeks

Course Duration: 16 Weeks Mod.
Module Title
Course Structure and Outline What You Learn
P1 Applied Network (3 Days) Analysis
Electrical Network Elements - Independent and Dependent Sources, Passive Elements Network Analysis Techniques - Review Review of Time and Frequency Domain responses of RC networks MOSFET Characteristics, MOSFET Capacitances CMOS Inverter - Conceptualizing the Inverter using Network Elements, Inverter VTC, Transient Response CMOS Gate Design PN Junction, BJT Device Characteristics and Applications Review OPAMP Applications - Review Quality Metrics of a Digital System Review of Number Systems , Combinational Logic Design Interpreting the Logic gate Data Sheets Designing with Mux, Demux, Decoders, Encoders Sequential Elements and Sequential Logic Design- D Latch, D Flop Design of Sequential Systems - Registers and Counters Introduction to C Programming - Structure of a C program, The C compilation process Types and Operators - C base types, Precedence & associativity, - Arithmetic operations Functions -The Function as a logical program unit, Parameter passing, Memory segments Control Flow -Logical expressions and operations, Decision Making, Loops, Introduction to Pointers Introduction to a Generic Microprocessor Instruction Execution Cycles, Single, Multi Cycle, Pipelined Data Paths Interrupts, Memory Mapping and Peripheral Interfaces Introduction to Bus Architecture overview - APB, AXI Synchronous Finite State Machine Design Data-path elements - Arithmetic Structures Introduction to and Programmable Platforms Design Capture and Simulation Practical Digital System Design Examples Driver for VLSI: Moore's law Evolution of Design Approaches (leading upto HDLs), Simulator and Synthesizers Specification formation to Micro architecture Hardware Modeling Overview, Verilog language concepts Modules and Ports

P2 Devices and Circuits for (4 Days) Microelectronics
P3 Digital System Design (4 Days)

P4 Basic C Programming (3 Days)
Review of Micro P5 Processors/ (3 Days) Microcontrollers
C1 Advanced Digital (5Days) System Design
C2 Chip Design (2 Days) Methodology - I
C3 Digital System Design (8Days) with Verilog
Dataflow Modeling Introduction to Test benches Operators Procedural Statements Controlled Operation Statements Coding for Finite State Machines Coding For Synthesis Tasks and Functions Advanced Verilog Test benches Introduction to Verification Introduction to Verification Plan Verification Tools Stimulus and Response Introduction to Bus Function Models Verification environment and its components Advanced Simulation and Synthesis Introduction to Design Verification RTL design, synthesis, verification, regression System Verilog Basics - Introduction to System Verilog, Enhancement Made in System Verilog over Verilog, Interface and Modports System Verilog for Verification - System Verilog Event Ordering, Clocking block and Program bloc,OOP's Concept of System Verilog - Parameterized classe, Virtual interface, Constrained Randomization techniques, Functional Coverage (Coverage Driven Verification) System Verilog Assertions - Introduction to Assertion, Properties, Sequences, Checkers, Assertions in design, Verification (for Coverage Analysis)
C4 Functional Verification (5 Days)
C5 Chip Design (3Days) Methodology - II

C6 Verification using (15 Days) System Verilog
FPGA Architecture - Basic Components of FPGA (LUT, CLB, Switch Matrix, IOB), FPGA Architecture
C7 Digital System Design (8 Days) using FPGAs
Optimal FPGA Design - HDL Coding Techniques for FPG, FPGA Design Techniques Synthesis Techniques, Implementation, Options - Overview, Achieving Timing Closure, Path Specific Constraints, Introduction to Advanced IO Timing FPGA Design Flow - Xilinx tool Flow, Reading Reports, Implementing IP cores, Pin Planning using Plan Ahead, Global Timing Constraints,Debugging Using Chipscope Pro Static Timing Analysis - Introduction Reset Techniques, Clock Domain Crossing, Multiple Clock Domains, Dual Synchronization Design and Verification Guidelines SoC Verification Methodology Physical Design, Manufacturing, Silicon validation
C8 Chip Design (2 Days) Methodology - III C7 Course Project
Course project
(15 Days)
NOTE: (1) The contents listed above is a representative outline and is subject to change at short notice in compliance with the current industry demands (2) Legend: P# - Primer Module, C# - Core Module
Course Fee: Rs.1,00,000/- +Tax (12.36%) Reference Books We recommend the following books for purchase which will be helpful to you at the time of our Professional Development Course
VHDL - Douglas Perry Verilog HDL - Samir Palnitkar (Indian Edition) Logic and Computer Design Fundamentals 2nd Edition - M. Morris Mano and Charles R. Kime FPGA-Based System Design Wayne Wolf.
We will be providing our own material and lab books for your daily assignments & practices.

Sandeepalani Course of 16 Weeks

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Sandeepalani Course of 16 Weeks

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Available Formats

Course Duration: 16 Weeks Mod.

Course Structure and Outline What You Learn

P1 Applied Network (3 Days) Analysis

P3 Digital System Design (4 Days)

Review of Micro P5 Processors/ (3 Days) Microcontrollers

C1 Advanced Digital (5Days) System Design

C2 Chip Design (2 Days) Methodology - I

C3 Digital System Design (8Days) with Verilog

C4 Functional Verification (5 Days)

C5 Chip Design (3Days) Methodology - II

C7 Digital System Design (8 Days) using FPGAs

C8 Chip Design (2 Days) Methodology - III C7 Course Project

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