VLSI PROJECTS LIST-2013

PROCESSOR ARCHITECTURE:1.Design and implementation of two variable multiplier using KCM and Vedic mathematics 2 .Design and implementation of a high performance multiplier using HDL !. "#$% implementation of binar& coded Decimal digit adders and multipliers '. High speed modified booth encoder multiplier for signed and unsigned numbers (. High speed signed Multiplier for Digital )ignal #rocessing applications *. +oeplit, Matri- %pproach for .inar& "ield Multiplication /sing 0uadrinomials 12333 +4%5)C%+2657 8. .inar& floating point "M% unit design with )2MD support 12333 +4%5)C%+2657 9. %n efficient implementation of floating point multiplier :. % 5ovel Low #ower and High )peed ;allace +ree Multiplier for 42)C #rocessor 1<. High speed and low space comple-it& "#$% based 3CC processor 11. High speed %sic design of Comple- multiplier using vedic mathematics 12. % new reversible design of .CD adder 1!. #arallel architecture of hierarchical optical flow estimation 1'. Design and characteri,ation of parallel prefi- adder using "#$% 1(. Design of Low #ower High )peed +runcation 3rror +olerant %dder and 2ts %pplication in Digital )ignal #rocessing 12333 +4%5)C%+2657

SIGNAL , IMAGE & VIDEO PROCESSING:1. 2mplementation of h&brid wave pipelined 2D D;+ using %)2C 2. Design of plural multiplier based on cordic algorithm for ""+ application !. Viterbi based 3fficient +est Data Compression 12333 +4%5)C%+2657 '. % feature based 4obust Digital 2mage ;ater mar=ing )cheme (. Digital 2mage ;ater mar=ing based on )uper 4esolution image reconstruction

*. ;ater mar=ing mobile phone color images with reed solomon error correcting code 8. %n efficient VL)2 architecture for lifting based Discrete ;avelet +ransform 12333 +4%5)C%+2657 9.Hardware 2mplementation of High +hroughput 4C' %lgorithm :. Design for image segment using gabor filter for disease detection 1<. %rea 3fficient #arallel "24 Digital "ilter )tructures for )&mmetric Convolutions .ased on "ast "24 %lgorithm 12333 +4%5)C%+2657 11. Hardware implementation of a digital water mar=ing s&stem for video %uthentication 12333 +4%5)C%+2657 12. Design and implementation of %rea optimi,ed %3) based "#$% 1!. % multi channel water mar=ing scheme based on DC+ D;+ 1'. %n implementation of a 2D "24 filter using the signed digit number s&stem 1(. "#$% based ""+ algorithm implementation in ;i Ma- communications s&stem 1*. "#$% design of %3) core architecture for portable hard dis= 18. image encr&ption based on %3) =e& 3-pansion 19. "eature e-traction of digital aerial images b& "#$% based implementation of edge detection algorithms 1:. %n efficient architecture design for V$% monitor controller 2<. Curve fitting algorithm "#$% implementation 21. "#$% implementation of %3) algorithm 22. Design and implementation of an "#$% based real time face recogani,ation s&stem 2!. % High )peed Low Comple-it& Modified 4adi- 2>( ""+ #rocessor for $igabit ;#%5 %pplications 2'. 3fficient VL)2 architecture for Discrete wavelet transform 2(. Construction of optimim Composite "ield %rchitecture for Compact High +hroughput %3) ) .o-es 12333 +4%5)C%+2657 2*. % High )peed Low Comple-it& Modified 4adi- 2>( ""+ #rocessor for $igabit ;#%5

%pplications

COMMUNICATION & BUS PROTOCOLS:1. High )peed Low #ower Viterbi Decoder Design for +CM Decoders 12333 +4%5)C%+2657 2. VHDL implementation of /%4+ with )tatus register !. VL)2 .ased 4obust 4outer %rchitecture '. Design and simulation of /%4+ serial communication module based on VHDL (. "#$% implementation of 4)2!2 to universal serial bus converter1/).7 *. Design of )erial Communication interface based on "#$% 8. Design of .uilding an %M.% %H. compliant Memor& Controller

8. Implementation of a Self-Motivated Arbitration Scheme for the Multilayer AHB

LOW POWER:1. Design of *' bit low power parallel prefi- VL)2 adder for high speed %rithmetic Circuits 2. Design of low power high speed vlsi adder sub s&stem !. % h&brid low power adder for high performance processor 1H2C#%7 '. Low power and area efficient carr& select adder 12333 +4%5)C%+2657 (. Design of low power and high performance 4adi- ' multiplier *. Design of low power +#$ using L# L")4 8. Design of low power and high speed configurable booth multiplier 9. Design and implementation of low power digital "24 filter based on low power multipliers and adders on @ilin- "#$% :. % ver& fast and low power carr& select adder circuit

1<. Design of low power column b&pass multiplier using "#$%

BIST ALGORITHMS:1. %ccumulator based ! weight pattern generation 12333 +4%5)C%+2657 2. 5onlinear Multi 3rror Correction Codes for 4eliable MLC 5%5D "lash Memories 12333 +4%5)C%+2657 !. )oft 3rror 4esilient "#$%s /sing .uilt 2n 2 D Hamming #roduct Code 12333 +4%5)C%+2657 '. /nified %rchitecture for 4eed )olomon Decoder Combined ;ith .urst 3rror correction 12333 +4%5)C%+2657 (. Direct Compare of 2nformation Coded ;ith 3rror Correcting Codes 12333 +4%5)C%+2657 *. % 5on binar& LD#C Decoder %rchitecture ;ith %daptive Message Control 12333 +4%5)C%+2657 8. #roduct Code )chemes for 3rror Correction in MLC 5%5D "lash Memories 12333 +4%5)C%+2657 9. 3fficient MaAorit& Logic "ault Detection ;ith Difference )et Codes for Memor& %pplications 12333 +4%5)C%+2657 :. Low Comple-it& 4eliabilit& .ased Message #assing Decoder %rchitectures for 5on .inar& LD#C Codes 12333 +4%5)C%+2657 1<.VHDL design and "#$% implementation of weighted maAorit& logic decoders 11. Designing 3fBcient Codecs for .us 2nvert .erger Code for "ull& %s&mmetric Communication 12333 +4%5)C%+2657