Sheet1

SMAP

ERR

RESET

DATA_XFER

REG_W/R

DATA_XFER

REG_W/R

Page 1

Sheet1

DATA_XFER

DATA_XFER

DATA_XFER

FSM_TR

REG_W/R

DATA_XFER

Page 2

Sheet1

DATA_XFER

DATA_XFER

REG_W/R

DATA_XFER

REG_W/R

DATA_XFER

FSM_TR

DATA_XFER

Page 3

Sheet1

RESET

DATA_XFER

DATA_XFER

DATA_XFER

DATA_XFER

DATA_XFER

DATA_XFER

Page 4

Sheet1

DATA_XFER

ERR

ERR

DATA_XFER

DATA_XFER

FSM_TR

DATA_XFER

Page 5

Sheet1

RESET

REG_W/R

DATA_XFER

REG_W/R

DATA_XFER

DATA_XFER

DATA_XFER

DATA_XFER

FSM_TR

Page 6

Sheet1

DATA_XFER

DATA_XFER

RESET

DATA_XFER

DATA_XFER

REG_W/R

Page 7

Sheet1

DATA_XFER

REG_W/R

DATA_XFER

DATA_XFER

DATA_XFER

DATA_XFER

DATA_XFER

Page 8

Sheet1

DATA_XFER

FSM_TR

DATA_XFER

DATA_XFER

DATA_XFER

ERR

REG_W/R

Page 9

Sheet1

DATA_XFER

RESET

FSM_TR

DATA_XFER

FSM_TR

REG_W/R

Page 10

Sheet1

ERR

DATA_XFER

DATA_XFER

DATA_XFER

DATA_XFER

DATA_XFER

Page 11

Sheet1

DATA_XFER

DATA_XFER

DATA_XFER

DATA_XFER

DATA_XFER

REG_W/R

Page 12

Sheet1

DATA_XFER

REG_W/R

ERR

DATA_XFER

DATA_XFER

DATA_XFER

REG_W/R

Page 13

Sheet1

DATA_XFER

DATA_XFER

REG_W/R

DATA_XFER

REG_W/R

REG_W/R

RESET

Page 14

Sheet1

RESET

REG_W/R

REG_W/R

RESET

REG_W/R

DATA_XFER

RESET

REG_W/R

Page 15

Sheet1

DATA_XFER

DATA_XFER

DATA_XFER

REG_W/R

DATA_XFER

DATA_XFER

DATA_XFER

DATA_XFER

Page 16

Sheet1

DATA_XFER

REG_W/R

DATA_XFER

REG_W/R

FSM_TR

FSM_TR

DATA_XFER

DATA_XFER

DATA_XFER

Page 17

Sheet1

REG_W/R

DATA_XFER

DATA_XFER

DATA_XFER

DATA_XFER

DATA_XFER

REG_W/R

DATA_XFER

Page 18

Sheet1

DATA_XFER

DATA_XFER

DATA_XFER

DATA_XFER

RESET

DATA_XFER

DATA_XFER

DATA_XFER

Page 19

Sheet1

DATA_XFER

ERR

DATA_XFER

DATA_XFER

DATA_XFER

DATA_XFER

DATA_XFER

DATA_XFER

Page 20

Sheet1

DATA_XFER

REG_W/R

DATA_XFER

ERR

DATA_XFER

DATA_XFER

DATA_XFER

Page 21

Sheet1

REG_W/R

RESET

DATA_XFER

RESET

REG_W/R

DATA_XFER

Page 22

Sheet1

REG_W/R

DATA_XFER

REG_W/R

ERR

REG_W/R

DATA_XFER

DATA_XFER

Page 23

Sheet1

DATA_XFER

FSM_TR

DATA_XFER

DATA_XFER

DATA_XFER

DATA_XFER

Page 24

Sheet1

DATA_XFER

DATA_XFER

REG_W/R

DATA_XFER

DATA_XFER

FSM_TR

REG_W/R

Page 25

Sheet1

ERR

REG_W/R

DATA_XFER

DATA_XFER

RESET

RESET

DATA_XFER

Page 26

Sheet1

REG_W/R

REG_W/R

DATA_XFER

DATA_XFER

DATA_XFER

ERR

REG_W/R

REG_W/R

DATA_XFER

Page 27

Sheet1

REG_W/R

DATA_XFER

REG_W/R

REG_W/R

REG_W/R

FSM_TR

DATA_XFER

DATA_XFER

DATA_XFER

Page 28

Sheet1

REG_W/R

DATA_XFER

DATA_XFER

DATA_XFER

DATA_XFER

DATA_XFER

DATA_XFER

REG_W/R

DATA_XFER

Page 29

Sheet1

RESET

DATA_XFER

DATA_XFER

DATA_XFER

DATA_XFER

FSM_TR

RESET

Page 30

Sheet1

DATA_XFER

DATA_XFER

ERR

DATA_XFER

DATA_XFER

DATA_XFER

Page 31

Sheet1

DATA_XFER

DATA_XFER

DATA_XFER

FSM_TR

DATA_XFER

DATA_XFER

DATA_XFER

Page 32

Sheet1

DATA_XFER

DATA_XFER

DATA_XFER

REG_W/R

DATA_XFER

REG_W/R

DATA_XFER

Page 33

Sheet1

REG_W/R

DATA_XFER

DATA_XFER

DATA_XFER

REG_W/R

DATA_XFER

DATA_XFER

Page 34

Sheet1

RESET

DATA_XFER

DATA_XFER

REG_W/R

REG_W/R

DATA_XFER

DATA_XFER

Page 35

Sheet1

REG_W/R

REG_W/R

DATA_XFER

DATA_XFER

RESET

REG_W/R

DATA_XFER

Page 36

Sheet1

DATA_XFER

REG_W/R

REG_W/R

DATA_XFER

ERR

REG_W/R

DATA_XFER

Page 37

Sheet1

DATA_XFER

RESET

DATA_XFER

DATA_XFER

DATA_XFER

DATA_XFER

DATA_XFER

Page 38

Sheet1

DATA_XFER

REG_W/R

DATA_XFER

RESET

DATA_XFER

DATA_XFER

DATA_XFER

Page 39

Sheet1

DATA_XFER

RESET

REG_W/R

DATA_XFER

DATA_XFER

DATA_XFER

Page 40

Sheet1

DATA_XFER

DATA_XFER

DATA_XFER

DATA_XFER

RESET

DATA_XFER

Page 41

Sheet1

DATA_XFER

DATA_XFER

DATA_XFER

REG_W/R

RESET

Page 42

Sheet1

RESET

DATA_XFER

DATA_XFER

DATA_XFER

REG_W/R

DATA_XFER

DATA_XFER

Page 43

Sheet1

DATA_XFER

DATA_XFER

DATA_XFER

DATA_XFER

DATA_XFER

DATA_XFER

DATA_XFER

Page 44

Sheet1

ERR

Page 45

Sheet1
SECTION

M-PHY ERROR transfers

MPHY RESET Cases

M-PHY - MODE/GEAR/SERIES CHANGE CASES

MPHY RMMI Interface tests

M-PHY - MODE/GEAR/SERIES CHANGE CASES

MPHY RMMI Interface tests

Page 46

Sheet1

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - RANDOM TEST CASES

M-PHY DATA transfers

M-PHY state transition

MPHY RMMI Interface tests

M-PHY - MODE/GEAR/SERIES CHANGE CASES

Page 47

Sheet1

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

MPHY RMMI Interface tests

M-PHY - MODE/GEAR/SERIES CHANGE CASES

MPHY RMMI Interface tests

M-PHY DATA transfers

M-PHY state transition

M-PHY - MODE/GEAR/SERIES CHANGE CASES

Page 48

Sheet1

MPHY RESET Cases

M-PHY - TEST MODES CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

Page 49

Sheet1

M-PHY DATA transfers

M-PHY ERROR transfers

M-PHY ERROR transfers

M-PHY DATA transfers

M-PHY DATA transfers

M-PHY state transition

M-PHY - MODE/GEAR/SERIES CHANGE CASES

Page 50

Sheet1

MPHY RESET Cases

MPHY RMMI Interface tests

M-PHY - MODE/GEAR/SERIES CHANGE CASES

MPHY RMMI Interface tests

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY DATA transfers

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY state transition

Page 51

Sheet1

M-PHY DATA transfers

M-PHY - JITTER & PPM Cases

MPHY RESET Cases

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

MPHY RMMI Interface tests

Page 52

Sheet1

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY Control transfers

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES/DATA BUS/PATTAREN LENGTH/SYNC LENGTH CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

Page 53

Sheet1

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY state transition

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY DATA transfers

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY ERROR transfers

MPHY RMMI Interface tests

Page 54

Sheet1

M-PHY - JITTER & PPM Cases

MPHY RESET Cases

M-PHY state transition

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY state transition

MPHY RMMI Interface tests

Page 55

Sheet1

M-PHY ERROR transfers

M-PHY - MODE/GEAR/SERIES/DATA BUS/PATTAREN LENGTH/SYNC LENGTH CHANGE CASES

M-PHY - JITTER & PPM Cases

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

Page 56

Sheet1

M-PHY - TEST MODES CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES/DATA BUS/PATTAREN LENGTH/SYNC LENGTH CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

MPHY RMMI Interface tests

Page 57

Sheet1

M-PHY - MODE/GEAR/SERIES CHANGE CASES

MPHY RMMI Interface tests

M-PHY ERROR transfers

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY DATA transfers

M-PHY DATA transfers

MPHY RMMI Interface tests

Page 58

Sheet1

M-PHY - MISC CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

MPHY RMMI Interface tests

M-PHY - MODE/GEAR/SERIES CHANGE CASES

MPHY RMMI Interface tests

MPHY RMMI Interface tests

MPHY RESET Cases

Page 59

Sheet1

MPHY RESET Cases

MPHY RMMI Interface tests

MPHY RMMI Interface tests

MPHY RESET Cases

MPHY RMMI Interface tests

M-PHY - MODE/GEAR/SERIES CHANGE CASES

MPHY RESET Cases

MPHY RMMI Interface tests

Page 60

Sheet1

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

MPHY RMMI Interface tests

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY DATA transfers

M-PHY - MODE/GEAR/SERIES CHANGE CASES

Page 61

Sheet1

M-PHY - MODE/GEAR/SERIES CHANGE CASES

MPHY RMMI Interface tests

M-PHY - MODE/GEAR/SERIES CHANGE CASES

MPHY RMMI Interface tests

M-PHY state transition

M-PHY state transition

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

Page 62

Sheet1

MPHY RMMI Interface tests

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - RANDOM TEST CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

MPHY RMMI Interface tests

M-PHY - MODE/GEAR/SERIES CHANGE CASES

Page 63

Sheet1

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

MPHY RESET Cases

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

Page 64

Sheet1

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY ERROR transfers

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY DATA transfers

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

Page 65

Sheet1

M-PHY - MODE/GEAR/SERIES CHANGE CASES

MPHY RMMI Interface tests

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY ERROR transfers

M-PHY - JITTER & PPM Cases

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

Page 66

Sheet1

MPHY RMMI Interface tests

MPHY RESET Cases

M-PHY - MODE/GEAR/SERIES CHANGE CASES

MPHY RESET Cases

MPHY RMMI Interface tests

M-PHY - MODE/GEAR/SERIES/DATA BUS/PATTAREN LENGTH/SYNC LENGTH CHANGE CASES

Page 67

Sheet1

MPHY RMMI Interface tests

M-PHY DATA transfers

M-PHY Control transfers

M-PHY ERROR transfers

MPHY RMMI Interface tests

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

Page 68

Sheet1

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY state transition

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

Page 69

Sheet1

M-PHY - RANDOM TEST CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

MPHY RMMI Interface tests

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY DATA transfers

M-PHY state transition

MPHY RMMI Interface tests

Page 70

Sheet1

M-PHY ERROR transfers

MPHY RMMI Interface tests

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY DATA transfers

MPHY RESET Cases

MPHY RESET Cases

M-PHY - MODE/GEAR/SERIES CHANGE CASES

Page 71

Sheet1

MPHY RMMI Interface tests

MPHY RMMI Interface tests

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY DATA transfers

M-PHY DATA transfers

M-PHY ERROR transfers

MPHY RMMI Interface tests

MPHY RMMI Interface tests

M-PHY - MODE/GEAR/SERIES CHANGE CASES

Page 72

Sheet1

MPHY RMMI Interface tests

M-PHY - MODE/GEAR/SERIES CHANGE CASES

MPHY RMMI Interface tests

MPHY RMMI Interface tests

MPHY RMMI Interface tests

M-PHY state transition

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY DATA transfers

M-PHY - MODE/GEAR/SERIES CHANGE CASES

Page 73

Sheet1

MPHY RMMI Interface tests

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

MPHY RMMI Interface tests

M-PHY - MODE/GEAR/SERIES CHANGE CASES

Page 74

Sheet1

MPHY RESET Cases

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY state transition

MPHY RESET Cases

Page 75

Sheet1

M-PHY - JITTER & PPM Cases

M-PHY - JITTER & PPM Cases

M-PHY ERROR transfers

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

Page 76

Sheet1

M-PHY - MISC CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY state transition

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

Page 77

Sheet1

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

MPHY RMMI Interface tests

M-PHY - JITTER & PPM Cases

MPHY RMMI Interface tests

M-PHY - MODE/GEAR/SERIES CHANGE CASES

Page 78

Sheet1

MPHY RMMI Interface tests

M-PHY - JITTER & PPM Cases

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY DATA transfers

MPHY RMMI Interface tests

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES/DATA BUS/PATTAREN LENGTH/SYNC LENGTH CHANGE CASES

Page 79

Sheet1

MPHY RESET Cases

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

MPHY RMMI Interface tests

MPHY RMMI Interface tests

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY DATA transfers

Page 80

Sheet1

MPHY RMMI Interface tests

MPHY RMMI Interface tests

M-PHY DATA transfers

M-PHY - RANDOM TEST CASES

MPHY RESET Cases

MPHY RMMI Interface tests

M-PHY - MODE/GEAR/SERIES CHANGE CASES

Page 81

Sheet1

M-PHY - JITTER & PPM Cases

MPHY RMMI Interface tests

MPHY RMMI Interface tests

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY ERROR transfers

MPHY RMMI Interface tests

M-PHY - MODE/GEAR/SERIES CHANGE CASES

Page 82

Sheet1

M-PHY - MODE/GEAR/SERIES CHANGE CASES

MPHY RESET Cases

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - RANDOM TEST CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

Page 83

Sheet1

M-PHY - MODE/GEAR/SERIES CHANGE CASES

MPHY RMMI Interface tests

M-PHY - MODE/GEAR/SERIES CHANGE CASES

MPHY RESET Cases

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - JITTER & PPM Cases

M-PHY - MODE/GEAR/SERIES CHANGE CASES

Page 84

Sheet1

M-PHY - MODE/GEAR/SERIES CHANGE CASES

MPHY RESET Cases

MPHY RMMI Interface tests

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - JITTER & PPM Cases

Page 85

Sheet1

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

MPHY RESET Cases

M-PHY - MODE/GEAR/SERIES CHANGE CASES

Page 86

Sheet1

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - JITTER & PPM Cases

M-PHY - MODE/GEAR/SERIES CHANGE CASES

MPHY RMMI Interface tests

MPHY RESET Cases

Page 87

Sheet1

MPHY RESET Cases

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

MPHY RMMI Interface tests

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

Page 88

Sheet1

M-PHY DATA transfers

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES/DATA BUS/PATTAREN LENGTH/SYNC LENGTH CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

M-PHY - MODE/GEAR/SERIES CHANGE CASES

Page 89

Sheet1

M-PHY ERROR transfers

Page 90

Sheet1
CATEGORY LOGNAME

COMPLIANCE

compliance_mphy_sync_pattern_width_corrupt.log

COMPLIANCE

compliance_mphy_line_reset_during_ls_burst.log

COMPLIANCE

compliance_mphy_ls_G5_to_hs_G3.log

COMPLIANCE

compliance_mphy_hs_burst_with_hs_G2_in_DigitalEnd_loopback_mode.log

COMPLIANCE

compliance_mphy_ls_G2_to_hs_G3.log

COMPLIANCE

compliance_mphy_hs_G1_hs_burst_with_TX_lanes_3_and_RX_lanes_4.log

Page 91

Sheet1

COMPLIANCE

compliance_mphy_ls_intra_mode_G6_to_G7.log

RANDOM

rand_mphy_mode_test_uvm.log

COMPLIANCE

compliance_mphy_hs_G2_SB_burst_xfer.log

COMPLIANCE

compliance_mphy_state_transition_from_ls_burst_to_line_cfg.log

COMPLIANCE

compliance_mphy_PWM_G1_ls_burst_with_TX_lanes_4_and_RX_lanes_1.log

COMPLIANCE

compliance_mphy_hs_G1_to_ls_G1.log

Page 92

Sheet1

COMPLIANCE

compliance_mphy_ls_G3_to_hs_G2.log

COMPLIANCE

compliance_mphy_ls_intra_mode_G3_to_G6.log

COMPLIANCE

compliance_rmmi_cntl_if_wr_tx_rx_in_stall_state_wo_inlncfg.log

COMPLIANCE

compliance_mphy_burst_hs_G3_HS_PREPARE_length_0.log

COMPLIANCE

compliance_mphy_ls_burst_with_PWM_G6_in_NearEnd_loopback_mode.log

COMPLIANCE

compliance_mphy_ls_PWM_G0_max_burst_xfer.log

COMPLIANCE

compliance_mphy_state_transition_from_stall_to_sleep.log

COMPLIANCE

compliance_mphy_burst_ls_G1_LS_PREPARE_length_0.log

Page 93

Sheet1

COMPLIANCE

compliance_mphy_reset_during_hs_burst.log

COMPLIANCE

compliance_mphy_rx_to_tx_loopback_bfm.log

COMPLIANCE

compliance_mphy_burst_ls_G7_with_min_tob.log

COMPLIANCE

compliance_mphy_burst_ls_G7_SYNC_length_0_SYNC_range_1.log

COMPLIANCE

compliance_mphy_hs_G1_to_ls_G5.log

COMPLIANCE

compliance_mphy_ls_intra_mode_G4_to_G7.log

COMPLIANCE

compliance_mphy_ls_G4_to_hs_G3.log

Page 94

Sheet1

COMPLIANCE

compliance_mphy_ls_PWM_G7_min_burst_xfer.log

COMPLIANCE

compliance_mphy_TOB_corrupt.log

COMPLIANCE

compliance_mphy_DIF_P_hibern8.log

COMPLIANCE

compliance_mphy_ls_PWM_G6_max_burst_xfer.log

COMPLIANCE

compliance_mphy_ls_PWM_G5_max_burst_xfer.log

COMPLIANCE

compliance_mphy_state_transition_from_sleep_to_hibern8.log

COMPLIANCE

compliance_mphy_ls_intra_mode_G3_to_G7.log

Page 95

Sheet1

COMPLIANCE

compliance_mphy_reset_during_hs_sync.log

COMPLIANCE

compliance_mphy_ls_burst_with_PWM_G0_in_NearEnd_loopback_mode.log

COMPLIANCE

compliance_mphy_hs_G2_to_ls_G1.log

COMPLIANCE

compliance_mphy_ls_burst_with_PWM_G5_in_DigitalEnd_loopback_mode.log

COMPLIANCE

compliance_mphy_burst_hs_G2_SYNC_length_15_SYNC_range_1.log

COMPLIANCE

compliance_mphy_burst_hs_G2_SYNC_length_0_SYNC_range_1.log

COMPLIANCE

compliance_mphy_ls_PWM_G1_max_burst_xfer.log

COMPLIANCE

compliance_mphy_burst_hs_G1_SYNC_length_0_SYNC_range_1.log

COMPLIANCE

compliance_mphy_state_transition_from_hs_burst_to_line_cfg.log

Page 96

Sheet1

COMPLIANCE

compliance_mphy_ls_PWM_G3_max_burst_xfer.log

COMPLIANCE

compliance_mphy_rnd_xcess_ppm.log

COMPLIANCE

compliance_mphy_rx_reset_removal_while_tx_in_sleep.log

COMPLIANCE

compliance_mphy_hs_G2_to_ls_G2.log

COMPLIANCE

compliance_mphy_ls_G2_to_hs_G1.log

COMPLIANCE

compliance_mphy_hs_G1_hs_burst_with_TX_lanes_4_and_RX_lanes_4.log

Page 97

Sheet1

COMPLIANCE

compliance_mphy_hs_G3_to_ls_G3.log

COMPLIANCE

compliance_mphy_reg_wr_rd.log

COMPLIANCE

compliance_mphy_burst_ls_G1_LS_PREPARE_length_15.log

COMPLIANCE

compliance_mphy_hs_intra_mode_G2_to_G1.log

COMPLIANCE

compliance_mphy_ls_intra_mode_G1_to_G5.log

COMPLIANCE

compliance_mphy_ls_intra_mode_G4_to_G6.log

COMPLIANCE

compliance_mphy_ls_intra_mode_G5_to_G6.log

Page 98

Sheet1

COMPLIANCE

compliance_mphy_ls_G4_to_hs_G1.log

COMPLIANCE

compliance_mphy_state_transition_from_sleep_to_stall.log

COMPLIANCE

compliance_mphy_ls_intra_mode_G5_to_G4.log

COMPLIANCE

compliance_mphy_ls_PWM_G4_min_burst_xfer.log

COMPLIANCE

compliance_mphy_hs_G2_to_ls_G5.log

COMPLIANCE

compliance_mphy_DIF_Z_burst.log

COMPLIANCE

compliance_mphy_ls_burst_with_PWM_G5_in_NearEnd_loopback_mode.log

Page 99

Sheet1

COMPLIANCE

compliance_mphy_neg_jitter.log

COMPLIANCE

compliance_mphy_line_reset_during_hs_prepare.log

COMPLIANCE

compliance_mphy_state_transition_from_sleep_to_ls_burst.log

COMPLIANCE

compliance_mphy_ls_intra_mode_G4_to_G5.log

COMPLIANCE

compliance_mphy_state_transition_from_stall_to_hibern8.log

COMPLIANCE

compliance_rmmi_cntl_if_rd_tx_rx_in_sleep_state.log

Page 100

Sheet1

COMPLIANCE

compliance_mphy_data_8b_10b_corrupt.log

COMPLIANCE

compliance_mphy_hs_intra_mode_G2_to_G3.log

COMPLIANCE

compliance_mphy_pos_jitter.log

COMPLIANCE

compliance_mphy_ls_G6_to_hs_G3.log

COMPLIANCE

compliance_mphy_hs_G3_to_ls_G6.log

COMPLIANCE

compliance_mphy_ls_intra_mode_G6_to_G2.log

Page 101

Sheet1

COMPLIANCE

compliance_mphy_rx_to_tx_loopback_dut.log

COMPLIANCE

compliance_mphy_ls_intra_mode_G7_to_G6.log

COMPLIANCE

compliance_mphy_ls_intra_mode_G4_to_G2.log

COMPLIANCE

compliance_mphy_hs_intra_mode_G1_to_G2.log

COMPLIANCE

compliance_mphy_ls_intra_mode_G6_to_G4.log

COMPLIANCE

compliance_mphy_ls_burst_with_PWM_G1_in_DigitalEnd_loopback_mode.log

Page 102

Sheet1

COMPLIANCE

compliance_mphy_ls_G7_to_hs_G1.log

COMPLIANCE

compliance_mphy_ls_burst_with_PWM_G7_in_NearEnd_loopback_mode.log

COMPLIANCE

compliance_mphy_DP_DN_same.log

COMPLIANCE

compliance_mphy_burst_hs_G3_SYNC_length_15_SYNC_range_0.log

COMPLIANCE

compliance_mphy_ls_PWM_G5_min_burst_xfer.log

COMPLIANCE

compliance_mphy_hs_G1_SB_burst_xfer.log

COMPLIANCE

compliance_rmmi_cntl_if_wr_tx_rx_in_hibern8_state_wo_inlncfg.log

Page 103

Sheet1

COMPLIANCE

compliance_mphy_tx_driver_polarity.log

COMPLIANCE

compliance_mphy_hs_G1_to_ls_G4.log

COMPLIANCE

compliance_mphy_ls_burst_with_PWM_G6_in_DigitalEnd_loopback_mode.log

COMPLIANCE

compliance_mphy_ls_intra_mode_G2_to_G3.log

COMPLIANCE

compliance_rmmi_cntl_if_wr_tx_rx_in_hibern8_state.log

COMPLIANCE

compliance_mphy_hs_burst_with_hs_G1_in_DigitalEnd_loopback_mode.log

COMPLIANCE

compliance_mphy_reset_during_hibern8.log

Page 104

Sheet1

COMPLIANCE

compliance_mphy_rx_reset_removal_while_tx_in_hibern8.log

COMPLIANCE

compliance_mphy_ls_burst_with_PWM_G0_in_DigitalEnd_loopback_mode.log

COMPLIANCE

compliance_mphy_hs_G1_hs_burst_with_TX_lanes_4_and_RX_lanes_3.log

COMPLIANCE

compliance_mphy_line_reset_during_ls_sync.log

COMPLIANCE

compliance_mphy_PWM_G1_ls_burst_with_TX_lanes_4_and_RX_lanes_2.log

COMPLIANCE

compliance_mphy_burst_hs_G1_SYNC_length_15_SYNC_range_0.log

COMPLIANCE

compliance_mphy_reset_during_ls_sync.log

COMPLIANCE

compliance_mphy_PWM_G1_ls_burst_with_TX_lanes_4_and_RX_lanes_4.log

Page 105

Sheet1

COMPLIANCE

compliance_mphy_burst_hs_G1_SYNC_length_0_SYNC_range_0.log

COMPLIANCE

compliance_mphy_ls_intra_mode_G7_to_G7.log

COMPLIANCE

compliance_mphy_hs_G3_to_ls_G4.log

COMPLIANCE

compliance_rmmi_cntl_if_wr_tx_rx_in_sleep_state_wo_inlncfg.log

COMPLIANCE

compliance_mphy_burst_hs_G2_SYNC_length_0_SYNC_range_0.log

COMPLIANCE

compliance_mphy_hs_G1_to_ls_G3.log

COMPLIANCE

compliance_mphy_hs_G3_SB_burst_xfer.log

COMPLIANCE

compliance_mphy_ls_intra_mode_G1_to_G3.log

Page 106

Sheet1

COMPLIANCE

compliance_mphy_burst_hs_G2_SYNC_length_15_SYNC_range_0.log

COMPLIANCE

compliance_mphy_PWM_G1_ls_burst_with_TX_lanes_2_and_RX_lanes_4.log

COMPLIANCE

compliance_mphy_ls_intra_mode_G5_to_G3.log

COMPLIANCE

compliance_mphy_ls_burst_with_PWM_G1_in_NearEnd_loopback_mode.log

COMPLIANCE

compliance_mphy_state_transition_from_line_cfg_to_sleep.log

COMPLIANCE

compliance_mphy_state_transition_from_line_cfg_to_stall.log

COMPLIANCE

compliance_mphy_ls_intra_mode_G2_to_G1.log

COMPLIANCE

compliance_mphy_ls_intra_mode_G2_to_G4.log

COMPLIANCE

compliance_mphy_burst_hs_G1_with_data_bus_40_bits.log

Page 107

Sheet1

COMPLIANCE

compliance_rmmi_cntl_if_rd_tx_rx_in_hibern8_state.log

COMPLIANCE

compliance_mphy_burst_ls_G6_SYNC_length_15_SYNC_range_0.log

COMPLIANCE

compliance_mphy_burst_hs_G3_with_data_bus_40_bits.log

COMPLIANCE

compliance_mphy_ls_intra_mode_G5_to_G1.log

RANDOM

rand_mphy_line_cfg_test_uvm.log

COMPLIANCE

compliance_mphy_ls_intra_mode_G5_to_G5.log

COMPLIANCE

compliance_mphy_PWM_G1_ls_burst_with_TX_lanes_1_and_RX_lanes_4.log

COMPLIANCE

compliance_mphy_burst_ls_G7_with_data_bus_40_bits.log

Page 108

Sheet1

COMPLIANCE

compliance_mphy_hs_G2_to_ls_G4.log

COMPLIANCE

compliance_mphy_burst_hs_G1_with_max_tob.log

COMPLIANCE

compliance_mphy_burst_hs_G3_SYNC_length_0_SYNC_range_1.log

COMPLIANCE

compliance_mphy_burst_ls_G6_SYNC_length_0_SYNC_range_0.log

COMPLIANCE

compliance_mphy_line_reset_during_hs_burst.log

COMPLIANCE

compliance_mphy_burst_hs_G3_SYNC_length_15_SYNC_range_1.log

COMPLIANCE

compliance_mphy_burst_hs_G3_with_data_bus_20_bits.log

COMPLIANCE

compliance_mphy_burst_hs_G3_with_data_bus_10_bits.log

Page 109

Sheet1

COMPLIANCE

compliance_mphy_ls_G6_to_hs_G2.log

COMPLIANCE

compliance_mphy_DIF_N_hibern8.log

COMPLIANCE

compliance_mphy_burst_hs_G1_SYNC_length_15_SYNC_range_1.log

COMPLIANCE

compliance_mphy_burst_ls_G6_SYNC_length_15_SYNC_range_1.log

COMPLIANCE

compliance_mphy_ls_G1_to_hs_G3.log

COMPLIANCE

compliance_mphy_ls_PWM_G1_min_burst_xfer.log

COMPLIANCE

compliance_mphy_ls_G2_to_hs_G2.log

COMPLIANCE

compliance_mphy_burst_hs_G1_with_data_bus_20_bits.log

Page 110

Sheet1

COMPLIANCE

compliance_mphy_hs_G2_to_ls_G3.log

COMPLIANCE

compliance_rmmi_cntl_if_rd_tx_rx_in_line_cfg_state.log

COMPLIANCE

compliance_mphy_ls_intra_mode_G3_to_G3.log

COMPLIANCE

compliance_mphy_DIF_Z_LR.log

COMPLIANCE

compliance_mphy_neg_xcess_ppm.log

COMPLIANCE

compliance_mphy_burst_ls_G6_random_sync_pattern.log

COMPLIANCE

compliance_mphy_ls_intra_mode_G5_to_G7.log

Page 111

Sheet1

COMPLIANCE

compliance_mphy_PWM_G1_ls_burst_with_TX_lanes_3_and_RX_lanes_4.log

COMPLIANCE

compliance_mphy_line_reset_during_sleep.log

COMPLIANCE

compliance_mphy_ls_G3_to_hs_G3.log

COMPLIANCE

compliance_mphy_reset_during_hs_prepare.log

COMPLIANCE

compliance_rmmi_cntl_if_wr_tx_rx_in_line_cfg_state.log

COMPLIANCE

compliance_mphy_hs_intra_mode_G3_to_G2.log

Page 112

Sheet1

COMPLIANCE

compliance_rmmi_cntl_if_rd_tx_rx_in_hs_burst_state.log

COMPLIANCE

compliance_mphy_ls_PWM_G0_min_burst_xfer.log

COMPLIANCE

compliance_mphy_reg_wr_rd_err.log

COMPLIANCE

compliance_mphy_DIF_Z_prepare.log

COMPLIANCE

compliance_mphy_ls_burst_with_PWM_G7_in_DigitalEnd_loopback_mode.log

COMPLIANCE

compliance_mphy_burst_ls_G7_with_max_tob.log

COMPLIANCE

compliance_mphy_ls_intra_mode_G5_to_G2.log

Page 113

Sheet1

COMPLIANCE

compliance_mphy_ls_G3_to_hs_G1.log

COMPLIANCE

compliance_mphy_state_transition_from_hibern8_to_sleep.log

COMPLIANCE

compliance_mphy_ls_intra_mode_G2_to_G5.log

COMPLIANCE

compliance_mphy_hs_G1_to_ls_G2.log

COMPLIANCE

compliance_mphy_burst_ls_G1_with_min_tob.log

COMPLIANCE

compliance_mphy_hs_G3_to_ls_mode.log

Page 114

Sheet1

RANDOM

rand_mphy_long_burst_test_uvm.log

COMPLIANCE

compliance_mphy_ls_intra_mode_G7_to_G2.log

COMPLIANCE

compliance_mphy_ls_burst_with_PWM_G4_in_DigitalEnd_loopback_mode.log

COMPLIANCE

compliance_mphy_ls_G5_to_hs_G2.log

COMPLIANCE

compliance_mphy_hs_G3_SA_burst_xfer.log

COMPLIANCE

compliance_mphy_state_transition_from_stall_to_hs_burst.log

COMPLIANCE

compliance_rmmi_cntl_if_rd_tx_rx_in_ls_burst_state.log

Page 115

Sheet1

COMPLIANCE

compliance_mphy_rd_err.log

COMPLIANCE

compliance_rmmi_cntl_if_wr_tx_rx_in_save_state.log

COMPLIANCE

compliance_mphy_burst_ls_G1_with_data_bus_20_bits.log

COMPLIANCE

compliance_mphy_ls_PWM_G3_min_burst_xfer.log

COMPLIANCE

compliance_mphy_reset_during_line_cfg.log

COMPLIANCE

compliance_mphy_line_reset_during_hs_sync.log

COMPLIANCE

compliance_mphy_ls_G5_to_hs_G1.log

Page 116

Sheet1

COMPLIANCE

compliance_rmmi_cntl_if_rd_tx_rx_in_disable_state.log

COMPLIANCE

compliance_rmmi_cntl_if_wr_cfgupdt_during_save_state_tx_rx.log

COMPLIANCE

compliance_mphy_burst_hs_G3_SYNC_length_0_SYNC_range_0.log

COMPLIANCE

compliance_mphy_ls_PWM_G2_min_burst_xfer.log

COMPLIANCE

compliance_mphy_ls_PWM_G4_max_burst_xfer.log

COMPLIANCE

compliance_mphy_DIF_Z_save.log

COMPLIANCE

compliance_mphy_ls_burst_with_PWM_G2_in_NearEnd_loopback_mode.log

COMPLIANCE

compliance_mphy_ls_burst_with_PWM_G3_in_DigitalEnd_loopback_mode.log

COMPLIANCE

compliance_mphy_ls_intra_mode_G6_to_G3.log

Page 117

Sheet1

COMPLIANCE

compliance_rmmi_cntl_if_wr_tx_rx_in_line_cfg_state_wo_inlncfg.log

COMPLIANCE

compliance_mphy_ls_intra_mode_G7_to_G5.log

COMPLIANCE

compliance_mphy_hs_burst_with_hs_G3_in_NearEnd_loopback_mode.log

COMPLIANCE

compliance_mphy_ls_burst_with_PWM_G4_in_NearEnd_loopback_mode.log

COMPLIANCE

compliance_rmmi_cntl_if_wr_tx_rx_in_stall_state.log

COMPLIANCE

compliance_mphy_state_transition_from_hibern8_to_stall.log

COMPLIANCE

compliance_mphy_ls_intra_mode_G2_to_G6.log

COMPLIANCE

compliance_mphy_hs_G2_SA_burst_xfer.log

COMPLIANCE

compliance_mphy_burst_ls_G7_with_data_bus_20_bits.log

Page 118

Sheet1

COMPLIANCE

compliance_mphy_hs_G1_hs_burst_with_TX_lanes_4_and_RX_lanes_2.log

COMPLIANCE

compliance_mphy_ls_intra_mode_G7_to_G4.log

COMPLIANCE

compliance_mphy_burst_hs_G3_random_sync_pattern.log

COMPLIANCE

compliance_mphy_burst_ls_G7_random_sync_pattern.log

COMPLIANCE

compliance_mphy_burst_hs_G3_with_min_tob.log

COMPLIANCE

compliance_mphy_burst_ls_G7_LS_PREPARE_length_0.log

COMPLIANCE

compliance_mphy_ls_mode_to_hs_G3.log

COMPLIANCE

compliance_rmmi_cntl_if_wr_cfgupdt_during_burst_state_tx_rx.log

COMPLIANCE

compliance_mphy_hs_G2_to_ls_G6.log

Page 119

Sheet1

COMPLIANCE

compliance_mphy_reset_during_ls_prepare.log

COMPLIANCE

compliance_mphy_hs_G1_to_ls_G6.log

COMPLIANCE

compliance_mphy_burst_hs_G1_random_sync_pattern.log

COMPLIANCE

compliance_mphy_ls_intra_mode_G3_to_G4.log

COMPLIANCE

compliance_mphy_burst_ls_G1_with_data_bus_40_bits.log

COMPLIANCE

compliance_mphy_state_transition_from_hs_burst_to_stall.log

COMPLIANCE

compliance_mphy_line_reset_during_tob.log

Page 120

Sheet1

COMPLIANCE

compliance_mphy_pos_xcess_jitter.log

COMPLIANCE

compliance_mphy_rnd_jitter.log

COMPLIANCE

compliance_mphy_sync_pattern_corrupt.log

COMPLIANCE

compliance_mphy_ls_intra_mode_G7_to_G1.log

COMPLIANCE

compliance_mphy_ls_intra_mode_G1_to_G7.log

COMPLIANCE

compliance_mphy_burst_ls_G7_SYNC_length_15_SYNC_range_1.log

Page 121

Sheet1

COMPLIANCE

compliance_mphy_line_config.log

COMPLIANCE

compliance_mphy_ls_intra_mode_G1_to_G6.log

COMPLIANCE

compliance_mphy_ls_intra_mode_G6_to_G1.log

COMPLIANCE

compliance_mphy_state_transition_from_ls_burst_to_sleep.log

COMPLIANCE

compliance_mphy_ls_intra_mode_G1_to_G4.log

COMPLIANCE

compliance_mphy_ls_intra_mode_G3_to_G1.log

COMPLIANCE

compliance_mphy_ls_intra_mode_G4_to_G1.log

Page 122

Sheet1

COMPLIANCE

compliance_mphy_ls_mode_to_hs_G1.log

COMPLIANCE

compliance_mphy_burst_ls_G6_SYNC_length_0_SYNC_range_1.log

COMPLIANCE

compliance_mphy_hs_G3_to_ls_G2.log

COMPLIANCE

compliance_mphy_hs_burst_with_hs_G3_in_DigitalEnd_loopback_mode.log

COMPLIANCE

compliance_mphy_pos_xcess_ppm.log

COMPLIANCE

compliance_mphy_hs_G1_hs_burst_with_TX_lanes_4_and_RX_lanes_1.log

COMPLIANCE

compliance_mphy_hs_G2_to_ls_mode.log

Page 123

Sheet1

COMPLIANCE

compliance_mphy_hs_G1_hs_burst_with_TX_lanes_2_and_RX_lanes_4.log

COMPLIANCE

compliance_mphy_rnd_xcess_jitter.log

COMPLIANCE

compliance_mphy_burst_ls_G7_with_data_bus_10_bits.log

COMPLIANCE

compliance_mphy_hs_G1_SA_burst_xfer.log

COMPLIANCE

compliance_rmmi_cntl_if_rd_tx_rx_in_stall_state.log

COMPLIANCE

compliance_mphy_ls_intra_mode_G1_to_G2.log

COMPLIANCE

compliance_mphy_hs_intra_mode_G1_to_G3.log

Page 124

Sheet1

COMPLIANCE

compliance_mphy_line_reset_during_sleep_with_TX_Controlled_Act_Timer.log

COMPLIANCE

compliance_mphy_ls_intra_mode_G3_to_G2.log

COMPLIANCE

compliance_mphy_hs_G1_to_ls_mode.log

COMPLIANCE

compliance_rmmi_cntl_if_wr_tx_rx_in_hs_burst_state_wo_inlncfg.log

COMPLIANCE

compliance_mphy_ls_burst_with_PWM_G3_in_NearEnd_loopback_mode.log

COMPLIANCE

compliance_mphy_burst_hs_G1_HS_PREPARE_length_0.log

COMPLIANCE

compliance_mphy_ls_PWM_G2_max_burst_xfer.log

Page 125

Sheet1

COMPLIANCE

compliance_mphy_hs_burst_with_hs_G1_in_NearEnd_loopback_mode.log

COMPLIANCE

compliance_rmmi_cntl_if_wr_tx_rx_in_sleep_state.log

COMPLIANCE

compliance_mphy_ls_PWM_G7_max_burst_xfer.log

RANDOM

rand_mphy_line_rst_test_uvm.log

COMPLIANCE

compliance_mphy_reset_during_disable.log

COMPLIANCE

compliance_mphy_hs_burst_with_hs_G2_in_NearEnd_loopback_mode.log

COMPLIANCE

compliance_mphy_burst_ls_G1_with_max_tob.log

Page 126

Sheet1

COMPLIANCE

compliance_mphy_neg_ppm.log

COMPLIANCE

compliance_rmmi_cntl_if_wr_tx_rx_in_hs_burst_state.log

COMPLIANCE

compliance_rmmi_cntl_if_rd_tx_rx_in_line_reset_state.log

COMPLIANCE

compliance_mphy_ls_intra_mode_G6_to_G5.log

COMPLIANCE

compliance_mphy_cntl_corrupt.log

COMPLIANCE

compliance_rmmi_cntl_if_wr_tx_rx_in_ls_burst_state.log

COMPLIANCE

compliance_mphy_ls_G7_to_hs_G3.log

Page 127

Sheet1

COMPLIANCE

compliance_mphy_burst_hs_G1_with_data_bus_10_bits.log

COMPLIANCE

compliance_mphy_reset_during_sleep.log

COMPLIANCE

compliance_mphy_hs_G3_to_ls_G7.log

RANDOM

rand_mphy_long_line_cfg_test_uvm.log

COMPLIANCE

compliance_mphy_burst_ls_G1_with_data_bus_10_bits.log

COMPLIANCE

compliance_mphy_hs_G1_to_ls_G7.log

COMPLIANCE

compliance_mphy_burst_ls_G7_LS_PREPARE_length_15.log

Page 128

Sheet1

COMPLIANCE

compliance_mphy_burst_hs_G1_with_min_tob.log

COMPLIANCE

compliance_mphy_hs_G1_hs_burst_with_TX_lanes_1_and_RX_lanes_4.log

COMPLIANCE

compliance_mphy_hs_G2_to_ls_G7.log

COMPLIANCE

compliance_mphy_reset_during_stall.log

COMPLIANCE

compliance_mphy_ls_intra_mode_G4_to_G4.log

COMPLIANCE

compliance_mphy_neg_xcess_jitter.log

COMPLIANCE

compliance_mphy_ls_intra_mode_G1_to_G1.log

Page 129

Sheet1

COMPLIANCE

compliance_mphy_ls_intra_mode_G2_to_G2.log

COMPLIANCE

compliance_mphy_line_reset_during_stall_with_TX_Controlled_Act_Timer.log

COMPLIANCE

compliance_mphy_ls_burst_with_PWM_G2_in_DigitalEnd_loopback_mode.log

COMPLIANCE

compliance_mphy_hs_G3_to_ls_G1.log

COMPLIANCE

compliance_mphy_burst_hs_G1_HS_PREPARE_length_15.log

COMPLIANCE

compliance_mphy_pos_ppm.log

Page 130

Sheet1

COMPLIANCE

compliance_mphy_burst_hs_G3_HS_PREPARE_length_15.log

COMPLIANCE

compliance_mphy_burst_data_xfer.log

COMPLIANCE

compliance_mphy_ls_mode_to_hs_G2.log

COMPLIANCE

compliance_mphy_burst_hs_G3_with_max_tob.log

COMPLIANCE

compliance_mphy_line_reset_during_ls_prepare.log

COMPLIANCE

compliance_mphy_ls_intra_mode_G2_to_G7.log

Page 131

Sheet1

COMPLIANCE

compliance_mphy_ls_intra_mode_G4_to_G3.log

COMPLIANCE

compliance_mphy_rnd_ppm.log

COMPLIANCE

compliance_mphy_hs_G3_to_ls_G5.log

COMPLIANCE

compliance_mphy_PWM_G1_ls_burst_with_TX_lanes_4_and_RX_lanes_3.log

COMPLIANCE

compliance_mphy_line_reset_during_stall.log

Page 132

Sheet1

COMPLIANCE

compliance_mphy_reset_during_ls_burst.log

COMPLIANCE

compliance_mphy_ls_G4_to_hs_G2.log

COMPLIANCE

compliance_mphy_ls_G1_to_hs_G1.log

COMPLIANCE

compliance_mphy_ls_G6_to_hs_G1.log

COMPLIANCE

compliance_rmmi_cntl_if_wr_tx_rx_in_ls_burst_state_wo_inlncfg.log

COMPLIANCE

compliance_mphy_burst_ls_G7_SYNC_length_15_SYNC_range_0.log

COMPLIANCE

compliance_mphy_ls_intra_mode_G6_to_G6.log

Page 133

Sheet1

COMPLIANCE

compliance_mphy_ls_PWM_G6_min_burst_xfer.log

COMPLIANCE

compliance_mphy_ls_intra_mode_G3_to_G5.log

COMPLIANCE

compliance_mphy_ls_G7_to_hs_G2.log

COMPLIANCE

compliance_mphy_hs_intra_mode_G3_to_G1.log

COMPLIANCE

compliance_mphy_burst_ls_G7_SYNC_length_0_SYNC_range_0.log

COMPLIANCE

compliance_mphy_ls_intra_mode_G7_to_G3.log

COMPLIANCE

compliance_mphy_ls_G1_to_hs_G2.log

Page 134

Sheet1

COMPLIANCE

compliance_mphy_SOB_corrupt.log

Page 135

Sheet1
TESTNAME

mphy_sync_pattern_width_corrupt_test

mphy_line_reset_during_ls_burst_test

mphy_ls_G5_to_hs_G3_test

mphy_hs_burst_with_hs_G2_in_DigitalEnd_loopback_mode_test

mphy_ls_G2_to_hs_G3_test

mphy_hs_G1_hs_burst_with_TX_lanes_3_and_RX_lanes_4_test

Page 136

Sheet1

mphy_ls_intra_mode_G6_to_G7_test

mphy_tb_random_mode_test

mphy_hs_G2_SB_burst_xfer_test

mphy_state_transition_from_ls_burst_to_line_cfg_test

mphy_PWM_G1_ls_burst_with_TX_lanes_4_and_RX_lanes_1_test

mphy_hs_G1_to_ls_G1_test

Page 137

Sheet1

mphy_ls_G3_to_hs_G2_test

mphy_ls_intra_mode_G3_to_G6_test

rmmi_cntl_if_wr_tx_rx_in_stall_state_wo_inlncfg_test

mphy_burst_hs_G3_HS_PREPARE_length_0_test

mphy_ls_burst_with_PWM_G6_in_NearEnd_loopback_mode_test

mphy_ls_PWM_G0_max_burst_xfer_test

mphy_state_transition_from_stall_to_sleep_test

mphy_burst_ls_G1_LS_PREPARE_length_0_test

Page 138

Sheet1

mphy_reset_during_hs_burst_test

mphy_rx_to_tx_loopback_bfm_test

mphy_burst_ls_G7_with_min_tob_test

mphy_burst_ls_G7_SYNC_length_0_SYNC_range_1_test

mphy_hs_G1_to_ls_G5_test

mphy_ls_intra_mode_G4_to_G7_test

mphy_ls_G4_to_hs_G3_test

Page 139

Sheet1

mphy_ls_PWM_G7_min_burst_xfer_test

mphy_TOB_corrupt_test

mphy_DIF_P_hibern8_test

mphy_ls_PWM_G6_max_burst_xfer_test

mphy_ls_PWM_G5_max_burst_xfer_test

mphy_state_transition_from_sleep_to_hibern8_test

mphy_ls_intra_mode_G3_to_G7_test

Page 140

Sheet1

mphy_reset_during_hs_sync_test

mphy_ls_burst_with_PWM_G0_in_NearEnd_loopback_mode_test

mphy_hs_G2_to_ls_G1_test

mphy_ls_burst_with_PWM_G5_in_DigitalEnd_loopback_mode_test

mphy_burst_hs_G2_SYNC_length_15_SYNC_range_1_test

mphy_burst_hs_G2_SYNC_length_0_SYNC_range_1_test

mphy_ls_PWM_G1_max_burst_xfer_test

mphy_burst_hs_G1_SYNC_length_0_SYNC_range_1_test

mphy_state_transition_from_hs_burst_to_line_cfg_test

Page 141

Sheet1

mphy_ls_PWM_G3_max_burst_xfer_test

mphy_rnd_xcess_ppm_test

mphy_rx_reset_removal_while_tx_in_sleep_test

mphy_hs_G2_to_ls_G2_test

mphy_ls_G2_to_hs_G1_test

mphy_hs_G1_hs_burst_with_TX_lanes_4_and_RX_lanes_4_test

Page 142

Sheet1

mphy_hs_G3_to_ls_G3_test

mphy_reg_wr_rd_test

mphy_burst_ls_G1_LS_PREPARE_length_15_test

mphy_hs_intra_mode_G2_to_G1_test

mphy_ls_intra_mode_G1_to_G5_test

mphy_ls_intra_mode_G4_to_G6_test

mphy_ls_intra_mode_G5_to_G6_test

Page 143

Sheet1

mphy_ls_G4_to_hs_G1_test

mphy_state_transition_from_sleep_to_stall_test

mphy_ls_intra_mode_G5_to_G4_test

mphy_ls_PWM_G4_min_burst_xfer_test

mphy_hs_G2_to_ls_G5_test

mphy_DIF_Z_burst_test

mphy_ls_burst_with_PWM_G5_in_NearEnd_loopback_mode_test

Page 144

Sheet1

mphy_neg_jitter_test

mphy_line_reset_during_hs_prepare_test

mphy_state_transition_from_sleep_to_ls_burst_test

mphy_ls_intra_mode_G4_to_G5_test

mphy_state_transition_from_stall_to_hibern8_test

rmmi_cntl_if_rd_tx_rx_in_sleep_state_test

Page 145

Sheet1

mphy_data_8b_10b_corrupt_test

mphy_hs_intra_mode_G2_to_G3_test

mphy_pos_jitter_test

mphy_ls_G6_to_hs_G3_test

mphy_hs_G3_to_ls_G6_test

mphy_ls_intra_mode_G6_to_G2_test

Page 146

Sheet1

mphy_rx_to_tx_loopback_dut_test

mphy_ls_intra_mode_G7_to_G6_test

mphy_ls_intra_mode_G4_to_G2_test

mphy_hs_intra_mode_G1_to_G2_test

mphy_ls_intra_mode_G6_to_G4_test

mphy_ls_burst_with_PWM_G1_in_DigitalEnd_loopback_mode_test

Page 147

Sheet1

mphy_ls_G7_to_hs_G1_test

mphy_ls_burst_with_PWM_G7_in_NearEnd_loopback_mode_test

mphy_DP_DN_same_test

mphy_burst_hs_G3_SYNC_length_15_SYNC_range_0_test

mphy_ls_PWM_G5_min_burst_xfer_test

mphy_hs_G1_SB_burst_xfer_test

rmmi_cntl_if_wr_tx_rx_in_hibern8_state_wo_inlncfg_test

Page 148

Sheet1

mphy_tx_driver_polarity_test

mphy_hs_G1_to_ls_G4_test

mphy_ls_burst_with_PWM_G6_in_DigitalEnd_loopback_mode_test

mphy_ls_intra_mode_G2_to_G3_test

rmmi_cntl_if_wr_tx_rx_in_hibern8_state_test

mphy_hs_burst_with_hs_G1_in_DigitalEnd_loopback_mode_test

mphy_reset_during_hibern8_test

Page 149

Sheet1

mphy_rx_reset_removal_while_tx_in_hibern8_test

mphy_ls_burst_with_PWM_G0_in_DigitalEnd_loopback_mode_test

mphy_hs_G1_hs_burst_with_TX_lanes_4_and_RX_lanes_3_test

mphy_line_reset_during_ls_sync_test

mphy_PWM_G1_ls_burst_with_TX_lanes_4_and_RX_lanes_2_test

mphy_burst_hs_G1_SYNC_length_15_SYNC_range_0_test

mphy_reset_during_ls_sync_test

mphy_PWM_G1_ls_burst_with_TX_lanes_4_and_RX_lanes_4_test

Page 150

Sheet1

mphy_burst_hs_G1_SYNC_length_0_SYNC_range_0_test

mphy_ls_intra_mode_G7_to_G7_test

mphy_hs_G3_to_ls_G4_test

rmmi_cntl_if_wr_tx_rx_in_sleep_state_wo_inlncfg_test

mphy_burst_hs_G2_SYNC_length_0_SYNC_range_0_test

mphy_hs_G1_to_ls_G3_test

mphy_hs_G3_SB_burst_xfer_test

mphy_ls_intra_mode_G1_to_G3_test

Page 151

Sheet1

mphy_burst_hs_G2_SYNC_length_15_SYNC_range_0_test

mphy_PWM_G1_ls_burst_with_TX_lanes_2_and_RX_lanes_4_test

mphy_ls_intra_mode_G5_to_G3_test

mphy_ls_burst_with_PWM_G1_in_NearEnd_loopback_mode_test

mphy_state_transition_from_line_cfg_to_sleep_test

mphy_state_transition_from_line_cfg_to_stall_test

mphy_ls_intra_mode_G2_to_G1_test

mphy_ls_intra_mode_G2_to_G4_test

mphy_burst_hs_G1_with_data_bus_40_bits_test

Page 152

Sheet1

rmmi_cntl_if_rd_tx_rx_in_hibern8_state_test

mphy_burst_ls_G6_SYNC_length_15_SYNC_range_0_test

mphy_burst_hs_G3_with_data_bus_40_bits_test

mphy_ls_intra_mode_G5_to_G1_test

mphy_tb_random_line_cfg_test

mphy_ls_intra_mode_G5_to_G5_test

mphy_PWM_G1_ls_burst_with_TX_lanes_1_and_RX_lanes_4_test

mphy_burst_ls_G7_with_data_bus_40_bits_test

Page 153

Sheet1

mphy_hs_G2_to_ls_G4_test

mphy_burst_hs_G1_with_max_tob_test

mphy_burst_hs_G3_SYNC_length_0_SYNC_range_1_test

mphy_burst_ls_G6_SYNC_length_0_SYNC_range_0_test

mphy_line_reset_during_hs_burst_test

mphy_burst_hs_G3_SYNC_length_15_SYNC_range_1_test

mphy_burst_hs_G3_with_data_bus_20_bits_test

mphy_burst_hs_G3_with_data_bus_10_bits_test

Page 154

Sheet1

mphy_ls_G6_to_hs_G2_test

mphy_DIF_N_hibern8_test

mphy_burst_hs_G1_SYNC_length_15_SYNC_range_1_test

mphy_burst_ls_G6_SYNC_length_15_SYNC_range_1_test

mphy_ls_G1_to_hs_G3_test

mphy_ls_PWM_G1_min_burst_xfer_test

mphy_ls_G2_to_hs_G2_test

mphy_burst_hs_G1_with_data_bus_20_bits_test

Page 155

Sheet1

mphy_hs_G2_to_ls_G3_test

rmmi_cntl_if_rd_tx_rx_in_line_cfg_state_test

mphy_ls_intra_mode_G3_to_G3_test

mphy_DIF_Z_LR_test

mphy_neg_xcess_ppm_test

mphy_burst_ls_G6_random_sync_pattern_test

mphy_ls_intra_mode_G5_to_G7_test

Page 156

Sheet1

mphy_PWM_G1_ls_burst_with_TX_lanes_3_and_RX_lanes_4_test

mphy_line_reset_during_sleep_test

mphy_ls_G3_to_hs_G3_test

mphy_reset_during_hs_prepare_test

rmmi_cntl_if_wr_tx_rx_in_line_cfg_state_test

mphy_hs_intra_mode_G3_to_G2_test

Page 157

Sheet1

rmmi_cntl_if_rd_tx_rx_in_hs_burst_state_test

mphy_ls_PWM_G0_min_burst_xfer_test

mphy_reg_wr_rd_err_test

mphy_DIF_Z_prepare_test

mphy_ls_burst_with_PWM_G7_in_DigitalEnd_loopback_mode_test

mphy_burst_ls_G7_with_max_tob_test

mphy_ls_intra_mode_G5_to_G2_test

Page 158

Sheet1

mphy_ls_G3_to_hs_G1_test

mphy_state_transition_from_hibern8_to_sleep_test

mphy_ls_intra_mode_G2_to_G5_test

mphy_hs_G1_to_ls_G2_test

mphy_burst_ls_G1_with_min_tob_test

mphy_hs_G3_to_ls_mode_test

Page 159

Sheet1

mphy_tb_random_long_burst_test

mphy_ls_intra_mode_G7_to_G2_test

mphy_ls_burst_with_PWM_G4_in_DigitalEnd_loopback_mode_test

mphy_ls_G5_to_hs_G2_test

mphy_hs_G3_SA_burst_xfer_test

mphy_state_transition_from_stall_to_hs_burst_test

rmmi_cntl_if_rd_tx_rx_in_ls_burst_state_test

Page 160

Sheet1

mphy_rd_err_test

rmmi_cntl_if_wr_tx_rx_in_save_state_test

mphy_burst_ls_G1_with_data_bus_20_bits_test

mphy_ls_PWM_G3_min_burst_xfer_test

mphy_reset_during_line_cfg_test

mphy_line_reset_during_hs_sync_test

mphy_ls_G5_to_hs_G1_test

Page 161

Sheet1

rmmi_cntl_if_rd_tx_rx_in_disable_state_test

rmmi_cntl_if_wr_cfgupdt_during_save_state_tx_rx_test

mphy_burst_hs_G3_SYNC_length_0_SYNC_range_0_test

mphy_ls_PWM_G2_min_burst_xfer_test

mphy_ls_PWM_G4_max_burst_xfer_test

mphy_DIF_Z_save_test

mphy_ls_burst_with_PWM_G2_in_NearEnd_loopback_mode_test

mphy_ls_burst_with_PWM_G3_in_DigitalEnd_loopback_mode_test

mphy_ls_intra_mode_G6_to_G3_test

Page 162

Sheet1

rmmi_cntl_if_wr_tx_rx_in_line_cfg_state_wo_inlncfg_test

mphy_ls_intra_mode_G7_to_G5_test

mphy_hs_burst_with_hs_G3_in_NearEnd_loopback_mode_test

mphy_ls_burst_with_PWM_G4_in_NearEnd_loopback_mode_test

rmmi_cntl_if_wr_tx_rx_in_stall_state_test

mphy_state_transition_from_hibern8_to_stall_test

mphy_ls_intra_mode_G2_to_G6_test

mphy_hs_G2_SA_burst_xfer_test

mphy_burst_ls_G7_with_data_bus_20_bits_test

Page 163

Sheet1

mphy_hs_G1_hs_burst_with_TX_lanes_4_and_RX_lanes_2_test

mphy_ls_intra_mode_G7_to_G4_test

mphy_burst_hs_G3_random_sync_pattern_test

mphy_burst_ls_G7_random_sync_pattern_test

mphy_burst_hs_G3_with_min_tob_test

mphy_burst_ls_G7_LS_PREPARE_length_0_test

mphy_ls_mode_to_hs_G3_test

rmmi_cntl_if_wr_cfgupdt_during_burst_state_tx_rx_test

mphy_hs_G2_to_ls_G6_test

Page 164

Sheet1

mphy_reset_during_ls_prepare_test

mphy_hs_G1_to_ls_G6_test

mphy_burst_hs_G1_random_sync_pattern_test

mphy_ls_intra_mode_G3_to_G4_test

mphy_burst_ls_G1_with_data_bus_40_bits_test

mphy_state_transition_from_hs_burst_to_stall_test

mphy_line_reset_during_tob_test

Page 165

Sheet1

mphy_pos_xcess_jitter_test

mphy_rnd_jitter_test

mphy_sync_pattern_corrupt_test

mphy_ls_intra_mode_G7_to_G1_test

mphy_ls_intra_mode_G1_to_G7_test

mphy_burst_ls_G7_SYNC_length_15_SYNC_range_1_test

Page 166

Sheet1

mphy_line_config_test

mphy_ls_intra_mode_G1_to_G6_test

mphy_ls_intra_mode_G6_to_G1_test

mphy_state_transition_from_ls_burst_to_sleep_test

mphy_ls_intra_mode_G1_to_G4_test

mphy_ls_intra_mode_G3_to_G1_test

mphy_ls_intra_mode_G4_to_G1_test

Page 167

Sheet1

mphy_ls_mode_to_hs_G1_test

mphy_burst_ls_G6_SYNC_length_0_SYNC_range_1_test

mphy_hs_G3_to_ls_G2_test

mphy_hs_burst_with_hs_G3_in_DigitalEnd_loopback_mode_test

mphy_pos_xcess_ppm_test

mphy_hs_G1_hs_burst_with_TX_lanes_4_and_RX_lanes_1_test

mphy_hs_G2_to_ls_mode_test

Page 168

Sheet1

mphy_hs_G1_hs_burst_with_TX_lanes_2_and_RX_lanes_4_test

mphy_rnd_xcess_jitter_test

mphy_burst_ls_G7_with_data_bus_10_bits_test

mphy_hs_G1_SA_burst_xfer_test

rmmi_cntl_if_rd_tx_rx_in_stall_state_test

mphy_ls_intra_mode_G1_to_G2_test

mphy_hs_intra_mode_G1_to_G3_test

Page 169

Sheet1

mphy_line_reset_during_sleep_with_TX_Controlled_Act_Timer_test

mphy_ls_intra_mode_G3_to_G2_test

mphy_hs_G1_to_ls_mode_test

rmmi_cntl_if_wr_tx_rx_in_hs_burst_state_wo_inlncfg_test

mphy_ls_burst_with_PWM_G3_in_NearEnd_loopback_mode_test

mphy_burst_hs_G1_HS_PREPARE_length_0_test

mphy_ls_PWM_G2_max_burst_xfer_test

Page 170

Sheet1

mphy_hs_burst_with_hs_G1_in_NearEnd_loopback_mode_test

rmmi_cntl_if_wr_tx_rx_in_sleep_state_test

mphy_ls_PWM_G7_max_burst_xfer_test

mphy_tb_random_line_rst_test

mphy_reset_during_disable_test

mphy_hs_burst_with_hs_G2_in_NearEnd_loopback_mode_test

mphy_burst_ls_G1_with_max_tob_test

Page 171

Sheet1

mphy_neg_ppm_test

rmmi_cntl_if_wr_tx_rx_in_hs_burst_state_test

rmmi_cntl_if_rd_tx_rx_in_line_reset_state_test

mphy_ls_intra_mode_G6_to_G5_test

mphy_cntl_corrupt_test

rmmi_cntl_if_wr_tx_rx_in_ls_burst_state_test

mphy_ls_G7_to_hs_G3_test

Page 172

Sheet1

mphy_burst_hs_G1_with_data_bus_10_bits_test

mphy_reset_during_sleep_test

mphy_hs_G3_to_ls_G7_test

mphy_tb_random_long_line_cfg_test

mphy_burst_ls_G1_with_data_bus_10_bits_test

mphy_hs_G1_to_ls_G7_test

mphy_burst_ls_G7_LS_PREPARE_length_15_test

Page 173

Sheet1

mphy_burst_hs_G1_with_min_tob_test

mphy_hs_G1_hs_burst_with_TX_lanes_1_and_RX_lanes_4_test

mphy_hs_G2_to_ls_G7_test

mphy_reset_during_stall_test

mphy_ls_intra_mode_G4_to_G4_test

mphy_neg_xcess_jitter_test

mphy_ls_intra_mode_G1_to_G1_test

Page 174

Sheet1

mphy_ls_intra_mode_G2_to_G2_test

mphy_line_reset_during_stall_with_TX_Controlled_Act_Timer_test

mphy_ls_burst_with_PWM_G2_in_DigitalEnd_loopback_mode_test

mphy_hs_G3_to_ls_G1_test

mphy_burst_hs_G1_HS_PREPARE_length_15_test

mphy_pos_ppm_test

Page 175

Sheet1

mphy_burst_hs_G3_HS_PREPARE_length_15_test

mphy_burst_data_xfer_test

mphy_ls_mode_to_hs_G2_test

mphy_burst_hs_G3_with_max_tob_test

mphy_line_reset_during_ls_prepare_test

mphy_ls_intra_mode_G2_to_G7_test

Page 176

Sheet1

mphy_ls_intra_mode_G4_to_G3_test

mphy_rnd_ppm_test

mphy_hs_G3_to_ls_G5_test

mphy_PWM_G1_ls_burst_with_TX_lanes_4_and_RX_lanes_3_test

mphy_line_reset_during_stall_test

Page 177

Sheet1

mphy_reset_during_ls_burst_test

mphy_ls_G4_to_hs_G2_test

mphy_ls_G1_to_hs_G1_test

mphy_ls_G6_to_hs_G1_test

rmmi_cntl_if_wr_tx_rx_in_ls_burst_state_wo_inlncfg_test

mphy_burst_ls_G7_SYNC_length_15_SYNC_range_0_test

mphy_ls_intra_mode_G6_to_G6_test

Page 178

Sheet1

mphy_ls_PWM_G6_min_burst_xfer_test

mphy_ls_intra_mode_G3_to_G5_test

mphy_ls_G7_to_hs_G2_test

mphy_hs_intra_mode_G3_to_G1_test

mphy_burst_ls_G7_SYNC_length_0_SYNC_range_0_test

mphy_ls_intra_mode_G7_to_G3_test

mphy_ls_G1_to_hs_G2_test

Page 179

Sheet1

mphy_SOB_corrupt_test

Page 180

Sheet1
TEST

SYNC Pattern error injection

LINE-RESET at different speed and state with TX_Controlled_ActTimer

MPHY INTER MODE_CHANGE

DigitalEnd loopback tests

MPHY INTER MODE_CHANGE

Multi-lane tests (taffic on all lanes)

Page 181

Sheet1

MPHY LS INTRA MODE_CHANGE

M-PHY RANDOM SPEED MODE TEST

Data transfer in HS Burst with all gears

State transition from LS_BURST to other states

Multi-lane tests (taffic on all lanes)

MPHY INTER MODE_CHANGE

Page 182

Sheet1

MPHY INTER MODE_CHANGE

MPHY LS INTRA MODE_CHANGE

RMMI Control IF Write in different states without RX_InLnCfg

data transfer with typical value of prepare

NearEnd loopback tests

Data transfer in LS Burst with all gears

State transition from STALL to other states

data transfer with typical value of prepare

Page 183

Sheet1

TX / RX RESET at different state and speeds

MPHY RX-to-TX LOOPBACK IN BFM

data transfer with typical values of TOB ls and hs burst

data transfer with typical values of sync length and sync range

MPHY INTER MODE_CHANGE

MPHY LS INTRA MODE_CHANGE

MPHY INTER MODE_CHANGE

Page 184

Sheet1

Data transfer in LS Burst with all gears

TOB corruption

DIF_P in HIBERN8 state

Data transfer in LS Burst with all gears

Data transfer in LS Burst with all gears

State transition from SLEEP to other states

MPHY LS INTRA MODE_CHANGE

Page 185

Sheet1

TX / RX RESET at different state and speeds

NearEnd loopback tests

MPHY INTER MODE_CHANGE

DigitalEnd loopback tests

data transfer with typical values of sync length and sync range

data transfer with typical values of sync length and sync range

Data transfer in LS Burst with all gears

data transfer with typical values of sync length and sync range

State transition from HS_BURST to other states

Page 186

Sheet1

Data transfer in LS Burst with all gears

MPHY PPM ERROR Cases ( If DUT Supports it )

RX wakeup cases

MPHY INTER MODE_CHANGE

MPHY INTER MODE_CHANGE

Multi-lane tests (taffic on all lanes)

Page 187

Sheet1

MPHY INTER MODE_CHANGE

Register Write / Read Transfers

data transfer with typical value of prepare

MPHY HS INTRA MODE_CHANGE

MPHY LS INTRA MODE_CHANGE

MPHY LS INTRA MODE_CHANGE

MPHY LS INTRA MODE_CHANGE

Page 188

Sheet1

MPHY INTER MODE_CHANGE

State transition from SLEEP to other states

MPHY LS INTRA MODE_CHANGE

Data transfer in LS Burst with all gears

MPHY INTER MODE_CHANGE

DIF_Z in BURST state

NearEnd loopback tests

Page 189

Sheet1

MPHY JITTER Cases

LINE-RESET at different speed and state with TX_Controlled_ActTimer

State transition from SLEEP to other states

MPHY LS INTRA MODE_CHANGE

State transition from STALL to other states

RMMI Control IF Read in all states

Page 190

Sheet1

Data Encoding Error

MPHY HS INTRA MODE_CHANGE

MPHY JITTER Cases

MPHY INTER MODE_CHANGE

MPHY INTER MODE_CHANGE

MPHY LS INTRA MODE_CHANGE

Page 191

Sheet1

MPHY RX-to-TX LOOPBACK IN DUT

MPHY LS INTRA MODE_CHANGE

MPHY LS INTRA MODE_CHANGE

MPHY HS INTRA MODE_CHANGE

MPHY LS INTRA MODE_CHANGE

DigitalEnd loopback tests

Page 192

Sheet1

MPHY INTER MODE_CHANGE

NearEnd loopback tests

DIF-P and DIF-N having Same value

data transfer with typical values of sync length and sync range

Data transfer in LS Burst with all gears

Data transfer in HS Burst with all gears

RMMI Control IF Write in different states without RX_InLnCfg

Page 193

Sheet1

TX_DRIVER_POLARITY change

MPHY INTER MODE_CHANGE

DigitalEnd loopback tests

MPHY LS INTRA MODE_CHANGE

RMMI Control IF Write in different states with RX_InLnCfg

DigitalEnd loopback tests

TX / RX RESET at different state and speeds

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RX wakeup cases

DigitalEnd loopback tests

Multi-lane tests (taffic on all lanes)

LINE-RESET at different speed and state with TX_Controlled_ActTimer

Multi-lane tests (taffic on all lanes)

data transfer with typical values of sync length and sync range

TX / RX RESET at different state and speeds

Multi-lane tests (taffic on all lanes)

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data transfer with typical values of sync length and sync range

MPHY LS INTRA MODE_CHANGE

MPHY INTER MODE_CHANGE

RMMI Control IF Write in different states without RX_InLnCfg

data transfer with typical values of sync length and sync range

MPHY INTER MODE_CHANGE

Data transfer in HS Burst with all gears

MPHY LS INTRA MODE_CHANGE

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data transfer with typical values of sync length and sync range

Multi-lane tests (taffic on all lanes)

MPHY LS INTRA MODE_CHANGE

NearEnd loopback tests

State transition from LINE-CFG to other states

State transition from LINE-CFG to other states

MPHY LS INTRA MODE_CHANGE

MPHY LS INTRA MODE_CHANGE

data transfer with all data bus sizes

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RMMI Control IF Read in all states

data transfer with typical values of sync length and sync range

data transfer with all data bus sizes

MPHY LS INTRA MODE_CHANGE

M-PHY RANDOM LINE CFG TRANSITION TEST

MPHY LS INTRA MODE_CHANGE

Multi-lane tests (taffic on all lanes)

data transfer with all data bus sizes

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MPHY INTER MODE_CHANGE

data transfer with typical values of TOB ls and hs burst

data transfer with typical values of sync length and sync range

data transfer with typical values of sync length and sync range

LINE-RESET at different speed and state with TX_Controlled_ActTimer

data transfer with typical values of sync length and sync range

data transfer with all data bus sizes

data transfer with all data bus sizes

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MPHY INTER MODE_CHANGE

DIF_N in HIBERN8 state

data transfer with typical values of sync length and sync range

data transfer with typical values of sync length and sync range

MPHY INTER MODE_CHANGE

Data transfer in LS Burst with all gears

MPHY INTER MODE_CHANGE

data transfer with all data bus sizes

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MPHY INTER MODE_CHANGE

RMMI Control IF Read in all states

MPHY LS INTRA MODE_CHANGE

DIF_Z in LINE_RESET state

MPHY PPM ERROR Cases ( If DUT Supports it )

data transfer with all possible values of sync pattern

MPHY LS INTRA MODE_CHANGE

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Multi-lane tests (taffic on all lanes)

LINE-RESET at different speed and state without TX_Controlled_ActTimer

MPHY INTER MODE_CHANGE

TX / RX RESET at different state and speeds

RMMI Control IF Write in different states with RX_InLnCfg

MPHY HS INTRA MODE_CHANGE

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RMMI Control IF Read in all states

Data transfer in LS Burst with all gears

Register Write / Read ERROR Transfers

DIF_Z in PREPARE state

DigitalEnd loopback tests

data transfer with typical values of TOB ls and hs burst

MPHY LS INTRA MODE_CHANGE

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MPHY INTER MODE_CHANGE

State transition from HIBERN8 to other states

MPHY LS INTRA MODE_CHANGE

MPHY INTER MODE_CHANGE

data transfer with typical values of TOB ls and hs burst

MPHY INTER MODE_CHANGE

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M-PHY RANDOM STATE TRANSITION TEST

MPHY LS INTRA MODE_CHANGE

DigitalEnd loopback tests

MPHY INTER MODE_CHANGE

Data transfer in HS Burst with all gears

State transition from STALL to other states

RMMI Control IF Read in all states

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RD Error

RMMI Control IF Write in different states with RX_InLnCfg

data transfer with all data bus sizes

Data transfer in LS Burst with all gears

TX / RX RESET at different state and speeds

LINE-RESET at different speed and state with TX_Controlled_ActTimer

MPHY INTER MODE_CHANGE

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RMMI Control IF Read in all states

RMMI Control IF CfgUpdate after Writes

data transfer with typical values of sync length and sync range

Data transfer in LS Burst with all gears

Data transfer in LS Burst with all gears

DIF_Z in SAVE state

NearEnd loopback tests

DigitalEnd loopback tests

MPHY LS INTRA MODE_CHANGE

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RMMI Control IF Write in different states without RX_InLnCfg

MPHY LS INTRA MODE_CHANGE

NearEnd loopback tests

NearEnd loopback tests

RMMI Control IF Write in different states with RX_InLnCfg

State transition from HIBERN8 to other states

MPHY LS INTRA MODE_CHANGE

Data transfer in HS Burst with all gears

data transfer with all data bus sizes

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Multi-lane tests (taffic on all lanes)

MPHY LS INTRA MODE_CHANGE

data transfer with all possible values of sync pattern

data transfer with all possible values of sync pattern

data transfer with typical values of TOB ls and hs burst

data transfer with typical value of prepare

MPHY INTER MODE_CHANGE

RMMI Control IF CfgUpdate after Writes

MPHY INTER MODE_CHANGE

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TX / RX RESET at different state and speeds

MPHY INTER MODE_CHANGE

data transfer with all possible values of sync pattern

MPHY LS INTRA MODE_CHANGE

data transfer with all data bus sizes

State transition from HS_BURST to other states

LINE-RESET at different speed and state with TX_Controlled_ActTimer

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MPHY JITTER ERROR Cases

MPHY JITTER Cases

SYNC Pattern error injection

MPHY LS INTRA MODE_CHANGE

MPHY LS INTRA MODE_CHANGE

data transfer with typical values of sync length and sync range

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MPHY LINE_CFG

MPHY LS INTRA MODE_CHANGE

MPHY LS INTRA MODE_CHANGE

State transition from LS_BURST to other states

MPHY LS INTRA MODE_CHANGE

MPHY LS INTRA MODE_CHANGE

MPHY LS INTRA MODE_CHANGE

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MPHY INTER MODE_CHANGE

data transfer with typical values of sync length and sync range

MPHY INTER MODE_CHANGE

DigitalEnd loopback tests

MPHY PPM ERROR Cases ( If DUT Supports it )

Multi-lane tests (taffic on all lanes)

MPHY INTER MODE_CHANGE

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Multi-lane tests (taffic on all lanes)

MPHY JITTER ERROR Cases

data transfer with all data bus sizes

Data transfer in HS Burst with all gears

RMMI Control IF Read in all states

MPHY LS INTRA MODE_CHANGE

MPHY HS INTRA MODE_CHANGE

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LINE-RESET at different speed and state with TX_Controlled_ActTimer

MPHY LS INTRA MODE_CHANGE

MPHY INTER MODE_CHANGE

RMMI Control IF Write in different states without RX_InLnCfg

NearEnd loopback tests

data transfer with typical value of prepare

Data transfer in LS Burst with all gears

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NearEnd loopback tests

RMMI Control IF Write in different states with RX_InLnCfg

Data transfer in LS Burst with all gears

M-PHY RANDOM LINE RESET TRANSITION TEST

TX / RX RESET at different state and speeds

NearEnd loopback tests

data transfer with typical values of TOB ls and hs burst

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MPHY PPM Cases ( If DUT Supports it )

RMMI Control IF Write in different states with RX_InLnCfg

RMMI Control IF Read in all states

MPHY LS INTRA MODE_CHANGE

Control symbol Encoding Error

RMMI Control IF Write in different states with RX_InLnCfg

MPHY INTER MODE_CHANGE

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data transfer with all data bus sizes

TX / RX RESET at different state and speeds

MPHY INTER MODE_CHANGE

M-PHY RANDOM SPECIFIC TRANSITION TEST

data transfer with all data bus sizes

MPHY INTER MODE_CHANGE

data transfer with typical value of prepare

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data transfer with typical values of TOB ls and hs burst

Multi-lane tests (taffic on all lanes)

MPHY INTER MODE_CHANGE

TX / RX RESET at different state and speeds

MPHY LS INTRA MODE_CHANGE

MPHY JITTER ERROR Cases

MPHY LS INTRA MODE_CHANGE

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MPHY LS INTRA MODE_CHANGE

LINE-RESET at different speed and state with TX_Controlled_ActTimer

DigitalEnd loopback tests

MPHY INTER MODE_CHANGE

data transfer with typical value of prepare

MPHY PPM Cases ( If DUT Supports it )

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data transfer with typical value of prepare

Data transfer in Bursts

MPHY INTER MODE_CHANGE

data transfer with typical values of TOB ls and hs burst

LINE-RESET at different speed and state with TX_Controlled_ActTimer

MPHY LS INTRA MODE_CHANGE

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MPHY LS INTRA MODE_CHANGE

MPHY PPM Cases ( If DUT Supports it )

MPHY INTER MODE_CHANGE

Multi-lane tests (taffic on all lanes)

LINE-RESET at different speed and state without TX_Controlled_ActTimer

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TX / RX RESET at different state and speeds

MPHY INTER MODE_CHANGE

MPHY INTER MODE_CHANGE

MPHY INTER MODE_CHANGE

RMMI Control IF Write in different states without RX_InLnCfg

data transfer with typical values of sync length and sync range

MPHY LS INTRA MODE_CHANGE

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Data transfer in LS Burst with all gears

MPHY LS INTRA MODE_CHANGE

MPHY INTER MODE_CHANGE

MPHY HS INTRA MODE_CHANGE

data transfer with typical values of sync length and sync range

MPHY LS INTRA MODE_CHANGE

MPHY INTER MODE_CHANGE

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SOB(MARKER 0) corruption

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DESCRIPTION Injecting the Errors in encoded Control symbols. SYNC pattern corruption keeps the width same as spec defined values but corrupts the pattern SYNC pattern width exceeds or sends lesser than specification defined width Stimulus: Randomly Corrupt the 8b/10b encoded control symbol values before driving it on the DP/DN lanes.

Lowest level reset mechanism in order to reset the M-RX via the LINE during operation in case of malfunction. LINE-RESET condition is a long DIF-P period, which can never occur during normal operation. Stimulus: LINE-RESET can be initiated by the Protocol Layer on the M-TX side of a LINK using the M-CTRL-LINERESET.request primitive Value of TX_Controlled_ActTimer is one

*NOTE : This LINE-RESET should be done in all ACTIVATED states. Expectations : - M-TX drives DIF-N for TACTIVATE before driving the LINE-RESET condition - LINE-RESET exits to SLEEP on a transition to DIF-N. - Exit of LINE_RESET should go to SLEEP state. Table 64 & Line 1000 -to- 1004 : - D.2.1 Inter-MODE GEAR Change Stimulus: Change the TX & RX MODE along with TX & RX GEAR and the SERIES appropriately for the MODE & GEAR/SERIES Change. Use command line argument Expectation :

Stimulus:

Table 64 & Line 1000 -to- 1004 : - D.2.1 Inter-MODE GEAR Change Stimulus: Change the TX & RX MODE along with TX & RX GEAR and the SERIES appropriately for the MODE & GEAR/SERIES Change. Use command line argument Expectation :

Stimulus:

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-- Running MPHY in different modes(LS and HS) randomly, enter and exit from hibern8 randomly. -- Bursts are performed with random gear values to cover all speed grades. -- writing in configuration registers during burst which will be updated after transiting in a save state. -- Randomizing the HS_PREPARE_LENGTH value from minimum to maximum values. Stimulus: -Expectation : -- All the transactions should be completed without any failure.

Normal Data transfer in Bursts Stimulus: transfer / Receive the Data on the RMMI Data Interface from BFM in Bursts. Expectation : Between the bursts the M-PHY StateMachine should wait in the STALL State. Data integrity on the Peer RMMI interface.

Mphy state transition from LS_BURST to other states Stimulus:

Stimulus:

Table 64 & Line 1000 -to- 1004 : - D.2.1 Inter-MODE GEAR Change Stimulus: Change the TX & RX MODE along with TX & RX GEAR and the SERIES appropriately for the MODE & GEAR/SERIES Change. Use command line argument Expectation :

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Table 64 & Line 1000 -to- 1004 : - D.2.1 Inter-MODE GEAR Change Stimulus: Change the TX & RX MODE along with TX & RX GEAR and the SERIES appropriately for the MODE & GEAR/SERIES Change. Use command line argument Expectation : Table 64 & Line 1000 -to- 1004 : - D.2.1 Intra-MODE GEAR Change Stimulus: Program the TX & RX GEAR and the SERIES appropriately for the GEAR Change. Gear combination can be given by command line argument Expectation :

RMMI Control I/F Writes on TX & RX interface in different states without RX_InLnCfg Stimulus:

Normal Data transfer in ls and hs mode with typical values of prepare length Stimulus:

Stimulus:

Normal Data transfer in Bursts Stimulus: transfer / Receive the Data on the RMMI Data Interface from BFM in Bursts. Expectation : Between the bursts the M-PHY StateMachine should wait in the SLEEP State. Data integrity on the Peer RMMI interface.

Mphy state transition from STALL to other states Stimulus:

Normal Data transfer in ls and hs mode with typical values of prepare length Stimulus:

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Apply the reset in Different state of module Stimulus: Apply the Reset to TX or RX with a random delay between them and see that TX & RX will come back to HIBERN8 after the reset release. All the registers have degault values.

RX-to-TX LOOPBACK By Enabling the Loopback mode the incoming data on RX can be transmitted on TX path before the decoding is done. Stimulus: -- Enable the RX-to-TX Loopback in BFM. Expectation : -- Check the Data sent from DUT is recieved without any Errors by DUT.

Normal Data transfer in ls and hs mode with typical values of TOB Stimulus:

Normal Data transfer in ls and hs mode with typical values of sync length and sync range Stimulus:

Table 64 & Line 1000 -to- 1004 : - D.2.1 Inter-MODE GEAR Change Stimulus: Change the TX & RX MODE along with TX & RX GEAR and the SERIES appropriately for the MODE & GEAR/SERIES Change. Use command line argument Expectation : Table 64 & Line 1000 -to- 1004 : - D.2.1 Intra-MODE GEAR Change Stimulus: Program the TX & RX GEAR and the SERIES appropriately for the GEAR Change. Gear combination can be given by command line argument Expectation :

Table 64 & Line 1000 -to- 1004 : - D.2.1 Inter-MODE GEAR Change Stimulus: Change the TX & RX MODE along with TX & RX GEAR and the SERIES appropriately for the MODE & GEAR/SERIES Change. Use command line argument Expectation :

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Normal Data transfer in Bursts Stimulus: transfer / Receive the Data on the RMMI Data Interface from BFM in Bursts. Expectation : Between the bursts the M-PHY StateMachine should wait in the SLEEP State. Data integrity on the Peer RMMI interface.

Injecting the Errors in encoded Control symbols. Stimulus: Randomly Corrupt the 8b/10b encoded control symbol values before driving it on the DP/DN lanes. +INJECT_MPHY_TOB_SYMBOL_ERR=1

-- MPHY DIF_P in HIBERN8 state Stimulus: Randomly insert DIF_P in HIBERN8 state

Normal Data transfer in Bursts Stimulus: transfer / Receive the Data on the RMMI Data Interface from BFM in Bursts. Expectation : Between the bursts the M-PHY StateMachine should wait in the SLEEP State. Data integrity on the Peer RMMI interface.

Normal Data transfer in Bursts Stimulus: transfer / Receive the Data on the RMMI Data Interface from BFM in Bursts. Expectation : Between the bursts the M-PHY StateMachine should wait in the SLEEP State. Data integrity on the Peer RMMI interface.

Mphy state transition from SLEEP to other states Stimulus: Table 64 & Line 1000 -to- 1004 : - D.2.1 Intra-MODE GEAR Change Stimulus: Program the TX & RX GEAR and the SERIES appropriately for the GEAR Change. Gear combination can be given by command line argument Expectation :

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Apply the reset in Different state of module Stimulus: Apply the Reset to TX or RX with a random delay between them and see that TX & RX will come back to HIBERN8 after the reset release. All the registers have degault values.

Stimulus:

Table 64 & Line 1000 -to- 1004 : - D.2.1 Inter-MODE GEAR Change Stimulus: Change the TX & RX MODE along with TX & RX GEAR and the SERIES appropriately for the MODE & GEAR/SERIES Change. Use command line argument Expectation :

Stimulus:

Normal Data transfer in ls and hs mode with typical values of sync length and sync range Stimulus:

Normal Data transfer in ls and hs mode with typical values of sync length and sync range Stimulus:

Normal Data transfer in Bursts Stimulus: transfer / Receive the Data on the RMMI Data Interface from BFM in Bursts. Expectation : Between the bursts the M-PHY StateMachine should wait in the SLEEP State. Data integrity on the Peer RMMI interface.

Normal Data transfer in ls and hs mode with typical values of sync length and sync range Stimulus:

Mphy state transition from HS_BURST to other states Stimulus:

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Normal Data transfer in Bursts Stimulus: transfer / Receive the Data on the RMMI Data Interface from BFM in Bursts. Expectation : Between the bursts the M-PHY StateMachine should wait in the SLEEP State. Data integrity on the Peer RMMI interface.

( in one million ideal clocks period ) This happens due to the minute error in the crystal Oscillating frequency. Induce the PPM (exceeding the limits ) On TX CLK Stimulus: By Enabling the ppm ( exceeding the limits) on the Clock of TX. +INJ_EXCESS_PPM = (NONE, POS, NEG, RAND) Expectation : Thresholds of the Shallow FIFO's should exceed when WR clk is faster. Shallow FIFO should become empty when RD Clk is faster.

Stimulus: Remove the reset from RX when 1.TX is in HIBERN8, 2.TX is in sleep

Table 64 & Line 1000 -to- 1004 : - D.2.1 Inter-MODE GEAR Change Stimulus: Change the TX & RX MODE along with TX & RX GEAR and the SERIES appropriately for the MODE & GEAR/SERIES Change. Use command line argument Expectation :

Table 64 & Line 1000 -to- 1004 : - D.2.1 Inter-MODE GEAR Change Stimulus: Change the TX & RX MODE along with TX & RX GEAR and the SERIES appropriately for the MODE & GEAR/SERIES Change. Use command line argument Expectation :

Stimulus:

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Table 64 & Line 1000 -to- 1004 : - D.2.1 Inter-MODE GEAR Change Stimulus: Change the TX & RX MODE along with TX & RX GEAR and the SERIES appropriately for the MODE & GEAR/SERIES Change. Use command line argument Expectation :

Register Write / Read Transfers Stimulus: Do the Register Write/Read operations in RTL for MPHY Registers thriugh the RMMI CNTL interface Valid Addr range : 'h0001 -to- 'h00E6 ** NOTE ** NOT Applicable for BFM

Normal Data transfer in ls and hs mode with typical values of prepare length Stimulus:

Table 64 & Line 1000 -to- 1004 : - D.2.1 Intra-MODE GEAR Change Stimulus: Program the TX & RX GEAR and the SERIES appropriately for the GEAR/SERIES Change. Expectation : Table 64 & Line 1000 -to- 1004 : - D.2.1 Intra-MODE GEAR Change Stimulus: Program the TX & RX GEAR and the SERIES appropriately for the GEAR Change. Gear combination can be given by command line argument Expectation : Table 64 & Line 1000 -to- 1004 : - D.2.1 Intra-MODE GEAR Change Stimulus: Program the TX & RX GEAR and the SERIES appropriately for the GEAR Change. Gear combination can be given by command line argument Expectation : Table 64 & Line 1000 -to- 1004 : - D.2.1 Intra-MODE GEAR Change Stimulus: Program the TX & RX GEAR and the SERIES appropriately for the GEAR Change. Gear combination can be given by command line argument Expectation :

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Table 64 & Line 1000 -to- 1004 : - D.2.1 Inter-MODE GEAR Change Stimulus: Change the TX & RX MODE along with TX & RX GEAR and the SERIES appropriately for the MODE & GEAR/SERIES Change. Use command line argument Expectation :

Mphy state transition from SLEEP to other states Stimulus: Table 64 & Line 1000 -to- 1004 : - D.2.1 Intra-MODE GEAR Change Stimulus: Program the TX & RX GEAR and the SERIES appropriately for the GEAR Change. Gear combination can be given by command line argument Expectation :

Normal Data transfer in Bursts Stimulus: transfer / Receive the Data on the RMMI Data Interface from BFM in Bursts. Expectation : Between the bursts the M-PHY StateMachine should wait in the SLEEP State. Data integrity on the Peer RMMI interface.

Table 64 & Line 1000 -to- 1004 : - D.2.1 Inter-MODE GEAR Change Stimulus: Change the TX & RX MODE along with TX & RX GEAR and the SERIES appropriately for the MODE & GEAR/SERIES Change. Use command line argument Expectation :

-- MPHY DIF_Z in BURST state Stimulus: Randomly insert DIF_Z in BURST state

Stimulus:

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Induce the Jitter On TX CLK Stimulus: By Enabling the jitter on the Clock of TX. +INJ_JITTER = (NONE, POS, NEG, RND) Expectation : No Data Loss *NOTE* : Random permissible Jitter should be part of all Test cases.

Lowest level reset mechanism in order to reset the M-RX via the LINE during operation in case of malfunction. LINE-RESET condition is a long DIF-P period, which can never occur during normal operation. Stimulus: LINE-RESET can be initiated by the Protocol Layer on the M-TX side of a LINK using the M-CTRL-LINERESET.request primitive Value of TX_Controlled_ActTimer is one

*NOTE : This LINE-RESET should be done in all ACTIVATED states. Expectations : - M-TX drives DIF-N for TACTIVATE before driving the LINE-RESET condition - LINE-RESET exits to SLEEP on a transition to DIF-N. - Exit of LINE_RESET should go to SLEEP state. Mphy state transition from SLEEP to other states Stimulus: Table 64 & Line 1000 -to- 1004 : - D.2.1 Intra-MODE GEAR Change Stimulus: Program the TX & RX GEAR and the SERIES appropriately for the GEAR Change. Gear combination can be given by command line argument Expectation :

Mphy state transition from STALL to other states Stimulus:

RMMI Control I/F Reads on TX & RX interface with random attribute ID Stimulus:

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Injecting the Data Errors while encoding. Stimulus: Randomly Corrupt the 8b/10b encoded data values before driving it on the DP/DN lanes. +INJECT_MPHY_DATA_SYMBOL_ERR=1 +INJECT_MPHY_DATA_SYMBOL_ERR_PC= (<= 100 % ) /> Table 64 & Line 1000 -to- 1004 : - D.2.1 Intra-MODE GEAR Change Stimulus: Program the TX & RX GEAR and the SERIES appropriately for the GEAR/SERIES Change. Expectation :

Induce the Jitter On TX CLK Stimulus: By Enabling the jitter on the Clock of TX. +INJ_JITTER = (NONE, POS, NEG, RND) Expectation : No Data Loss *NOTE* : Random permissible Jitter should be part of all Test cases.

Table 64 & Line 1000 -to- 1004 : - D.2.1 Inter-MODE GEAR Change Stimulus: Change the TX & RX MODE along with TX & RX GEAR and the SERIES appropriately for the MODE & GEAR/SERIES Change. Use command line argument Expectation :

Table 64 & Line 1000 -to- 1004 : - D.2.1 Inter-MODE GEAR Change Stimulus: Change the TX & RX MODE along with TX & RX GEAR and the SERIES appropriately for the MODE & GEAR/SERIES Change. Use command line argument Expectation : Table 64 & Line 1000 -to- 1004 : - D.2.1 Intra-MODE GEAR Change Stimulus: Program the TX & RX GEAR and the SERIES appropriately for the GEAR Change. Gear combination can be given by command line argument Expectation :

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RX-to-TX LOOPBACK By Enabling the Loopback mode the incoming data on RX can be transmitted on TX path before the decoding is done. Stimulus: -- Enable the RX-to-TX Loopback in DUT. Expectation : -- Check the Data sent from BFM is recieved without any Errors by BFM.

Table 64 & Line 1000 -to- 1004 : - D.2.1 Intra-MODE GEAR Change Stimulus: Program the TX & RX GEAR and the SERIES appropriately for the GEAR Change. Gear combination can be given by command line argument Expectation : Table 64 & Line 1000 -to- 1004 : - D.2.1 Intra-MODE GEAR Change Stimulus: Program the TX & RX GEAR and the SERIES appropriately for the GEAR Change. Gear combination can be given by command line argument Expectation :

Table 64 & Line 1000 -to- 1004 : - D.2.1 Intra-MODE GEAR Change Stimulus: Program the TX & RX GEAR and the SERIES appropriately for the GEAR/SERIES Change. Expectation : Table 64 & Line 1000 -to- 1004 : - D.2.1 Intra-MODE GEAR Change Stimulus: Program the TX & RX GEAR and the SERIES appropriately for the GEAR Change. Gear combination can be given by command line argument Expectation :

Stimulus:

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Table 64 & Line 1000 -to- 1004 : - D.2.1 Inter-MODE GEAR Change Stimulus: Change the TX & RX MODE along with TX & RX GEAR and the SERIES appropriately for the MODE & GEAR/SERIES Change. Use command line argument Expectation :

Stimulus:

DIF-P and DIF-N having Same value Stimulus: Randomly do DIF-P and DIF-N having Same value

Normal Data transfer in ls and hs mode with typical values of sync length and sync range Stimulus:

Normal Data transfer in Bursts Stimulus: transfer / Receive the Data on the RMMI Data Interface from BFM in Bursts. Expectation : Between the bursts the M-PHY StateMachine should wait in the SLEEP State. Data integrity on the Peer RMMI interface.

Normal Data transfer in Bursts Stimulus: transfer / Receive the Data on the RMMI Data Interface from BFM in Bursts. Expectation : Between the bursts the M-PHY StateMachine should wait in the STALL State. Data integrity on the Peer RMMI interface.

RMMI Control I/F Writes on TX & RX interface in different states without RX_InLnCfg Stimulus:

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Line 1011 : - TX_DRIVER_POLARITY is used to change the polarity of the LINE if DP and DN of the M-TX are cross connected to the DN and DP of the M-RX. Stimulus: Write to the TX_DRIVER_POLARITY Attribute. If TX_DRIVER_POLARITY is changed to a new value by the Protocol after the initial local RESET, the Protocol should change this attribute value to the new value after a subsequent local RESET is applied and de-asserted, and before M-TX is requested to exit HIBERN8 state. Expectation :

Table 64 & Line 1000 -to- 1004 : - D.2.1 Inter-MODE GEAR Change Stimulus: Change the TX & RX MODE along with TX & RX GEAR and the SERIES appropriately for the MODE & GEAR/SERIES Change. Use command line argument Expectation :

Stimulus: Table 64 & Line 1000 -to- 1004 : - D.2.1 Intra-MODE GEAR Change Stimulus: Program the TX & RX GEAR and the SERIES appropriately for the GEAR Change. Gear combination can be given by command line argument Expectation :

RMMI Control I/F Writes on TX & RX interface in different states with RX_InLnCfg Stimulus:

Stimulus:

Apply the reset in Different state of module Stimulus: Apply the Reset to TX or RX with a random delay between them and see that TX & RX will come back to HIBERN8 after the reset release. All the registers have degault values.

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Stimulus: Remove the reset from RX when 1.TX is in HIBERN8, 2.TX is in sleep

Stimulus:

Stimulus:

Lowest level reset mechanism in order to reset the M-RX via the LINE during operation in case of malfunction. LINE-RESET condition is a long DIF-P period, which can never occur during normal operation. Stimulus: LINE-RESET can be initiated by the Protocol Layer on the M-TX side of a LINK using the M-CTRL-LINERESET.request primitive Value of TX_Controlled_ActTimer is one

*NOTE : This LINE-RESET should be done in all ACTIVATED states. Expectations : - M-TX drives DIF-N for TACTIVATE before driving the LINE-RESET condition - LINE-RESET exits to SLEEP on a transition to DIF-N. - Exit of LINE_RESET should go to SLEEP state.

Stimulus:

Normal Data transfer in ls and hs mode with typical values of sync length and sync range Stimulus:

Apply the reset in Different state of module Stimulus: Apply the Reset to TX or RX with a random delay between them and see that TX & RX will come back to HIBERN8 after the reset release. All the registers have degault values.

Stimulus:

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Normal Data transfer in ls and hs mode with typical values of sync length and sync range Stimulus: Table 64 & Line 1000 -to- 1004 : - D.2.1 Intra-MODE GEAR Change Stimulus: Program the TX & RX GEAR and the SERIES appropriately for the GEAR Change. Gear combination can be given by command line argument Expectation :

Table 64 & Line 1000 -to- 1004 : - D.2.1 Inter-MODE GEAR Change Stimulus: Change the TX & RX MODE along with TX & RX GEAR and the SERIES appropriately for the MODE & GEAR/SERIES Change. Use command line argument Expectation :

RMMI Control I/F Writes on TX & RX interface in different states without RX_InLnCfg Stimulus:

Normal Data transfer in ls and hs mode with typical values of sync length and sync range Stimulus:

Table 64 & Line 1000 -to- 1004 : - D.2.1 Inter-MODE GEAR Change Stimulus: Change the TX & RX MODE along with TX & RX GEAR and the SERIES appropriately for the MODE & GEAR/SERIES Change. Use command line argument Expectation :

Normal Data transfer in Bursts Stimulus: transfer / Receive the Data on the RMMI Data Interface from BFM in Bursts. Expectation : Between the bursts the M-PHY StateMachine should wait in the STALL State. Data integrity on the Peer RMMI interface. Table 64 & Line 1000 -to- 1004 : - D.2.1 Intra-MODE GEAR Change Stimulus: Program the TX & RX GEAR and the SERIES appropriately for the GEAR Change. Gear combination can be given by command line argument Expectation :

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Normal Data transfer in ls and hs mode with typical values of sync length and sync range Stimulus:

Stimulus: Table 64 & Line 1000 -to- 1004 : - D.2.1 Intra-MODE GEAR Change Stimulus: Program the TX & RX GEAR and the SERIES appropriately for the GEAR Change. Gear combination can be given by command line argument Expectation :

Stimulus:

Mphy state transition from LINE-CFG to other states Stimulus:

Mphy state transition from LINE-CFG to other states Stimulus: Table 64 & Line 1000 -to- 1004 : - D.2.1 Intra-MODE GEAR Change Stimulus: Program the TX & RX GEAR and the SERIES appropriately for the GEAR Change. Gear combination can be given by command line argument Expectation : Table 64 & Line 1000 -to- 1004 : - D.2.1 Intra-MODE GEAR Change Stimulus: Program the TX & RX GEAR and the SERIES appropriately for the GEAR Change. Gear combination can be given by command line argument Expectation :

Normal Data transfer in ls and hs mode with all data bus sizes Stimulus:

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RMMI Control I/F Reads on TX & RX interface with random attribute ID Stimulus:

Normal Data transfer in ls and hs mode with typical values of sync length and sync range Stimulus:

Normal Data transfer in ls and hs mode with all data bus sizes Stimulus: Table 64 & Line 1000 -to- 1004 : - D.2.1 Intra-MODE GEAR Change Stimulus: Program the TX & RX GEAR and the SERIES appropriately for the GEAR Change. Gear combination can be given by command line argument Expectation :

-- Performing LS_BURST to LINE_CFG and HS_BURST to LINE_CFG transitions with driving some data in LINE_CFG. -- Performing LINE_CFG to SLEEP and LINE_CFG to STALL transitions. -- Performing LINE_CFG to LINE_RESET transition. -- Randomly varying LS_PREPARE_LENGTH for its minimum to maximum values. Stimulus: -Expectation : -- All the transactions should be completed without any failure. Table 64 & Line 1000 -to- 1004 : - D.2.1 Intra-MODE GEAR Change Stimulus: Program the TX & RX GEAR and the SERIES appropriately for the GEAR Change. Gear combination can be given by command line argument Expectation :

Stimulus:

Normal Data transfer in ls and hs mode with all data bus sizes Stimulus:

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Table 64 & Line 1000 -to- 1004 : - D.2.1 Inter-MODE GEAR Change Stimulus: Change the TX & RX MODE along with TX & RX GEAR and the SERIES appropriately for the MODE & GEAR/SERIES Change. Use command line argument Expectation :

Normal Data transfer in ls and hs mode with typical values of TOB Stimulus:

Normal Data transfer in ls and hs mode with typical values of sync length and sync range Stimulus:

Normal Data transfer in ls and hs mode with typical values of sync length and sync range Stimulus:

Lowest level reset mechanism in order to reset the M-RX via the LINE during operation in case of malfunction. LINE-RESET condition is a long DIF-P period, which can never occur during normal operation. Stimulus: LINE-RESET can be initiated by the Protocol Layer on the M-TX side of a LINK using the M-CTRL-LINERESET.request primitive Value of TX_Controlled_ActTimer is one

*NOTE : This LINE-RESET should be done in all ACTIVATED states. Expectations : - M-TX drives DIF-N for TACTIVATE before driving the LINE-RESET condition - LINE-RESET exits to SLEEP on a transition to DIF-N. - Exit of LINE_RESET should go to SLEEP state. Normal Data transfer in ls and hs mode with typical values of sync length and sync range Stimulus:

Normal Data transfer in ls and hs mode with all data bus sizes Stimulus:

Normal Data transfer in ls and hs mode with all data bus sizes Stimulus:

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Table 64 & Line 1000 -to- 1004 : - D.2.1 Inter-MODE GEAR Change Stimulus: Change the TX & RX MODE along with TX & RX GEAR and the SERIES appropriately for the MODE & GEAR/SERIES Change. Use command line argument Expectation :

-- MPHY DIF_N in HIBERN8 state Stimulus: Randomly insert DIF_N in HIBERN8 state

Normal Data transfer in ls and hs mode with typical values of sync length and sync range Stimulus:

Normal Data transfer in ls and hs mode with typical values of sync length and sync range Stimulus:

Table 64 & Line 1000 -to- 1004 : - D.2.1 Inter-MODE GEAR Change Stimulus: Change the TX & RX MODE along with TX & RX GEAR and the SERIES appropriately for the MODE & GEAR/SERIES Change. Use command line argument Expectation :

Normal Data transfer in Bursts Stimulus: transfer / Receive the Data on the RMMI Data Interface from BFM in Bursts. Expectation : Between the bursts the M-PHY StateMachine should wait in the SLEEP State. Data integrity on the Peer RMMI interface.

Table 64 & Line 1000 -to- 1004 : - D.2.1 Inter-MODE GEAR Change Stimulus: Change the TX & RX MODE along with TX & RX GEAR and the SERIES appropriately for the MODE & GEAR/SERIES Change. Use command line argument Expectation :

Normal Data transfer in ls and hs mode with all data bus sizes Stimulus:

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Table 64 & Line 1000 -to- 1004 : - D.2.1 Inter-MODE GEAR Change Stimulus: Change the TX & RX MODE along with TX & RX GEAR and the SERIES appropriately for the MODE & GEAR/SERIES Change. Use command line argument Expectation :

RMMI Control I/F Reads on TX & RX interface with random attribute ID Stimulus: Table 64 & Line 1000 -to- 1004 : - D.2.1 Intra-MODE GEAR Change Stimulus: Program the TX & RX GEAR and the SERIES appropriately for the GEAR Change. Gear combination can be given by command line argument Expectation :

-- MPHY DIF_Z in LINE_RESET state Stimulus: Randomly insert DIF_Z in LINE_RESET state

( in one million ideal clocks period ) This happens due to the minute error in the crystal Oscillating frequency. Induce the PPM (exceeding the limits ) On TX CLK Stimulus: By Enabling the ppm ( exceeding the limits) on the Clock of TX. +INJ_EXCESS_PPM = (NONE, POS, NEG, RAND) Expectation : Thresholds of the Shallow FIFO's should exceed when WR clk is faster. Shallow FIFO should become empty when RD Clk is faster.

Normal Data transfer in ls and hs mode with all possible values of sync patterns Stimulus: Table 64 & Line 1000 -to- 1004 : - D.2.1 Intra-MODE GEAR Change Stimulus: Program the TX & RX GEAR and the SERIES appropriately for the GEAR Change. Gear combination can be given by command line argument Expectation :

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Stimulus:

Lowest level reset mechanism in order to reset the M-RX via the LINE during operation in case of malfunction. LINE-RESET condition is a long DIF-P period, which can never occur during normal operation. Stimulus: LINE-RESET can be initiated by the Protocol Layer on the M-TX side of a LINK using the M-CTRL-LINERESET.request primitive Value of TX_Controlled_ActTimer is zero

*NOTE : This LINE-RESET should be done in all ACTIVATED states. Expectations : - M-TX drives DIF-N for TACTIVATE before driving the LINE-RESET condition - LINE-RESET exits to SLEEP on a transition to DIF-N. - Exit of LINE_RESET should go to SLEEP state.

Table 64 & Line 1000 -to- 1004 : - D.2.1 Inter-MODE GEAR Change Stimulus: Change the TX & RX MODE along with TX & RX GEAR and the SERIES appropriately for the MODE & GEAR/SERIES Change. Use command line argument Expectation :

Apply the reset in Different state of module Stimulus: Apply the Reset to TX or RX with a random delay between them and see that TX & RX will come back to HIBERN8 after the reset release. All the registers have degault values.

RMMI Control I/F Writes on TX & RX interface in different states with RX_InLnCfg Stimulus:

Table 64 & Line 1000 -to- 1004 : - D.2.1 Intra-MODE GEAR Change Stimulus: Program the TX & RX GEAR and the SERIES appropriately for the GEAR/SERIES Change. Expectation :

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RMMI Control I/F Reads on TX & RX interface with random attribute ID Stimulus:

Normal Data transfer in Bursts Stimulus: transfer / Receive the Data on the RMMI Data Interface from BFM in Bursts. Expectation : Between the bursts the M-PHY StateMachine should wait in the SLEEP State. Data integrity on the Peer RMMI interface.

Accesses invalid registers(Invalid Attribute Index) on Attribute Write / Read Transfers Stimulus: Do the Attribute Write/Read operations in RTL for MPHY Registers thriugh the RMMI CNTL interface Valid Addr range : 'h0001 -to- 'h00E6 Types of Errors : -- Invalid Attribute Index -- Try to write any Invalid value to the Attribute ** NOTE ** NOT Applicable for BFM

-- MPHY DIF_Z in PREPARE state Stimulus: Randomly insert DIF_Z in PREPARE state

Stimulus:

Normal Data transfer in ls and hs mode with typical values of TOB Stimulus: Table 64 & Line 1000 -to- 1004 : - D.2.1 Intra-MODE GEAR Change Stimulus: Program the TX & RX GEAR and the SERIES appropriately for the GEAR Change. Gear combination can be given by command line argument Expectation :

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Table 64 & Line 1000 -to- 1004 : - D.2.1 Inter-MODE GEAR Change Stimulus: Change the TX & RX MODE along with TX & RX GEAR and the SERIES appropriately for the MODE & GEAR/SERIES Change. Use command line argument Expectation :

Mphy state transition from HIBERN8 to other states Stimulus: Table 64 & Line 1000 -to- 1004 : - D.2.1 Intra-MODE GEAR Change Stimulus: Program the TX & RX GEAR and the SERIES appropriately for the GEAR Change. Gear combination can be given by command line argument Expectation :

Table 64 & Line 1000 -to- 1004 : - D.2.1 Inter-MODE GEAR Change Stimulus: Change the TX & RX MODE along with TX & RX GEAR and the SERIES appropriately for the MODE & GEAR/SERIES Change. Use command line argument Expectation :

Normal Data transfer in ls and hs mode with typical values of TOB Stimulus:

Table 64 & Line 1000 -to- 1004 : - D.2.1 Inter-MODE GEAR Change Stimulus: Change the TX & RX MODE along with TX & RX GEAR and the SERIES appropriately for the MODE & GEAR/SERIES Change. Use command line argument Expectation :

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-- Performing various state transitions in SLEEP, STALL, LS_BURST, HS_BURST, HIBERN8, LINE_CFG, LINE_RESET states. -- Line reset is asserting with both tx_act_timer enable and disable randomly. -- Line reset is asserting during a burst. -- Burst to Line cfg trnasition is being performed. -- Randomizing the HS_SYNC_LENGTH value from minimum to maximum value. Stimulus: -Expectation : -- All the transactions should be completed without any failure. Table 64 & Line 1000 -to- 1004 : - D.2.1 Intra-MODE GEAR Change Stimulus: Program the TX & RX GEAR and the SERIES appropriately for the GEAR Change. Gear combination can be given by command line argument Expectation :

Stimulus:

Table 64 & Line 1000 -to- 1004 : - D.2.1 Inter-MODE GEAR Change Stimulus: Change the TX & RX MODE along with TX & RX GEAR and the SERIES appropriately for the MODE & GEAR/SERIES Change. Use command line argument Expectation :

Normal Data transfer in Bursts Stimulus: transfer / Receive the Data on the RMMI Data Interface from BFM in Bursts. Expectation : Between the bursts the M-PHY StateMachine should wait in the STALL State. Data integrity on the Peer RMMI interface.

Mphy state transition from STALL to other states Stimulus:

RMMI Control I/F Reads on TX & RX interface with random attribute ID Stimulus:

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Injecting the RD Errors in encoded data. Stimulus: Randomly 8b/10b encoding should insert the RD Error.

RMMI Control I/F Writes on TX & RX interface in different states with RX_InLnCfg Stimulus:

Normal Data transfer in ls and hs mode with all data bus sizes Stimulus:

Normal Data transfer in Bursts Stimulus: transfer / Receive the Data on the RMMI Data Interface from BFM in Bursts. Expectation : Between the bursts the M-PHY StateMachine should wait in the SLEEP State. Data integrity on the Peer RMMI interface.

Apply the reset in Different state of module Stimulus: Apply the Reset to TX or RX with a random delay between them and see that TX & RX will come back to HIBERN8 after the reset release. All the registers have degault values.

Lowest level reset mechanism in order to reset the M-RX via the LINE during operation in case of malfunction. LINE-RESET condition is a long DIF-P period, which can never occur during normal operation. Stimulus: LINE-RESET can be initiated by the Protocol Layer on the M-TX side of a LINK using the M-CTRL-LINERESET.request primitive Value of TX_Controlled_ActTimer is one

*NOTE : This LINE-RESET should be done in all ACTIVATED states. Expectations : - M-TX drives DIF-N for TACTIVATE before driving the LINE-RESET condition - LINE-RESET exits to SLEEP on a transition to DIF-N. - Exit of LINE_RESET should go to SLEEP state. Table 64 & Line 1000 -to- 1004 : - D.2.1 Inter-MODE GEAR Change Stimulus: Change the TX & RX MODE along with TX & RX GEAR and the SERIES appropriately for the MODE & GEAR/SERIES Change. Use command line argument Expectation :

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RMMI Control I/F Reads on TX & RX interface with random attribute ID Stimulus:

RMMI Control I/F Writes on TX & RX interface during Data Burst and issue a Cfgupdt after/during the burst Stimulus:

Normal Data transfer in ls and hs mode with typical values of sync length and sync range Stimulus:

Normal Data transfer in Bursts Stimulus: transfer / Receive the Data on the RMMI Data Interface from BFM in Bursts. Expectation : Between the bursts the M-PHY StateMachine should wait in the SLEEP State. Data integrity on the Peer RMMI interface.

Normal Data transfer in Bursts Stimulus: transfer / Receive the Data on the RMMI Data Interface from BFM in Bursts. Expectation : Between the bursts the M-PHY StateMachine should wait in the SLEEP State. Data integrity on the Peer RMMI interface.

-- MPHY DIF_Z in SAVE state Stimulus: Randomly insert DIF_Z in SAVE state

Stimulus:

Stimulus: Table 64 & Line 1000 -to- 1004 : - D.2.1 Intra-MODE GEAR Change Stimulus: Program the TX & RX GEAR and the SERIES appropriately for the GEAR Change. Gear combination can be given by command line argument Expectation :

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RMMI Control I/F Writes on TX & RX interface in different states without RX_InLnCfg Stimulus: Table 64 & Line 1000 -to- 1004 : - D.2.1 Intra-MODE GEAR Change Stimulus: Program the TX & RX GEAR and the SERIES appropriately for the GEAR Change. Gear combination can be given by command line argument Expectation :

Stimulus:

Stimulus:

RMMI Control I/F Writes on TX & RX interface in different states with RX_InLnCfg Stimulus:

Mphy state transition from HIBERN8 to other states Stimulus: Table 64 & Line 1000 -to- 1004 : - D.2.1 Intra-MODE GEAR Change Stimulus: Program the TX & RX GEAR and the SERIES appropriately for the GEAR Change. Gear combination can be given by command line argument Expectation :

Normal Data transfer in Bursts Stimulus: transfer / Receive the Data on the RMMI Data Interface from BFM in Bursts. Expectation : Between the bursts the M-PHY StateMachine should wait in the STALL State. Data integrity on the Peer RMMI interface.

Normal Data transfer in ls and hs mode with all data bus sizes Stimulus:

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Stimulus: Table 64 & Line 1000 -to- 1004 : - D.2.1 Intra-MODE GEAR Change Stimulus: Program the TX & RX GEAR and the SERIES appropriately for the GEAR Change. Gear combination can be given by command line argument Expectation :

Normal Data transfer in ls and hs mode with all possible values of sync patterns Stimulus:

Normal Data transfer in ls and hs mode with all possible values of sync patterns Stimulus:

Normal Data transfer in ls and hs mode with typical values of TOB Stimulus:

Normal Data transfer in ls and hs mode with typical values of prepare length Stimulus:

Table 64 & Line 1000 -to- 1004 : - D.2.1 Inter-MODE GEAR Change Stimulus: Change the TX & RX MODE along with TX & RX GEAR and the SERIES appropriately for the MODE & GEAR/SERIES Change. Use command line argument Expectation :

RMMI Control I/F Writes on TX & RX interface during Data Burst and issue a Cfgupdt after/during the burst Stimulus:

Table 64 & Line 1000 -to- 1004 : - D.2.1 Inter-MODE GEAR Change Stimulus: Change the TX & RX MODE along with TX & RX GEAR and the SERIES appropriately for the MODE & GEAR/SERIES Change. Use command line argument Expectation :

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Apply the reset in Different state of module Stimulus: Apply the Reset to TX or RX with a random delay between them and see that TX & RX will come back to HIBERN8 after the reset release. All the registers have degault values.

Table 64 & Line 1000 -to- 1004 : - D.2.1 Inter-MODE GEAR Change Stimulus: Change the TX & RX MODE along with TX & RX GEAR and the SERIES appropriately for the MODE & GEAR/SERIES Change. Use command line argument Expectation :

Normal Data transfer in ls and hs mode with all possible values of sync patterns Stimulus: Table 64 & Line 1000 -to- 1004 : - D.2.1 Intra-MODE GEAR Change Stimulus: Program the TX & RX GEAR and the SERIES appropriately for the GEAR Change. Gear combination can be given by command line argument Expectation :

Normal Data transfer in ls and hs mode with all data bus sizes Stimulus:

Mphy state transition from HS_BURST to other states Stimulus:

Lowest level reset mechanism in order to reset the M-RX via the LINE during operation in case of malfunction. LINE-RESET condition is a long DIF-P period, which can never occur during normal operation. Stimulus: LINE-RESET can be initiated by the Protocol Layer on the M-TX side of a LINK using the M-CTRL-LINERESET.request primitive Value of TX_Controlled_ActTimer is one

*NOTE : This LINE-RESET should be done in all ACTIVATED states. Expectations : - M-TX drives DIF-N for TACTIVATE before driving the LINE-RESET condition - LINE-RESET exits to SLEEP on a transition to DIF-N. - Exit of LINE_RESET should go to SLEEP state.

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Induce Excess Jitter On TX CLK Stimulus: Enable the jitter and induce excess jitter on the Clock of TX. +INJ_EXCESS_JITTER = (NONE, POS, NEG, RAND) Expectation : Data Loss / Multiple samples of same bit can happen

Induce the Jitter On TX CLK Stimulus: By Enabling the jitter on the Clock of TX. +INJ_JITTER = (NONE, POS, NEG, RND) Expectation : No Data Loss *NOTE* : Random permissible Jitter should be part of all Test cases.

Injecting the Errors in encoded Control symbols. SYNC pattern corruption keeps the width same as spec defined values but corrupts the pattern SYNC pattern width exceeds or sends lesser than specification defined width Stimulus: Randomly Corrupt the 8b/10b encoded control symbol values before driving it on the DP/DN lanes. Table 64 & Line 1000 -to- 1004 : - D.2.1 Intra-MODE GEAR Change Stimulus: Program the TX & RX GEAR and the SERIES appropriately for the GEAR Change. Gear combination can be given by command line argument Expectation : Table 64 & Line 1000 -to- 1004 : - D.2.1 Intra-MODE GEAR Change Stimulus: Program the TX & RX GEAR and the SERIES appropriately for the GEAR Change. Gear combination can be given by command line argument Expectation :

Normal Data transfer in ls and hs mode with typical values of sync length and sync range Stimulus:

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D.3.1 TX_LCC_Enable Stimulus: LINE CFG when the OMC is present. Expectation : Table 64 & Line 1000 -to- 1004 : - D.2.1 Intra-MODE GEAR Change Stimulus: Program the TX & RX GEAR and the SERIES appropriately for the GEAR Change. Gear combination can be given by command line argument Expectation : Table 64 & Line 1000 -to- 1004 : - D.2.1 Intra-MODE GEAR Change Stimulus: Program the TX & RX GEAR and the SERIES appropriately for the GEAR Change. Gear combination can be given by command line argument Expectation :

Mphy state transition from LS_BURST to other states Stimulus: Table 64 & Line 1000 -to- 1004 : - D.2.1 Intra-MODE GEAR Change Stimulus: Program the TX & RX GEAR and the SERIES appropriately for the GEAR Change. Gear combination can be given by command line argument Expectation : Table 64 & Line 1000 -to- 1004 : - D.2.1 Intra-MODE GEAR Change Stimulus: Program the TX & RX GEAR and the SERIES appropriately for the GEAR Change. Gear combination can be given by command line argument Expectation : Table 64 & Line 1000 -to- 1004 : - D.2.1 Intra-MODE GEAR Change Stimulus: Program the TX & RX GEAR and the SERIES appropriately for the GEAR Change. Gear combination can be given by command line argument Expectation :

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Table 64 & Line 1000 -to- 1004 : - D.2.1 Inter-MODE GEAR Change Stimulus: Change the TX & RX MODE along with TX & RX GEAR and the SERIES appropriately for the MODE & GEAR/SERIES Change. Use command line argument Expectation :

Normal Data transfer in ls and hs mode with typical values of sync length and sync range Stimulus:

Table 64 & Line 1000 -to- 1004 : - D.2.1 Inter-MODE GEAR Change Stimulus: Change the TX & RX MODE along with TX & RX GEAR and the SERIES appropriately for the MODE & GEAR/SERIES Change. Use command line argument Expectation :

Stimulus:

( in one million ideal clocks period ) This happens due to the minute error in the crystal Oscillating frequency. Induce the PPM (exceeding the limits ) On TX CLK Stimulus: By Enabling the ppm ( exceeding the limits) on the Clock of TX. +INJ_EXCESS_PPM = (NONE, POS, NEG, RAND) Expectation : Thresholds of the Shallow FIFO's should exceed when WR clk is faster. Shallow FIFO should become empty when RD Clk is faster.

Stimulus:

Table 64 & Line 1000 -to- 1004 : - D.2.1 Inter-MODE GEAR Change Stimulus: Change the TX & RX MODE along with TX & RX GEAR and the SERIES appropriately for the MODE & GEAR/SERIES Change. Use command line argument Expectation :

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Stimulus:

Induce Excess Jitter On TX CLK Stimulus: Enable the jitter and induce excess jitter on the Clock of TX. +INJ_EXCESS_JITTER = (NONE, POS, NEG, RAND) Expectation : Data Loss / Multiple samples of same bit can happen

Normal Data transfer in ls and hs mode with all data bus sizes Stimulus:

Normal Data transfer in Bursts Stimulus: transfer / Receive the Data on the RMMI Data Interface from BFM in Bursts. Expectation : Between the bursts the M-PHY StateMachine should wait in the STALL State. Data integrity on the Peer RMMI interface.

RMMI Control I/F Reads on TX & RX interface with random attribute ID Stimulus: Table 64 & Line 1000 -to- 1004 : - D.2.1 Intra-MODE GEAR Change Stimulus: Program the TX & RX GEAR and the SERIES appropriately for the GEAR Change. Gear combination can be given by command line argument Expectation :

Table 64 & Line 1000 -to- 1004 : - D.2.1 Intra-MODE GEAR Change Stimulus: Program the TX & RX GEAR and the SERIES appropriately for the GEAR/SERIES Change. Expectation :

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Lowest level reset mechanism in order to reset the M-RX via the LINE during operation in case of malfunction. LINE-RESET condition is a long DIF-P period, which can never occur during normal operation. Stimulus: LINE-RESET can be initiated by the Protocol Layer on the M-TX side of a LINK using the M-CTRL-LINERESET.request primitive Value of TX_Controlled_ActTimer is one

*NOTE : This LINE-RESET should be done in all ACTIVATED states. Expectations : - M-TX drives DIF-N for TACTIVATE before driving the LINE-RESET condition - LINE-RESET exits to SLEEP on a transition to DIF-N. - Exit of LINE_RESET should go to SLEEP state. Table 64 & Line 1000 -to- 1004 : - D.2.1 Intra-MODE GEAR Change Stimulus: Program the TX & RX GEAR and the SERIES appropriately for the GEAR Change. Gear combination can be given by command line argument Expectation :

Table 64 & Line 1000 -to- 1004 : - D.2.1 Inter-MODE GEAR Change Stimulus: Change the TX & RX MODE along with TX & RX GEAR and the SERIES appropriately for the MODE & GEAR/SERIES Change. Use command line argument Expectation :

RMMI Control I/F Writes on TX & RX interface in different states without RX_InLnCfg Stimulus:

Stimulus:

Normal Data transfer in ls and hs mode with typical values of prepare length Stimulus:

Normal Data transfer in Bursts Stimulus: transfer / Receive the Data on the RMMI Data Interface from BFM in Bursts. Expectation : Between the bursts the M-PHY StateMachine should wait in the SLEEP State. Data integrity on the Peer RMMI interface.

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Stimulus:

RMMI Control I/F Writes on TX & RX interface in different states with RX_InLnCfg Stimulus:

Normal Data transfer in Bursts Stimulus: transfer / Receive the Data on the RMMI Data Interface from BFM in Bursts. Expectation : Between the bursts the M-PHY StateMachine should wait in the SLEEP State. Data integrity on the Peer RMMI interface.

-- Performing various LINE_RESET state transitions with PHY and PROTOCOL controlled line reset. -- Performing LINE_RESET during BURST(both LS and HS) state. Stimulus: -Expectation : -- All the transactions should be completed without any failure.

Apply the reset in Different state of module Stimulus: Apply the Reset to TX or RX with a random delay between them and see that TX & RX will come back to HIBERN8 after the reset release. All the registers have degault values.

Stimulus:

Normal Data transfer in ls and hs mode with typical values of TOB Stimulus:

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Induce the PPM On TX CLK Stimulus: By Enabling the ppm on the Clock of TX. +INJ_PPM = (NONE, POS, NEG, RAND) Expectation : No Data Loss *NOTE* : Random permissible PPM should be part of all Test cases.

RMMI Control I/F Writes on TX & RX interface in different states with RX_InLnCfg Stimulus:

RMMI Control I/F Reads on TX & RX interface with random attribute ID Stimulus: Table 64 & Line 1000 -to- 1004 : - D.2.1 Intra-MODE GEAR Change Stimulus: Program the TX & RX GEAR and the SERIES appropriately for the GEAR Change. Gear combination can be given by command line argument Expectation :

Injecting the Errors in encoded Control symbols. Stimulus: Randomly Corrupt the 8b/10b encoded control symbol values before driving it on the DP/DN lanes. +INJECT_MPHY_SOB_SYMBOL_ERR=1 +INJECT_MPHY_EOB_SYMBOL_ERR=1 +INJECT_MPHY_TOB_SYMBOL_ERR=1 +INJECT_MPHY_CNTL_SYMBOL_ERR=1 ( ENUM :: SOB, EOB, TOB, SYNC, ANY ) +INJECT_MPHY_CNTL_SYMBOL_ERR_PC= (<= 100 % ) />

RMMI Control I/F Writes on TX & RX interface in different states with RX_InLnCfg Stimulus:

Table 64 & Line 1000 -to- 1004 : - D.2.1 Inter-MODE GEAR Change Stimulus: Change the TX & RX MODE along with TX & RX GEAR and the SERIES appropriately for the MODE & GEAR/SERIES Change. Use command line argument Expectation :

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Normal Data transfer in ls and hs mode with all data bus sizes Stimulus:

Apply the reset in Different state of module Stimulus: Apply the Reset to TX or RX with a random delay between them and see that TX & RX will come back to HIBERN8 after the reset release. All the registers have degault values.

Table 64 & Line 1000 -to- 1004 : - D.2.1 Inter-MODE GEAR Change Stimulus: Change the TX & RX MODE along with TX & RX GEAR and the SERIES appropriately for the MODE & GEAR/SERIES Change. Use command line argument Expectation :

-- This test runs some particular long state transition sequences randomly which are as follows - STALL - HS_BURST - STALL - HS_BURST - LINE_CFG - SLEEP - STALL - HS_BURST - LINE_CFG SLEEP - LS_BURST - LINE_CFG - SLEEP - LS_BURST(1) - LINE_CFG - SLEEP - SLEEP/STALL - BURST/BURST(1) - LINE_CFG - SLEEP [HIBERN8 - SLEEP - STALL] / [STALL - HIBERN8 - STALL] - LS_BURST - LINE_CFG - SLEEP - STALL - HS_BURST - LINE_CFG - SLEEP - STALL - SLEEP LS_BURST - SLEEP - LS_BURST(1) - LINE_CFG - SLEEP - STALL - HS_BURST NOTE - '(1)' represents that the corresponding burst is performed with gear 1. - ' / ' represents that the former or later one will be performed randomly. Stimulus: -Expectation : -- All the transactions should be completed without any failure. Normal Data transfer in ls and hs mode with all data bus sizes Stimulus:

Table 64 & Line 1000 -to- 1004 : - D.2.1 Inter-MODE GEAR Change Stimulus: Change the TX & RX MODE along with TX & RX GEAR and the SERIES appropriately for the MODE & GEAR/SERIES Change. Use command line argument Expectation :

Normal Data transfer in ls and hs mode with typical values of prepare length Stimulus:

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Normal Data transfer in ls and hs mode with typical values of TOB Stimulus:

Stimulus:

Table 64 & Line 1000 -to- 1004 : - D.2.1 Inter-MODE GEAR Change Stimulus: Change the TX & RX MODE along with TX & RX GEAR and the SERIES appropriately for the MODE & GEAR/SERIES Change. Use command line argument Expectation :

Apply the reset in Different state of module Stimulus: Apply the Reset to TX or RX with a random delay between them and see that TX & RX will come back to HIBERN8 after the reset release. All the registers have degault values. Table 64 & Line 1000 -to- 1004 : - D.2.1 Intra-MODE GEAR Change Stimulus: Program the TX & RX GEAR and the SERIES appropriately for the GEAR Change. Gear combination can be given by command line argument Expectation :

Induce Excess Jitter On TX CLK Stimulus: Enable the jitter and induce excess jitter on the Clock of TX. +INJ_EXCESS_JITTER = (NONE, POS, NEG, RAND) Expectation : Data Loss / Multiple samples of same bit can happen Table 64 & Line 1000 -to- 1004 : - D.2.1 Intra-MODE GEAR Change Stimulus: Program the TX & RX GEAR and the SERIES appropriately for the GEAR Change. Gear combination can be given by command line argument Expectation :

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Table 64 & Line 1000 -to- 1004 : - D.2.1 Intra-MODE GEAR Change Stimulus: Program the TX & RX GEAR and the SERIES appropriately for the GEAR Change. Gear combination can be given by command line argument Expectation :

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Lowest level reset mechanism in order to reset the M-RX via the LINE during operation in case of malfunction. LINE-RESET condition is a long DIF-P period, which can never occur during normal operation. Stimulus: LINE-RESET can be initiated by the Protocol Layer on the M-TX side of a LINK using the M-CTRL-LINERESET.request primitive Value of TX_Controlled_ActTimer is one

*NOTE : This LINE-RESET should be done in all ACTIVATED states. Expectations : - M-TX drives DIF-N for TACTIVATE before driving the LINE-RESET condition - LINE-RESET exits to SLEEP on a transition to DIF-N. - Exit of LINE_RESET should go to SLEEP state.

Stimulus:

Table 64 & Line 1000 -to- 1004 : - D.2.1 Inter-MODE GEAR Change Stimulus: Change the TX & RX MODE along with TX & RX GEAR and the SERIES appropriately for the MODE & GEAR/SERIES Change. Use command line argument Expectation :

Normal Data transfer in ls and hs mode with typical values of prepare length Stimulus:

Induce the PPM On TX CLK Stimulus: By Enabling the ppm on the Clock of TX. +INJ_PPM = (NONE, POS, NEG, RAND) Expectation : No Data Loss *NOTE* : Random permissible PPM should be part of all Test cases.

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Normal Data transfer in ls and hs mode with typical values of prepare length Stimulus:

Normal Data transfer in Bursts Stimulus: transfer / Receive the Data on the RMMI Data Interface from BFM in Bursts. Expectation : Gear(with min and max speed) and mode will be selected randomely from burst to burst.

Table 64 & Line 1000 -to- 1004 : - D.2.1 Inter-MODE GEAR Change Stimulus: Change the TX & RX MODE along with TX & RX GEAR and the SERIES appropriately for the MODE & GEAR/SERIES Change. Use command line argument Expectation :

Normal Data transfer in ls and hs mode with typical values of TOB Stimulus:

Lowest level reset mechanism in order to reset the M-RX via the LINE during operation in case of malfunction. LINE-RESET condition is a long DIF-P period, which can never occur during normal operation. Stimulus: LINE-RESET can be initiated by the Protocol Layer on the M-TX side of a LINK using the M-CTRL-LINERESET.request primitive Value of TX_Controlled_ActTimer is one

*NOTE : This LINE-RESET should be done in all ACTIVATED states. Expectations : - M-TX drives DIF-N for TACTIVATE before driving the LINE-RESET condition - LINE-RESET exits to SLEEP on a transition to DIF-N. - Exit of LINE_RESET should go to SLEEP state. Table 64 & Line 1000 -to- 1004 : - D.2.1 Intra-MODE GEAR Change Stimulus: Program the TX & RX GEAR and the SERIES appropriately for the GEAR Change. Gear combination can be given by command line argument Expectation :

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Table 64 & Line 1000 -to- 1004 : - D.2.1 Intra-MODE GEAR Change Stimulus: Program the TX & RX GEAR and the SERIES appropriately for the GEAR Change. Gear combination can be given by command line argument Expectation :

Sheet1

Induce the PPM On TX CLK Stimulus: By Enabling the ppm on the Clock of TX. +INJ_PPM = (NONE, POS, NEG, RAND) Expectation : No Data Loss *NOTE* : Random permissible PPM should be part of all Test cases.

Table 64 & Line 1000 -to- 1004 : - D.2.1 Inter-MODE GEAR Change Stimulus: Change the TX & RX MODE along with TX & RX GEAR and the SERIES appropriately for the MODE & GEAR/SERIES Change. Use command line argument Expectation :

Stimulus:

Lowest level reset mechanism in order to reset the M-RX via the LINE during operation in case of malfunction. LINE-RESET condition is a long DIF-P period, which can never occur during normal operation. Stimulus: LINE-RESET can be initiated by the Protocol Layer on the M-TX side of a LINK using the M-CTRL-LINERESET.request primitive Value of TX_Controlled_ActTimer is zero

*NOTE : This LINE-RESET should be done in all ACTIVATED states. Expectations : - M-TX drives DIF-N for TACTIVATE before driving the LINE-RESET condition - LINE-RESET exits to SLEEP on a transition to DIF-N. - Exit of LINE_RESET should go to SLEEP state.

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Apply the reset in Different state of module Stimulus: Apply the Reset to TX or RX with a random delay between them and see that TX & RX will come back to HIBERN8 after the reset release. All the registers have degault values.

Table 64 & Line 1000 -to- 1004 : - D.2.1 Inter-MODE GEAR Change Stimulus: Change the TX & RX MODE along with TX & RX GEAR and the SERIES appropriately for the MODE & GEAR/SERIES Change. Use command line argument Expectation :

Table 64 & Line 1000 -to- 1004 : - D.2.1 Inter-MODE GEAR Change Stimulus: Change the TX & RX MODE along with TX & RX GEAR and the SERIES appropriately for the MODE & GEAR/SERIES Change. Use command line argument Expectation :

Table 64 & Line 1000 -to- 1004 : - D.2.1 Inter-MODE GEAR Change Stimulus: Change the TX & RX MODE along with TX & RX GEAR and the SERIES appropriately for the MODE & GEAR/SERIES Change. Use command line argument Expectation :

RMMI Control I/F Writes on TX & RX interface in different states without RX_InLnCfg Stimulus:

Normal Data transfer in ls and hs mode with typical values of sync length and sync range Stimulus: Table 64 & Line 1000 -to- 1004 : - D.2.1 Intra-MODE GEAR Change Stimulus: Program the TX & RX GEAR and the SERIES appropriately for the GEAR Change. Gear combination can be given by command line argument Expectation :

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Normal Data transfer in Bursts Stimulus: transfer / Receive the Data on the RMMI Data Interface from BFM in Bursts. Expectation : Between the bursts the M-PHY StateMachine should wait in the SLEEP State. Data integrity on the Peer RMMI interface. Table 64 & Line 1000 -to- 1004 : - D.2.1 Intra-MODE GEAR Change Stimulus: Program the TX & RX GEAR and the SERIES appropriately for the GEAR Change. Gear combination can be given by command line argument Expectation :

Table 64 & Line 1000 -to- 1004 : - D.2.1 Inter-MODE GEAR Change Stimulus: Change the TX & RX MODE along with TX & RX GEAR and the SERIES appropriately for the MODE & GEAR/SERIES Change. Use command line argument Expectation :

Table 64 & Line 1000 -to- 1004 : - D.2.1 Intra-MODE GEAR Change Stimulus: Program the TX & RX GEAR and the SERIES appropriately for the GEAR/SERIES Change. Expectation :

Normal Data transfer in ls and hs mode with typical values of sync length and sync range Stimulus: Table 64 & Line 1000 -to- 1004 : - D.2.1 Intra-MODE GEAR Change Stimulus: Program the TX & RX GEAR and the SERIES appropriately for the GEAR Change. Gear combination can be given by command line argument Expectation :

Table 64 & Line 1000 -to- 1004 : - D.2.1 Inter-MODE GEAR Change Stimulus: Change the TX & RX MODE along with TX & RX GEAR and the SERIES appropriately for the MODE & GEAR/SERIES Change. Use command line argument Expectation :

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Injecting the Errors in encoded Control symbols. Stimulus: Randomly Corrupt the 8b/10b encoded control symbol values before driving it on the DP/DN lanes. +INJECT_MPHY_SOB_SYMBOL_ERR=1

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