Scribd
Upload
90 views4 pages

A High Efficiency Boost Converter For TFT-LCD Bias Supply

The document describes the design of a high efficiency boost converter for TFT-LCD bias supply using a 0.5-μm 5V, 3.5-μm 30-V CMOS process. Key aspects of the design include a current mode control scheme, compensation circuit to ensure stability, and a clock and ramp generator to prevent subharmonic oscillations. Simulation results show the boost converter operates efficiently across an input voltage range of 2.5-5V, output voltage range of 10-20V, with a maximum efficiency of 92%

Uploaded by

Hamid Bouali
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
90 views4 pages

A High Efficiency Boost Converter For TFT-LCD Bias Supply

The document describes the design of a high efficiency boost converter for TFT-LCD bias supply using a 0.5-μm 5V, 3.5-μm 30-V CMOS process. Key aspects of the design include a current mode control scheme, compensation circuit to ensure stability, and a clock and ramp generator to prevent subharmonic oscillations. Simulation results show the boost converter operates efficiently across an input voltage range of 2.5-5V, output voltage range of 10-20V, with a maximum efficiency of 92%

Uploaded by

Hamid Bouali
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 4

1

A High Efciency Boost Converter


For TFT-LCD Bias Supply
Hyunseok Nam, Inseok Kim, Youngkook Ahn, and Jeongjin Roh
Department of Electronic, Electrical, Control and Instrumentation Engineering, Hanyang University,
Ansan 426-791, Korea
Tel:+82-31-400-5168, Fax:+82-31-501-5622
Email:jroh@hanyang.ac.kr
AbstractIn this paper, a high efciency boost converter is
designed using a 0.5-m 5V, 3.5-m 30-V CMOS process for
TFT-LCD Bias supply. The boost converter can be adjusted
with external resistors. The boost converters input power supply
range is 2.5V 5V, the output voltage range is 10V-20V and
the clock frequency is 1.3 MHz. The maximum load current is
120mA at an input power supply of 3V, output voltage of 20V and
the maximum efciency is 92% with input power supply at 5V,
output voltage of 12V, and load current of 120mA. The simulation
results show the successful operation of the boost converter.
I. INTRODUCTION
W
ITH the increasing popularity of portable devices,
customers continue to demand longer battery runtime,
smaller size, and lower cost. Based on these demands from
the marketplace, optimized DC-DC converters are essential in
order to supply power efciently to support various mobile
device functions [1]. Especially the demand for power man-
agement circuits for LCD displays, for notebooks, personal
digital assistants, and pocket PCs, is increasing. Accordingly,
in this paper, the optimized boost converter for TFT LCD bias
is designed with current mode control.
A charge pump or a switching regulator circuit is generally
used to generate a voltage higher than the supply voltage.
Whereas a charge pump circuit uses a capacitor to store energy,
a switching regulator uses an inductor. The latest mobile
devices require high power consumption, which calls for a
switching regulator type boost converter with a high efciency
even at signicant load currents.
Both voltage mode and current mode controls are commonly
used to design DC-DC converters. With a narrower bandwidth
than the current mode control, voltage mode cannot quickly
respond to abrupt changes in output voltage and current.
Furthermore, two poles, generated by the external inductor
and capacitor used as the low pass lter, complicate the
compensation circuit structure, making it difcult to secure
stability of the overall circuit. On the other hand, current mode
control has wider bandwidth than voltage mode, enabling
quick response to abrupt changes in output voltage and current.
The second pole is also nearer to the switching frequency,
which simplies the compensation circuit. However, in addi-
tion to the loop for detecting the output voltage, current mode
control requires another loop circuit for detecting the inductor
current. Furthermore, if the duty cycle is greater than 0.5, the
entire circuit becomes unstable. Therefore, an articial ramp
Fig. 1. Block diagram of the designed boost converter.
signal is required to solve the stability problem [2]- [3]. In
this paper, the boost converter is designed with current mode
control to provide wide bandwidth and, good line and load
regulation.
II. BOOST CONVERTER CIRCUIT
Fig. 1 shows the designed boost converter. The region sur-
rounded by dark lines is the on-chip integrated controller of the
boost converter. The boost converter control circuit contains a
soft-start circuit that consists of bandgap, R
SS
, M
SS
and C
SS
to prevent any inrush current [4]. The compensation circuit for
achieving overall boost converter loop stability consists of the
error amplier, C
C
and R
C
. The articial ramp circuit prevents
instability when the duty cycle exceeds 0.5, and the clock
generator provides the clock signal required for the entire
system. The SR latch generates the pulse-width modulation
(PWM) signal, and the level shifter and the buffer circuit are
implemented to deliver the PWM signal to the power transistor.
There is also an inductor current sensing circuit, and the high-
voltage (HV) bias circuit to supply bias current to the high-
voltage blocks.
To briey explain the overall mechanism of the boost
converter, when there is an abrupt transition from a light load
to a heavy load, the boost converters output voltage drops and
the feedback (FB) node voltage also decreases according to
the resistance ratio. The decreased feedback voltage raises the
error amplier output voltage, which the comparator compares
The 23rd International Technical Conference on Circuits/Systems,
Computers and Communications (ITC-CSCC 2008)
1025
2
R
C
C
C
FB
Vref
OTA
Fig. 2. Compensation circuit.
G
a
i
n
,

d
B
1k 10k 100k 1M 10M
Frequency, Hz
Gain=
g
m
R
c
OTA gain
0
Fig. 3. Frequency characteristic of the compensation circuit.
with the sum of the current sensing and articial ramp signals.
The error ampliers increased output signal slows down the
reset time of the SR latch, which controls the PWM duty cycle.
The generated PWM signal then increases the inductor current
through the level shifter and buffer circuits and compensates
for the output voltage decreased by the heavy load. If there
is a transition from a heavy load to a light load, the circuit
operates in the opposite manner.
A. Compensation circuit
The compensation circuit and its frequency characteristic
are shown in Fig. 2 and 3, respectively. The designed boost
converter circuit is controlled in current mode, and the second
pole is closer to the switching frequency making compensation
simpler than for a voltage mode converter. A simple propor-
tional integral (PI) compensation circuit is used [6], and overall
stability of the boost converter can be achieved by positioning
the reference point at a desired spot using R
C
and C
C
values.
The equation for compensation circuits can be expressed as
follows:
A
v
= G
m
R
out
(1 +
s

z
) (1)
MP1
MP4
MP2
MN1
MN2 MN3 MN4
MP5
MP3
VSS
Vg
1 : K
V
P
V
N
Fig. 4. Operational transconductance amplier (OTA).

z
=
1
R
c
C
c
(2)
where G
m
and R
out
denote the transconductance and output
resistance of OTA, respectively.
The converters unity gain frequency set by the feedback
loop is usually set within 20 % of the switching frequency to
reduce the effect of switching noise. For the purposes of this
paper, adequate R
c
and C
c
values were selected to achieve a
phase margin of 60 degrees at Vg=3V, VGH=10V and load
current=100mA. Fig. 4 shows the OTA structure used in the
compensation circuit. The OTA transconductance G
m
can be
written as follows [7]:
G
m
=
I
out
V
P
V
N
= K g
mp4,5
. (3)
B. Clock and Ramp Generator
Vg
Vref
M1
C1
I
REF
hys_comp
Clock
Ramp
Fig. 5. Clock and ramp generator.
1026
3
TABLE I
PERFORMANCE SUMMARY OF THE SIMULATED BOOST
CONVERTER.
Process 0.5-m 5V, 3.5-m 30V
Switching frequency 1.3MHz
Supply voltage 2.5V 5V
Output voltage 10V 20V
Efciency(MAX) 92% @ Vg=5V, VGH=12V, Iout=120mA
Core area 2150m 2150m
Subharmonic oscillation is a well-known problem for cur-
rent mode switching converters with the duty ratio D larger
than 0.5. To avoid subharmonic oscillation, the slope of the
compensation ramp m
a
must be larger than half of the slope
of inductor current m
2
during the second subinterval

DT. The
value of m
a
is generally determined as follows [8]:
m
a

m
2
2
(4)
where m
2
denotes the slope (V g V GH)/L in the region
where inductor current decreases.
The circuit for generating the articial ramp signal and the
clock signal is shown in Fig. 5. The slope of the articial ramp
is determined by I
REF
and C1. When I
REF
from the current
source charges the capacitor C1, the voltage at the ramp node
increases at a xed rate I
REF
/C1, which is equal to the slope
m
a
. If the increasing ramp signal reaches V
ref
, the output node
of the hysteresis comparator switches from low to high and the
clock also becomes high. Once the clock switches to the high
state, it turns on transistor M1. In turn, C1 is discharged and
the ramp node voltage decreases. When the ramp node voltage
decreases to the low boundary of the hysteresis comparator,
its output switches from high to low, the clock drops to the
low state, and M1 is switched off, triggering I
REF
to charge
C1.
III. SIMULATION RESULTS
Simulation results show the successful operation of the
boost converter. Table I summarizes the overall characteristics.
The maximum efciency of the boost converter is 92 % at Vg
= 5 V, VGH = 12 V, and load current = 120 mA. Fig. 6
illustrates output voltages according to variation in the load
current. The test is conducted with Vg = 3 V, VGH = 10
V, inductor = 4.7 uH, capacitor = 4.7 uF, and a load current
variation of 10 100 10 mA. Fig. 7 also illustrates output
voltages according to variation in the load current. The test
is conducted with Vg = 3 V, VGH = 20 V, inductor = 4.7
uH, capacitor = 4.7 uF, and a load current variation of 10
100 10 mA. As the simulation results indicate, the boost
converter displays stable operation even under substantial load
current variation. Fig. 8 shows the start-up operation of the
boost converter. The test is conducted with Vg = 3 V, VGH
= 10 V, inductor = 4.7 uH, capacitor = 4.7 uF. The efciency
of the boost converter is shown in Fig. 9.
IV. CONCLUSION
In this paper, the boost converter is designed using a 0.5
m 5 V, 3.5 m 30-V CMOS process for TFT-LCD bias
Fig. 6. Load transient response.(Vg=3V, VGH=10V)
Fig. 7. Load transient response.(Vg=3V, VGH=20V)
Fig. 8. Startup operation.
1027
4
L=4.7uH, C=4.7uF
50
55
60
65
70
75
80
85
90
95
100
10 60 110 160 210
Load current (mA)
E
f
f
i
c
i
e
n
c
y
(
%
)
Vg=5V, VGH=12V
Vg=3V, VGH=20V
Fig. 9. Power conversion efciency.
supply. Simulation results verify that the boost converter is
accurately controlled by external resistors. The boost converter
not only displays stable operation even under substantial load
current variation but also provides power conversion efciency
higher than 90 %. The boost converter is capable of supplying
optimized power for a wide range of systems, especially for
TFT-LCD bias supply.
ACKNOWLEDGEMENT
This work was supported by the Korea Science and En-
gineering Foundation (KOSEF) grant funded by the Korea
government (MEST) (No. R01-2008-000-11056-0).
REFERENCES
[1] C. Shi, B. C. Walker, E. Zeisel, B. Hu, and G. H. McAllister, A highly
integrated power management IC for advanced mobile applications,
IEEE J. Solid-State Circuits, vol. 42, no. 8, pp. 1723-1731, Aug. 2007.
[2] A. I. Pressman, Switching Power Supply Design, second edition, McGraw-
Hill, 1998.
[3] C. F. Lee and P. K. T. Mok, A monolithic current-mode CMOS DC-DC
converter with on-chip current-sensing technique, IEEE J. Solid-State
Circuits, vol. 39, no. 1, pp. 3-14, Jan. 2004.
[4] LT1946: 1.2MHz boost DC/DC converter with 1.5A switch and soft-
start,2001, http://www.linear.com
[5] C. Y Leung, P. K. T. Mok, and K. N. Leung, A 1-V integrated current-
mode boost converter in standard 3.3/5-V CMOS technologies, IEEE J.
Solid-State Circuits, vol. 40, no. 11, pp. 2265-2274, Nov. 2005.
[6] J. Roh, High-performance error amplier for fast transient DC-DC
converters, IEEE Trans. Circuit and Syst, vol. 52, no. 9, pp. 591-595.
Sept. 2005.
[7] R. J. Baker, CMOS Circuit, Design, Layout, and Simulation, second
edition, WILEY-INTERSCIENCE, 2005.
[8] R. W. Erickson, and D. Maksimovic, Fundamentals of power electronics,
2nd edition, KAP, 2001.
1028

You might also like

pFad - Phonifier reborn

Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.

Note: This service is not intended for secure transactions such as banking, social media, email, or purchasing. Use at your own risk. We assume no liability whatsoever for broken pages.


Alternative Proxies:

Alternative Proxy

pFad Proxy

pFad v3 Proxy

pFad v4 Proxy