__________________________ DIS8051 Cross-Disassembler User's Guide __________________________

Data Sync Engineering P.O. Box 146 East Stroudsburg, PA 18301 TEL (717) 421-1977 FAX (717) 421-9095 DIS8051 (C) Copyright 1989 by Data Sync Engineering. All rights reserved.

USER NOTICE Data Sync Engineering would like to thank all of those who have contributed towards the development of this software. We have decided to place the full version of DIS8051 into the public domain. You may copy and use this software on the conditions that the program is not distributed in modified form, that no fee or consideration is charged, and that this notice is not bypassed or removed. Any contributions for use of this software would be greatly appreciated.

PC-DOS is a trademark of International Business Machines Corp. MS-DOS is a trademark of Microsoft Corporation. Instruction Mnemonics copyrighted Intel Corp., 1980.

DIS8051 CROSS-DISASSEMBLER User's Guide

Table of Contents

GENERAL 1.0 1.1 1.2 Distribution Disk Contents . . . . . . . . . . . . . 1 General Description . . . . . . . . . . . . . . . . . 1 System Requirements . . . . . . . . . . . . . . . . . 1

USING THE DIS8051 DISASSEMBLER 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 Disassembler Output Format . . . Input File Types . . . . . . . . Getting Started . . . . . . . . . The Output File . . . . . . . . . Tag File Description . . . . . . Advanced DIS8051 Options . . . . A Guided Tour . . . . . . . . . Disassembly Output Description . Altering the Disassembler Format Cross Reference Lists . . . . . . Operand Text Files . . . . . . . Text File Modification Rules . . Error Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 4 5 6 7 8 12 13 14 15 16 17

APPENDICES 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 INTEL HEX Format . . . . . . . . . . . 8051/52 - Arithmetic Instructions . . . 8051/52 - Logical Instructions . . . . 8051/52 - Data Transfer Instructions . 8051/52 - Boolean Variable Instructions 8051/52 - Program Branching . . . . . . Special Function Register Map . . . . . Bit Addressable Register Map . . . . . Special Function Register Assignments . Interrupt Vectors and Priority Levels . User RAM Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 19 20 21 22 23 25 26 27 31 31

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1.0 DISTRIBUTION DISK CONTENTS DIS8051.COM OPERAND.BIT OPERAND.BYT EXAMPLE.BIN EXAMPLE.HEX EXAMPLE.LST Disassembler program. Mnemonic text for Bit Addressable SFR's. Mnemonic text for Data Memory SFR's. "Example" program assembled as a BINARY file. "Example" program assembled as a HEX file. "Example" program listing.

1.1 GENERAL DESCRIPTION The DIS8051 is a cross-disassembly tool. "Cross" meaning that while running on one type of a computer, it disassembles code for another. In many ways, the DIS8051 is similar to a debugger with the exception that it produces a source program code that is suitable for an assembler. Features, such as, ASCII character display, Label generation, and cross-reference lists greatly aid in the complicated task of reconstructing or debugging a program. A separate control file, called a TAG file, allows the user to mark (or tag) specific program areas to be disassembled as Text statements, HEX byte statements or simply ignored from disassembly. External Operand mnemonic text files, enable the DIS8051 to be "tailored" or "adapted" to a wide variety of 8051 type Microcontrollers. 1.2 SYSTEM REQUIREMENTS DIS8051 operates under MS-DOS 2.0 or greater and uses about 15K of memory. An additional 390K of memory is allocated for symbols and table storage. A typical system requirement would be about 512K bytes of memory. DIS8051 produces a disassembled program with cross-references in three passes. Pass #1 reads the input file and tabulates symbols and references. Pass #2 rereads the input file and begins writing each line of program code. Pass #3 writes the sorted cross-reference lists for Labels, Data Memory, Bit Addressable Memory and Immediate Bytes. An 8K Binary file, typically 23K in HEX format, may produce a disassembled source file of approximately 173K. While it is possible to run DIS8051 on a floppy disk, a hard disk would be recommended for speed considerations.

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2.0 DISASSEMBLER OUTPUT FORMAT All program code is written out using the conventional assembler format. This format divides each line in the program into four fields: label, op code, operand and comments. The LABEL field is used to assign a symbolic name or label to the location of an instruction, so that it can be referenced by other instructions in the program. For example, the instruction LJMP L0100 will cause the program counter to be unconditionally loaded with the memory address 0100H which was assigned to the label L0100. The instruction at label L0100 will be the next instruction to be executed after the JUMP (LJMP) instruction is executed. Most instructions will not be labeled, however, if an instruction is referenced, the label will begin in the leftmost column of the line and will begin with the optional character (default = "L"). The body of the label will contain the target address value. The label is ended with the optional character (default = ":") and followed by a tab. If no label was assigned, the label field is skipped using a tab character. The OP CODE field is mandatory for every line in the program that contains an instruction. The op code begins in field 2 and is separated from the label field by a tab character. The OPERAND field is used to specify data or an address for instructions that require an operand. The operand begins in field 3 and is separated from the op code by a tab character. The DIS8051 provides three types of operand forms: 000H - 0FFH L0000 - LFFFF ACC, DPL, SBUF Hexadecimal format. Label format. Mnemonic format.

The COMMENT field is used to add an explanatory note to a statement. The contents of the comment field are ignored by the assembler. The text of the comment field will be preceded by the optional character (default = semicolon ";"). Comments may be used alone without being appended to a line that contains an instruction. DIS8051 uses the comment field in one of three forms: 1. To identify the location and contents of the current instruction. 2. To deblock program segments for easier interpretation. 3. To append the cross-reference lists.

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2.1 INPUT FILE TYPES The DIS8051 can disassemble Hex or Binary coded files. HEX Hex files are translated versions of binary files. These translations are in a format of all ASCII characters. The entire file is broken down into groups of one-byte digits (which are ASCII characters). Each such group is given a separate load address (the place where it is to be loaded in memory) and a count (Number of characters in the group). In addition, there's a checksum in each group for detecting errors. HEX files can be transmitted from computer to computer or Downloaded to EPROM programmers.

If we take a look at an actual HEX file, we'll see something like this: :03000000020100FA :1001000090011812010880FEE493A3B4000122308C :1001100099FDC299F59921084558414D504C45002B :00000001FF

BINARY

Binary files are images of the program as it will appear in memory. The binary image cannot be easily transmitted or Downloaded because it consists of eight-bit bytes. Communication adapters usually use the eighth bit for Parity checking which leaves only seven bits for communication. Since every possible combination of eight bits can be part of a binary file, there would be no way to signal the end of a transmission.

Just as the eighth bit is used as a Parity check in communications, it is also used to enable graphic or special character symbols in video display adapters. Viewing a binary file on the screen would show a series of characters and symbols that won't make any sense. Programs that organize and display the contents of binary files are usually called DUMP or HEXDUMP programs. The following is a view of a binary file using HEXDUMP: 0000 02 01 0010 FF FF : : 0100 90 01 0110 99 FD 00 FF : 18 C2 FF FF : 12 99 FF FF : 01 F5 FF FF : 08 99 FF FF : 80 21 FF FF : FE 08 FF FF : E4 45 FF FF : 93 58 FF FF : A3 41 FF FF : B4 4D FF FF : 00 50 FF FF : 01 4C FF FF : 22 45 FF FF : 30 00 ................ ................ .............."0 ......!.EXAMPLE.

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2.2 GETTING STARTED The HEX and BINARY data shown on the previous page, were from the example files supplied on this disk. The files are called EXAMPLE.HEX and EXAMPLE.BIN. The original listing, EXAMPLE.LST which is a text file, has been included for reference. We will use these files within the descriptions of command and statement syntax.

****************************************

To disassemble the EXAMPLE.HEX program in a very basic format, simply type:

DIS8051 EXAMPLE.HEX <RETURN>

The following messages will appear: ...................................................................... . . . DIS8051 Cross Disassembler Version 2.x PC/MS-DOS . . Copyright (C) 1989 Data Sync Engineering All rights reserved. . . . . Memory initialization ... . . No Tag File . . Starting PASS Number 1 - Processing: 0110 . . Starting PASS Number 2 - Processing: 0110 . . . . Successful Disassembly -- Source File Created. . ......................................................................

EXAMPLE.HEX has been disassembled and a new file called EXAMPLE.SRC was created. This new file contains the assembly language source code.

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2.3 THE OUTPUT FILE

The source file created (EXAMPLE.SRC) will look like: ;===============================================================; ; Disassembled Using DIS8051 - (C)1989 Data Sync Engineering ; ;===============================================================; ; ; ORG 00000H ; LJMP L0100 ; ORG 00100H ; ; L0100: MOV DPTR,#L0118 LCALL L0108 ; L0106: SJMP L0106 ; L0108: CLR A MOVC A,@A+DPTR INC DPTR CJNE A,#000H,L010F RET ; L010F: JNB TI,L010F CLR TI MOV SBUF,A AJMP L0108 ; L0118: ORL A,058H AJMP L024D ; JNC L016A ORL A,000H ; ; Unresolved Address Reference list ; ; L016A: EQU 0016AH L024D: EQU 0024DH ; END

As you can see, DIS8051 automatically inserted Labels for memory location references and Directive statements for Assembler control. A code segmentation method is also performed by inserting blank comment lines after certain instructions, such as RET and JMP, and before a line that contains a Label.

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Since PASS 1 assigned label operands to the memory referenced instructions, PASS 2 inserts these labels at their appropriate addresses. If a memory location reference was not found as an instruction address then DIS8051 automatically EQUATES the value to that label and shows it in the Unresolved Reference list. Unresolved References are generally caused by the disassembly of ASCII text characters, Program Tables or by accesses made to undefined I/O devices or other external memory. A separate file, called a Tag file, can be used to further control the disassembly process by marking these areas of the program for a specified mode of disassembly.

2.4 TAG FILE DESCRIPTION The Tag file tells the DIS8051 what mode of disassembly to switch to. This file can be created with any ASCII text editor and is identified with the same filename but has the file extension of ".TAG". Entries into the tag file consist of a four character hexadecimal start address followed by the "=" character then the command character. There are four basic disassembly modes; Instruction disassembly, Skip or ignore byte disassembly, Hex Byte table disassembly and ASCII Text disassembly (Define Byte statements containing ASCII text characters). An additional command called "Generate Label equate", forces DIS8051 to build an equate list defining the I/O and External Memory addresses. This "Equate List" is written at the beginning of the disassembled file and is not recorded within the Unresolved Address References.

Tag File Command Summary: Function Character --------G or g S or s I or i B or b T or t

Result -----------------------------------------------------GENERATE Label Equate for specified address. SKIP disassembly (ignores marked bytes). INSTRUCTION disassembly. Define BYTE disassembly (DB 000H). TEXT disassembly (DB 'text').

* See ALTERING DISASSEMBLER FORMAT for more Tag File features.

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2.5 ADVANCED DIS8051 OPTIONS The DIS8051 contains powerful disassembly options that provide a more complete detail on the program that is being disassembled.

Advanced Option Summary: Option letter -----B or b C or c L or l R or r T or t X or x

Result -------------------------------------------------------Tells DIS8051 to input a Binary coded file. Append comment field Hexdump to each instruction line. Converts output assembly code to lower case characters. Append Cross-reference lists to end of source file. Include Tag File disassembly parameters. Write Cross-Reference lists only, no assembly code.

Option letters must be preceded by a slash "/" and may be grouped together (e.g. DIS8051 EXAMPLE.HEX /LCTR).

COMMENT FIELD HEXDUMP Comment fields are appended to each line containing a disassembled instruction. They show the Program Counters value, the HEX bytes utilized by the current instruction and the displayable ASCII character equivalent of the Hex bytes. Undisplayable characters, such as control characters, are shown as periods ".".

CROSS-REFERENCE LISTS The Cross-reference lists produced by the DIS8051, map out all Program Code and Memory usages. The listing shows the Label or Memory address followed by all locations that refer to that address. The referencing locations are identified by the Program Counter value shown in the comment field hexdump.

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2.6 A GUIDED TOUR

STEP 1 - Disassemble the EXAMPLE.HEX program with hexdump and cross-reference lists. Type:

DIS8051 EXAMPLE.HEX /RC <RETURN>

The following messages will appear: ...................................................................... . . . DIS8051 Cross Disassembler Version 2.x PC/MS-DOS . . Copyright (C) 1989 Data Sync Engineering All rights reserved. . . . . Memory initialization ... . . No Tag File . . Starting PASS Number 1 - Processing: 0110 . . Starting PASS Number 2 - Processing: 0110 . . Starting PASS Number 3 - Xref lists: 0000 . . . . Successful Disassembly -- Source File Created. . ......................................................................

STEP 2 - View the disassembled listing (EXAMPLE.SRC). ;===============================================================; ; Disassembled Using DIS8051 - (C)1989 Data Sync Engineering ; ;===============================================================; ; ; ORG 00000H ; LJMP L0100 ;0000 02 01 00 ... ; ; ORG 00100H ; ; L0100: MOV DPTR,#L0118 ;0100 90 01 18 ... LCALL L0108 ;0103 12 01 08 ... ; L0106: SJMP L0106 ;0106 80 FE ..

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A GUIDED TOUR (cont.)

L0108: CLR A ;0108 E4 MOVC A,@A+DPTR ;0109 93 INC DPTR ;010A A3 CJNE A,#000H,L010F ;010B B4 00 01 RET ;010E 22 ; L010F: JNB TI,L010F ;010F 30 99 FD CLR TI ;0112 C2 99 MOV SBUF,A ;0114 F5 99 AJMP L0108 ;0116 21 08 ; L0118: ORL A,058H ;0118 45 58 AJMP L024D ;011A 41 4D ; JNC L016A ;011C 50 4C ORL A,000H ;011E 45 00 ; ; Unresolved Address Reference list ; ; L016A: EQU 0016AH L024D: EQU 0024DH ; ; Cross-references to LABELS ; ; L0100= 0000 ; L0106= 0106 ; L0108= 0103 0116 ; L010F= 010B 010F ; L0118= 0100 ; L016A= 011C ; L024D= 011A ; ; Cross-references to Data Memory locations ; ; M: 00= 011E ; M: 58= 0118 ; M: 99= 0114 ; ; Cross-references to BIT addressable locations ; ; B: 99= 010F 0112 ; ; Immediate Byte references ; ; #: 00= 010B ; END

. . . ... " 0.. .. .. !. EX AM PL E.

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A GUIDED TOUR (cont.) When looking at the listing, notice that the area between locations 0118 to 011E contain ASCII text characters. It is also the same area that is generating the Unresolved Address References. Hint: A complete disassembly should not produce any Unresolved Address References.

STEP 3 - Using your text editor, create a file called EXAMPLE.TAG. In this file, write the following lines: 0118=T 011F=B FFFF The above Tag File commands specify that; starting at location 0118, switch to TEXT mode disassembly. Then at location 011F switch to Define Byte disassembly. The FFFF is used to signal the end of the Tag file command list. Each line of the Tag file contains only one command, but there is no limit to its length except that the "FFFF" address designation must be used to signal the end.

STEP 4 - Now disassemble the EXAMPLE.HEX program again using the Tag File parameters, lower-case character option and hexdump feature. Type:

DIS8051 EXAMPLE.HEX /TCL <RETURN>

...................................................................... . . . DIS8051 Cross Disassembler Version 2.x PC/MS-DOS . . Copyright (C) 1989 Data Sync Engineering All rights reserved. . . . . Memory initialization ... . . Tag File Processed . . Starting PASS Number 1 - Processing: 0110 . . Starting PASS Number 2 - Processing: 0110 . . . . Successful Disassembly -- Source File Created. . ......................................................................

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STEP 5 - By the way, we used the lower-case option to satisfy the programmers who prefer that listing method. The final EXAMPLE.SRC result should now look like:

;===============================================================; ; Disassembled Using DIS8051 - (C)1989 Data Sync Engineering ; ;===============================================================; ; ; ; org 00000h ; ljmp L0100 ;0000 02 01 00 ... ; ; org 00100h ; ; L0100: mov dptr,#L0118 ;0100 90 01 18 ... lcall L0108 ;0103 12 01 08 ... ; L0106: sjmp L0106 ;0106 80 FE .. ; L0108: clr a ;0108 E4 . movc a,@a+dptr ;0109 93 . inc dptr ;010A A3 . cjne a,#000h,L010F ;010B B4 00 01 ... ret ;010E 22 " ; ; L010F: jnb ti,L010F ;010F 30 99 FD 0.. clr ti ;0112 C2 99 .. mov sbuf,a ;0114 F5 99 .. ajmp L0108 ;0116 21 08 !. ; ; L0118: db 'EXAMPLE' db 000h ;011F 00 . ; ; Unresolved Address Reference list ; ; ; ; end

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2.7 DISASSEMBLY OUTPUT DESCRIPTION

The ORG assembly directives were inserted from information contained in the HEX file. ORG ; LJMP ; ORG 00100H L0100 ;0000 02 01 00 ... 00000H

:03 0000 00 020100 FA :10 0100 00 90011812010880FEE493A3B400012230 8C ---| +---> HEX file Load Address information

L0100: MOV LCALL ; L0106: SJMP ; L0108: CLR MOVC INC CJNE RET ; L010F: JNB CLR MOV AJMP ; L0118: ORL AJMP ; JNC ORL

DPTR,#L0118 L0108 L0106 A A,@A+DPTR DPTR A,#000H,L010F TI,L010F TI SBUF,A L0108 A,058H L024D L016A A,000H

;0100 90 01 18 ;0103 12 01 08 ;0106 80 FE ;0108 ;0109 ;010A ;010B ;010E ;010F ;0112 ;0114 ;0116 E4 93 A3 B4 00 01 22 30 C2 F5 21 99 FD 99 99 08

... ... .. . . . ... " 0.. .. .. !. EX AM

;0118 45 58 ;011A 41 4D

;011C 50 4C ;011E 45 00 ----- -------| | Program Counter <--------------+ | | HEX bytes utilized <---------+

PL E. --| | | | | ASCII equivalent of HEX bytes <------+

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2.8 ALTERING THE DISASSEMBLER FORMAT

Because of variations in Assembler Formats and Directive statement syntax, it may become necessary to alter certain directive and delimiter sequences. The Tag File can be used to change the default setting of these formats. Listed below are the output formats and their default settings:

Format Default Tag Max Type Setting Function Size -------------------------------------------------------------------Origin Equate Define Define Directive Directive Directive for HEX Bytes Directive for ASCII Text ORG EQU DB DB L : : ' ; SRC 8-bit 0--H O E D A L W X Y Z F M $ 4 4 4 4 1 1 1 1 1 3 -

Start-of-Label character End-of-Equate-Name delimiter char End-of-Label-Name delimiter char Text delimiter characters Comment Field delimiter character Output File Extension Mask 7-bits for ASCII hexdump Alternate HEX Notation

Valid examples of format changes: Tag Command line Change from: To: -------------------------------------------------------------------0000=O.ORG 0000=EEQ 0000=DDFB 0000=ATEXT 0000=LZ 0000=X 0000=Y" 0000=Z* 0000=FTST 0000=$ ORG EQU DB DB L X ' ; SRC 0--H .ORG EQ DFB TEXT Z (no delimiter) " * TST $--

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2.9 CROSS REFERENCE LISTS ; ; ; ; ; ; ; ; ; Cross-references to LABELS L0100= 0000 L0106= 0106 L0108= 0103 0116 L010F= 010B 010F L0118= 0100 L016A= 011C L024D= 011A ----- ---| | | +-------> Program address producing the reference. | +----------> Referenced Label (instruction address).

; Cross-references to Data Memory locations ; ; M: 99= 0114 -- -- ---| | | | | +--------> Program address producing the reference. | | | +---------> Data Memory Byte Address (99 = address for SBUF). | +------> Indicates address is for Data Memory or byte memory. ; Cross-references to BIT addressable locations ; ; B: 99= 010F 0112 -- -- ---- ---| | | | | | +-----+--> Program addresses producing the reference. | | | +---------> Bit Addressable Memory (99 = bit address for TI). | +------> Indicates address is for a BIT Addressable memory. ; Immediate Byte references ; ; #: 00= 010B -- -- ---| | | | | +--------> Program addresses producing the reference. | | | +---------> Immediate Values (usually called CONSTANTS). | +------> Indicates immediate byte value.

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2.10 OPERAND TEXT FILES When a disassembly process is started, the DIS8051 loads in two text files, OPERAND.BYT and OPERAND.BIT. These files contain the text substitution for the BYTE and BIT address mnemonics. They are used to adapt the DIS8051 disassembler to other members of the 8051 family. The rules, on the following page, should be followed when modifying the OPERAND.BYT and OPERAND.BIT files. Entries within the files begin with Byte or Bit address "00" and end with address "FF". Each line contains a total of ten characters including the carriage-return and line-feed. An operand mnemonic is terminated by the "=" character. Any text after this character is ignored.

The following examples show the difference between the 8052 and 80C152 SFR register assignment:

Special Function Register BYTE address (OPERAND.BYT) Byte Address -----------C8 8052 -------T2CON=== 80C152 -------IEN1====

Special Function Register BIT addresses (OPERAND.BIT) Bit Address ----------C8 C9 CA CB CC CD CE CF 8052 -------T2CP==== T2C===== TR2===== EXEN2=== TLCK==== RCLK==== EXF2==== TF2===== 80C152 -------EGSRV=== EGSRE=== EDMA0=== EGSTV=== EDMA1=== EGSTE=== 0CEH==== 0CFH====

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2.11 TEXT FILE MODIFICATION RULES

1.

All text should be entered in upper case characters.

2.

The "=" is used to end the mnemonic text word.

3.

Only up to a seven character mnemonic can be used.

4.

Each line must contain eight characters plus CR and LF. Any fill character can be used as long as the "=" character precedes it.

5.

All characters after the "=" will not be inserted into the assembly output file.

6.

Non applicable mnemonics, such as BIT addresses CE & CF of the 80C152, must contain at least one printable character. Hex notations (0--H) are generally recommended.

7.

Although, address locations 00 to 7F are not part of the SFR register range, they are set to the hex notations 000H to 07FH. Symbol names can be used instead.

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2.12 ERROR MESSAGES

Error -- No Input File Specified -------------------------------Filename was missing in the command line. Command Line syntax: DIS8051 <filename>[.ext] [/options] Error -- Input File Did Not Open -------------------------------Input File was not found. Check Drive, Path or Filename. Error -- Input File Empty ------------------------No data found in input file. Check File contents. Error -- Insufficient Disk Space -------------------------------Disk or Directory Full. Insert a new disk or delete unused files. Load Error In HEX File ---------------------Checksum Error in HEX File. Try another HEX file. Error When Loading Operand Text Files ------------------------------------Either wrong file length, Empty File, or File Not Found. Check OPERAND.BIT and OPERAND.BYT files.

A large amount of memory has been allocated for Cross-reference tables. If in the event, which is unlikely, an overflow has occured, a warning message will be displayed and that particular reference list will be truncated at it's maximum capacity of 32,766 references.

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3.0 INTEL HEX FORMAT

DATA RECORD --BYTE # 1 2 & 3 4 & 5 6 & 7 8 & 9 10 to X X+1 & X+2 X+3 & X+4 Colon (:), signifies start of a record. Number of data bytes in this record. Load address for this record, High Byte. Load address for this record, Low Byte. Record type, must be "00". Data bytes, two ASCII hex characters each. Checksum, two ASCII hex characters. CR & LF, (carriage return & line-feed).

END RECORD --BYTE # 1 2 & 3 4 to 7 8 & 9 10 & 11 12 & 13 Colon (:), signifies start of a record. Record length, must be "00". Start address, "0000" = end record. Record type Checksum, two ASCII hex characters. CR & LF, (carriage return & line-feed).

The CHECKSUM is the two's complement of the 8-bit sum of the Record Length, the two byte Load Address, the Record Type, and all the Data bytes.

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3.1 8051 INSTRUCTION SET - ARITHMETIC OPERATIONS

Assembly form Byte/Cycle Flags,Notes Description _________________________________________________________________________ ADD ADD ADD ADD ADDC ADDC ADDC ADDC DA A DEC DEC DEC DEC A Rn direct @Ri A,Rn A,direct A,@Ri A,#data A,Rn A,direct A,@Ri A,#data 1/1 2/1 1/1 2/1 1/1 2/1 1/1 2/1 1/1 1/1 1/1 2/1 1/1 1/4 1/1 1/1 2/1 1/1 1/2 1/4 1/1 2/1 1/1 2/1 AC,CY,OV AC,CY,OV AC,CY,OV AC,CY,OV AC,CY,OV AC,CY,OV AC,CY,OV AC,CY,OV CY,4 Add Add Add Add Add Add Add Add Register to Accumulator Direct Byte to Accumulator Indirect RAM to Accumulator Immediate Data to Accumulator Register to Acc with Carry Direct Byte to Acc with Carry Indirect RAM to Acc with Carry Immediate Data to Acc with Carry

Decimal Adjust Accumulator Decrement Decrement Decrement Decrement Accumulator Register Direct Byte Indirect RAM

DIV AB INC INC INC INC INC A Rn direct @Ri DPTR

CY=0,OV,5 Divide Accumulator by B Register Increment Increment Increment Increment Increment Accumulator Register Direct Byte Indirect RAM Data Pointer

MUL AB SUBB SUBB SUBB SUBB A,Rn A,direct A,@Ri A,#data

CY=0,OV,7 Multiply Accumulator and B Register AC,CY,OV AC,CY,OV AC,CY,OV AC,CY,OV Subtract Register from Acc w/borrow Sub Direct Byte from Acc w/borrow Sub Indirect RAM from Acc w/borrow Sub Immediate Data from Acc w/borrow

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3.2 8051 INSTRUCTION SET - LOGICAL OPERATIONS

Assembly form Byte/Cycle Flags,Notes Description _________________________________________________________________________ ANL ANL ANL ANL ANL ANL A,Rn A,direct A,@Ri A,#data direct,A direct,#data 1/1 2/1 1/1 2/1 2/1 3/2 1/1 1/1 1/1 2/1 1/1 2/1 2/1 3/2 1/1 1/1 1/1 1/1 1/1 1/1 2/1 1/1 2/1 2/1 3/2 CY CY AND AND AND AND AND AND Register to Accumulator Direct Byte to Accumulator Indirect RAM to Accumulator Immediate Data to Accumulator Accumulator to Direct Byte Immediate Data to Direct Byte

CLR A CPL A ORL ORL ORL ORL ORL ORL RL A RLC A RR A RRC A SWAP A XRL XRL XRL XRL XRL XRL A,Rn A,direct A,@Ri A,#data direct,A direct,#data A,Rn A,direct A,@Ri A,#data direct,A direct,#data

Clear Accumulator Complement Accumulator OR OR OR OR OR OR Register to Accumulator Direct Byte to Accumulator Indirect RAM to Accumulator Immediate Data to Accumulator Accumulator to Direct Byte Immediate Data to Direct Byte

Rotate Accumulator Left Rotate Acc Left through Carry Rotate Accumulator Right Rotate Acc Right through Carry Swap Nibbles within the Accumulator Exclusive-OR Exclusive-OR Exclusive-OR Exclusive-OR Exclusive-OR Exclusive-OR Register to Accumulator Direct Byte to Acc Indirect RAM to Acc Immediate Data to Acc Acc to Direct Byte Imm Data to Direct Byte

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3.3 8051 INSTRUCTION SET - DATA TRANSFER

Assembly form Byte/Cycle Flags,Notes Description _________________________________________________________________________ MOV MOV MOV MOV A,Rn A,direct A,@Ri A,#data 1/1 2/1 1/1 2/1 1/1 2/2 2/1 2/1 2/2 3/2 2/2 3/2 1/1 2/2 2/1 Move Move Move Move Register to Accumulator Direct Byte to Accumulator Indirect RAM to Accumulator Immediate Data to Accumulator

MOV Rn,A MOV Rn,direct MOV Rn,#data MOV MOV MOV MOV MOV direct,A direct,Rn direct,direct direct,@Ri direct,#data

Move Accumulator to Register Move Direct Byte to Register Move Immediate Data to Register Move Move Move Move Move Accumulator to Direct Byte Register to Direct Byte from Direct Byte to Direct Byte Indirect RAM to Direct Byte Immediate Data to Direct Byte

MOV @Ri,A MOV @Ri,direct MOV @Ri,#data

Move Accumulator to Indirect RAM Move Direct Byte to Indirect RAM Move Immediate Data to Indirect RAM Load Data Pointer w/ 16-bit Constant Move Code Byte relative DPTR to Acc Move Code Byte relative to PC to Acc Pop Direct Byte from Stack Push Direct Byte onto Stack Exchange Register with Accumulator Exchange Direct Byte with Accumulato Exchange Indirect RAM with Acc Exchange Low Nibble Ind RAM with Acc

MOV DPTR,#data16 3/2 MOVC A,@A+DPTR MOVC A,@A+PC POP direct PUSH direct XCH A,Rn XCH A,direct r XCH A,@Ri XCHD A,@Ri 1/1 1/1 1/2 1/2 2/2 2/2 1/1 2/1

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3.4 8051 INSTRUCTION SET - BOOLEAN VARIABLE MANIPULATION

Assembly form Byte/Cycle Flags,Notes Description _________________________________________________________________________ ANL C,bit ANL C,/bit CLR C CLR bit CPL C CPL bit JB bit,rel JNB bit,rel JBC bit,rel JC rel JNC rel MOV C,bit MOV bit,C ORL C,bit ORL C,/bit SETB C SETB bit 2/2 2/2 1/1 2/1 1/1 2/1 3/2 3/2 3/2 2/2 2/2 2/1 2/2 2/2 2/2 1/1 2/1 CY CY CY CY AND Direct Bit to Carry AND complement of Direct Bit to Cy Clear Carry Clear Direct Bit Complement Carry Complement Direct Bit

CY

Jump if Direct Bit is set Jump if Direct Bit is Not set AC,CY,OV,6 Jump if Direct Bit set then Clear it Jump if Carry is set Jump if Carry is Not set Move Direct Bit to Carry Move Carry to Direct Bit OR Direct Bit to Carry OR complement of Direct Bit to Carry Set Carry Set Direct Bit

CY CY CY

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3.5 8051 INSTRUCTION SET - PROGRAM BRANCHING

Assembly form Byte/Cycle Flags,Notes Description _________________________________________________________________________ ACALL addr 11 r AJMP addr 11 2/2 2 CY,3 CY,3 CY,3 CY,3 Absolute Jump, 11-bit address Comp Dir Byte to Acc, Jmp not equal Compare Immed to Acc & Jump not equa Compare Immed to Reg & Jump not equa Comp Imm to Indir Ri, Jump not equal Decrement Register & Jump if not zer Decrement Direct Byte & Jump not zer 2/2 1 Absolute Subroutine Call, 11-bit add

CJNE A,direct,rel 3/2 CJNE A,#data,rel 3/2 l CJNE Rn,#data,rel 3/2 l CJNE @Ri,#data,rel3/2 DJNZ Rn,rel o DJNZ direct,rel o JMP @A+DPTR JNZ rel JZ rel LCALL addr 16 LJMP addr 16 NOP RET RETI SJMP rel 1/2 2/2 2/2 3/2 3/2 1/1 1/2 1/2 2/2 3/2 2/2

Jump indirect relative to the DPTR Jump if Accumulator is Not Zero Jump if Accumulator is Zero Long Subroutine Call, 16-bit Address Long Jump, 16-bit Address No Operation Return from subroutine Return from Interrupt Short Jump, relative address

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NOTES 1. Starting with 11H as the opcode base, the final opcode is formed by placing bits 8, 9, and 10 of the target address in bits 5, 6, and 7 of the opcode. The 8 possible opcodes in hexadecimal are then: 11, 31, 51, 71, 91, B1, D1, F1 2. Starting with 01H as the opcode base, the final opcode is formed by placing bits 8, 9, and 10 of the target address in bits 5, 6, and 7 of the opcode. The 8 possible opcodes in hexadecimal are then: 01, 21, 41, 61, 81, A1, C1, E1 3. The Carry Flag is set if the Destination Operand is less than the Source Operand, otherwise the Carry Flag is clear. 4. The Carry Flag is set if the BCD result in the Accumulator is greater than decimal 99. 5. The Overflow Flag is set if the B Register contains zero (flags a divide by zero operation). Otherwise the Overflow Flag is cleared. 6. If any of the condition code flags are specified as the operand of this instruction, they will be reset by the instruction if they were originally set. 7. The high byte of the 16-bit product is placed in the B Register, the low byte in the Accumulator.

NOTES ON THE INSTRUCTION SET AND THE ADDRESSING MODES addr 11 - 11-bit destination address. Used by ACALL and AJMP. Branch will be within the same 2K-byte page of Program Memory as the first byte of the following instruction. addr 16 - 16-bit destination address. Used by LCALL and LJMP. A branch can be anywhere within the 64K-byte Program Memory address space. bit - Direct Addressed bit in Internal Data RAM or Special Function Register. direct - 8-bit internal data location's address. This could be an Internal Data RAM location (0-127) or an SFR [i.e., I/O port, control register, status register, ect.(128-255)]. rel - Signed (two's complement) 8-bit offset byte. Used by SJMP and all conditional jumps. Range is -128 to +127 bytes relative to first byte of the following instruction. Rn - Register R0-R7 of the currently selected Register Bank. @Ri - 8-bit internal data RAM location (0-255) addressed indirectly through register R0 or R1. #data - 8-bit constant included in instruction. #data 16 - 16-bit constant included in instruction.

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M: M: M: M: M: M: M: M:

80= 81= 82= 83= 84= 85= 86= 87=

P0 SP DPL DPH

PCON

M: M: M: M: M: M: M: M:

A0= P2 A1= A2= A3= A4= A5= A6= A7=

M: M: M: M: M: M: M: M:

C0= C1= C2= C3= C4= C5= C6= C7=

M: M: M: M: M: M: M: M:

E0= ACC E1= E2= E3= E4= E5= E6= E7=

M: M: M: M: M: M: M: M:

88= 89= 8A= 8B= 8C= 8D= 8E= 8F=

TCON TMOD TL0 TL1 TH0 TH1

M: M: M: M: M: M: M: M:

A8= IE A9= AA= AB= AC= AD= AE= AF=

M: M: M: M: M: M: M: M:

C8= C9= CA= CB= CC= CD= CE= CF=

T2CON RCAP2L RCAP2H TL2 TH2

M: M: M: M: M: M: M: M:

E8= E9= EA= EB= EC= ED= EE= EF=

M: M: M: M: M: M: M: M:

90= P1 91= 92= 93= 94= 95= 96= 97=

M: M: M: M: M: M: M: M:

B0= P3 B1= B2= B3= B4= B5= B6= B7=

M: M: M: M: M: M: M: M:

D0= PSW D1= D2= D3= D4= D5= D6= D7=

M: M: M: M: M: M: M: M:

F0= B F1= F2= F3= F4= F5= F6= F7=

M: M: M: M: M: M: M:

98= SCON 99= SBUF 9A= 9B= 9C= 9D= 9E=

M: M: M: M: M: M: M:

B8= IP B9= BA= BB= BC= BD= BE=

M: M: M: M: M: M: M:

D8= D9= DA= DB= DC= DD= DE=

M: M: M: M: M: M: M:

F8= F9= FA= FB= FC= FD= FE=

M: 9F=

M: BF=

M: DF=

M: FF=

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B: B: B: B: B: B: B: B:

80= 81= 82= 83= 84= 85= 86= 87=

P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7

B: B: B: B: B: B: B: B:

A0= A1= A2= A3= A4= A5= A6= A7=

P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7

B: B: B: B: B: B: B: B:

C0= C1= C2= C3= C4= C5= C6= C7=

B: B: B: B: B: B: B: B:

E0= E1= E2= E3= E4= E5= E6= E7=

ACC.0 ACC.1 ACC.2 ACC.3 ACC.4 ACC.5 ACC.6 ACC.7

B: B: B: B: B: B: B: B:

88= 89= 8A= 8B= 8C= 8D= 8E= 8F=

IT0 IE0 IT1 IE1 TR0 TF0 TR1 TF1

B: B: B: B: B: B: B: B:

A8= A9= AA= AB= AC= AD= AE= AF=

EX0 ET0 EX1 ET1 ES ET2 EA

B: B: B: B: B: B: B: B:

C8= C9= CA= CB= CC= CD= CE= CF=

T2CP T2C TR2 EXEN2 TCLK RCLK EXF2 TF2

B: B: B: B: B: B: B: B:

E8= E9= EA= EB= EC= ED= EE= EF=

B: B: B: B: B: B: B: B:

90= 91= 92= 93= 94= 95= 96= 97=

P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7

B: B: B: B: B: B: B: B:

B0= B1= B2= B3= B4= B5= B6= B7=

P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7

B: B: B: B: B: B: B: B:

D0= D1= D2= D3= D4= D5= D6= D7=

P OV RS0 RS1 F0 AC CY

B: B: B: B: B: B: B: B:

F0= F1= F2= F3= F4= F5= F6= F7=

B.0 B.1 B.2 B.3 B.4 B.5 B.6 B.7

B: B: B: B: B: B: B:

98= 99= 9A= 9B= 9C= 9D= 9E=

RI TI RB8 TB8 REN SM2 SM1

B: B: B: B: B: B: B:

B8= B9= BA= BB= BC= BD= BE=

PX0 PT0 PX1 PT1 PS PT2

B: B: B: B: B: B: B:

D8= D9= DA= DB= DC= DD= DE=

B: B: B: B: B: B: B:

F8= F9= FA= FB= FC= FD= FE=

B: 9F= SM0

B: BF=

B: DF=

B: FF=

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3.8 SPECIAL FUNCTION REGISTER ASSIGNMENTS

Reg Byte Bit Address Byte / Bit Name Addr 7 6 5 4 3 2 1 0 Description ------ ---- --------------------------------- -------------------------P0 80 87 86 85 84 83 82 81 80 | | | | | | | +--> | | | | | | +------> | | | | | +----------> | | | | +--------------> | | | +------------------> | | +----------------------> | +--------------------------> +------------------------------> Port P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 0 Port Port Port Port Port Port Port Port 0 0 0 0 0 0 0 0 bit bit bit bit bit bit bit bit 0 1 2 3 4 5 6 7

SP DPL DPH PCON

81 82 83 87

Stack Pointer Data Pointer Low (DPTR) Data Pointer High (DPTR) Power IDL PD GF0 GF1 Control register Idle mode bit Power down bit General Purpose flag General Purpose flag

- - - - - - - | | | | | | | +--> | | | | | | +------> | | | | | +----------> | | | | +--------------> | | | +------------------> | | +----------------------> | +--------------------------> +------------------------------>

SMOD Double Baud Rate bit

TCON g

88

8F 8E 8D 8C 8B 8A 89 88 Timer / Counter control | | | | | | | +--> IT0 INT0 edge control | | | | | | +------> IE0 INT0 edge detect fla | | | | | | | | | | | +----------> IT1 INT1 edge control INT1 edge detect fla Timer 0 run control Timer 0 overflow fla Timer 1 run control Timer 1 overflow fla

+--------------> IE1

g | | g | g TMOD l | | | | | | | | | | | | | | | | | +--> M0 | +------> M1 +----------> C/T Timer 0 operate mode Timer 0 operate mode Counter/Timer 0 slct 89 Timer /Counter Mode Contro +--------------------------> TR1 +------------------------------> TF1 | +------------------> TR0 +----------------------> TF0

| | | |

+--------------> GATE Timer 0 gate Timer 1 operate mode Timer 1 operate mode Counter/Timer 1 slct

| | +------------------> M0 | +----------------------> M1 +--------------------------> C/T

+------------------------------> GATE Timer 1 gate

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SPECIAL FUNCTION REGISTER ASSIGNMENTS (cont.)

Reg Byte Bit Address Byte / Bit Name Addr 7 6 5 4 3 2 1 0 Description ------ ---- --------------------------------- -------------------------TL0 TL1 TH0 e TH1 e P1 90 97 96 95 94 93 92 91 90 | | | | | | | +--> | | | | | | +------> | | | | | +----------> | | | | +--------------> | | | +------------------> | | +----------------------> | +--------------------------> +------------------------------> 9F | | | | | | t | t +------------------------------> SM0 t SBUF P2 99 A0 A7 | | | | A6 | | | | A5 | | | | A4 | | | | Serial Data Buffer Port P2.0 P2.1 P2.2 P2.3 2 Port Port Port Port 2 2 2 2 bit bit bit bit 0 1 2 3 Serial Port mode slc +--------------------------> SM1 Serial Port mode slc 9E | | | | | | 9D | | | 9C | | | 9B | | | 9A 99 98 | | +--> | +------> +----------> Port P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 1 Port Port Port Port Port Port Port Port 1 1 1 1 1 1 1 1 bit bit bit bit bit bit bit bit 0 1 2 3 4 5 6 7 8D Timer / Counter 1 high byt 8A 8B 8C Timer / Counter 0 low byte Timer / Counter 1 low byte Timer / Counter 0 high byt

SCON

98

Serial Control RI Rcvr interrupt flag TI Xmit interrupt flag RB8 9th bit rcvd/stop bi 9th bit transmission Receiver enable Serial Port mode slc

t | | +--------------> TB8 | +------------------> REN +----------------------> SM2

A3 A2 A1 A0 | | | +--> | | +------> | +----------> +-------------->

| | | +------------------> | | +----------------------> | +--------------------------> +------------------------------>

P2.4 P2.5 P2.6 P2.7

Port Port Port Port

2 2 2 2

bit bit bit bit

4 5 6 7

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SPECIAL FUNCTION REGISTER ASSIGNMENTS (cont.)

Reg Byte Bit Address Byte / Bit Name Addr 7 6 5 4 3 2 1 0 Description ------ ---- --------------------------------- -------------------------IE 0 | . | 1 | . | t | p | s +--------------------------> Enable all interrupt +------------------------------> EA | +----------------------> ET2 Timer 2 ovflow or Ca | | +------------------> ES Serial Port interrup | | | +--------------> ET1 Timer 1 overflow int | | | | +----------> EX1 Enable interrupt INT | | | | | +------> ET0 Timer 0 overflow int A8 AF AE AD AC AB AA A9 A8 Interrupt Enable register | | | | | | | +--> EX0 Enable interrupt INT

P3

B0

B7 B6 B5 B4 B3 B2 B1 B0 | | | | | | | +--> | | | | | | +------> | | | | | +----------> | | | | +--------------> | | | +------------------> | | +----------------------> | +--------------------------> +------------------------------>

Port P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7

3 Port Port Port Port Port Port Port Port 3 3 3 3 3 3 3 3 bit bit bit bit bit bit bit bit 0 1 2 3 4 5 6 7

IP

B8

BF BE BD BC BB BA B9 B8 | | | | | | | +--> | | | | | | +------> | | | | | +----------> | | | | +--------------> | | | +------------------> | | +----------------------> | +--------------------------> +------------------------------>

Interrupt Priority Control PX0 INT0 priority PT0 Timer 0 priority PX1 INT1 priority PT1 Timer 1 priority PS Serial Port priority PT2 Timer 2 priority

T2CON

C8

CF | | |

CE | | |

CD | | |

CC | | |

CB | | |

CA C9 C8 | | +--> | +------> +---------->

Timer T2CP T2C TR2

/ Counter 2 control Capture/reload flag Internal/Ext select Timer 2 start/stop

| | | | g g

| |

| |

| +--------------> EXEN2 Timer 2 ext enable +------------------> TCLK Transmit clock flag

| +----------------------> RCLK Receive clock flag +--------------------------> EXF2 Timer 2 external fla Timer 2 overflow fla

+------------------------------> TF2

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SPECIAL FUNCTION REGISTER ASSIGNMENTS (cont.)

Reg Byte Bit Address Byte / Bit Name Addr 7 6 5 4 3 2 1 0 Description ------ ---- --------------------------------- -------------------------RCAP2L CA e RCAP2H CB TL2 TH2 e PSW D0 D7 D6 D5 D4 D3 D2 D1 D0 | | | | | | | +--> | | | | | | +------> | | | | | +----------> | | | | +--------------> | | | +------------------> | | +----------------------> | +--------------------------> +------------------------------> Program Status Word P ACC parity flag -User definable flag OV Overflow flag RS0 Reg bank select 0 RS1 Reg bank select 1 F0 Gen purpose Flag 0 AC Auxiliary carry flag CY Carry flag CC CD T/C 2 Capt reg. high byte Timer / Counter 2 low byte Timer / Counter 2 high byt T/C 2 Capture reg. low byt

ACC

E0

E7 E6 E5 E4 E3 E2 E1 E0 | | | | | | | +--> | | | | | | +------> | | | | | +----------> | | | | +--------------> | | | +------------------> | | +----------------------> | +--------------------------> +------------------------------>

Accumulator ACC.0 Accumulator ACC.1 Accumulator ACC.2 Accumulator ACC.3 Accumulator ACC.4 Accumulator ACC.5 Accumulator ACC.6 Accumulator ACC.7 Accumulator

bit bit bit bit bit bit bit bit

0 1 2 3 4 5 6 7

F0

F7 F6 F5 F4 F3 F2 F1 F0 | | | | | | | +--> | | | | | | +------> | | | | | +----------> | | | | +--------------> | | | +------------------> | | +----------------------> | +--------------------------> +------------------------------>

B Register B.0 B register B.1 B register B.2 B register B.3 B register B.4 B register B.5 B register B.6 B register B.7 B register

bit bit bit bit bit bit bit bit

0 1 2 3 4 5 6 7

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3.10 INTERRUPT VECTORS & PRIORITY LEVELS Event ------------------Reset External INT0 Counter / Timer 0 External INT1 Counter / Timer 1 Serial RCV & XMIT flag Timer 2 & External 2 Vector -----000 003 00B 013 01B 023 02B Priority level ----------------- Highest priority

- Lowest priority

3.11 USER RAM MEMORY MAP Byte Bit Address Byte / Bit Addr 7 6 5 4 3 2 1 0 Description -------- --------------------------------- --------------------------30 -> 7F 80 bytes general user RAM

2F 2E 2D 2C 2B 2A 29 28 27 26 25 24 23 22 21 20 18 -> 1F 10 -> 17 08 -> 0F 00 -> 07

7F 77 6F 67 5F 57 4F 47 3F 37 2F 27 1F 17 0F 07 -

7E 76 6E 66 5E 56 4E 46 3E 36 2E 26 1E 16 0E 06 -

7D 75 6D 65 5D 55 4D 45 3D 35 2D 25 1D 15 0D 05 -

7C 74 6C 64 5C 54 4C 44 3C 34 2C 24 1C 14 0C 04 -

7B 73 6B 63 5B 53 4B 43 3B 33 2B 23 1B 13 0B 03 -

7A 72 6A 62 5A 52 4A 42 3A 32 2A 22 1A 12 0A 02 -

79 71 69 61 59 51 49 41 39 31 29 21 19 11 09 01 -

78 70 68 60 58 50 48 40 38 30 28 20 18 10 08 00 -

Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit

addressable addressable addressable addressable addressable addressable addressable addressable addressable addressable addressable addressable addressable addressable addressable addressable

RAM RAM RAM RAM RAM RAM RAM RAM RAM RAM RAM RAM RAM RAM RAM RAM

location location location location location location location location location location location location location location location location

Bank 3 registers R0 -> R7 Bank 2 registers R0 -> R7 Bank 1 registers R0 -> R7 Bank 0 registers R0 -> R7