STM32F103ZET6 development board with 3.

2" TFT module

STM32 development board based on STMicroelectronics (ST) has introduced the highest series of ARM CortexM3 chip
configuration as the core component STM32!"3#$T%
CPU: STM32F103ZET6; (LQFP144-pin, on-chip integrated 512K Flash, 64K RAM, 1!it A " #, # " A; P$M,
CA%, U&!, &#'(, F&MC and other reso)rces*
1. The information of the board
CPU: &+M,F1-,./+0; (LQFP144-pin, integrated 112 3lash, 042RAM, 1!it A " #, # " A; P$M, CA%,
U&!, &#'(, F&MC and other reso)rces on the chip*
Can 4e /5panded to 112 &RAM, M %(R FLA&6 (on-4oard s)pport 3or the largest 1-47 &RAM, 10M
o3 %(R FLA&6* to 8eet the large capacit9 re:)ire8ents, 3or e5a8ple, data ac:)isition, processing and
anal9sis;
Can 4e e5panded to 10M %A%# FLA&6 to 8eet re:)ire8ents <hich need a large capacit9, s)ch as
rich color o3 the pict)re storage, data storage 3or8, doc)8ent 8anage8ent applications and so on;
$ith ,; inch +F+ color3)l to)ch screen 8od)le, F&MC control, color to)ch 8od)le con3ig)ration
A#&=>4,(or R&M1>4, instead* controller, s)pport 3or a &# card (&P' 8ode* can 4e )sed to store
pict)res, in s)pport o3 A+41#!555 o3 a #A+A FLA&6 (can 4e )sed 3or storage*
one channel CA% co88)nication inter3ace, &%01?6#,- chip
+<o channel R&, inter3ace
one channel R&4>1 co88)nication inter3ace
An &# card connector &#'( control
A 'C 8e8or9 inter3ace, <ith standard 4LC- (//PR(M*
A &P' 8e8or9 inter3ace, <ith standard A+41#!101# (#A+A FLA&6*
one channel ad@)st8ent potentio8eter A#C inp)t
+hree channel leads to A#C inp)t ter8inals
+<o channel ter8inal 4loc7 P$M o)tp)t
+<o channel leads to #AC o)tp)t ter8inals
A 4)AAer, 3iBe )sers L/# lights, a po<er indicator light, a U&! co88)nication indicator, 3o)r operation
7e9s, a reset 4)tton;
Po<er &elect @)8per, s)pport e5ternal 1? po<er s)ppl9, U&! po<er s)ppl9 or CL'%2 po<er s)ppl9
!oard &iAe: 1,CM D 1-CM
All ' " ( port thro)gh the standard pitch leads ;14MM,
Rich in ro)tines, not onl9 3)nctional 8od)les M#2-4oard test-so)rce: L/# lights into the <ater si5 e5a8ples,
R+C, according to health, P$M, 4)AAer, U&!, &# card, A#C, #AC, 1C, R&,, R&4>1 pass, CA%, to)ch-
screen test, +F+ LC# screen test ;;;;;
4)t also there are s)ccess3)l transplantation UC(&, UCEU' a n)84er o3 ro)tines can 4e directl9 applied to
ind)strial control e:)ip8ent or hand-held instr)8ent o3 h)8an-co8p)ter inter3ace design, so that 9o)r
prod)ct 3ro8 the 8onoton9 o3 4lac7 and <hite, into the color3)l <orldF 'nspire 9o)r design inspirationF
Power supply:
/5ternal 1? po<er s)ppl9: connect the #C1? po<er adapter to the C,, the CP4 insert to 1-;
U&! po<er s)ppl9: connect the U&! to the U&! connector inter3ace C4, the CP4 insert to -,;
CL'%2 po<er s)ppl9: Connect the CL'%2 ARM to C1, and inp)t Gpo<er on per8H on CL'%2
C(MMA%#/R;
Clock source:
+he deBelop8ent has t<o cloc7 so)rce to proBide the ti8e setting 3or the s9ste8 ti8e and R+C ti8e, R+C
ti8e is ,;=0>76., the s9ste8 ti8e is >M6.;
2. !ir!uit and interfa!e in"tru!tion
Boot opto!:
/84edded )ser Flash
&9ste8 8e8or9 <ith 4oot loader 3or '&P
/84edded &RAM 3or de4)gging, the 4oot <a9 can 4e choose as 4elo< option:
BOOT0

JP8

BOOT1

JP9

Boot mode
ANY

1-2

2-3
or open

2-3 The development board settin #"er Fla"h !or the
boot "a#$ BOOT1 %an be on a dis%retional pla%e$ it
%an be 1-2$ 2-3&'e!a(lt settin) or open*
2-3 1-2 The development is S$"tem Memor$ boot "a#
1-2 1-2 The development is Embedded S%&M boot "a#

"esett!# w$y:
Can )se 4elo< t<o <a9s to reset the 4oard
1;Reset 7e9: Reset

&1

;'np)t the resetting signal Bia C+AE inter3ace;

S%ul$to! !put:
+he A'%-

A'%1

A'% o3 the C%1 connect onto the &+M,F1-,./ o)tside si8)lation inp)t pin
PC-

PC1

PC;
P&M !put:
+he P$M-

P$M1 o3 the C%1 connect onto the &+M,F1-,./ ti8er o)tp)t pin P!-

P!1;
'(C output:
+he #AC-

#AC1 o3 the C%1 connect onto the &+M,F1-,./ #AC o)tp)t port PA4

PA1; #AC-

#AC1
o)tp)t ports is 8)ltiple5ing <ith &P'1I%&&

&P'1I&C2 pin; '3 the #AC- and #AC1 <ere )sed, need to open
the @)8per <ire C1, C;
)SB:
Jumper
'() JP+ 1-2

,-B 1*./ ,-B0

JP+2-3

,-B 1*./ ,-B0* ,-B 1O PB. &de!a(lt settin)*

'spl$y !ter*$ce:
,-54- +F+ color3)l LC# connect to &+M,F1-,./ F&MC lin7ing 4an71 %(R"P&RAM4

1 red
L/#

#1

1* connect to standard '( port PF0

>

1- 3or displa9ing

CP, color3)l +F+ screen inter3ace:

Pin
n(mber
-inal
des%ription
2orrespondin
1O
Pin
n(mber
-inal
des%ription
2orrespondin
1O
Pin
n(mber
-inal
des%ription
2orrespondi
n 1O
1 333 po"er 2 4N'

3 'B00 P'15
5 'B01 P'1. . 'B02 P'0 6 'B03 P'1
+ 'B05 P7+ 8 'B0. P78 9 'B06 P79
10 'B0+ P710 11 'B08 P711 12 'B09 P712
13 'B10 P713 15 'B11 P715 1. 'B12 P71.
16 'B13 P'8 1+ 'B15 P'9 18 'B1. P'10
19 2- P412 20 8- P90 21 :8 P'.
22 8' P'5 23 87-7T 87-7T 25 7N PA1
2. ;1-O PB15 26 1NT P4+ 2+ ;O-1 PB1.
28 <7 P48 29 -2</ PB13 30 9=2- P411
31 TP=2- PB12 32 -'=2- P41.
S"(M:
107510 &RAM connect to F&MC 4an71 %(R"P&RAM,

&)pport >-4it and 10-4it store inter3ace 8ode;

+(+' Fl$s,:
1 E4it 5> or E4it 5> %A%# Flash connect to %A%# 4an7 o3 F&MC inter3ace

+he read9"4)s9 signal <ire

o3 the %A%# FLA&6 Bia CP11 connect to &+M,F1-,./ F&MC $A'+ signal <ire or F&MCI'%+ signal
<ire;
>(mper -ettin des%ription
'(11 JP11 is settin 1-2

read#?b(s# %onne%t to :A1T &de!a(lt settin)*

JP11 is settin 2-3

read#?b(s# %onne%t to 9-;2=1NT2*

+-" Fl$s,:
10 M4it

M!9te

%(R Flash connect to F&MC 4an71 %(R"P&RAM

%(R Flash connect to !K+/ pin

( dra< )p the resistance* to choose the 10-4it operation 8ode;
>(mper -ettin des%ription
'(12 JP12 short$ it is "ritten prote%tion&'e!a(lt settin@ short )
JP12 open$ the "ritten prote%tion %lose*
3. Co!!ectors:
+he de3inition o3 the S%ul$to! !put

P&M o)tp)t

'(C o)tp)t and C+1 inter3ace:

Pin number Description Pin number Description
! A&'" % ()M!
2 A&'! * +',
3 A&'2 - ,AC"
. +', / ,AC!
0 ()M" !" +',
C(+ 4)s inter3ace C+2 de3inition:
Pin number Description Pin number Description
! CA'1 2 CA'2
"S4/5 4)s inter3ace C+3 de3inition:
Pin number Description Pin number Description
! .0-3 2 .0-A
"S232co88)nication inter3ace C-+1

C-+2 de3inition:
"S232 co!!ector C-+1

C-+2 0*ro!t 1ew2

(* C%(1 de3inition
(in
number
*e"!ription (in
number
*e"!ription
1 N2 6 N2
2 ,-A8T1=PA9 + N2
3 ,-A8T1=PA10 8 N2
5 N2 9 N2
. 4N'
(,* C%( de3inition
(in
number
*e"!ription (in
number
*e"!ription
1 N2 6 N2
2 ,-A8T2=PA2 + N2
3 ,-A8T2=PA3 8 N2
5 N2 9 N2
. 4N'
3T(4 5e6u##!# co!!ector 35 5e*!to!:
Pin number Description Pin number Description
! 3435 po6er 2 3435 po6er
3 (3. . +',
0 (A!0 % +',
* (A!3 - +',
/ (A!. !" +',
!! RTC7 !2 +',
!3 (33 !. +',
!0 R$S$T8 !% +',
!* ,3+R9 !- +',
!/ ,3+AC7 2" +',
)SB !ter*$ce 5e*!to!:
Pin n(mber 9(n%tion des%ription Pin n(mber 9(n%tion des%ription
0 'P - ';
3 3B,-

po"er

4 4N'
3T(4 $!5 S&' 5e6u##!# %o5e 3P6 5e*!to!:
$hen it is in 3T(4 %o5e, 8a7e s)re to inset the 5 @)8per o3 the 3P6, <hen it is in S&' %o5e, onl9 inset
the +M&( &$#'( * and +C2 ( &$#CL2 *;
(in
number
*e"!ription (in
number
*e"!ription
1 NT8-T

PB5

2 T'1

PA1.

3 T;-

PA13

5 T2/

PA15

. T'O

PB3

TFT 7C' 3829

3.2: ;<4( 262k TFT=7C' %o5ule
4-LRE!L,- pi5els
>-4it or 10-4it parallel 4)s inter3ace,>-4it 8ode )se =46C1=, latch lo< >-4it (short R= ena4le >-4it 8ode*
open R= is 10-4it 8ode(de3a)lt*, )se high >-4it operation 4)s in >-4it 8ode lo< >-4it 3loat
LC# driBer is &&#1J>
;=-,;,? operating Boltage
ResistiBe 4-<ire +o)ch Panel integrated
R&1>4, to)ch panel controller on4oard directl9 co8pati4le <ith A#&=>4,
&tandard ;1488 PC! headers 3or protot9ping
&)pport a &# card inter3ace
&)pport a A+M/L #ataFlash A+41#!555 series deBice
can directl9 )se A?R,P'C,C11,ARM;&+M, MCU driBer
3.2: ;<4( 262k TFT=7C' %o5ule P>+ 5escrpto!
P1N 'e!inition P1N 'e!inition
1 333 2 4N'
3 'B00 5 'B01
. 'B02 6 'B03
+ 'B05 8 'B0.
9 'B06 10 'B0+
11 'B08 12 'B09
13 'B010 15 'B11
1. 'B012 16 'B13
1+ 'B015 18 'B1.
19 2- 20 8-
21 :8 22 8'
23 87-7T 25 7N ba%A=liht enable
2. ;1-O -P1 26 1NT
2+ ;O-1 -P1 28 <7
29 -2</ -P1 30 9=2- 'ATA9<A-B
31 TP=2- 32 -'=2-
Ko!ektory STM32F103ZET
3P1 = 7e1? @ spo5!A
6/A#/R ,-D
Alternate Re8ap Alternate Re8ap
1 P/, P/
, P/1 4 P/4
1 ?!A+ 0 P/0
= PC14 > PC1,
J PF- 1- PC11
11 PF 1 PF1
1, PF4 14 PF,
11 PF0 10 PF1
1= PF> 1> PF=
1J PF1- - PFJ
1 PC1 PC-
, PC, 4 PC
1 ?R/F- 0 ?&&A
= ?##A > ?R/FM
J PA1 U&AR+IR+& ,- PA- U&AR+IC+&
,1 PA, U&AR+IR5 , PA U&AR+I+5
,, PA1 &P'1-&C2 ,4 PA4 &P'1I%&&
,1 PA> +'M1IC61, U&AR+1IC2 ,0 PCJ
,= PC1 A#C1I'%11 ,> PC4 A#C1I'%14
,J P!1 A#C1I'%J 4- P!- A#C1I'%>, +'M,IC6,
41 PF11 4 P!
4, PF1, 44 PF1
41 PF11 40 PF14
4= PE1 4> PE-
4J P/> 1- P/=
11 P/1- 1 P/J
1, P/1 14 P/11
11 P/14 10 P/1,
1= P!1- 1> P/11
1J E%# 0- P!11
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3P2 @ Pr$1? @ ,or!A
6/A#/R ,-D
Alternate Re8ap Alternate Re8ap
1 P/1 P/-
, P!J +'M4IC64 'CI&#A 4 P!> +'M4IC6, 'C1I&CL
1 P!= 'CI&#A U&AR+1IR50 P!0 'CI&CL
U&AR+1I+5
= P!1 &P'1IM(&' > P!4 &P'1IM'&(
J P!, &P'1I&C2 1- PE11
11 PE14 1 PE1,
1, PE1 14 PE11
11 PE1- 10 PEJ
1= P#= 1> P#0 U&AR+-R5
1J P#1 U&AR+-+5 - P#4 U&AR+-
R+&
1 P#, U&AR+-C+& P#
, P#1 4 P#-
1 PC1 0 PC11 U&AR+,IR5
= PC1- U&AR+,I+5> PA11 &P'1I%&&
J PA14 &$CL2 ,- PA1, &$#'(
,1 PA1 U&AR+1IR+& , PA11 U&AR+1IC+&
,, PA1- U&AR+1IR5 ,4 PAJ U&AR+1I+5
,1 PA= &P'1-M(&' ,0 PA0 &P'1-M'&(
,= PC> +'M,IC6, ,> PC=
+'M,IC6
,J PC0 +'M,IC61 4- PE>
41 PE= 4 PE0
4, PE1 44 PE4
41 PE, 40 PE
4= P#11 4> P#14
4J P#1, 1- P#1
11 P#11 1 P#1-
1, P#J 14 P#>
11 P!11 &P'IM(&', U&AR+,IR+& +'M11IC6 10 P!14 &P'IM'&(, +'M1IC6%+'M11IC61
1= P!1, &P'I&C2, +'M1IC61%, U&AR+,IR+& 1> P!1 &P'I%&&, U&AR+,IC2
1J E%# 0- ,?,
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)S("T1 PraBN O hornP