Semiconductor Components Industries, LLC, 2011

November, 2011 Rev. 8

1 Publication Order Number:
MC34151/D
MC34151, MC33151
High Speed Dual
MOSFET Drivers
The MC34151/MC33151 are dual inverting high speed drivers
specifically designed for applications that require low current digital
circuitry to drive large capacitive loads with high slew rates. These
devices feature low input current making them CMOS and LSTTL
logic compatible, input hysteresis for fast output switching that is
independent of input transition time, and two high current totem pole
outputs ideally suited for driving power MOSFETs. Also included is
an undervoltage lockout with hysteresis to prevent erratic system
operation at low supply voltages.
Typical applications include switching power supplies, dc to dc
converters, capacitor charge pump voltage doublers/inverters, and
motor controllers.
These devices are available in dualinline and surface mount
packages.
Features
Two Independent Channels with 1.5 A Totem Pole Output
Output Rise and Fall Times of 15 ns with 1000 pF Load
CMOS/LSTTL Compatible Inputs with Hysteresis
Undervoltage Lockout with Hysteresis
Low Standby Current
Efficient High Frequency Operation
Enhanced System Performance with Common Switching Regulator
Control ICs
Pin Out Equivalent to DS0026 and MMH0026
These are PbFree and HalideFree Devices
Figure 1. Representative Block Diagram
+
+
+
-
V
CC
6
5.7V
Logic Input A
2
Logic Input B
4
GND
3
1
0
0
k
Drive Output A
7
Drive Output B
5
+
+
+
+
1
0
0
k
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See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
ORDERING INFORMATION
PDIP8
P SUFFIX
CASE 626
MARKING
DIAGRAMS
1
8
1
8
MC3x151P
AWL
YYWWG
SOIC8
D SUFFIX
CASE 751
1
8
x = 3 or 4
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = PbFree Package
PIN CONNECTIONS
1 8 N.C. N.C.
(Top View)
2 7 Drive Output A Logic Input A
3 6 V
CC
GND
4 5 Drive Output B Logic Input B
3151V
ALYWG
G
1
8
(Note: Microdot may be in either location)
3x151
ALYWG
G
1
8
MC3x151 MC33151V
MC34151, MC33151
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2
MAXIMUM RATINGS
Rating Symbol Value Unit
Power Supply Voltage V
CC
20 V
Logic Inputs (Note 1) V
in
0.3 to V
CC
V
Drive Outputs (Note 2)
Totem Pole Sink or Source Current
Diode Clamp Current (Drive Output to V
CC
)
I
O
I
O(clamp)
1.5
1.0
A
Power Dissipation and Thermal Characteristics
D Suffix SOIC8 Package Case 751
Maximum Power Dissipation @ T
A
= 50C
Thermal Resistance, JunctiontoAir
P Suffix 8Pin Package Case 626
Maximum Power Dissipation @ T
A
= 50C
Thermal Resistance, JunctiontoAir
P
D
R
qJA
P
D
R
qJA
0.56
180
1.0
100
W
C/W
W
C/W
Operating Junction Temperature T
J
+150 C
Operating Ambient Temperature
MC34151
MC33151
MC33151V
T
A
0 to +70
40 to +85
40 to +125
C
Storage Temperature Range T
stg
65 to +150 C
Electrostatic Discharge Sensitivity (ESD) (Note 3)
Human Body Model (HBM)
Machine Model (MM)
Charged Device Model (CDM)
ESD
2000
200
1500
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. For optimum switching speed, the maximum input voltage should be limited to 10 V or V
CC
, whichever is less.
2. Maximum package power dissipation limits must be observed.
3. ESD protection per JEDEC Standard JESD22A114F for HBM
per JEDEC Standard JESD22A115A for MM
per JEDEC Standard JESD22C101D for CDM.
MC34151, MC33151
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ELECTRICAL CHARACTERISTICS (V
CC
= 12 V, for typical values T
A
= 25C, for min/max values T
A
is the only operating
ambient temperature range that applies [Note 3], unless otherwise noted.)
Characteristics Symbol Min Typ Max Unit
LOGIC INPUTS
Input Threshold Voltage Output Transition High to Low State
Output Transition Low to High State
V
IH
V
IL

0.8
1.75
1.58
2.6

V
Input Current High State (V
IH
= 2.6 V)
Input Current Low State (V
IL
= 0.8 V)
I
IH
I
IL

200
20
500
100
mA
DRIVE OUTPUT
Output Voltage Low State (I
Sink
= 10 mA)
Output Voltage Low State (I
Sink
= 50 mA)
Output Voltage Low State (I
Sink
= 400 mA)
Output Voltage High State (I
Source
= 10 mA)
Output Voltage High State (I
Source
= 50 mA)
Output Voltage High State (I
Source
= 400 mA)
V
OL
V
OH

10.5
10.4
9.5
0.8
1.1
1.7
11.2
11.1
10.9
1.2
1.5
2.5

V
Output Pulldown Resistor R
PD
100 kW
SWITCHING CHARACTERISTICS (T
A
= 25C)
Propagation Delay (10% Input to 10% Output, C
L
= 1.0 nF)
Logic Input to Drive Output Rise
Logic Input to Drive Output Fall
t
PLH(in/out)
t
PHL(in/out)

35
36
100
100
ns
Drive Output Rise Time (10% to 90%) C
L
= 1.0 nF
Drive Output Rise Time (10% to 90%) C
L
= 2.5 nF
t
r

14
31
30

ns
Drive Output Fall Time (90% to 10%) C
L
= 1.0 nF
Drive Output Fall Time (90% to 10%) C
L
= 2.5 nF
t
f

16
32
30

ns
TOTAL DEVICE
Power Supply Current
Standby (Logic Inputs Grounded)
Operating (C
L
= 1.0 nF Drive Outputs 1 and 2, f = 100 kHz)
I
CC

6.0
10.5
10
15
mA
Operating Voltage V
CC
6.5 18 V
1. For optimum switching speed, the maximum input voltage should be limited to 10 V or V
CC
, whichever is less.
2. Maximum package power dissipation limits must be observed.
3. T
low
= 0C for MC34151 T
high
= +70C for MC34151
40C for MC33151 +85C for MC33151
MC34151, MC33151
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Figure 2. Switching Characteristics Test Circuit Figure 3. Switching Waveform Definitions
Figure 4. Logic Input Current versus
Input Voltage
Figure 5. Logic Input Threshold Voltage
versus Temperature
Figure 6. Drive Output LowtoHigh Propagation
Delay versus Logic Overdrive Voltage
Figure 7. Drive Output HightoLow Propagation
Delay versus Logic Input Overdrive Voltage
V
in
, INPUT VOLTAGE (V)
,

I
N
P
U
T

C
U
R
R
E
N
T

(
m
A
)
i
n
I
V
CC
= 12 V
T
A
= 25C
T
A
, AMBIENT TEMPERATURE (C)
V
t
h
,

I
N
P
U
T

T
H
R
E
S
H
O
L
D

V
O
L
T
A
G
E

(
V
)
V
CC
= 12 V
Upper Threshold
Low State Output
Lower Threshold
High State Output
V
in
, INPUT OVERDRIVE VOLTAGE BELOW LOWER THRESHOLD (V)
t
P
L
H
(
I
N
/
O
U
T
)
,

D
R
I
V
E

O
U
T
P
U
T

P
R
O
P
A
G
A
T
I
O
N

D
E
L
A
Y

(
n
s
)
Overdrive Voltage is with Respect
to the Logic Input Lower Threshold
V
th(lower)
V
CC
= 12 V
C
L
= 1.0 nF
T
A
= 25C
V
in
, INPUT OVERDRIVE VOLTAGE ABOVE UPPER THRESHOLD (V)
t
P
H
L
(
I
N
/
O
U
T
)
,

D
R
I
V
E

O
U
T
P
U
T

P
R
O
P
A
G
A
T
I
O
N

D
E
L
A
Y

(
n
s
)
V
CC
= 12 V
C
L
= 1.0 nF
T
A
= 25C
V
th(upper)
Overdrive Voltage is with Respect
to the Logic Input Lower Threshold
+
+
+
-
6
5.7V
Logic Input
2
4
3
1
0
0
k
Drive Output
7
5
+
+
+
+
1
0
0
k
12
V
4.7 0.1
50 C
L
+
5.0 V
0 V
10%
90%
t
PHL
t
PLH
90%
10%
t
f
t
r
Logic Input
t
r
, t
f
10 ns
Drive Output
2.4
2.0
1.6
1.2
0.8
0.4
0
2.2
2.0
1.8
1.6
1.4
1.2
1.0
200
160
120
80
40
0
200
160
120
80
40
0
0 2.0 4.0 6.0 8.0 10 12 -55 -25 0 25 50 75 100 125
-1.6 -1.2 -0.8 -0.4 0 0 1.0 2.0 3.0 4.0
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V
CC
= 12 V
V
in
= 5 V to 0 V
C
L
= 1.0 nF
T
A
= 25C
Figure 8. Propagation Delay Figure 9. Drive Output Clamp Voltage
versus Clamp Current
Figure 10. Drive Output Saturation Voltage
versus Load Current
Figure 11. Drive Output Saturation Voltage
versus Temperature
Figure 12. Drive Output Rise Time Figure 13. Drive Output Fall Time
90%
10%
50 ns/DIV
90%
10%
10 ns/DIV
90%
10%
10 ns/DIV
I
O
, OUTPUT LOAD CURRENT (A)
V
c
l
a
m
p
,

O
U
T
P
U
T

C
L
A
M
P

V
O
L
T
A
G
E

(
V
)
High State Clamp
(Drive Output Driven Above V
CC
)
V
CC
GND
Low State Clamp
(Drive Output Driven Below Ground)
V
CC
= 12 V
80 ms Pulsed Load
120 Hz Rate
T
A
= 25C
I
O
, OUTPUT LOAD CURRENT (A)
V
s
a
t
,

O
U
T
P
U
T

S
A
T
U
R
A
T
I
O
N

V
O
L
T
A
G
E
(
V
)
Source Saturation
(Load to Ground)
V
CC
= 12 V
80 ms Pulsed Load
120 Hz Rate
T
A
= 25C
V
CC
Sink Saturation
(Load to V
CC
)
GND
T
A
, AMBIENT TEMPERATURE (C)
V
s
a
t
,

O
U
T
P
U
T

S
A
T
U
R
A
T
I
O
N

V
O
L
T
A
G
E
(
V
)
Source Saturation
(Load to Ground)
Sink Saturation
(Load to V
CC
)
V
CC
= 12 V
I
source
= 400 mA
I
sink
= 400 mA
V
CC
I
source
= 10 mA
I
sink
= 10 mA
GND
Drive Output
Logic Input
V
CC
= 12 V
V
in
= 5 V to 0 V
C
L
= 1.0 nF
T
A
= 25C
V
CC
= 12 V
V
in
= 5 V to 0 V
C
L
= 1.0 nF
T
A
= 25C
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 -55 -25 0 25 50 75 100 125
3.0
2.0
1.0
0
0
-1.0
0
-1.0
-2.0
-3.0
3.0
2.0
1.0
0
0
-0.5
-0.7
-0.9
-1.1
1.9
1.7
1.5
1.0
0.8
0.6
0
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Figure 14. Drive Output Rise and Fall Time
versus Load Capacitance
Figure 15. Supply Current versus Drive Output
Load Capacitance
Figure 16. Supply Current versus Input Frequency Figure 17. Supply Current versus Supply Voltage
C
L
, OUTPUT LOAD CAPACITANCE (nF)
-
t
,

O
U
T
P
U
T

R
I
S
E

F
A
L
L

T
I
M
E
(
n
s
)
t
f
t
r t
r
V
CC
= 12 V
V
IN
= 0 V to 5.0 V
T
A
= 25C
C
L
, OUTPUT LOAD CAPACITANCE (nF)
I
C
C
,

S
U
P
P
L
Y

C
U
R
R
E
N
T

(
m
A
)
V
CC
= 12 V
Both Logic Inputs Driven
0 V to 5.0 V
50% Duty Cycle
Both Drive Outputs Loaded
T
A
= 25C
f = 500 kHz
f = 200 kHz
f = 50 kHz
I
C
C
,

S
U
P
P
L
Y

C
U
R
R
E
N
T

(
m
A
)
1
2
3
4
Both Logic Inputs Driven
0 V to 5.0 V,
50% Duty Cycle
Both Drive Outputs Loaded
T
A
= 25C
1 - V
CC
= 18 V, C
L
= 2.5 nF
2 - V
CC
= 12 V, C
L
= 2.5 nF
3 - V
CC
= 18 V, C
L
= 1.0 nF
4 - V
CC
= 12 V, C
L
= 1.0 nF
f, INPUT FREQUENCY (Hz)
I
C
C
,

S
U
P
P
L
Y

C
U
R
R
E
N
T

(
m
A
)
V
CC
, SUPPLY VOLTAGE (V)
T
A
= 25C
Logic Inputs at V
CC
Low State Drive Outputs
Logic Inputs Grounded
High State Drive Outputs
f
80
60
40
20
0
80
60
40
20
0
80
60
40
20
0
8.0
6.0
4.0
2.0
0
0.1 1.0 10 0.1 1.0 10
100 1.0 M 0 4.0 8.0 12 16 10 k
APPLICATIONS INFORMATION
Description
The MC34151 is a dual inverting high speed driver
specifically designed to interface low current digital
circuitry with power MOSFETs. This device is constructed
with Schottky clamped Bipolar Analog technology which
offers a high degree of performance and ruggedness in
hostile industrial environments.
Input Stage
The Logic Inputs have 170 mV of hysteresis with the input
threshold centered at 1.67 V. The input thresholds are
insensitive to V
CC
making this device directly compatible
with CMOS and LSTTL logic families over its entire
operating voltage range. Input hysteresis provides fast
output switching that is independent of the input signal
transition time, preventing output oscillations as the input
thresholds are crossed. The inputs are designed to accept a
signal amplitude ranging from ground to V
CC
. This allows
the output of one channel to directly drive the input of a
second channel for masterslave operation. Each input has
a 30 kW pulldown resistor so that an unconnected open input
will cause the associated Drive Output to be in a known high
state.
Output Stage
Each totem pole Drive Output is capable of sourcing and
sinking up to 1.5 A with a typical on resistance of 2.4 W at
1.0 A. The low on resistance allows high output currents
to be attained at a lower V
CC
than with comparative CMOS
drivers. Each output has a 100 kW pulldown resistor to keep
the MOSFET gate low when V
CC
is less than 1.4 V. No over
current or thermal protection has been designed into the
device, so output shorting to V
CC
or ground must be
avoided.
Parasitic inductance in series with the load will cause the
driver outputs to ring above V
CC
during the turnon
transition, and below ground during the turnoff transition.
With CMOS drivers, this mode of operation can cause a
destructive output latchup condition. The MC34151 is
immune to output latchup. The Drive Outputs contain an
internal diode to V
CC
for clamping positive voltage
transients. When operating with V
CC
at 18 V, proper power
supply bypassing must be observed to prevent the output
ringing from exceeding the maximum 20 V device rating.
Negative output transients are clamped by the internal NPN
pullup transistor. Since full supply voltage is applied across
MC34151, MC33151
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7
the NPN pullup during the negative output transient, power
dissipation at high frequencies can become excessive.
Figures 20, 21, and 22 show a method of using external
Schottky diode clamps to reduce driver power dissipation.
Undervoltage Lockout
An undervoltage lockout with hysteresis prevents erratic
system operation at low supply voltages. The UVLO forces
the Drive Outputs into a low state as V
CC
rises from 1.4 V
to the 5.8 V upper threshold. The lower UVLO threshold is
5.3 V, yielding about 500 mV of hysteresis.
Power Dissipation
Circuit performance and long term reliability are
enhanced with reduced die temperature. Die temperature
increase is directly related to the power that the integrated
circuit must dissipate and the total thermal resistance from
the junction to ambient. The formula for calculating the
junction temperature with the package in free air is:
T
J
= T
A
+ P
D
(R
qJA
)
where: T
J
= Junction Temperature
T
A
= Ambient Temperature
P
D
= Power Dissipation
R
qJA

=
Thermal Resistance Junction to Ambient
There are three basic components that make up total
power to be dissipated when driving a capacitive load with
respect to ground. They are:
P
D

=
P
Q
+ P
C
+ P
T
where: P
Q
= Quiescent Power Dissipation
P
C
= Capacitive Load Power Dissipation
P
T
= Transition Power Dissipation
The quiescent power supply current depends on the
supply voltage and duty cycle as shown in Figure 17. The
devices quiescent power dissipation is:
P
Q
= V
CC
I
CCL
(1D) + I
CCH
(D)
where: I
CCL
= Supply Current with Low State Drive
Outputs
I
CCH
= Supply Current with High State Drive
Outputs
D = Output Duty Cycle
The capacitive load power dissipation is directly related
to the load capacitance value, frequency, and Drive Output
voltage swing. The capacitive load power dissipation per
driver is:
P
C
= V
CC
(V
OH
V
OL
) C
L
f
where: V
OH
= High State Drive Output Voltage
V
OL
= Low State Drive Output Voltage
C
L
= Load Capacitance
f = frequency
When driving a MOSFET, the calculation of capacitive
load power P
C
is somewhat complicated by the changing
gate to source capacitance C
GS
as the device switches. To aid
in this calculation, power MOSFET manufacturers provide
gate charge information on their data sheets. Figure 18
shows a curve of gate voltage versus gate charge for the ON
Semiconductor MTM15N50. Note that there are three
distinct slopes to the curve representing different input
capacitance values. To completely switch the MOSFET
on, the gate must be brought to 10 V with respect to the
source. The graph shows that a gate charge Q
g
of 110 nC is
required when operating the MOSFET with a drain to source
voltage V
DS
of 400 V.
V
G
S
,

G
A
T
E
-
T
O
-
S
O
U
R
C
E

V
O
L
T
A
G
E

(
V
)
Q
g
, GATE CHARGE (nC)
C
GS
=
D Q
g
16
12
8.0
4.0
0
0 40 80 120 160
V
DS
= 100 V V
DS
= 400 V
8.9 nF
2.0 nF
MTM15N50
I
D
= 15 A
T
A
= 25C
Figure 18. GateToSource Voltage
versus Gate Charge
D V
GS
The capacitive load power dissipation is directly related to
the required gate charge, and operating frequency. The
capacitive load power dissipation per driver is:
P
C(MOSFET)
= V
C
Q
g
f
The flat region from 10 nC to 55 nC is caused by the
draintogate Miller capacitance, occurring while the
MOSFET is in the linear region dissipating substantial
amounts of power. The high output current capability of the
MC34151 is able to quickly deliver the required gate charge
for fast power efficient MOSFET switching. By operating
the MC34151 at a higher V
CC
, additional charge can be
provided to bring the gate above 10 V. This will reduce the
on resistance of the MOSFET at the expense of higher
driver dissipation at a given operating frequency.
The transition power dissipation is due to extremely short
simultaneous conduction of internal circuit nodes when the
Drive Outputs change state. The transition power
dissipation per driver is approximately:
P
T
= V
CC
(1.08 V
CC
C
L
f 8 y 10
4
)
P
T
must be greater than zero.
Switching time characterization of the MC34151 is
performed with fixed capacitive loads. Figure 14 shows that
for small capacitance loads, the switching speed is limited
by transistor turnon/off time and the slew rate of the
internal nodes. For large capacitance loads, the switching
speed is limited by the maximum output current capability
of the integrated circuit.
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LAYOUT CONSIDERATIONS
High frequency printed circuit layout techniques are
imperative to prevent excessive output ringing and overshoot.
Do not attempt to construct the driver circuit on
wirewrap or plugin prototype boards. When driving
large capacitive loads, the printed circuit board must contain
a low inductance ground plane to minimize the voltage spikes
induced by the high ground ripple currents. All high current
loops should be kept as short as possible using heavy copper
runs to provide a low impedance high frequency path. For
optimum drive performance, it is recommended that the
initial circuit design contains dual power supply bypass
capacitors connected with short leads as close to the V
CC
pin
and ground as the layout will permit. Suggested capacitors are
a low inductance 0.1 mF ceramic in parallel with a 4.7 mF
tantalum. Additional bypass capacitors may be required
depending upon Drive Output loading and circuit layout.
Proper printed circuit board layout is extremely
critical and cannot be over emphasized.
The MC34151 greatly enhances the drive capabilities of common switching
regulators and CMOS/TTL logic devices.
Figure 19. Enhanced System Performance with
Common Switching Regulators
Figure 20. MOSFET Parasitic Oscillations
Figure 21. Direct Transformer Drive Figure 22. Isolated MOSFET Drive
Series gate resistor R
g
may be needed to damp high frequency parasitic
oscillations caused by the MOSFET input capacitance and any series
wiring inductance in the gate-source circuit. R
g
will decrease the
MOSFET switching speed. Schottky diode D
1
can reduce the driver's
power dissipation due to excessive ringing, by preventing the output pin
from being driven below ground.
Output Schottky diodes are recommended when driving inductive loads at
high frequencies. The diodes reduce the driver's power dissipation by
preventing the output pins from being driven above V
CC
and below ground.
+
-
V
CC
47 0.1
6
5.7V
TL494
or
TL594
2
4
3
1
0
0
k
1
0
0
k
7
5
V
in
+
+
+ +
+
+
1
0
0
k
1N5819
D
1
R
g
V
in
+
+
1
0
0
k
1
0
0
k
3
7
5
4 X
1N5819
+
+
+
+
3
1
0
0
k
1N
5819
Isolation
Boundary
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9
Output Load Regulation
I
O
(mA) +V
O
(V) V
O
(V)
0 27.7 13.3
1.0 27.4 12.9
10 26.4 11.9
20 25.5 11.2
30 24.6 10.5
50 22.6 9.4
Figure 23. Controlled MOSFET Drive Figure 24. Bipolar Transistor Drive
Figure 25. Dual Charge Pump Converter
The totem-pole outputs can furnish negative base current for enhanced
transistor turn-off, with the addition of capacitor C
1
.
The capacitor's equivalent series resistance limits the Drive Output Current
to 1.5 A. An additional series resistor may be required when using tantalum or
other low ESR capacitors.
In noise sensitive applications, both conducted and radiated EMI can
be reduced significantly by controlling the MOSFET's turn-on and
turn-off times.
+
1
0
0
k
V
in
R
g(on)
R
g(off)
+
I
B
+
0
-
Base Charge
Removal
1
0
0
k
C
1
V
in
+
-
V
CC
= 15 V
4.7 0.1
6
5.7V
6.8 10
7
1N5819
2
+ V
O
2.0 V
CC
47
1
0
0
k
1
0
0
k
5
6.8 10
1N5819
4
- V
O
- V
CC
330pF
47
3
10k
+
+
+
+
+
+
+
+
+
+
+
MC34151, MC33151
http://onsemi.com
10
ORDERING INFORMATION
Device Package Shipping

MC34151DG SOIC8
(PbFree)
98 Units / Rail
MC34151DR2G SOIC8
(PbFree)
2500 Tape & Reel
MC34151PG PDIP8
(PbFree)
50 Units / Rail
MC33151DG SOIC8
(PbFree)
98 Units / Rail
MC33151DR2G SOIC8
(PbFree)
2500 Tape & Reel
MC33151PG PDIP8
(PbFree)
50 Units / Rail
MC33151VDR2G SOIC8
(PbFree)
2500 Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
MC34151, MC33151
http://onsemi.com
11
PACKAGE DIMENSIONS
PDIP8
P SUFFIX
CASE 62605
ISSUE M
1 4
5 8
F
NOTE 5
D
e
b
L
A1
A
E3
E
A
TOP VIEW
C
SEATING
PLANE
0.010 C A
SIDE VIEW
END VIEW
END VIEW
NOTE 3
DIM MIN NOM MAX
INCHES
A 0.210
A1 0.015
b 0.014 0.018 0.022
C 0.008 0.010 0.014
D 0.355 0.365 0.400
D1 0.005
e 0.100 BSC
E 0.300 0.310 0.325
L 0.115 0.130 0.150
5.33
0.38
0.35 0.46 0.56
0.20 0.25 0.36
9.02 9.27 10.02
0.13
2.54 BSC
7.62 7.87 8.26
2.92 3.30 3.81
MIN NOM MAX
MILLIMETERS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSION E IS MEASURED WITH THE LEADS RE-
STRAINED PARALLEL AT WIDTH E2.
4. DIMENSION E1 DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
E1 0.240 0.250 0.280 6.10 6.35 7.11
E2
E3 0.430 10.92
0.300 BSC 7.62 BSC
E1
D1
M
8X
e/2
E2
c
MC34151, MC33151
http://onsemi.com
12
PACKAGE DIMENSIONS
SOIC8
D SUFFIX
CASE 75107
ISSUE AK
1.52
0.060
7.0
0.275
0.6
0.024
1.270
0.050
4.0
0.155

mm
inches

SCALE 6:1
*For additional information on our PbFree strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
SEATING
PLANE
1
4
5 8
N
J
X 45
_
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 75101 THRU 75106 ARE OBSOLETE. NEW
STANDARD IS 75107.
A
B S
D
H
C
0.10 (0.004)
DIM
A
MIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.053 0.069
D 0.33 0.51 0.013 0.020
G 1.27 BSC 0.050 BSC
H 0.10 0.25 0.004 0.010
J 0.19 0.25 0.007 0.010
K 0.40 1.27 0.016 0.050
M 0 8 0 8
N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244
X
Y
G
M Y M 0.25 (0.010)
Z
Y M 0.25 (0.010) Z S X S
M
_ _ _ _
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including Typicals must be validated for each customer application by customers technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
MC34151/D
PUBLICATION ORDERING INFORMATION
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For additional information, please contact your local
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