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Aether Tutorial
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VLSI Full Custom IC Design EDA Tools

TUTORIALS
SCHEMATIC SIMULATION IC LAYOUT VERIFICATION
(AETHER AEOLUS ARGUS)

Contents
1. Preface ...................................................................................................................................... 1
1.1 Introduction to Empyrean ............................................................................................. 1
1.2 Platform Requirements ................................................................................................. 1
1.3 Installation of software ................................................................................................. 1
1.4 Environment Setup........................................................................................................ 1
1.5 Starting the Aether Software ........................................................................................ 1
2. Design Manager ........................................................................................................................ 2
2.1 Setting PDK .................................................................................................................... 2
2.2 Setting paths to the PDK and ChargePump libraries ..................................................... 3
2.3 Creating a New Library .................................................................................................. 4
2.4 Introducing Common Commands ................................................................................. 5
3. Schematic Capture .................................................................................................................... 8
3.1 Creating a Schematic Cellview ...................................................................................... 8
3.2 Adding Instances to a Schematic ................................................................................... 9
3.3 Changing Object Properties ........................................................................................ 11
3.4 Creating Pins to a Schematic ....................................................................................... 12
3.5 Creating Wires to a Schematic .................................................................................... 13
3.6 Create Note Text/Shape .............................................................................................. 15
3.7 Saving a Design ............................................................................................................ 17
4. Symbol Creation ...................................................................................................................... 18
4.1 Creating a Symbol ....................................................................................................... 18
4.2 Editing and Saving a Symbol ........................................................................................ 19
5. Analog Simulation and Results Display ................................................................................... 21
5.1 Building the Test Design .............................................................................................. 21
5.2 Exporting the Netlist ................................................................................................... 22
5.3 Running Simulation ..................................................................................................... 24
5.4 Displaying Simulation Results ...................................................................................... 26
5.5 Optimizing of the Circuit ............................................................................................. 29
6. Layout Capture ........................................................................................................................ 32
6.1 Creating Full-Custom Layout Manually ....................................................................... 32
6.2 Creating Full-Custom Layout using Schematic Driven Layout (SDL) ............................ 33
6.3 Placing of the Layout ................................................................................................... 37
6.4 Routing of the Layout .................................................................................................. 45
7. Physical Verification ................................................................................................................ 53
7.1 DRC .............................................................................................................................. 53
7.2 LVS ............................................................................................................................... 54
8. Charge pump Design Flow....................................................................................................... 58
8.1 Making Specification ................................................................................................... 58
8.2 Adding basic logical gate circuit .................................................................................. 58
8.3 The Main Circuitof ChargePump ................................................................................. 64
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8.4 Completing the Design and Simulation of ChargePump ............................................. 67
8.5 Summarizing the Performance of Charge pump ......................................................... 73

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1. Preface
1.1 Introduction to Empyrean
The Empyrean is a set of software design tools used to set up, control, and run
circuit simulations. The Empyrean allows you to set design variables, select
model files, and to select analyses to add, modify, or delete from next
simulation run. The Empyrean provides a user-friendly graphical interface that
includes pull-down menus and icons for making fast and easy changes. The
Empyrean also provides control for accessing the simulation results and
displaying the results to the wave display tool Iwave. The results can be
entered into other tools for waveform processing or to obtain specific data
using expressions.
1.2 Platform Requirements
1.3 Installation of software
1.4 Environment Setup
Before start the software, you must source setup files setup.csh (or setup.
bash) of empyrean tools.
For environment of B shell:
%> source < install_dir>/empyrean/setup.bash
For environment of C shell:
%> source < install_dir>/empyrean/setup.csh
1.5 Starting the Aether Software
Ensure that you are in the tutorial directory. Start the Aether software from a
terminal window by typing the following command:
%>aether &
The Design Manager (DM) appears shown as in Figure 1-1
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Figure 1-1 Design Manager
Note: Empyrean uses the term library to mean both reference libraries, which
contain defined components for a specific technology, and design libraries, in
which you create your own designs. Reference libraries typically contain
well-characterized cells that can be instantiated in many different designs.
Examples are the analog, sheet and basic libraries. Design libraries contain
cells currently under development by a particular user, group, or for a
design project. Initially, the Library lists only the library names that are set in
lib.defs file which will be created in the first time you start Aether. This file in
tutorial directory contains the paths to the libraries used in the design session.


2. Design Manager
In this chapter, you will be performing the following tasks in the Design
Manager:
Setting Reference PDK
Setting the Paths to the 018um_PDK and ChargePump libraries
Creating a New Library
Introduction of Common Commands

2.1 Setting PDK
For the rest of the tutorial, you will design a ChargePump based on
018um_PDK. Please refer to the circuits in the library of ChargPump if you
meet any difficulties in you design.
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2.2 Setting paths to the PDK and ChargePump libraries
To set the paths for the 018um_PDK and ChargePump libraries, do the
following:
1. From the DESIGN MANAGER, choose Tools Library Path Editor. The
Library Path Editor form appears as shown in Figure 2-1:

Figure 2-1 Library Path Editor

2. In the Library Path Editor, choose EditAdd Library to add the names
and paths of the two libraries.

Figure 2-2 Add Library in Library Path Editor

3. Click OK.
The software automatically updates the Library list after adding the two
libraries as shown in Figure 2-3.
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Figure 2-3 Finished Add Library of Library Path Editor


Note: If the path displays in red or orange in the Library Path Editor form, that
indicates that the path is incorrect.
4. Click Save button in the Library Path Editor form.
The Library list in DESIGN MANAGER and the lib.defs file will be updated as
well.
2.3 Creating a New Library
To create a new library, do the following:
1. From the DESIGN MANAGER, choose File New Library or select icon
or right-click the library display space (shown in Figure 2-4) to display the
New Library form as shown in Figure 2-5.

Figure 2-4 Activate New Library command

2. In the New Library form, set the Library Name.
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3. Specify the In Directory field by selecting icon .
4. Select Attach To Library/Reference To Libraries/Load From File/Do Not
Need to set Technology. In this tutorial, you should select Attach To
Library 018um_PDK.

Note: The technology file is a large data file that specifies all of the
technology-dependent parameters associated with that particular library.
Design rules, symbolic device definitions, and parasitic values are some of the
technology-specific parameters common to all cells in a library.

5. Set Gds Layer Map and Display Resource.
6. Click OK.

Figure 2-5 New Library Form
2.4 Introducing Common Commands
1. Quick Searching of Library/Cell/View
In the Quick Searching fields in red box as shown in Figure 2-6, type the
characters. The Library/Cell/View Name which matches the search criteria will
be highlight by association searching.
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Figure 2-6 Quick Search
2. Copy Library/Cell/View
To copy Library/Cell/View, from the DESIGN MANAGER, choose Edit Copy
or select icon or right-click the Library/Cell/View name as shown inFigure
2-5.



3. Open Mode/Open /Open(Read-Only)
To choose the default open mode for your designs, select Icon (Editable) or
(Read-only).Right-click the Library/Cell/View name to change the mode
manually to Open or Open (Read-Only).
Figure 2-7 Copy Library/Cell/View Form
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Figure 2-8 Setting Open Mode & Open Status

4. Show/Hide Layout/Schematic/Symbol
To Reveal/hide objects in the view list, select icons in the top-right of toolbar as
shown in Figure 2-9. Select icon or to reveal/hide layouts, or to
reveal/hide schematics, or to reveal/hide symbols.

Figure 2-9 Setting Show/Hide View

Note: If you ever need a brief hint of what a button on the toolbar is used for,
just place the cursor over the button and a brief description will appear.





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3. Schematic Capture
In this chapter, you will be performing the following tasks:
Creating a Schematic cellview by Aether Schematic Editor (SE)
Creating Instances to a Schematic
Updating Design Objects
Creating Pins to a Schematic
Creating Wires to a Schematic
Create Note Text/Shape
Saving a Design
3.1 Creating a Schematic Cellview
To create a new schematic cell view, do the following:
1. From the DESIGN MANAGER, choose File New Cell/View or select
icon or right-click the library display space (shown in Figure 3-1) to
display the New Cell/View form as shown in Figure 3-2.

Figure 3-1 Activate New Cell/View command
2. Set up the Create New Cell/View form as follows:

Figure 3-2 New Cellview Form
3. Click OK when done. A blank schematic window for the cp_amp design
appears.
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Figure 3-3 Schematic Editor
3.2 Adding Instances to a Schematic
In the steps below, you will build the cp_amp schematic.
1. In the cp_amp schematic window, choose CreateInstance or select
icon or press bind key <I> to display the Create Instance form as shown
in Figure 3-4.
2. Click the Browse icon to open up a Library Browser from which you can
select components to place.
3. Set Library/Cell/View names to 018um_PDK/p18/symbol in the Browser
form.
4. Change the property values of p18 to Length=0.6u / Entry Switch=Finger
Width / Finger Width=8u / Fingers=4 / SD Metal Width=0.23u in the Create
Instance form. Then, move your cursor to the schematic window and click
left mouse button (LMB) to place a component.
5. After entering components, click Cancel in the Create Instance form or
press Esc with your cursor in the schematic window.

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Figure 3-4 Create Instance

You can also create instances by copy command follow the steps below.
1. Select PM1, choose Edit Copy or select icon or press bind key <C> to
active the command.
2. Move your cursor to the schematic window, and click <LMB> to place the
yellow new copy component.
3. You can press the F3 function key to display the Copy form as shown in
Figure 3-5. Click / / to set components R90/MX/MY.


Figure 3-5 Copy Form
If you place components in the wrong location, do the following:
1. Choose EditStretch/ Move or select icon / or press bind key
<M>/<shift+M> commands if you place components in the wrong location.
Then click <LMB>.
2. You might also need to rotate specific components after you place them in
the schematic. You can rotate components at the time you place them or
Move/Stretch them. Click the right button of mouse (RMB)/<shift+RMB > /
<ctrl+RMB> to set components R90/MX/MY.
Add other components to build the schematic as shown in Figure 3-6.You will
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update the Library Name, Cell Name, and the property values given in Table
3-1 as you place each component.
Table 3-1 Parameters of MOS components


Figure 3-6 Place MOS components

Note: Real-time Check of Aether highlights the floating pins in yellow that
indicates they are incorrect and will disappear after pins being connected.



3.3 Changing Object Properties
To change the Instances parameters, do the following:
1. If you place a component with the wrong property values, use the
EditProperty command or select icon or press bind key <Q> to
change the parameters.
2. You can either update single or multiple objects in a selected mode in the
Schematic Editor. You can select multiple objects by choose menu Select
or press bind key <Shift+A>.
Inst Name Cell Name Length Fingers Finger Width SD Metal Width
NM0 n18 2u 4 13u 0.23u
NM1,NM2 n18 0.6u 4 4u 0.23u
NM3,NM4 n18 4u 8 4u 0.23u
NM5 n18 2u 8 13u 0.23u
PM0,PM1 p18 0.6u 4 8u 0.23u
PM2 p18 0.6u 20 6u 0.23u
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3. Use the First, Next, Previous and Last buttons on the Edit Instance
Properties form as shown in Figure 3-7 to scroll through a set of selected
objects and update them. Only one object at a time will highlight in the
schematic window.
4. It is possible to modify most quantities that appear on the form. The most
common changes concern components property values are W, L and
Finger of MOS and pin names, and pin direction etc.


Figure 3-7 Set Property values
3.4 Creating Pins to a Schematic
Next, you will be performing creating pins tasks:
1. In the schematic window, choose Create Pin or select icon or press
bind key <P> to start the create pin form as shown in Figure 3-8.
2. Type the pin names in the Add Pin form. You can create multi pins by
typing <space> between them.
3. Pins have special pin Direction (input, output, switch or input/Output) as
shown in Figure 3-9.These should be consistent throughout your design.
Make sure the Direction field is set to Input for inn, inp, vbias, set to Output
for out and set to InputOutput for vdd, vss.
4. Create Wire automatically after you place pin in the schematic when turn
on the option Create Wire After Place.
5. Press <Esc> to cancel the create pin command.
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Figure 3-8 Create Pin Form


Figure 3-9 Pin directions

Note: You can always edit the properties of the pin if you make a mistake
when placing it.
3.5 Creating Wires to a Schematic
Create wires to connect components and pins in the design.
1. Choose Create Wire or select icon or press bind key <W> in the
schematic window.
2. Click on a pin as the first point for your wiring. A diamond shape appears
over the starting point of this wire. A small square appears on the pin
follows the cursor.
3. Move your cursor to the destination point for your wire and click <LMB> to
finish wiring.

You can create wires conveniently as the steps below:
1. When you move the cursor near the pin after activating Create Wire
command, a diamond appears over the pin.
2. Click <Shift+LMB>, the two pins which are covered by diamond are
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connected, as shown in Figure 3-10

Figure 3-10 Create Wire Conveniently

You can add meaningful net names to specific wires in the design or connect
Floating Wires. Choose Create->Wire Name or select icon or press bind key
<L> to start the Create wire name form, as shown in Figure 3-11.


Figure 3-11 Create Wire Name
Wire the instances together until your schematic looks as follows:
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Figure 3-12 Schematic cp_amp

3.6 Create Note Text/Shape
You can create Note Text/Shape to add meaningful information for both
schematic and layout engineers. For example, schematic engineer can tell
layout engineer to match NM2/NM by Note Text/Shape.
1. Choose Create Note Text or select icon or press bind key <T> in the
schematic window.
2. Create Note Text form appears as shown in Figure 3-13. You can set Note
Text to different types, such as For Physical Design and For Circuit
Design.

Figure 3-13 Create Note Test
3. Click <LMB> to place the Note Text.

To Create Note Shape, do the following:
1. Choose Create Note Shape to display the Create Note Shape form as
shown in Figure 3-14.
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2. Set the shape type, Line style and Draw Mode.



Figure 3-14 Create Note Shape Form
3. You can select icon to active Shape Line / Rectangle /
Polygon / Circle / Ellipse / Arc command.
4. Click <LMB> to place the Note Shape.

Now your schematic looks as follows:

Figure 3-15 Added Note Text/Shape

Choose Verify-> Show Note Text, you can verify Note Text by typing key
words in Search Key field as shown in Figure 3-16.
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Figure 3-16 Show Note Text Form
3.7 Saving a Design
Up to this point, you have created a drawing of the schematic. Now, do
Electrical Rules Check (ERC) and save the design and connectivity
information in the system database.

Choose Check command to do ERC, do the following:
1. Choose VerifyCheck or select icon .
2. Check Report form appears to allow your viewing the result of check.
3. Choose Verify->Find Marker to locate the position of errors.

Choose Check and Save command to do ERC, do the following:
1. Choose FileCheck and Save or select icon or press bind key <
Shift+X > in the schematic window.
2. Check&Save Report form appears to allow your viewing the result.
3. Choose Verify->Find Marker to locate the position of errors.

Note: Choose Create->No ERC or select icon to add No ERC component
to the nets which have to float, thus Floating Net error will be ignored by ERC.

Once you have established electrical connectivity with the Check and Save
command, you can use the design as input to other tools, such as a simulator.


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4. Symbol Creation
In this chapter, you will be performing the following tasks:
Creating a Symbol view by Aether Schematic Editor (SE)
Editing and Saving a Symbol
4.1 Creating a Symbol
To use a cp_amp as an element in other designs, you now create a symbol cell
view for cp_amp. There are two ways to create symbol:
Mode 1: From the DESIGN MANAGER, choose File New Cell/View or
select icon or right-click the library display space to create a
symbol.
Mode 2: In the Schematic Editor, choose CreateSymbol View to create a
symbol. Symbol is automatic ally created, based on the symbols
primary input and output pins.
The second way to create a symbol is more convenient, as shown below:
1. In the Schematic Editor window, choose Create->Symbol View, the
Symbol view form appears as shown in Figure 4-1.

Figure 4-1 Create Symbol View Form
2. Verify that From View Name field is set to schematic, and To View Name
field is set to symbol. By default, pins are placed at the left side of the
symbol if their directions are input, at the right side of the symbol if their
directions are output, and on top of the symbol if their directions are
InputOutput.
3. Click OK when done. A new window displays an automatically created
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symbol as shown in Figure 4-2.

Figure 4-2 cp_amp symbol view
4.2 Editing and Saving a Symbol
In the steps below, you will modify your cp_amp symbol to look like more
intuitive than the one that was automatically created.
1. Move your cursor over the symbol, until the entire green rectangle is
highlighted (selected). Click LMB to select it.
2. Choose EditDelete or select icon or press bind key <Del> to delete
the objects.
3. Choose Create Polygon/Line or select icon / or press bind key
<Shift+P>/<Shift+L>. Follow the prompts at the bottom of the schematic,
draw the triangle shown in the final picture. The bind key <u> will undo the
entire shape if you make a mistake. The commands Undo /Redo
Stretch Move may help you to edit the symbol if you ever need.
4. Choose CreateLabel or select iconor press bind key <Ctrl+L>, the
Create Label form appears as shown in Figure 4-3. You can add
[@instanceName]/ [@cellName] to any cell view.

Figure 4-3 Create Label form
5. Select CreateSelection Box, the Create Selection Box form appears as
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shown in Figure 4-4.
6. Click Automatic to draw a new red selection box automatically. The
selection box defines the symbols selectable region after it is placed in
another cellview.

Figure 4-4 Create Selction Box
7. Select Check/Check and Save in the symbol editor window to save your
edited symbol view to disk. Figure 4-5 shows the final Symbol View of
cp_amp.

Figure 4-5 Symbol View after Editing
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5. Analog Simulation and Results Display
In this chapter, you will be performing the following tasks:
Building the Test Design
Running Simulation with Aeolus in two ways
Displaying Simulation Results with Iwave
5.1 Building the Test Design
Now, you will build the test design cp_amp_tb cellview which will contain an
instance of the cp_amp and supply sources from Aether Schematic Editor.
1. Create design/cp_amp_tb/schematic by Create Cell/View commands.
2. Update the property values given in the Table 5-1as you place each
Instance.
3. Create pins, wires and net names.
Figure 5-1 shows the final schematic of a voltage follower.
Check your design for errors and Save the design and connectivity information
in the system database using the Check and Save command.
The string cp_amp in the table is variable of DC voltage.
Instance
Name
Library Name Cell Name Property Values
I__0 reference_lib cp_amp
V1 analog vsin
DC=vout_cp, ACMAG=1, ACPHASE=0,
V0=vout_cp, VA=10m, FREQ=10M,
TD=0, THETA=0, PHASE=0
V2 analog vdc DC=1.8
V3 analog vdc DC=0.55
I1 basic gnd
Table 5-1 Property Values of cp_amp_tb
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Figure 5-1 Schematic of cp_amp_tb for Test
5.2 Exporting the Netlist
You may want to use analog circuit design environment to create a netlist but
run the simulator in standalone mode or you may want to modify the netlist,
perhaps to take advantage of features that the design environment interface to
your simulator does not support or you may want to read the netlist before
starting the simulation, you may generate and export a netlist first. There are
three ways to generate and export the netlist:
Mode 1: In the Schematic Editor, choose FileExport Netlist to export the
netlist. The netlist contains component information but no simulation
control data.
Mode 2: From the DESIGN MANAGER, choose FileExportNetlist to
export the netlist. The netlist contains component information but no
simulation control data.
Mode 3: In the Schematic Editor, choose ToolsMDESimulation to start the
Mixed-signal Design Environment, and then export the netlist. The
output file contains both the netlist and the simulator control
information required.

First, introduce mode1:
1. In the Schematic Editor, choose FileExport Netlist to display the Export
Netlist form as shown in Figure 5-2.
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Figure 5-2 Export Netlist Form

2. In the Export Netlist form, note General/Format/HDL/CDL/SPICE tabs:
Set different types of netlist in HDL/CDL/SPICE tabs;
Set the format of a netlist in Format tabs;
Set Simulate Type, Output File, View Name List and so on in General tabs.
3. Click OK to generate and export a netlist.

Second, introduce mode 2:
1. From the DESIGN MANAGER, choose FileExportNetlist to display the
Export Netlist form as shown in Figure 5-2.
2. Set tabs.
3. Click OK.

Last, introduce mode 3:
1. In the Schematic Editor, choose ToolsMDESimulation to start the
Mixed-signal Design Environment as shown in Figure 5-3.
2. In the MDE window, set Model File, types of Analysis, values of
Parameters, and Simulation Data.
3. After setting up simulation, choose SimulationNetlistCreate to
generate and export a netlist.
4. Choose SimulationNetlistDisplay, a vi form appears to allow your
viewing the resulted netlist.
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Figure 5-3 Mixed-signal Design Environment From
5.3 Running Simulation
Up to this point, you have generated and exported a netlist. Next, you will run
simulations based on the cp_amp_tb design. There are two ways to run
simulation, one is running simulation by command lines, and the other is
running simulation in MDE window.

To run simulation by typing command lines, do the followings:

1. Open the netlist which has been generated and exported in DE/SE form by
Text Editor.
2. Edit the netlist: Adding model and corner commands, such as
.LIB ./models/model.lib tt or .LIB ./models/model.lib res_tt; Adding
simulation control commands, such as
*Simulation Control
.param vout_cp=0.9
.tran 1n 10u
.print v(*) i(*)
.option post probe
3. Save and quit the netlist editing form.
4. In the terminal, run Simulation with Aeolus by typing the following
command:
%>aeolus cp_amp_td.netlist
5. After simulation, the result files are saved in the current directory. The
wave file of the cp_amp_tb is called cp_amp_tb.netlist.tr0.

To run simulation in MDE window, do the followings:
1. In the Schematic Editor, choose ToolsMDESimulation to start the
Mixed-signal Design Environment as shown in Figure 5-4.
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Figure 5-4 Mixed-signal Design Environment Form

2. In the MDE window, choose SetupModel LibraryAdd Model Library or
select icon to start the Select Model Files form, in which you set the
Model File.
3. Choose AnalysisChoose Analysis or select icon , Setup Analysis form
appears, in which you set Simulate Types, such as Tran/DC/AC/OP/Noise
etc.
4. Choose SetupParametersAdd Parameter or select icon , set values
of parameters.
5. Choose SetupOutputsSelect Form Schematic/Add All Current/Add All
Voltage to configure Simulation Data to be saved.
a) (Optional)Choose Select Form Schematic, and then select the nodes
to plot with clicking LMB in the Schematic Editor, the Pins/Nets
selected will be adding to the Outputs form, as shown in Figure 5-5.

Figure 5-5 Select From Schematic

b) (Optional)Choose Add All Current/Add All Voltage, you can add
Currents/Voltages of all the Pins/Nets to the Outputs form, as shown in
Figure 5-6.
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Figure 5-6 Add All Current/Add All Voltage
6. Choose SimulationRun/Netlist and Run or select icon / to start the
simulation.
7. After simulation, the result files and log file are saved in the current
directory. The wave file of the cp_amp_tb is called cp_amp_tb.netlist.tr0.
5.4 Displaying Simulation Results
The common way to view or display simulation results is to plot the results.
Iwave provides a lot of information in a fast visual format. There are two ways
to display simulation results in Iwave, one is starting by command lines, and
the other is starting in MDE window.

To display simulation results in Iwave by command lines, do the followings:
1. Start the Iwave from a terminal window by typing the following command:

%>iwave or %>iwave wavefile <wave_file>

2. In the Iwave window, choose FileOpen or select icon or press bind
key <Ctrl+O> to display the Open File form in which one or more wave files
can be displayed as shown in Figure 5-7.

Figure 5-7 Iwave window
3. In Signal Manager Panel of Iwave window, wave files and their directories
are listed in Files region; the output signals which can be plotted are listed
in Signal region. To display the signals by double-clicking them with LMB.

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To display simulation results in Iwave in MDE window, do the followings:
1. In the Iwave window, choose SimulationRun/Netlist And Run or select
icon / to start the simulation.
2. When the simulation is done, Iwave form appears automatically, in which
signals in the outputs list can be displayed as shown in Figure 5-8.

Figure 5-8 Iwave Form
3. In the MDE window, choose ResultsCross Probe, Iwave window
appears, too. Choose FileOpen or select icon or press bind key
<Ctrl+O> to display specified wave files.

In addition, certain measurements can be performed in Iwave window.
1. Choose ViewZoom In X/Y/Area, Zoom Out X/Y or select icon
/ / / or press bind key <H>/<V>/<Z>/<Shift+Z> to zoom in/out
waves.
2. Choose EditStack/Unstack or press bind key <S>/<Shift+S> to
Stack/Unstack display.
3. Choose ToolsMeasure Tool or press bind key <F10> to start Measure
Tool as shown in Figure 5-9.
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Figure 5-9 Measure Tool Form
4. Choose CursorAdd X-cursor/Y-cursor or Remove Cursor/All Cursor to
display the cursor for measurement.
5. Choose ToolsCalculator to start the form which allows you to manipulate
and analyze simulation data as shown below.

Figure 5-10 Calculator Form

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5.5 Optimizing of the Circuit
To improve the performance of the cp_amp, you may optimize the circuit and
change the schematic and symbol, do the followings:
1. Open design/cp_amp/schematic,
2. Add components NM6 / NM7/ NM8 / NM9 / NM10 / PM3 /I__0/I__1 to the
schematic refer to Table 5-2.
Instance Name Cell Name Length Fingers
Finger
Width
SD Metal
Width
NM0 n18 2u 4 13u 0.23u
NM1,NM2 n18 0.6u 4 4u 0.23u
NM3,NM4 n18 4u 8 4u 0.23u
NM5 n18 2u 8 13u 0.23u
PM0,PM1 p18 0.6u 4 8u 0.23u
PM2 p18 0.6u 20 6u 0.23u
NM6,NM7 n18 0.18u 2 2u 0.23u
NM8 n18 2u 8 13u 0.23u
NM9NM10 n18 4u 3 4u 0.5u
PM3 p18 0.2u 1 0.23u 0.23u
I__0,I__1 cp_inv
Table 5-2 Parameters of the optimized circuit

When signal of ctl is active, NM0,NM7 and NM8 result in a doubling of DC
current of the second stage of op-amp. NM9 and NM10 perform as power
filtering.
Adding Instances and sub-circuits to the Schematic as shown in Figure 5-11,
then add Pin/Wire, do the followings:
1. Add p18 symbol/n18 symbol from library of 018um_PDK by command of
Create Instance;
2. Add cp_inv/symbol from library of ChargePump;
3. Create pins / wires by commands of Create Pin / Create Wire.
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Figure 5-11 The optimized schematic of cp_amp

To update the cp_amp/symbol duo to the adding of ctl Pin in the schematic,
select EditMoreUpdate Symbol View. The new symbol is as shown in
Figure 5-12.

Figure 5-12 Updated Symbol View
Schematic of cp_amp_tb for Test is update as shown in Figure 5-13.

Figure 5-13 Test Bench
Now, you will simulate the updated circuit similar to the procedure described in
the former section 5.3, and then view the simulation results in Iwave as shown
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in the figure below.

Figure 5-14 Simulation Results
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6. Layout Capture
In this chapter, you will be performing the following tasks:
Generate the layout manually
Generate the layout using Aether SDL in Layout Editor
Place & Route of the layout
6.1 Creating Full-Custom Layout Manually
After updating the Schematic and Symbol, you will create the layout of the
circuit. The first approach to create layout is by adding each elements with
commands manually, as shown below:

1. From the DESIGN MANAGER, choose File New Cell/View or select
icon or right-click the library display space to display the New Cell/View
form, make sure that set both View Name and View Type to Layout in the
New Cell/View window.
2. Click OK when done. A blank layout window for the cp_amp design
appears as shown in Figure 6-1.

Figure 6-1 Layout Editor Form

In the steps below, you will add all the elements to the layout, take PM0&PM1
for example, do the following:
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1. In the cp_amp layout window, choose CreateInstance or select icon
or press bind key <I> to display the Create Instance form.
2. Type manually or Click the Browse icon to open up a Library Browser
from which you can select components to place. Set Library/Cell/View
names to 018um_PDK/p18/layout in the form.
3. Change the property values of p18 to Length=0.6u / Entry Switch=Finger
Width / Finger Width=8u / Fingers=4 / SD Metal Width=0.23u in the Create
Instance form. Click / / or bind key to <RMB>/ <Shift+RMB> /
<Ctrl+RMB> set components R90/MX/MY.
4. Then, move your cursor to the schematic window and click left mouse
button (LMB) to place a component as shown in Figure 6-2. After entering
components, click Cancel in the Create Instance form or press Esc with
your cursor in the schematic window.

Figure 6-2 Create Instance in LE
Create PM1using command Copy because the parameters between PM0 &
PM1are same, do the following:
1. Choose Edit Copy or select icon or press bind key <C> to active the
command.
2. Move your cursor to the schematic window, and click <LMB> to place the
yellow new copy component.
3. You can press the F3 function key to display the Copy form. Click / /
to set components R90/MX/MY.
6.2 Creating Full-Custom Layout using Schematic Driven
Layout (SDL)
Aether lets you generate Full-custom layouts from schematics automatically by
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Schematic Driven Layout (SDL). It lets you both speed up and customize the
layout process. There are two ways to use SDL:
Mode 1: From the Schematic Editor, choose SDLStart SD.
Mode 2: From the Schematic Editor, choose SDLGenerate Hierarchy

Generate Hierarchy is used for the complex circuits which usually is performed
hierarchically. In this tutorial, you will focus on the function of SDLStart SDL
to generate full-custom layouts.
To start SDL, do the following:
1. From the DESIGN MANAGER, choose File Open Cell/View to open the
schematic in design / cp_amp which has been created.
2. In the Schematic Editor, choose VerifyCheck/Check Hierarchy to do
ERC check and make sure the electrical connections in the Schematic are
correct.
3. In the Schematic Editor, choose SDLStart SDL, the Select Layout form
appears; in this form, click the Browse icon to open up a Library Browser
from which you can select the Library/Cell/View of the layout as shown in
Figure 6-3.

Figure 6-3 Select Layout form

4. Click OK when done, the Layout form of cp_amp appears as shown in
Figure 6-4.
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Figure 6-4 cp_amp Layout Editor

5. In the design area of the layout, a large yellow rectangle, which describes
the boundary for placement and routing, and several small purple
rectangles called the Soft Pins. The SDL panel on the left side of design
windows contains Nets and Devices list and Schematic Worldview.

To obtain an initial placement with the instances and pins, do the followings:
1. In the SDL view, select all the components in the schematic Worldview
window using the Select command or shortcut;
2. Choose SDL Generate Devices or press bind key <G> after selecting
the subjects, and then, move your cursor to the layout editing window and
click left mouse button (LMB) to place the components as shown in Figure
6-5.
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Figure 6-5 Cp_Amp Layout Editor after Generate Devices

Note: The typeface of Nets and Devices list in SDL panel is traditional black
when the Nets and Devices are not generated in the LE as shown in Figure 6-4;
however it turns to green italics when the Nets and Devices have been
generated as shown in Figure 6-5.

The function of Cross Probing continuously monitors connections of
components in the layout and compares them with connections in the
schematic.
1. Select PM0&PM1 in the Devices list can highlight them both in layout
window and schematic window as shown in Figure 6-6.
2. From the DESIGN MANAGER, choose File Open Cell/View to open the
schematic in design / cp_amp which has been created. Select any
components in the devices list or layout window or schematic window, the
corresponding components in the other windows will be highlighted, in
other words, they are cross probing.
3. To view the contents of the components, press bind key < Shift+f >; To
view only the bounding boxes again, press bind key < Ctrl+f >
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Figure 6-6 Cross Probing of Schematic and Layout

6.3 Placing of the Layout
Up to this point, you have generated devices and put them in the layout. Next,
you will place those components using commands such as Devices Matching,
Devices Fold/Unfold, Align and Move etc.

From the schematic of cp_amp, the device groups of PM0 & PM1 and NM1 &
NM2 should be matching to improve the performance of the circuit. Take PM0
& PM1 for example:
1. Make sure to define parameters through Cell Mapping before completing
Devices Matching. From the DESIGN MANAGER, choose Tools Cell
Mapping->parameter mapping. The Cell Mapping form appears. Set the
fields of Parameter Name and Mapping Name as shown in Figure 6-7.
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Figure 6-7 Cell Maping
2. Then click Save to restore the change.
3. Choose SDLDevices Matching after select PM0&PM1, Devices
Matching form appears as shown in Figure 6-8.

Figure 6-8 Devices Matching Form
4. In the Devices Matching window, set the Fold Number to 4, then, there are
6 Matching form in the Matching Patterns region. Choose the type of
ABBA/BAAB, set X and Y space by X Space and Y Space. Select Shared
S&D on, the source and drain of a MOS will be connected. Select Add
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Dummy on, the devices will be added with dummy to improve the
performance of the circuit.
5. Click OK when done. The matching PM0 & PM1 is shown in Figure
6-9Figure 6-9.

Figure 6-9 PM0&PM1 after Matching
To meet the demand of layout placing, you may Fold/Unfold the devices. Take
PM3 as an example:
1. Choose SDL Device Fold after selecting PM3, Device Fold form
appears as shown in Figure 6-10.

Figure 6-10 Device Fold
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2. Set Desired Number of Segment to 10, turn Split Mode on.
3. PM2 is changed to 10 components named PM2_0~ PM2_9 which is
convenient for placing after clicking OK, as shown in Figure 6-11.

Figure 6-11 Split of PM2
4. Observe the change of PM2 after choosing SDL Device Fold.
5. Finally, change the parameters back as shown in Table 5-2 Parameters of the
optimized circuit
6. .

Next, complete the placing of the layout using commands Align/Move/Stretch.
Note that sharing the source and drain of the matching component PM0&PM1
may take less area.
1. Choose SDL Ungroup Device after selecting PM0&PM1 to ungroup
them.
2. Choose Edit Align or select icon or press bind key <A> to active the
command.
3. Click F3, the option window appears as shown in Figure 6-12. Turn the
Spacing on to set the space between the reference point or line and the
adjusted point or line. Snap Mode is to set the types of moving the point or
line.

Figure 6-12 Align F3 Form
4. Select the object need to be moved, and a green box or circle will indicate
the original object or point, as shown in Figure 6-13.
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Figure 6-13 Align
5. Select the reference object which may be a point, a line or a whole
component. Take a line as a reference here as shown in Figure 6-13, it is a
white line.
6. Repeat the above operations. The final placing of PM0&PM1 is as shown
in Figure 6-14.

Figure 6-14 PM0&PM1 after Align
7. Select <Shift+LMB>,and then you can select multipoint, lines or
components to align.

Adjust the place of components by commands Move/Stretch.

1. Choose EditStretch/ Move or select icon / or press bind key
<M>/<shift+M> commands if you place components in the wrong location.
Then click <LMB>.
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2. Click F3, the option window appears.
3. Click the right button of mouse (RMB)/<shift+RMB > / <ctrl+RMB> to set
components R90/MX/MY.

Connect the gate of MOS automatically with the help of PDK may accelerate
the work schedule. Take PM0&PM1 as an example:
1. Press the bind key <Q> you are able to modify the properties after
selecting the two MOS in LE.
2. Click First, Next, Previous and Last to change the highlight of the selecting
components.
3. Change the property of Gate Connection from None to Top/Bottom
(Please refer to Table 6-2) in Edit Instance Properties window, and then
click OK.
4. Share drains of PM0&PM1 by command Align as shown in Figure 6-15.

Figure 6-16 Gate Connection of PM0&PM1
5. Repeat the above operations. Change the properties of all the components
refer to Table 6-1.
6. Instance Name Gate Connection SD Switch
NM0 Bottom
NM1_2/NM1_3/
NM2_2/ NM2_3
Top
None/ None /
Switch / Switch
NM1_0/ NM1_1/
NM2_0/ NM2_1
Bottom
None/ None /
Switch / Switch
NM3 Bottom
NM4 Top
NM5 Top
PM0_2/PM0_3/
PM1_2/ PM1_3
Bottom
Switch / Switch /
None / None
PM0_0/ PM0_1/
PM1_0/ PM1_1
Top
Switch / Switch /
None / None
PM2 Bottom
NM6 Top
NM7 Top
NM8 Top
NM9 Top
NM10 Bottom
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PM3 Bottom
I__0
I__1
Table 6-1 Gate Connection
Please refer to Table 6-2 about the direction and coordinate of components.
Instance Name Rotate Origin
NM0 R90 (31,28.195)
NM1_2/NM1_3/
NM2_2/ NM2_3
MY/ R0/
MY / R0/
(12.52,33.93)/(14.38,33.93)/
(13.66,33.93)/(13.24,33.93)/
NM1_0/ NM1_1/
NM2_0/ NM2_1
R0/MY/
R0/ MY/
(12.1,29.09)/(14.8,29.09)/
(10.96,29.09)/(15.94,29.09)/
NM3 R0 (3.46,21.885)
NM4 R0 (3.46,16.585)
NM5 R0 (3.46,1.17)
PM0_2/PM0_3/
PM1_2/ PM1_3
R180/ MX /
R180/ MX /
(6.28,36.345)/(5.86,36.345)/
(5.14,36.345)/(7,36.345)/
PM0_0/ PM0_1/
PM1_0/ PM1_1
MX/ R180/
MX / R180/
(3.58,44.965)/(8.56,44.965)/
(4.72,44.965)/(7.42,44.965)/
PM2 R0 (10.52,41.605)
NM6 R270 (33.32,30.865)
NM7 R270 (33.29,32.845)
NM8 R0 (23.78,1.17)
NM9 R270 (37.86,43.995)
NM10 R270 (42.95,43.995)
PM3 R90 (35.97,46.395)
I__0 R90 (42.14,45.135)
I__1 R90 (42.14,46.445)
Table 6-2 coordinate of components
Finally, the placing of layout is as shown in Figure 6-17
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Figure 6-17 layout placement

ECO Check will check the discrepancies between schematic and layout.
1. Choose SDL ECO Checker, Device checker window appears as shown
in Figure 6-18. Turn Hierarchical ECO Checker on to view the Hierarchical
ECO check message.
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Figure 6-18 ECO Checker
2. Click Cancel to close this window.
6.4 Routing of the Layout
Up to this point, you have completed the placing of devices. Next, you will
route them. Creating guardring is a good step to start. Guardring is usually
used for preventing noise and prevent Latch-up effect. To create a guard ring,
define guardring rules in Technology Manager first.

Note: The TF rule should be defined and the layout engineer will not be
allowed to change it. Creating the following rules is only for a good
understanding of this function.

1. Select ToolsTechnology Manager, a window appears as shown in
Figure 6-19.
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Figure 6-19 Technology Manager
2. Type NWGR in Guardring Rule Name area. Set layer Definition as shown
above. Make sure Contact and Metal layer are Choppable which means
only chop contact layer and Metal1 layer when doing chop command.
3. Set other Rule Definition areas shown in Figure 6-20

Figure 6-20 Rule Definition
4. When you change the rule sets, click SAVE or Select FileDump
Technology File to save the new rule files.
5. Select CreateGuard Ring in LE, Create Guard Ring window appears as
shown in Figure 6-21, set Guardring Template to NWGR,Type to Line
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Figure 6-21 Create Guardring NWGR
6. Click coordinates (2.85,36.655) (2.85,45.725)(9.29,45.725) (9.29,27.585)
(2.85,27.585) with LMB in LE, and then double-click (2.85,36.655) to
create the GuardRing of PM0&PM1.

To create the Guardring of NM1&NM automatically, do the following:
1. Create a new rule called PGR as shown below:

Figure 6-22 PGR Rule
2. Select CreateGuard Ring in LE, set Guardring Template to PGR, Type
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to Auto, Boundary Spacing to 0.14, select Rectangular and click Generate!
3. Resize the Guard Ring for routing. Finally, the coordinate of NM1&NM2
are (10.23,33.51) (10.23,27.465) (16.67,27.465) (16.67,39.555)
(10.23,39.555) and (10.23,33.51).

Aether SE can show so-called flight lines for the nets in the layout which are
not yet connected. The flight lines connect the pins that belong to the same net,
and flight lines that belong to the same net have the same color as shown in
Figure 6-23 . Take PM0&PM1 for an example:
1. In the SDL panel, press F to show or hide the flyline.

Figure 6-23 Display of Flylines

From the schematic, PM0&PM1 act as Active Load, so connect the drain of
PM1 and the gates of PM0&PM1, and do the following:
1. Show the LSW panel, and select layer M1 dg;
2. Choose Create Path or select icon or press bind key <P> to active the
command.
3. Press F3 to open the option window as shown in Figure 6-23, make sure to
turn Toggle Button of Auto Detect Edge and With Same Layer on. Auto
Detect Edge is used to automatically detecting the width of Metal and
making the new path maintains the same width. With Same Layer is used
to avoiding generating the path of wrong layers.
4. In the option window, type the Width and Width step of the path. Press <
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[ > or < ] > to decrease or increase the width of the path according to the
step setting in Width step when creating path.
5. Set the end type, Snap Mode, justification and so on after click the
Pull-down Menu More Option.

Figure 6-24 Option Form of Create Path
6. The edge of the drain of PM1_0is highlight when the cursor is nearby, click
<LMB> to create path with Metal1 to connect the drain of PM1_2, the gates
of PM0&PM1 and the drain of PM1_3 , as shown in Figure 6-25:

Figure 6-25 Create Path
7. Double-click <LMB> to finish creating Path.
8. Using the above methods to connect the shared drains of PM1_0& PM1_1
and connect the sources of PM0&PM1 to guardring with Metal1.

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Next, connect the drain of PM0. Metal1 has been used for connecting Gates,
so Metal2 will be used for connecting the drain of PM0. Therefore, add Via
M2_M1 to the drains of PM0_0 , PM0_1 ,PM0_2 and PM0_3 first, do the
following:

1. From the LE, Choose Create Via or select icon or press bind key
<Shift+V>, the Create Via form appears as shown in Figure 6-26.

Figure 6-26 Edit Via Properties Form
2. Set Via Definition to M2_M1Rows to 2Columns to 1 and Width/Hight/X
Spacing/Y Spacing to 0.26m.
3. Click OK. The Via is generated as shown in Figure 6-27.

Figure 6-27 Via M2_M1
The next, connect those three via by Metal 2/ Metal 3, do the following:
1. Create path using Metal 2 by command of Create Path.
2. Press bind key <+>/<-> to change layer of the path. Connect the shared
drains of PM0_2 and PM0_3 to Metal3 with Via M3_M2, set the
Rows/Columns to 2 of the Via. Now, the layout is as shown in Figure 6-28.
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Figure 6-28 Connect the Drain of PM0
The followings are to connect the drain of PM1 outside of Guardring for the
routing next.
1. Create a path with Metal3 with width 0.9m, shown in Figure 6-29

Figure 6-29 Connect the Drain of PM1
2. Create Vias in the red boxes in Figure 6-29 for connecting Meta1 and
Metal3, turn Auto Mode on after choosing Create Via. Click the overlapping
area of M1 and M3, a option form appears as shown in Figure 6-30.
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Figure 6-30 Create Via
3. Set the Bottom LayertoM1 dg and Top Layer to M3 dg, click Generate, via
will generate automatically which is from Meta1 to Metal3.

Repeat the operations as shown above, complete the routing of the layout, and
the final layout is as shown in Figure 6-31.

Figure 6-31 Layout after Routing
The final step to complete the layout is to change the soft pins from SDL to the
true hard pin. The soft pin is only used to indicate the electrical connection.
1. Choose SDLGenerate Hard Pin and set Pin Name Height to 1 in the
form.
2. Click OK. The pins will automatically generate to the responding metal.
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7. Physical Verification
In this chapter, you will be performing the following tasks with Argus which is
the physical verification product of Huada Empyrean software Co., Ltd:
Do ERC check of the layout
Do LVS check of the layout
Back annotate the results
7.1 DRC
Layout must be drawn according to strict design rules. After you have finished
your layout, an automatic program will check each and every polygon in your
design against these design rules and report violations. This process is called
Design Rule Checking (DRC) and MUST be done for every layout to ensure it
will function properly when fabricated.
To do DRC with Argus, do the following:
1. From Layout Editor, choose VerifyArgusRun Argus DRC, the Argus
Interactive DRC form appears as shown in Figure 7-1.
2. Toggle the Tap of Rules, specify a path to run Argus. The default path is
the directory you invoke the Argus Interactive. If you want, you can click
the Browse button, and select the run directory. Then define the rules
format and specify the rule file from the Browse Button to find the file
called drc.rule in verification folder.

Figure 7-1 Setting Rules Tap of Argus DRC
3. Toggle the Tap of Inputs, set the layout format to GDSII and turn Export
from layout viewer on, keep other settings and then click Run DRC.
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Figure 7-2 Setting Inputs Tap of Argus DRC
4. Back annotate tool PVE form and drc.sum file will pop up after finishing
DRC as shown below. Click on the First error and window will zoom in to
the errors or warnings as desired. You can search for and highlight same
type errors by using .

Figure 7-3 Back Annotation with Arugs PVE
5. You may then proceed to correct the errors according to the design rules
until only density errors left which may be ignored but for final layout.
7.2 LVS
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Once the layout fulfills all the design rules, the next verification step follows.
The netlist behind the layout view is extracted and compared to that of the
schematic view. Do the Layout Versus Schematic (LVS) Check as following:
1. From Layout Editor, choose VerifyArgusRun Argus LVS, the Argus
Interactive LVS form appears as shown in Figure 7-4 which is similar to
DRC form.
2. Toggle the Tap of Rules, specify a path to run Argus. The default path is
the directory you invoke the Argus Interactive. If you want, you can click
the Browse button, and select the run directory. Then define the rules
format and specify the rule file from the Browse Button to find the file
called lvs.rule in verification folder.

Figure 7-4 Setting Rules Tap of Argus LVS
3. Toggle the Tap of Inputs, set the layout format to GDSII and turn Export
from layout viewer on, as shown in Figure 7-5; set the netlist format to
SPICE/CDL and turn Export from schematic viewer on.
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Figure 7-5 Setting Layout Format of Argus LVS


Figure 7-6 Setting Netlist Format of Argus LVS
4. Press Browse Button to specify the cp_amp.cdl which is the CDL netlist,
then you can do LVS check too.
5. To export the netlist, choose FileExportNetlist from DESIGN
MANAGER. Set the Simulate Type to CDL in the tap of general, type
cp_amp.cdl in Output File, as shown in Figure 7-7. Click OK, the CDL
netlist will be exported in the current working directory.
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Figure 7-7 Export CDL Netlist from Design Manager
6. Click Run LVS, Back annotate tool PVE form and LVS report file will pop
up after finishing LVS. LVS check pass if the LVS results are CORRECT.

Figure 7-8 Argus LVS Result

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8. Charge pump Design Flow
In this chapter, you will be performing the following tasks:
Making Specification for a charge pump circuit
Adding basic logical circuit
Completing the main circuits and do simulation
8.1 Making Specification
It is important that make Specification before IC designing. The aim of IC
design is to satisfy, improve and optimize specifications by circuits design and
simulation. The specification of a Charge pump shown as table below

Specification signification
values
Min Typical Max
Icp
The output current of
Charge pump
25uA 225uA 375uA
Icp
The mismatch of output
current
3%
T
charging and discharging
cycles of charge pump
1us
Ivdd power consumption 1.5mA
Area chip area 10000um
2

Table 8-1 The Specification of a ChargePump

8.2 Adding basic logical gate circuit
First, create some common logical circuits.
1. From the Design Manager, create a new cell cp_inv, please refer to 3.1 if
you have any difficulty. Add schematic view, symbol view and layout view
respectively shown as in Figure 8-1 to Figure 8-3.
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Figure 8-1 Schematic of cp_inv

Figure 8-2 Symbol of cp_inv
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Figure 8-3 Layout of cp_inv
2. From Design Manager, create a new cell called cp_or. Add schematic view,
symbol view and layout view respectively shown as in Figure 8-4 to Figure
8-6. Note that in the ChargePump directory, there are two types of layout
of cp_inv, the layout whose View name is layout is invoked by cp_top, and
the other is invoked by cp_amp and cmp_core.
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Figure 8-4 Schematic View of cp_or

Figure 8-5 Symbol View of cp_or
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Figure 8-6 One of Layout Views of cp_or
3. The Parameters of PMOS mentioned above: w=1u, L=0.18u, finger=1;
NMOS: w=0.6u, L=0.18u, finger=1.
4. From Design Manager, create a new cell called cp_Tgate. Add schematic
view, symbol view and layout view respectively shown as in Figure 8-7 to
Figure 8-9.
5. The Parameters of PMOS: Length=0.18u Entry Switch=Finger Width
Finger Width=2u Fingers=16 SD Metal Width=0.23u; NMOS:
Length=0.18u Entry Switch=FingerWidth Finger Width=1.2u Fingers=16
SD Metal Width=0.23u
6. Note that in the ChargePump directory, there are two types of layout of
cp_or. It is convenient for routing of layout.
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Figure 8-7 Schematic View of cp_Tgate

Figure 8-8 Symbol View of cp_Tgate
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Figure 8-9 One of Layout Views of cp_Tgate

8.3 The Main Circuitof ChargePump
Next, design the most important cell in ChargePump: cp_core.

Figure 8-10 Schematic of cp_core
The parameters of MOS and resistance are shown in the Table 8-2.

Cell
Name
Length/
Segment
Length
Fingers/
Segments
Finger
Width/
Segment
SD
Metal
Width
function
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Width
NM0 n18 2u 2 13u 0.23u Bias
NM4 n18 0.18u 4 1.2u 0.23u Enable
NM2 n18 2u 2 13u 0.23u Bias
NM3 n18 0.18u 4 1.2u 0.23u Enable
R1 rpdif 20u 10 0.42u filter
NM1 n18 4u 12 4u 0.23u filter
NM11 n18 0.18u 4 1.2u 0.23u Enable
NM5 n18 2u 1 13u 0.23u
Providing sink current
25uA
NM6 n18 2u 2 13u 0.23u
Providing sink current
50uA
NM7 n18 2u 4 13u 0.23u
Providing sink current
100uA
NM8 n18 2u 8 13u 0.23u
Providing sink current
200uA
NM9 n18 0.18u 8 1.2u 0.23u Enable
NM10 n18 0.18u 16 1.2u 0.23u
icp<0> control(control
sink current)
NM13 n18 0.18u 4 1.2u 0.23u
icp<1> control (control
sink current)
NM14 p18 0.18u 2 1.2u 0.23u
icp<2> control (control
sink current)
PM0 p18 2u 2 20u 0.23u
Providing bias current
for PMOS
PM1 p18 0.18u 4 2u 0.23u Enable
PM2 p18 2u 1 20u 0.23u
Providing sink current
25uA
PM3 p18 2u 2 20u 0.23u
Providing sink current
50uA
PM4 p18 2u 4 20u 0.23u
Providing sink current
100uA
PM5 p18 2u 8 20u 0.23u
Providing sink current
200uA
PM6 p18 0.18u 2 2u 0.23u Enable
PM7 p18 0.18u 4 2u 0.23u
icp<0> control(control
sink current)
PM8 p18 0.18u 8 2u 0.23u
icp<1> control(control
sink current)
PM9 p18 0.18u 16 2u 0.23u
icp<2> control(control
sink current)
Table 8-2 Parameters of MOS and Resistors
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In the top left of schematic, two group buffers called cp_inv responding to en
and icp_tune<2:0> provide control signals. To add them, do the following:
1. To add instance cp_inv, press bindkey <I> to display the Add Instance
form. Type Iinv<3:0> and Iinv1<3:0> in the Instance Name field.
2. Select Createwide Wire or press bindkey <Shift+W> to create buses
between cp_inv.

According to the specification, the output current is the combination of 25uA,
50uA, 100uA and 200uA. The current of 25uA is always providing unless the
turnoff of Enable. The rest currents are controlled by icp_tune<2:0>. Finally,
the output current is fit for the specification.

Figure 8-11 Add instance Array
The following table shows the definition of pins. Then, create symbol from
the schematic shown in Figure 8-12.
Pin Name Direction Definition
Ibias50u input Input bias current
en_cp input Enable
icp_tune<2:0> input control input current of
Charge pump
vbias output Output Bias Voltage for
cp_amp
Isource inout The output of Source
Current
Isink inout The output of Sink
Current
vdd inout Power
vss inout Gnd

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Figure 8-12 Symbol View of cp_core
You may generate custom layouts from schematics automatically by SDL
(Schematic Driven Layout).

Figure 8-13 Layout of cp_core
8.4 Completing the Design and Simulation of ChargePump
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From Design Manage, create the schematic and layout views of cp_top, the
schematic view is as shown in Figure 8-14. Invoke cp_core, cp_amp, cp_Tgate,
cp_inv and cp_or which are already designed. The cp_amp and the four
cp_Tgate are provided the charge release path for charge sharing effect.

Figure 8-14 Schematic of cp_top
Choose CreateSymbol View to create symbol of cp_top and modify it to the
one as shown in Figure 8-15, you may use commands to create line or circle.

Figure 8-15 Symbol of cp_top
The following table defines the parameters of pins:
Pin Name Direction Definition
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en input Enable
Icp_tune<2:0> input Control input current
up input Control output current of
source
upb input
dw input Control output current of
sink
dwb input
cp_out output
output current of
chargepump
vdd input power
vss input gound
Ibias_skin_50u inout Bias current

Return to the Design Manager, create a new test bench: cp_top_tb as shown
in Figure 8-16:

Figure 8-16 Generate Hierarchy form
The parameters of all the sources shown in the following table:

Instance
Name
Library
Name
Cell
Name
parameters
V0 analog vdc DC=1.8
I1 analog Idc DC=50u
V2 analog vdc DC=itune0
V3 analog vdc DC=itune1
V4 analog vdc DC=itune2
V5 analog vdc DC=vcp_out
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V6 analog vpulse
DC=1.8, ACMAG=0, ACPHASE=0, V1=1.8, V2=0,
TD=0.1u, TR=1n,TF=1n, PW=0.5u,PER=1u
V7 analog vpulse
DC=0, ACMAG=0, ACPHASE=0, V1=0, V2=1.8,
TD=0.1u, TR=1n,TF=1n, PW=0.5u,PER=1u
V8 analog vpulse
DC=1.8, ACMAG=0, ACPHASE=0, V1=1.8, V2=0,
TD=0, TR=1n,TF=1n, PW=0.5u,PER=1u
V9 analog vpulse
DC=0, ACMAG=0, ACPHASE=0, V1=0, V2=1.8, TD=0,
TR=1n,TF=1n, PW=0.5u,PER=1u

The parameter TD=0.1u of V6 and V7 is intended to test the current matching
between source and sink by transient simulation.

Next, simulate the circuit similar to the procedure described in the former
section 5.3. Set Parameters and Analysis to that as shown in Figure 8-17 and
Figure 8-18 respectively in MDE.

Figure 8-17 Parameters Setting

Figure 8-18 Analysis Setting
Then display simulation results in iWave. Select i(vv5)#7 in the left bottom of
the panel with <LMB>. Seven curves of current print on the screen.
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Figure 8-19 transcient result of i(vv5)#7

Get the max unmatched of Positive sink current and negative current is nearly
5uA, when vcp_out=0.6V and input current is 225uA.

To get the max Current consumption with command line, do the following:

1. Change the model
.LIB ./models/model.lib tt
.LIB ./models/model.lib res_tt
To:
.LIB ./models/model.lib ff
.LIB ./models/model.lib res_ff
2. Change
*Simulation Control
.param vcp_out=0.9 itune0=0 itune1=0 itune2=1.8
.tran 1n 10u SWEEP vcp_out 0.6 1.2 0.1
.print v(*) i(*)
.option post probe
To:
*Simulation Control
.param vcp_out=0.9 itune0=1.8 itune1=1.8 itune2=1.8
.tran 1n 10u
.print v(*) i(*)
.option post probe
Then, re-simulate the circuit similar to the procedure described in the former
section 5.3.Open iWave, print i(vv0) which is nearly 1.05mA, as shown in
Figure 8-20.
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Figure 8-20 measure max Current consumption in iWave

Next, choose SDLGenerate Hierarchy to creating the final layout.
1. From Design Manager, create a layout view called cp_top.
2. Select SDLGenerate Hierarchy, a form appears as shown in Figure
8-21.Turn the Do Nothing When No Cell Mapping option off, and then click
OK. Layout has been generated.

Figure 8-21 Generate Hierarchy
3. Place layout in positions that correspond to the relative positions of their
schematic symbols, then the final layout is the same as shown in Figure
8-22. Next, choose VerifyArgusRun Argus DRC/LVS to do physical
verification. Press bindkey <K> to measure the layout, the length and width
is nearly 106um and 65um respectively, so the area of the layout is about
6890um
2
.

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Figure 8-22 Final Layout of ChargePump
8.5 Summarizing the Performance of Charge pump
The comparison table between Simulation Results and Specification is as
shown in the table below. The design is satisfy the specification.

parameters
Simulation Results Specification
Min Typical Max Min Typical Max
Icp 25uA 225uA 375uA 25uA 225uA 375uA
Icp 2.22% 3%
T 1us 1us
Ivdd 1.05mA 1.5mA
Area 6890um
2
10000um
2


In this tutorial, an entire design flow is provided. Through chapter 2 to chapter
7, schematic capture with Aether SE, simulation with Aeolus, layout capture
with Aether LE and physical verification with Argus is introduced. In chapter 8,
a ChargePump is designed base on the former designs.






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