AN7554
AN7554
AN7554
com
FAN7554
Description
8-DIP
Applications
Off-Line & DC-DC converter
8-SOP
Rev. 1.0.3
2003 Fairchild Semiconductor Corporation
FAN7554
Vref
8
OVP
3.5V
R
off
15V/9V
OSC
CLK
_
PWM
MAX. 1V
+
_
FB
Vref
1.5V
0.3V
+
_
1k
on
PWR
/
SAVE
+
_
100uA
34V
UVLO
Vref
S/S
Vcc
7
+
Rt/Ct
2R
1mA
14V
OUT
IS
S
Q
R
Vref
Vcc
Offset(0.1V)
5uA
OLP
S
R
OVP-out
OCL-out
+
_
6V
OCL
UVLO-out
2V
5 GND
Symbol
Value
Unit
Supply voltage
Vcc
30
Output current
IO
VFB
-0.3 to VSD
VIS
-0.3 to VOC
PD
0.85
0.42
Operating temperature
TOPR
-25 to +85
Storage temperature
TSTG
-55 to +150
Rja
147.8
291.4
C/W
Note:
1. Junction -to -air thermal resistance test environments.
- JESD51-2 : Integrated circuits thermal test method environmental conditions-natural convection (still air).
- JESD51-3 : Low effective thermal conductivity test board for leaded surface mount packages.
- JESD51-10 : Test boards for through-hole perimeter leaded package thermal measurements.
FAN7554
Temperature Characteristics
( -25C Ta 85C )
Parameter
Symbol
Value
Unit
VREF3
0.5
FOSC2
PIN Array
Vref
Vcc
OUT
GND
YWW
FA N7554
1
FB
S/S
IS
Rt/Ct
PIN Definitions
Pin Number
Pin Name
FB
Inverting(-) input of pwm comparator, on/off control & OLP sensing terminal.
S/S
Soft start
IS
Rt/Ct
GND
Ground
OUT
Vcc
Power supply
Vref
Output of 5V reference
FAN7554
Electrical Characteristics
(Ta = 25C, Vcc=16V, Rt=10k, Ct=3.3nF unless otherwise specified)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
4.90
5.00
5.10
20
mV
VREF
Line regulation
VREF1
Load regulation
VREF2
25
mV
ISC
Tj = 25C
0.1
0.18
FOSC
Tj = 25C
45
50
55
kHz
0.05
1.0
FOSC1
VRH
2.8
VRL
1.2
Discharge current
Idisch
VRT/CT = 3.3V
6.1
9.4
mA
V
VTH(IS)
VFB = 5V
0.8
1.0
1.2
VTH(FB)
VIS = 0V
0.2
0.3
0.4
1.0
mA
IFB
D(MAX)
92
95
98
D(MIN)
ISD
4V VFB VSD
3.5
6.5
uA
VSD
VFB > 5V
5.4
6.6
VOC
1.6
2.4
VOVP
30
34
38
ISINK
VOFF
mA
1.2
1.5
1.8
1.1
mA
Vcc = 16V
5.2
IS/S
VLIM(S/S)
<OUTPUT SECTION>
Low output voltage1
VOL1
0.15
0.4
VOH1
13
15
17
VOL2
1.5
2.5
VOH2
12
14
16
tR
Tj = 25C, CL = 1nF
80
ns
tF
Tj = 25C, CL = 1nF
40
ns
<UVLO SECTION>
VTH(ST)
13.2
15
16.2
VOPR(M)
8.2
10.2
FAN7554
Symbol
Conditions
Min.
Typ.
Max.
Unit
IST
0.1
0.2
mA
IOP
10
mA
IOFF
0.2
0.4
mA
VFB<VTH(FB),VS/S<VOFF
Note:
1. These parameters, although guaranteed, are not 100% tested in production.
FAN7554
[ Rt vs. Freqency ]
100.000
10000.0
0.33n
1.1n
3.3n
11n
33n
100.0
10.0
Frequency[kHz]
1000.0
10.000
1K
2K
5K
10K
20K
50K
100K
1.000
1.0
0.1
0.100
10
100
0.1
Rt[Kohm]
10
100
Ct[nF]
[ Ct vs Duty ]
800
95.0
700
85.0
Duty [%]
65.0
55.0
45.0
35.0
25.0
500
Tr
Tf
400
300
200
100
15.0
0.1
10
Ct [nF]
600
Time [nsec]
1K
2K
5K
10K
20K
50K
100K
75.0
100
10
Cload [ nF]
100
FAN7554
FAN7554
Operation Description
The FAN7554 has all the basic features of the current mode SMPS control IC. Its basic configuration includes the UVLO with
6V hysteresis, a band gap reference, the oscillator that can oscillate up to 500kHz according to Rt/Ct (connected externally), a
PWM logic circuit , a gate driver, and the feedback circuit that has the current source and soft start function. The FAN7554 has
various functions such as an over load protection, an over current protection, and an over voltage protection. The over load
protection forces the FAN7554 to stop its operation if the load current is higher than the preset value. The protection circuit
can also be prevented from operating during transient states by ensuring that a certain amount of the time passes before the
protection circuit operates. The shutdown circuit is configured for an auto-restart, so the FAN7554 automatically restarts when
Vcc drops to 9V (stop voltage).
Start-Up
The start-up circuit is made up of an under voltage lock out (UVLO), the protection for low voltage conditions, and the 5V
reference (Vref), which supplies bias voltage to the control circuit after start-up. The start voltage of the UVLO is 15V , and
the stop voltage after turn on is 9V. It has a 6V hysteresis. The minimum operating current for start-up threshold is typically
100uA, and this can reduce the power dissipation on the start-up resistor. The Vref is composed of the band gap reference
circuit with its superior temperature characteristics and supplies power to all the FAN7554 circuits and Rt/Ct, with the
exceptions of the ULVO circuit and ON/OFF control circuit.
DC Link
Icc(mA)
7.0
VCC
UVLO
5V
Internal bias
Vref
Good logic
0.01
15V/9V
FAN7554
Vcc (V)
9
15
Soft Start
The SMPS output load usually contains a capacitive load component. During initial start-up, the output voltage increases at a
fixed time constant because of this component. If the feedback loop, which controls the output voltage, was to start without
the soft start circuit, the feedback loop would appear to be open during initial start-up , so, at start-up, the feedback voltage
applied to the PWM comparators inverting input (-) reaches its maximum value(1V).
During this time, the peak value of the drain current would stay at the maximum value, and the maximum power would be
delivered to the secondary load side from the start. When the maximum power is delivered to the secondary side for this initial
fixed time, the entire circuit is seriously stressed. The use of a soft start can avoid such stresses. At start-up, the soft start
capacitor Cs is charged by 1mA and 100uA current sources.
The voltage of the inverting terminal of the PWM comparator increases to 1/3 of the Cs voltage at a fixed time constant.
Subsequently, the drain peak current is limited by the gradual increase in the Cs voltage and this causes the output voltage to
increase smoothly. When the Cs voltage becomes greater than 3V, the diode Ds turns off consequently, the feedback capacitor
Cfb is charged by 1mA and 5uA current sources. This charge voltage determines the comparators inverting voltage. Then, Cs
voltage charges to 5V by 100uA current source. The soft start capacitor Cs is discharged when the UVLO good logic starts, so
the soft start is repeated at re-start.
FAN7554
S/S
2
100uA
5V
Ds
2R
Output drive
R
1mA
Cfb
Cs
5uA 5V
Vcc
FAN7554
1
FB
Figure 13. Soft Start Circuit & Circuit Flow
Oscillator
As shown in figure14, the oscillator frequency is programmed by values selected for timing components Rt and Ct. Capacitor
Ct is charged to almost 2.8V through resistor Rt from the 5V reference and discharged to 1.2V by an internal current source.
The oscillator generates the clock signal while the timing capacitor Ct is discharged. The gate drive output becomes low during
the clock time. Rt and Ct selection determine the oscillator frequency and maximum duty cycle. Charge and discharge times
can be calculated through the equations below.
Charging time : tc = 0.55RtCt
Discharging time : td = RtCtln[(0.0063Rt - 2.8) / (0.0063Rt - 3.8)]
where the oscillator frequency : fosc = (tc + td)-1 (10%)
When Rt > 5k, fosc = 1 / (0.55RtCt) = 1.8 / (RtCt)
Vhigh(2.8V)
Vref
Sawtooth waveform
8
Rt
Ct
CT
Ct 4
Discharge
Clock
[ Rt > 5k]
Vlow(1.2V)
tc
td
Gate Drive
Discharge
Internal clock
Vhigh(2.8V)
2.8V
/1.2V
Sawtooth waveform
[ Rt < 5k]
Vlow(1.2V)
tc
td
FAN7554
Internal clock
FAN7554
Feedback
As shown in figure16, the internal oscillator clock turns on the MOSFET. The feedback comparator operates to turn it off
again, when the MOSFET current reaches a set value proportional to Vfb. The feedback capacitor Cfb is charged by the internal current sources , 1mA and 5uA, and is discharged by the secondary side photo-coupler to control the output voltage.
DRIN
OUT
6
OSC
2R Vfb/3
Vfb
S
R
1mA
Cfb
IS
3
5uA 5V
Vsense
Vcc
Rs
FAN7554
1
FB
Delayed Shutdown
During the normal operation, the feedback voltage is between 0~3V. If the output terminal overloads or an error happens to
the feedback loop, the delayed shutdown circuit operates. When the feedback voltage is less than 3V, the feedback capacitor is
charged by current sources, 1mA and 5uA; when the feedback voltage becomes greater than 3V, the capacitor is charged by the
5uA current source because diode D1 turns off. When the feedback voltage is less than 3V, the charge slope becomes an exponential function and, when it is greater than 3V, the charge slope becomes linear. When the feedback voltage reaches almost
6V, the FAN7554 shuts down. The shut down circuit is configured for
auto-restart, so it automatically restarts when Vcc reaches the under voltage 9V.
FB
1
DRIN
5uA
OUT
6
OSC
Vcc
2R
D1
R
R
1mA
Cfb
IS
3
5V
Rs
Over Current
Comparator
Shutdown
R
6V
UVLO - out
10
FAN7554
FAN7554
Vfb
6V
t1
t2
Figure 17-B . Delayed Shutdown & Feedback Waveform
Gate Driver
The gate drive circuit has the totem-pole output configuration. The output has 1A peak current and 200mA average current
drive ability.
DRAIN
Clock
OUT
6
Shutdown
FAN7554
Figure 18. Gate Drive Circuit
ON/OFF Control
The FAN7554 is able to use the feedback pin for ON/OFF control by placing NPN transistor between the cathode of the
KA431 and ground as shown in figure 19. When the transistor turns on, the current flows through the photo diode and
saturates the photo transistor. As a result, the feedback voltage is dropped to zero. When the feedback voltage is below 0.3V,
the soft start voltage starts to discharge by connecting the internal resistor 1k in parallel with the external capacitor Cs. When
the soft start voltage becomes less than 1.5V, all the blocks in the FAN7554 are turned off , with the exceptions of the UVLO
block and ON/OFF control block. The operation current is about 200uA. So the stand-by power is reduced and SMPS
efficiency is improved. When the feedback voltage exceeds 0.3V, the FAN7554 normally operates by turning on Vref block.
11
FAN7554
VCC
7
Vref
3.5V
R
S
Q
100uA
OFF
S/S
2
ON
1K
1.5V
UVLO
PWR
/
SAVE
5V
Vref
15V/9V
0.3V
Vo
FB
Cs
Good logic
Internal bias
Cfb
5uA
FAN7554
Vcc
Remote control
Vref
Icc
5V
4.5mA
0.2mA
t
VS/S
5V
Slope (dv/dt) = 1k * Cs
3V
Slope (dv/dt) = (1mA +100uA) / Cs
1.5V
t
Vfb
0.3~3V
OFF Signal
Slope (dv/dt) = (5uA) / Cfb
ON Signal
0.3V
Normal State
OFF State
Figure 20. ON-OFF Control Circuit Waveforms
12
Normal State
FAN7554
Protection Circuits
The FAN7554 has many built-in protection circuits that do not need additional components, providing reliability without cost
increase. These protection circuits have the auto-restart configuration. In this configuration, the protection circuits reset when
Vcc is below UVLO stop threshold (9V) and restarts when Vcc is above UVLO start threshold voltage (15V)
6V
Shutdown
R
UVLO out
Vfb
Vo
OSC
2R
1mA
Cfb
S
5uA 5V
Vcc
FAN7554
KA431
1
FB
V
6V
t1
13
FAN7554
BD
T101
NTC
12V/3.5A
L201
D201
R103
C102
R104
C104
R101
R203
C201
R102
C202
D101
R204
C103
C301 C302
LF101
R202
R201
C101
Q101
D102
IC301
R106
R105
R205 C203
TNR
FUSE
IC201
D103
7
R108
FAN7554
R107
Input:85 ~ 265VAC
50/60Hz
FB
S/S
14
C109
R109
R110
C105
IC301
IC101
IS Rt/Ct
C108
C106
C107
R111
FAN7554
Value
Note
Part
FUSE
FUSE
250 2A
NTC
5D-11
Value
Note
CAPACITOR
-
NTC
-
RESISTOR
C101
100nF/ 275V
Box Capacitor
C102
100nF/ 275V
Box Capacitor
C103
470nF/ 400WV
Electrolytic
C104
103/ 1kV
Film Capacitor
R101
330k
1W
C105
104
Ceramic
R102
C106
1uF/ 10V
Electrolytic
R103, R104
100k
1W
C107
101
Ceramic
R105
22
C108
122
Ceramic
R106
4.7k
C109
22uF/ 50V
Electrolytic
R107
12k
C201
330uF
Electrolytic
R108
10
C202
330uF
Electrolytic
R109
1k
C203
104
Ceramic
R110
0.5
2W
C301
R201
1k
C302
R202
1k
R203
4.7k
R204
1.2k
LF101
30mH
R205
L201
6.4uH
INDUCTOR
MOSFET
Q101
FQP6N70
DIODE
Fairchild
IC
D201
MBRF10100CT
D101
UF4007
Fairchild
IC101
FAN7554
Fairchild
D102
1N4148
IC201
KA431
Fairchild
D103
UF4004
Fairchild
IC301
Opto-coupler
Fairchild
BD
G3SBA60
15
FAN7554
Transformer Specification
3mm
6mm
2mm
12
10
NP
NB
8
11
NP
N12V
N12V
NB
NP
bottom
top
Winding Specification
No.
Pin(S F)
Wire
Turns
Winding Method
NP
13
0.35 1
44
N12V
7 11
0.35 4
12
NP
13
0.35 1
44
NB
54
0.35 1
13
Electrical Characteristic
Closure
Pin
Spec.
Inductance
1-3
400uH 10%
100kHz, 1V
Leakagel
1-3
10uH MAX .
16
Remarks
FAN7554
D201
BD
L201
+12V/2A
T101
R103
C104
R105
C102
R106
C103
R104
C201
C202
D102
C301 C302
D202
L101
+5V/3A
R107 D103
R201
D104
C105
C101
L202
C203
R101
IC2
FUSE
R102
R113
D101
RT101
Input: 85 ~ 265VAC
50/60Hz
C204
R202
R108
5
8
7
6
Vref Vcc OUT GND
Q101
R110
FAN7554
C106
F/B S/S
1
2
IC301
IS Rt/Ct
3
4
C110
C111
C107 C108
R203
R109
R112
C109 R111
IC301
R204
C205
IC201
17
FAN7554
Value
Note
Part
FUSE
FUSE
250 2A
RT101
DSC 10D-11
Value
Note
CAPACITOR
-
NTC
-
RESISTOR
C101
470nF/ 275V
Box Capacitor
C102, C103
470nF/ 400WV
Electrolytic
C104
223/ 630V
Film
C105
33uF/ 35V
Film Capacitor
R101
330k
1W
C106
104
Ceramic
R102
C107
1uF/ 35V
Electrolytic
R103, R104
56k
1W
C108
101
Ceramic
R105, R106
220k
1W
C109
122
Ceramic
R107
10
C110
272
Film
R108
20
C111
333
Film
R109
4.7k
C201, C202
1000uF/ 35V
Electrolytic
R110
1.2k
C203
330uF/ 16V
Electrolytic
R111
0.5//0.5//0.5
2W
C204
2200uF/ 16V
Electrolytic
R112
1k
C205
104
Ceramic
R113
12k
C301, C302
332/ 1kV
Ceramic
R201, R202
10k
R203
1k
LF101
30mH
R204
330
L201
INDUCTOR
MOSFET
Q101
SSH8N80
DIODE
Fairchild
IC
18
D101
1N4004
D102
FR157
IC101
FAN7554
Fairchild
D103
UF4007
IC201
KA431
Fairchild
D201
MBRF10100CT
IC301
Opto-Coupler
Fairchild
D202
MBR3045PT
BD
PBS406GU
FAN7554
Transformer specification
Schematic Diagram (Top view)
1
Np ; 32turn
13, 14
Ns,12 ; 5turn
Nvcc ; 6turn
3
8, 9
Np ; 32turn
Ns,12 ; 5turn
Nvcc ; 5turn
7
Ns,5 ; 4turn
Ns,5 ; 4turn
Np ; 32turn
10,11,12
Winding Specification
No.
Pin(S F)
Wire
Turns
NP
13
0.65 1
32
NS , 5
8 11
0.65 4
NS, 12
49
0.65 4
NP
13
0.65 1
32
NVCC
76
0.65 1
19
FAN7554
Mechanical Dimensions
Package
Dimensions in millimeters
8-SOP
Symbol
Min
Nom
Max
1.75
A1
0.10
0.15
0.25
A2
1.25
1.45
1.50
0.35
0.37
0.51
0.19
0.20
0.25
4.80
4.90
5.00
3.80
3.90
4.00
1.27BSC
5.79
5.99
6.20
0.25
0.50
0.50
0.70
0.90
GP
20
0.36 BSC
aaa
0.25
bbb
0.10
FAN7554
8-DIP
21
FAN7554
Ordering Information
Product Number
Package
FAN7554
8-DIP
FAN7554D
8-SOP
Operating Temperature
-25C ~ 85C
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER
DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
www.fairchildsemi.com
10/2/03 0.0m 001
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2003 Fairchild Semiconductor Corporation