Signal Integrity Analysis

Guidelines

Document ID

BRD.GL.SI

Author
Ravi Kumar Chirugudu

Revision

Date

Change Note

1.1

30.10.01

Document Formatting changes

2.0

April
17,2006

Changes as mentioned in the

revision history. A new section on
Gigabit simulations added

ravikumar.chirugudu@wipro.com

Jinto N Jose
jinto.jose@wipro.com

Aloke B, Nitin Jain, Bijesh,

Suresh

VLSI / System Design Business Unit

Wipro Technologies
Bangalore

Signal Integrity Analysis Guidelines

BRD.GL.SI.2.0

Revision History
Revision

Description

Date

Changes By

0.1

Draft Document

26.06.01

Ravi Kumar
Chirugudu

0.2

Graphical illustrations added

25.07.01

Ravi Kumar
Chirugudu

0.3

Internal Review comments incorporated

16.08.01

Ravi Kumar & Jinto

1.0

Formatting the document

03.09.01

Ravi kumar & Jinto

30.10.01

Anand Mathew

April 17,
2006

Bijesh Radhakrishnan
Suresh Babu K
Nitin Jain
Aloke Bhattacharya

1.1

2.0

Removal of section 2 + change of

formatting
- Review of the whole document and
updation as per the new technologies
- Addition of Gigabit simulations section by
Nitin Jain

VLSI / System Design Business Unit

Wipro Technologies

Signal Integrity Analysis

Guidelines

Revision 2.0

For More Information :

April 17,2006

Wipro Technologies,
72, Keonics Electronics City,
Bangalore 561 229, INDIA
Phone : +91.80.8520408, Fax : +91.80.8520478
Email : info@wipro.com, Internet : http://www.wipro.com

Confidential information
This document contains confidential information. The contents of this document may not
be transmitted or reproduced for use or distribution without express permission of
WIPRO Ltd.

Signal Integrity Analysis Guidelines

BRD.GL.SI.2.0

TABLE OF CONTENTS

INTRODUCTION .......................................................................................................................................6

GUIDELINES.............................................................................................................................................8
2.1 GEN GENERIC GUIDELINES ................................................................................................................8
2.1.1 SEL Selection and Creation of Device Model .......................................................................8
2.1.2 VAL Validation of the IBIS Model ........................................................................................11
2.1.3 IDN Identifying Critical Interfaces ........................................................................................22
2.1.4 TES Test Conditions............................................................................................................25
2.1.5 TER Termination Strategy ...................................................................................................30
2.2 PRE GUIDELINES FOR PRE-LAYOUT ANALYSIS ..................................................................................30
2.2.1 REQ Test Requirements .....................................................................................................30
2.2.2 SIM Selection of Simulation Environment ...........................................................................32
2.2.3 FID Signal Fidelity Checks ..................................................................................................34
2.2.4 GEN Generation of Component Selection, Placement and Routing Guidelines.................36
2.3 POS GUIDELINES FOR POST-LAYOUT ANALYSIS ................................................................................39
2.3.1 REQ Test Requirements .....................................................................................................39
2.3.2 FID Signal Fidelity Checks ..................................................................................................39
2.4 SIMULATION OF MULTI GIGABIT SIGNALS (A STEP FURTHER).................................................................41
2.4.1 Gigabit design challenges ......................................................................................................41
2.4.2 Losses at Gigabit rates ...........................................................................................................41
2.4.3 Impact of losses......................................................................................................................42
2.4.4 Gigabit Simulations.................................................................................................................43
2.4.5 Opening Eye Diagram ............................................................................................................44

APPENDICES .........................................................................................................................................46
3.1 APPENDIX A. VERIFICATION OF RULES .................................................................................................46
3.2 APPENDIX B. REFERENCES ..................................................................................................................47

GLOSSARY.............................................................................................................................................47

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LIST OF FIGURES
Figure 1: SI Analysis Flow................................................................................................................................7
Figure 2: Building Blocks of IBIS model...........................................................................................................8
Figure 3: Outputs of same device under different operating conditions. .........................................................9
Figure 4: Signals from devices of same type but different vendor.................................................................10
Figure 5: Connector Model.............................................................................................................................11
Figure 6: Graphical display of IBIS data in Mentor Graphics visual IBIS editor.............................................13
Figure 7: Flight time analysis .........................................................................................................................14
Figure 8: AC Test Loads ................................................................................................................................15
Figure 9: Outputs from a fast driver and slow driver. .....................................................................................16
Figure 10: IBIS input structure model ............................................................................................................17
Figure 11: IBIS Output Structure Model.........................................................................................................17
Figure 12: V/T Table ......................................................................................................................................21
Figure 13: s2iplt Waveform ............................................................................................................................22
Figure 14: s2iplt Waveform ............................................................................................................................22
Figure 15: Effect of Fast Drivers on unterminated nets .................................................................................23
Figure 16:Effect of trace length on signal quality. ..........................................................................................24
Figure 17: Signal deterioration due to a stub caused by test interface..........................................................25
Figure 18: Differential Signal - Properly routed and Terminated ...................................................................26
Figure 19: Differential Signal with a skew between P& N..............................................................................27
Figure 20: Single Ended Signal (P/N) ............................................................................................................27
Figure 21: Selection of programmable buffer in specctraquest .....................................................................29
Figure 22: Effect of terminations on a signal..................................................................................................30
Figure 23: Point to Point topology..................................................................................................................31
Figure 24: Daisy Chain Topology...................................................................................................................31
Figure 25:Star Topology.................................................................................................................................32
Figure 26: Mixed Topology.............................................................................................................................32
Figure 25: Equivalent model of a via..............................................................................................................33
Figure 27: A net with multiple drivers. ............................................................................................................34
Figure 28: AC DRC parameters .....................................................................................................................35
Figure 29: Source termination at ideal and non-ideal positions.....................................................................37
Figure 30: Signal on end terminated line for ideal and non-ideal termination placements............................38
Figure 31: 100 psec rise time, 2 GHz clock signal at the end of a 36 inch backplane trace, 4 .....................41
Figure 32: Total attenuation in the 36 inch long backplane trace from conductor loss, dielectric loss and the
combination ....................................................................................................................................................42
Figure 33: Eye Diagram .................................................................................................................................44

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Signal Integrity Analysis Guidelines

1 INTRODUCTION
The term Signal Integrity (SI) addresses two concerns in the electrical design aspects the timing and
the quality of the signal. Does the signal reach its destination when it is supposed to? And also, when it
gets there, is it in good condition? The goal of signal integrity analysis is to ensure reliable high-speed
data transmission.
SI analysis is carried in two parts:
1. Pre Route Analysis
2. Post Route Analysis
As data rates increase and digital rise times grow steadily shorter in high-speed digital systems, it
becomes increasingly important to pre-serve signal integrity in logic design. In the pre-route stage, SI
analysis can be used to select technology for I/Os, clock distributions, chip package types, component
types, board stackups, pin assignments, net topologies, and termination strategies. With various design
parameters considered, batch SI simulations on different corner cases will progressively formulate a set
of optimized guidelines for physical designs of later stage. SI analysis at this stage is also called
constraint driven SI design because the guidelines developed will be used as constraints for component
placement and routing. The objective of constraint driven SI design at the pre-route stage is to ensure
that the signal integrity of the physical layout, which follows the placement/routing constraints for noise
and timing budget, will not exceed the maximum allowable noise levels. Comprehensive and in-depth
pre-route SI analysis will cut down the redesign efforts and place/route iterations, and eventually reduce
design cycle.
With an initial physical layout, post-route SI analysis verifies the correctness of the SI design guidelines
and constraints. It checks SI violations in the current design, such as reflection noise, ringing, cross talk
and ground bounce. It may also uncover SI problems that are overlooked in the pre-route stage,
because post-route analysis works with physical layout data rather than estimated data or models,
therefore it should produce more accurate simulation results.
This document has been organized such that it addresses both generic and specific considerations in
separate sections. Each guideline is nailed down as either RULE or RECommendation for ease of use.
The General guidelines section is applicable for all components. The General guidelines sub-section
is applicable for all components in that section
When SI analysis is thoroughly implemented throughout the whole design process, a reliable high
performance system can be achieved with fast turn-around. All the board designers based on the client
needs should use this document. SI analysis is an iterative process at various stages of the design.
Figure 1 shows the role of SI analysis at various stages of the full design flow.

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Figure 1: SI Analysis Flow

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2 GUIDELINES
2.1 GEN Generic Guidelines
2.1.1 SEL Selection and Creation of Device Model
Based on the customer requirements and availability of the Tool, the device model is selected. Two
common device models are SPICE model and IBIS model. IBIS stands for I/O Buffer Information
Specification. It is a fast and accurate Behavioral method of modeling I/O buffers. SPICE is a
computerized modelling technique developed by Berkeley University in the 1960's - originally for the
design of integrated circuits, but has found universal use for other applications. Since SPICE models
disclose vital information about the circuit design of the device, most of the device manufacturers
provide IBIS models rather than SPICE models. Another advantage is that IBIS models take less
simulation time compared to the corresponding SPICE models.
IBIS model is based on V/I and V/T curve data derived from measurements or full circuit simulation. The
characteristics of the Input and Output buffers of integrated circuits can be defined with V/I and V/T
curves. Using V/I and V/T table data that describes the input/output buffer characteristics of integrated
circuits, semiconductor vendors can easily provide models to customers without giving up IP
(Intellectual Property). This is the fundamental reason for more IBIS models becoming available every
day. Model accuracy is not compromised using IBIS format. A user can perform signal integrity analysis
(ex. reflection, cross-talk, mismatched impedance, etc) using IBIS models much faster than SPICE. A
behavioral approach to simulation allows this speed advantage over structural method such as SPICE.
As board designs gets more complex, all nets (critical and presumed non-critical) need to be simulated.
This is possible using a behavioral approach. IBIS can run in the order of 25X faster than SPICE and
provide valuable signal integrity information. The behavioral diagram of important building blocks of IBIS
model is shown in the following Figure 2

Power
Clamp

Input
Package

Pull up
Ramp
(V/T)

Pull up
V/I

Power
Clamp

GND
Clamp
Functional
Logic
with
enable
Power
Clamp

Output
Package

Pull down
Ramp

Pull down
V/I

GND
Clamp

(V/T)

Enable
Package
GND
Clamp

(Input Section)

(Output Section)

Figure 2: Building Blocks of IBIS model

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2.1.1.1

[RULE]

The model should be selected based on operating conditions

If a device can operate at different Vcc supplies then the model corresponding to the correct
supply voltage should be selected. Nowadays many devices support a wide range of supply
voltage. The characteristics of the device may not be same throughout the supply voltages
supported. So it is a must to select the IBIS model corresponding to the supply used in the design.
For example, 2.5V device will have different drive capabilities compared to 3.3V device for the
same device part no. Figure 3 shows the simulation results of the same device with different
supply voltages.

Figure 3: Outputs of same device under different operating conditions.

2.1.1.2

[RULE]

The model should be selected based on selected package style

The IBIS model parameters change depending on the style of package used. The IBIS
model has information about RLC parameters of the package. These parameters are given by the
key words
R_pkg - Package resistance,
L_pkg - Package Inductance and
C_pkg - Package Capacitance.
In some cases the vendors give same IBIS model for all the available packages for that
particular component. Usually in such models the RLC information corresponding to any one
package will be active at a time. The rest will be commented out. The user should identify the
correct package used in his design and should enable the appropriate R_pkg., L_pkg and C_pkg.

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2.1.1.3

[RULE]

The model should be selected based on version of the device

When working with new chips, it is common to have many versions of the device. The user
should ensure that the IBIS model used for the simulation corresponds to the correct version of the
device used in the design. For instance, a new chip, which is still in development stage, has to be
used as an interface IC for UTOPIA or POS or PCI interface. In the first revision, the chip may not
meet the requirements as specified by the standards. The vendor gives a work around plan for
that particular version of the chip. The next revision may have completely different characteristics
with different work around plans. Hence it becomes very important to use the model of the version
for which the board is designed.

2.1.1.4

[RULE]

The model should be selected based on chosen vendor

Many vendors may have same device with same family, package type etc. But the
characteristics of the device may vary with vendor. So it should be ensured that the IBIS model
used for simulation is obtained for the exact part used in the design. For example, LVCMOS
device available from Texas Instruments and Philips may have different timing drive characteristics
after meeting the minimum family requirements. The Figure 4 shows the outputs of two drivers of
the same family but from different vendors.

Figure 4: Signals from devices of same type but different vendor

2.1.1.5

[RULE]

If IBIS model is not available it should be created from SPICE model

Some times IBIS models are not available directly. If SPICE model is available it can also be used
to generate the simulation model. Some tools give direct support for SPICE models. If XTK is used
for simulation, then SPI2MOD utility can be used to generate XTK models for simulation. If the tool

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supports only IBIS models then a SPICE to IBIS conversion utility can be used. Various third party
utilities are available for SPICE to IBIS conversion.
2.1.1.6

[REC]

Connector models may be created using RLC parameters provided by vendor

Unlike other active components the models of the connectors may not be readily available. The SI
person needs to make the model using the parameters of the connector like its inductance,
Capacitance and series resistance. The values for connector parameters and the equivalent model
should be obtained from the manufacturers. The value of L1 and R1 has to be assigned based on the
test condition i.e. whether for mated connector or for an open connector.
A connector can be modeled as a combination of inductor, capacitor and transmission line as shown in the
Figure 5.

Figure 5: Connector Model

This may be incorporated in the simulation topology file using the modeling language/GUI of the tool
For example, in XTK, the connectors can be modeled using the 'TOPSPEC statement. An example of
connector is given bellow.
TOPSPEC CONN_1
NODE C1 1 TYPE CAPACITOR
SERIES R1 1 TYPE RESISTOR
SERIES L1 1 TYPE INDUCTOR
NODE C2 1 TYPE CAPACITOR
ENDTOP

2.1.2 VAL Validation of the IBIS Model

Accurate models of semiconductors, passive components, and parasitics are necessary to create
accurate circuit- or system-level simulations. Conversely, bad models will result in bad electricalnetwork-simulation results. For this reason, bench verification of circuit models is crucial prior to
shipping any product boards for fabrication. You should count on initially spending about half of your
time obtaining, debugging, and verifying simulation models.
Start obtaining semiconductor models early, so you have time to verify that your technology and
part selection are adequate for your system-design performance requirements. As soon as module
designers know what part families the design uses, signal-integrity engineers must obtain, debug, and
verify IBIS models.

2.1.2.1

[RULE]

The models should be checked for syntax errors

Majority of all IBIS models is generated through SPICE translation. At the same time, there are
various models that are generated through actual measurements of Silicon. In addition,
measurements are often used to refine/validate/improve existing models, previously generated from
SPICE. Regardless of source, the model must pass the Parser Test to make sure that syntactically

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Signal Integrity Analysis Guidelines

the model meets the IBIS specification. The syntax checking can be done using a tool called
PARSER or using Mentor Graphics Visual IBIS Editor (free version is available). A parser test
checks if the ASCII model syntactically confirm to the specifications. It is highly recommended by the
IBIS committee to run ibischk3 (ver3.2) even if the generated model is IBISv2.1 or below (as of Dec
2005, the latest version of Visual IBIS editor from Mentor Graphics supports IBIS 4.0 syntax
checking). The Parser flags WARNINGS and ERROR messages with line numbers and descriptive
information. The information obtained will be as shown below.
Parser test
IBISCHK3 V3.2.2 (preliminary)
Checking 2000a.ibs for IBIS 3.2 Compatibility...
WARNING (line 71) - IBIS files should not contain tab characters.
WARNING (line 148) - Pull-up Minimum data is non-monotonic
WARNING (line 274) - Pull down Maximum data is non-monotonic
...
WARNING - Model 'IN': MIN VI curves cannot drive through Vmeas=1.5V
given load Rref=500 Ohms to Vref=0V
WARNING - Model 'IN': MAX VI curves cannot drive through Vmeas=1.5V
given load Rref=500 Ohms to Vref=0V
WARNING - Model 'OE': TYP VI curves cannot drive through Vmeas=1.5V
given load Rref=500 Ohms to Vref=0V
.
WARNING - Model 'OUT': MAX AC Rising Endpoints (0.00V, 2.83V) not within
0.057V (2%) of (0.58V, 3.60V) on VI curves for 50 Ohms to 3.6V
WARNING - Model 'OUT': MAX AC Falling Endpoints (-0.00V, 2.82V) not within
0.056V (2%) of (0.58V, 3.60V) on VI curves for 50 Ohms to 3.6V
Errors: 0
Warnings: 21
File Passed

Usually the warnings can be ignored(however, it is better to review the list of warnings). All Errors have to
be corrected. For example, an error can be if it is non-monotonic by greater than 10 percent. Most of the
SI tools correct the non-monotonic points. Warnings/errors related to non-monotonicity of the IBIS model
are very common- and the best way to verify this is to view the V-I/V-t waveforms. V-I/V-t waveforms can
be viewed using the free Visual IBIS editor from Mentor graphics. In the process of converting the IBIS
models to the internal format of the SI analysis tool(e.g. DML models of cadence Specctraquest), the tool
will sometimes remove the non-monotonic points and create the intermediate file. We should be careful
about this modification done by the conversion. Here also it is recommended to view the V-I/V-t curve
using the waveform viewer available in the SI analysis tool and confirm that the model conversion is
proper.
The following figure shows the GUI of Visual IBIS editor (IBIS-> View Data menu ). A pullup curve for
Micron MT47H64M4BP 1.8V DDR2 SDRAM is shown in the diagram. Other tabs in the same GUI can
show Pulldown, Power/GND clamp, Rising/Falling waveform.

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Figure 6: Graphical display of IBIS data in Mentor Graphics visual IBIS editor
The IBISCHK is available in http://www.eigroup.org/ibis/tools.htm .

2.1.2.2
1.

[RULE]

The models should be checked for complete pin listing

IBIS has always been a component-centric model as opposed to structural (SPICE) models, which are more
buffer-centric. At the same time, IBIS is mostly used on board level SI Analysis. The user translates the PCB
database to generate transmission line models of the board traces. Then IBIS models are tied to the proper
Drivers and Receivers on the board. The end user then can drive any pins of the device connected to whatever
net on the board to run a simulation. This becomes a problem if the model has an incomplete set of pins. So the
complete pin list should be ensured in all IBIS models. For example, in case of FPGA ( Field Programmable
Gate Array) devices, each device will be available in multiple different type of Packages(e.g PQFP/BGA etc)
with totally different pin assignments. Instead of providing a different IBIS model for each different type of
package, Xilinx/Altera provides IBIS models with only a few pins of each type of IO instantiated in the model.
Specific to each package, a separate package model is provided to take care of package parasitics. To avoid
manually editing the IBIS model provided by Xilinx, the IBISwriter software available with Xilinx ISE6.3i (or later)
can be used . This will automatically generate an IBIS model as per the signal names and package selected in
the design. Similarly, Altera Quartus II can be used to create IBIS models for Altera FPGAs. Please refer to the
user manual/online help of Xilinx ISE/ Altera Quartus II for more details regarding this. Similar problem might be
there for any other device with multiple packages- so it is always recommended to open the IBIS file and verify
that the pin assignment list in the [Pin] section of the IBIS model matches correctly with the pin assignment of
as per the datasheet/package details.

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2.1.2.3

[RULE]

The models should be checked for timing test load

For Common CLK applications, Flight time analysis is a key factor of SI simulations. Tflight(max)
determines how far apart you can place two component without violating timing budget while
Tflight(min) determines how close to place the two components. In order to do this, the simulator
needs to know the manufacturers test load conditions under which Tco(Clk-to-out)is guaranteed.
These test loads can be different from vendor to vendor. Once the test load is defined in the IBIS
model, the simulator can derive the time it takes to reach the voltage measure point under the test
load condition. The simulator then subtracts this test load delay from actual system load delay in order
to report the correct flight time from the Driver to the Receiver. For XTK (View logic) users, this is
called TIME_TO_VM. The time it takes to reach the voltage measure point. Without the test load, the
simulator cannot calculate this TIME_TO_VM. TIME_TO_VM is automatically calculated when the
IBIS model is translated to XTK (using ibis2xtk). This timing analysis cannot be performed if the test
load conditions are not provided in the IBIS model. Typical flight time analysis is shown in Figure 7.

Figure 7: Flight time analysis

Tflight (max) <= Tclkper- Tco(max) Ts min PCB skew CLK Jitter
Tflight (min) >= Th Tco + PCB skew
Where Tclkper is Clock period, Tco is Clock to out time of the driver, Ts is the setup time, Th is hold
time. PCB skew account for the skew introduced by traces during routing.

Timing parameters in IBIS

[Model] DS00C032_I/O
Model_ type I/O
Polarity Non-Inverting
Enable Active-Low
Vinl = 0.8V
Vinh = 2.0V

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Vmeas= 1.50V
Cref = 8.0pF
Rref = 10.0K
Vref = 0.0V

The four parameters shown in blue letters in the above list are the timing test load and they should
be added for the Output, 3-state, I/O models etc. Model users do not need to run any simulations or
analysis to obtain these timing test loads. Just pick them off the datasheet AC test load conditions.

Vmeas = Output Voltage measure point. Typically Vdd/2

Vref = Test load pull-up or pull-down reference voltage
Rref = Test load resistive value
Cref = Test load Capacitive value
Typical AC test loads are given below.
Vcc

Input

Output

Vmeas=1.5
Vref = 0.0
Rref = 1000
Cref = 50pf

Co

CL include load and stray

capacitance
Input PRR is 1.0MHz, Th is 500ns

AC test Circuit
Q
50

Vmeas = 1.5
Vref =1.5V
Rref = 50
Cref = 0pf

VT = 1.5V
3.3V I/O output load
equivalent.
Figure 8: AC Test Loads
Two typical datasheet test loads are shown in Figure 8. The first figure shows a Capacitive load to
GND. This value of CL was 50pF for a logic device. Cref represents this load. Since there is no Rref, it
is assumed to be high-impedance. The second figure illustrates a different test load for a Memory
device and the IBIS test load description is shown on the right.

2.1.2.4

[RULE]

The models should be checked for availability of all types of buffer models the IC
support.

In certain cases a particular IC may support different type of interfaces. For instance MPC931 PLL
clock driver has LVPECL, and LVCMOS interface. It should be ensured that all these models are
available. For instance MPC940L clock driver has two independent supplies; one for input section and
one for output section. So the proper combination of the buffer models has to be selected. In case of
FPGA, the I/O banks can be configured in LVTTL, LVPECL, LVCMOS2.5, LVCMOS3.3, HSTL logic etc.
Even in HSTL it can be configured as Class 1, 2, 3, 4. Even in a particular family or Class the outputs

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can be selected for Slow/Fast outputs. Figure 9 shows the outputs of a fast and slow driver. Hence
proper care has to be taken in selecting the buffer model, which has been used in the design.

Figure 9: Outputs from a fast driver and slow driver.

2.1.2.5

[RULE]

In case of a differential signal, proper check should be done for the presence of the
model for both p and n and whether the [Diff_Pin] statement is there for associating
a P driver/receiver with the N.

SI analysis tools like Specctraquest can automatically detect a differential pair topology if pair of nets are identified as
differential pair by using the [Diff_Pin] statement in IBIS model. We have seen many IBIS models where the [Diff Pin]
statement is missing for a differential pair. Hence, if the device has any differential pair signals, the IBIS model should
be manually checked for the [Diff_Pin] statement. An example of a [Diff_Pin] statement is shown below:
|**********************DIFF PIN*********************************************
[Diff_pin] inv_pin vdiff tdelay_typ tdelay_min tdelay_max
|
E8
F8
250mV
0ns
NA
NA
B7
A8
250mV
0ns
NA
NA

2.1.2.6

[RULE]

The models should be checked for presence of minimum, typical and maximum
values for C comp, R, L & C data of the package.

The models should have the minimum, maximum and typical values of C_comp, R, L and C of the
package and V/I and V/T tables. Following figures will illustrate the input and output structure of IBIS
model.

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Figure 10: IBIS input structure model

Following are the parameters required to model the Input structure:

C_pkg: Package capacitance
R_pkg: Package resistance
L_pkg: Package Inductance
The C_pkg is the Lumped Capacitance value due to the package. Similarly L_pkg and R_pkg are
lumped resistance and inductance values due to the package. This value is specific for each package
and should have values specified at minimum, maximum and typical conditions.
C_comp is a key parameter particularly for receiver inputs and should be characterized and
provided in the model. C_comp defines the silicon die capacitance and does not account for the
package capacitance. Typ, Min and Max values for C-comp have to be there in the IBIS model.

Figure 11: IBIS Output Structure Model

Following are the parameters required to model the Output structure:
C_pkg: Package capacitance
R_pkg: Package resistance
L_pkg: Package Inductance
C-pkg, L_pkg and R_pkg are lumped capacitance, inductance and Resistance which are specific
to package.
C_comp: Output pad capacitance of device. Minimum, Maximum and typical values exist for this
C_comp also.
If individual R_pin, L_pin and C_pin are specified, then the global package parameters mentioned
above are ignored. IBIS also allows detailed package information through matrices where mutual as
well as self-numbers can be specified (e.g.. Rij, Lij and Cij).

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An example of package/pin data is shown here.

Package/Pin data
|**********************************************************************
|
[Pin] signal_name model_name
R_pin L_pin C_pin
|
1 AGND
GND
.0m
2.52n 0.24p
2 RCLK_R/F
DS92LV1210_CTL
50.0m 1.96n 0.30p
3 REFCLK
DS92LV1210_CTL
50.0m 1.45n 0.20p
4 VCC
POWER
50.0m 1.14n 0.14p
5 RI+
DS92LV1210_RI
50.0m 1.15n 0.05p
6 RIDS92LV1210_RI
50.0m 1.18n 0.08p
7 PWRDN*
DS92LV1210_CTL
50.0m 0.87n 0.07p
8 REN
DS92LV1210_CTL
50.0m 0.87n 0.07p
9 RCLK
DS92LV1210_ROUT 50.0m 1.18n 0.08p
10 LOCK*
DS92LV1210_ROUT 50.0m 1.15n 0.05p
11 AVCC
GND
50.0m 1.14n 0.14p
12 AGND
GND
50.0m 1.45n 0.20p
13 AGND
GND
50.0m 1.96n 0.30p
14 DGND
GND
50.0m 2.52n 0.24p
15 ROUT9
DS92LV1210_ROUT 50.0m 2.52n 0.24p
16 ROUT8
DS92LV1210_ROUT 50.0m 1.96n 0.30p
17 ROUT7
DS92LV1210_ROUT 50.0m 1.45n 0.20p
18 ROUT6
DS92LV1210_ROUT 50.0m 1.14n 0.14p
19 ROUT5
DS92LV1210_ROUT 50.0m 1.15n 0.05p
20 DGND
GND
50.0m 1.18n 0.08p
21 DVCC
POWER
50.0m 0.87n 0.07p
22 DGND
GND
50.0m 0.87n 0.07p
23 DVCC
POWER
50.0m 1.18n 0.08p
24 ROUT4
DS92LV1210_ROUT 50.0m 1.15n 0.05p
25 ROUT3
DS92LV1210_ROUT 50.0m 1.14n 0.14p
26 ROUT2
DS92LV1210_ROUT 50.0m 1.45n 0.20p
27 ROUT1
DS92LV1210_ROUT 50.0m 1.96n 0.30p
28 ROUT0 D
S92LV1210_ROUT
50.0m 2.52n 0.24p
|
[Diff_pin] inv_pin vdiff
tdelay_typ
tdelay_min
tdelay_max
|
| The '+' pin is Diff_pin and the '-' pin is the inv_pin
|
5
6
0.1
0
0
0
The per-pin package numbers are the self-resistance, self-inductance and self-capacitance. Most
companies involved in packaging generate package matrix with all the self and mutual numbers. Even
if the mutual numbers are not given self-numbers should be present in the IBIS models.

Accurate package parasitic can have an impact on high-speed Signal Integrity Analysis. IBIS also
allows very detailed package modeling through filename.pkg file. [Resistance Matrix], [Inductance

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Matrix] and [Capacitance Matrix] can be defined within the package model. These files may be
available only through NDA.

2.1.2.7

[RULE]

The models should be checked for presence of minimum, typical and maximum
values for pull up and pull down V/I curves, Power clamp, ground clamp and V/T
tables

The data points under keywords [Pulldown], [Pullup], [GND Clamp], [POWER Clamp] define the
V/I curves of the pull-down and pull-up structures of an output buffer and the V/I curves of the
clamping diodes connected to the GND and the POWER pins, respectively. Currents are considered
positive when their direction is into the component.
[Power Clamp]: V/I table of the upper ESD structure if present
[GND Clamp]: V/I table of the lower ESD structure if present
[Pullup]: Voh/Ioh data for the output in High state
[Pulldown]: Vol/Iol data for the output in Low state
[Ramp]: dV/dT data for both rising edge and falling edge into a resistive load. The dV/dT is measured
from 20% to 80% of the signal swing.
In each of these sections, the first column contains the voltage value, and the three remaining
columns hold the typical, minimum, and maximum current values. The four entries, Voltage, I (typ),
I(min), and I(max) should appear on a single line and must be separated by at least one white space
or tab character. All four columns are required under these keywords. However, data is only required
in the typical column. If minimum and/or maximum current values are not given, the reserved word
"NA" must be present. "NA" can be present for currents in the typical column, but numeric values
MUST be specified for the first and last voltage points on any V/I curve. Each V/I curve must have
at least 2, but not more than 100, voltage points.
Monotonic Requirements:
To be monotonic, the V/I table data must meet any one of the following 8 criteria:
1- The CURRENT axis either increases or remains constant as the voltage axis is increased.
2- The CURRENT axis either increases or remains constant as the voltage axis is decreased.
3- The CURRENT axis either decreases or remains constant as the voltage axis is increased.
4- The CURRENT axis either decreases or remains constant as the voltage axis is decreased.
5- The VOLTAGE axis either increases or remains constant the current axis is increased.
6- The VOLTAGE axis either increases or remains constant as the current axis is decreased.
7- The VOLTAGE axis either decreases or remains constant as the current axis is increased.
8- The VOLTAGE axis either decreases or remains constant as the current axis is decreased.
An example of V/I curve is for Pull-up, Pull down, GND clamp and power clamp is given below.
[Pulldown]
| Voltage
Ityp)
I(min)
I(max)
|
-5.0V
-40.0m
-34.0m
-45.0m
-4.0V
-39.0m
-33.0m
-43.0m
|
.
|
.
0.0V
0.0m
0.0m
0.0m
|
.
|
.
5.0V
40.0m
34.0m
45.0m
10.0V
45.0m
40.0m
49.0m
|
[Pullup]
| Note: Vtable = Vcc - Voutput
|
| Voltage
I(typ)
I(min)
I(max)

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|

|
|
|
|

-5.0V
-4.0V
.
.
0.0V
.
.
5.0V
10.0V

32.0m
31.0m

30.0m
29.0m

35.0m
33.0m

0.0m

0.0m

0.0m

-32.0m
-38.0m

-30.0m
-35.0m

-35.0m
-40.0m

|
[GND Clamp]
|
| Voltage
I(typ)
I(min)
I(max)
|
-5.0V -3900.0m -3800.0m -4000.0m
-0.7V
-80.0m
-75.0m
-85.0m
-0.6V
-22.0m
-20.0m
-25.0m
-0.5V
-2.4m
-2.0m
-2.9m
-0.4V
0.0m
0.0m
0.0m
5.0V
0.0m
0.0m
0.0m
|
[POWER Clamp]
| Note: Vtable = Vcc - Voutput
|
| Voltage
I(typ)
I(min)
I(max)
|
-5.0V
4450.0m
NA
NA
-0.7V
95.0m
NA
NA
-0.6V
23.0m
NA
NA
-0.5V
2.4m
NA
NA
-0.4V
0.0m
NA
NA
0.0V
0.0m
NA
NA
V/T table data contains the switching characteristics over time. The IBIS specification supports 100
waveform tables per model keyword. But, many times, model developers look at the examples in an
IBIS specification to understand the loading conditions they should apply. Since only two examples
are shown, they end up providing exactly two V/T tables under the same loading conditions as the
examples in the specification. The ideal case is to provide 4 V/T tables: 2 for the Rising waveform
and 2 for the Falling waveform. The combination of all these 4 V/T tables truly captures the turn-on
and turn-off of the P-channel and N-channel transistors. V/T tables are shown in Figure 12

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Figure 12: V/T Table

V/T waveform Data

[Rising Waveform]
R_fixture = 50.000
V_fixture = 3.30
V_fixture_min = 3.00
V_fixture_max = 3.60
C_fixture = 0pF
L_fixture = 0nH

[Falling Waveform]
R_fixture = 50.000
V_fixture = 3.30
V_fixture_min = 3.0
V_fixture_max = 3.60
C_fixture = 0pF
L_fixture = 0nH

[Rising Waveform]
R_fixture = 50.000
V_fixture = 0.00
C_fixture = 0pF
L_fixture = 0nH

[Falling Waveform]
R_fixture = 50.000
V_fixture = 0.00
C_fixture = 0pF
L_fixture = 0nH

For a SPICE translated model, the *_fixture values are zero.

For a Measurement based model, use proper *_fixture values

Some simulators are sensitive in using these V/T tables. If all the sub parameters are not provided, they
may resort back to the Ramp numbers and throw away the V/T tables. Consult with your EDA vendor for
multiple V/T support. V/T tables ensure accurate modeling of the switching behavior of I/O buffers.
In case of IBIS models, if Vmeas is not defined in the model, SI Analysis tool will not accept the model
loaded against the device list.
2.1.2.8

[REC]

The model may be simulated for specified load, voltage level conditions in the data
sheet to cross check the results with the data sheet

The model may be simulated with the specific load, voltage swing in the data sheet for cross
checking the values given in the data sheet.
It is highly recommended to plot out the V/I and V/T curves. A graphical view can show various
strange details that are missed in the ASCII file. Examples are shown below.

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The waveforms in this page were obtained using the s2iplt tool. But the same can be obtained and
checked using the visual IBIS editor from Mentor Graphics.

Figure 13: s2iplt Waveform

This is a [Power Clamp] data of a model. The vendor never bothered to view the data before
distributing the model. While the scale shows very little current, this sort of non-monotonic data can
throw off some simulators. For V/T data, graphical viewing of the switching waveform is critical. Some
weak buffers may not be able to drive 50 Ohm (heavy load) and you may see a flat line over the
entire sweep range.

Figure 14: s2iplt Waveform

The model for Maximum conditions never passes through (0,0,0) which cannot happen in reality.
Most likely it is an offsetting error and errors of such type should be checked out. Sometimes a
SPICE simulation may not converge over the full IBIS specified sweep range. In that case the user
tweaks the sweep range to the point it converges and then extrapolates the data to the end point.
All the Typ, Min and Max tables need to span the proper voltage ranges (since each is referenced
to its own Vdd value). Since [Pull-up] V/I tables are offset by Vdd, this becomes a critical step.
Many other instances of strange data can be shared but the importance of plotting out the data is
very critical. This is a valuable step for both the Model developer and the end user.

2.1.3 IDN Identifying Critical Interfaces

2.1.3.1

[RULE]

The nets having very fast drivers should be simulated

For a net to become critical from signal Integrity point of view, the Rise time of signal is a very
important parameter. Driver having good drive capability produces fast edge rate signals on the
traces. And if the traces are not properly terminated, these fast edges can cause multiple
reflections along the trace causing Signal Degradation. To account for such cases, the nets having
Fast Drivers (typ. having drive > 4mA or above 20MHz) should be simulated to ensure the signal
quality. Speaking in terms of Signal time, the nets having signal rise time less than six times the
propagation delay on the trace should be simulated. Typically if the trace delays are shorter than

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one sixth of the signal rise time, the interconnect behaves like a lumped circuit, there by restricting
all the reflections within the rise time area, giving clean logic levels. Figure 15 shows a waveform
for an unterminated net with FAST driver versus a slow driver simulated under same conditions.

Figure 15: Effect of Fast Drivers on unterminated nets

2.1.3.2

[RULE]

The nets having very sensitive receivers should be simulated

In some cases, Interfaces may have Receivers, which are very sensitive. For Example Receivers
may have small overshoot and undershoot limits. Crossing these limits can degrade the device
reliability and may cause device failure. In such cases, it becomes more critical to ensure that the
signal at the receiver pins never crosses these limits. Simulation should be done on these nets to
ensure signal quality. It is ideal to limit the undershoot to 0.5V though the chip can withstand more
than that. The reason is the high undershoot will be followed by ringing with is of higher frequency
and the impact of this on the Vcc and ground may cause Signal Integrity issues for the rest of the
circuit. If the undershoot limit is stringent than 0.5V then that value of the IC should be taken in to
consideration.
2.1.3.3

[RULE]

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The nets having long traces should be simulated.

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For a given driver/receiver topology, large trace lengths can make an interface critical from SI point
of view. There are two reasons. First, Signal integrity of a net becomes critical when the trace delays
become comparable with the rise and fall time of the driver. Figure 16 shows the signals at a receiver
for which the distance to driver is 1inch (Blue) and another for which the distance to driver is 4 inches
(Red). The same driver and receiver combination is used to generate both the signals. Second,
timing issues may crop up if the driver cannot drive long traces.

Figure 16:Effect of trace length on signal quality.

2.1.3.4

[RULE]

The nets should be identified based on the functionality

Nets, which are critical from their functionality point, should be simulated. For this all the nets can
be categorized as per their functionality. For example:
Clock Nets: Validate clock timing distribution, check clock waveform at destination, confirm clock
skew designs, validate clock signal termination, build clock skew budget
Address/Data Bus Signals: Validate Bus topology, validate bus termination scheme, validate
bus signal integrity, validate bus timing, validate bus driver tolerance
I/O Signals: Differential I/O, Line terminations for critical I/O, I/O Noise coupling from/into board.

2.1.3.5

[RULE]

Interfaces having stringent timing requirements should be simulated

As the frequency of operation increases the timing margins available for accounting Trace delays,
clock skew, finite rise and fall times becomes small. The interfaces that are timing critical (having less
margins) should be simulated to find left out margins available for these factors.
.
2.1.3.6

[RULE]

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Board to Board interfaces, Test interfaces and Emulator interfaces has to be

simulated for effective termination

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Board-to-Board interfaces should be simulated. Interfaces provided only for test purposes should
be simulated. These interfaces will be left open when the test equipment is not connected. So these
interfaces should be simulated to see the effect of the test interface on the main signal path for both
the cases where test equipment is connected and not connected. For example many signals on a
board may be connected to a logic analyzer header (MICTOR connector). This may be acting as an
open stub when logic analyzer is not connected. The net should be simulated with and without logic
analyzer and proper guidelines should be given for routing and placement so that the effect on the
main signal path is minimal.
Similarly the interfaces used for emulators and other programmers should be simulated and see
the effect in their absence. Proper terminations are to be ensured for test/emulator interfaces.

Figure 17: Signal deterioration due to a stub caused by test interface.

2.1.3.7

[RULE]

All Edge triggered signals should be simulated

For example, an interrupt signal is normally considered to be a static signal and usually not
considered for SI analysis. But if it is an interrupt signal which is edge triggered, problems will come if
the signal is not monotonic. For a normal level triggered signal, if the trace length is small
(propagation delay less than half the rise time), then the reflection occurs within the rising edge of the
signal and we can ignore that because the receiver will not sample the signal during that rising edge.
But if it is an edge-triggered signal, then we cannot ignore any non-monotonic edge. This applies for
any clock signal also (as most of the clocks may go to some edge triggered Flip flop).

2.1.4 TES Test Conditions

2.1.4.1

[RULE]

The trace lengths should be decided based on the specified/maximum frequency of

operation

As per the tool, we can have an infinite length of the trace with proper termination. The reality is the
capacitance of the trace comes in to the picture and if you consider a 200 MHz signal you may not
have any signal at the end of the long trace. For example consider the case of a source termination
how the trace length should be decided.
Normally source termination is decided based on following:

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1. to avoid transmission line reflections by proper termination.

2. the value is selected based on the drive capability of the driver. If the driver has 20-Ohm output
impedance, we may have to place 30 Ohm for proper termination when using 50-Ohm trace to take
care of (1). But this is not always true. If the trace length is so large or the drive strength is so poor in
spite of good rise time at the output of the driver, which normally is the case, the series resistor will not
be 30 Ohm. The value may have to be less than 20 Ohm. Treat R as the source termination resistance
and C as the total capacitive load (trace capacitance+ Input pin capacitance + load capacitance) and
apply 2.2RC for getting the rise time (assuming infinite current source). Even for a slow logic like TTL,
the peak currents are as high as 600 mA. Hence it can be approximated that the driver is an infinite
AC current source. Based on the application, proper value can be selected to keep the 2.2RC value
under control. If the application demands for sharp rising edges, then the effect on the rise time due
to Output impedance of the device and output pin capacitance also has to be considered for limiting
the trace length. Compute 2.2RC separately for the chip parameters and load parameters. The root
mean square value of both these values will give an approximation of the rise time.
2.1.4.2

[RULE]

Double-ended signals should be simulated as differential nets.

Differential nets should be simulated in differential mode only since what matters at the receiver
end is a differential signal and not the individual signals of the differential pair w.r.t. Ground. There are
cases where the signals when simulated as single ended signals show good signal quality but when
viewed differentially the quality may not be same. To prevent such false SI results differential signal
quality must be analyzed. For example Figure 18 shows a differential signal when P and N signals
are routed properly, with zero skew. Figure 19 shows a differential signal for the same driver/receiver
termination and topology but with a skew between P and N. Figure 20 shows the single ended signal
for both the cases. The single ended signal is good in quality in both the cases. But we can see the

deterioration in the differential signal in Figure 19, which would have been left unnoticed if it were not
simulated differentially.
Figure 18: Differential Signal - Properly routed and Terminated

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Figure 19: Differential Signal with a skew between P& N

Figure 20: Single Ended Signal (P/N)

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2.1.4.3

[RULE]

Source synchronous signals should be simulated along with the strobe signal.

About source synchronous timing: many of the high speed interfaces nowadays use source
synchronous timing to take care of the timing margin reduction due to propagation delay on the board.
As operating frequency of the interfaces increases, the propagation delay of the signal in PCB which is
about 1 ns/ 6inch becomes a considerable percentage of the time period of the clock in a common
clock signaling environment. To take care of this problem, modern high speed buses like Intel AGTL+
Data and Address bus(used in Pentium IV), DDR SDRAM Data bus use Source synchronous timing
where along with the Data/Address a strobe signal is also driven by the driver. At the receiver end the
data/address will be sampled with respect to the strobe signal, and not with respect to the local clock.
So during PCB routing if we match the delay of the data and the strobe signal, the propagation delay
in PCB will not reduce the timing margin.
For simulation of Data and Strobe together, both the data and strobe topologies need to be extracted
together (this is supported by Cadence Specctraquest SigXP v15.0 or above). In Specctraquest, we
can use the Custom Measurements feature to automatically check the data setup and hold timings
with respect to strobe. However, for batch simulation of large number of nets, MS excel sheet based
approach can be used to check the data setup and hold with respect to strobe.

2.1.4.4

[RULE]

For IBIS models using the [Model Selector] keyword, ensure that the proper model
is selected in the SI analysis tool during simulation.

About [Model selector] keyword used for programmable buffers: IBIS uses [Model Selector]
keyword to model Programmable I/O buffers. Programmable I/O buffers are the I/O buffers where
different buffer models (with individual V-I and V-t curves) are provided for one Pin. This is used
for configurable I/O buffers. For example, in Micron DDR2 SDRAMs, on die termination is
available for Data(DQ), Strobe(DQS/DQS#), Data Mask(DQM). The value of this termination
resistor is configurable to Open (i.e. no termination)/50ohm/75ohm/150ohm. For each of those
values, the V-I and V-t curve of the I/O buffer will be different. To support these different values of
termination resistors, [Model selector] option is used in the IBIS model as shown below(Taken
from Micron MT47H64M4BP DDR2 IBIS model):
[Model Selector] DQ
|
DQ_FULL
Full-Strength IO Driver with
DQ_FULL_ODT50
Full-Strength IO Driver with
DQ_FULL_ODT75
Full-Strength IO Driver with
DQ_FULL_ODT150
Full-Strength IO Driver with

no
50
75
150

ODT
Ohm ODT Submodel
Ohm ODT Submodel
Ohm ODT Submodel

.
[Pin]
|
B7
......
C2
......
C8

signal_name

model_name

R_pin

L_pin

C_pin

DQS

DQ

63.0m

1.89nH

0.29pF

DQ1

DQ

77.6m

2.65nH

0.35pF

DQ0

DQ

77.9m

2.71nH

0.35pF

As shown above, in the [Pin] statement, model_name DQ is used and in the [Model Selector]
statement, options DQ_FULL, DQ_FULL_ODT50, DQ_FULL_ODT75, DQ_FULL_ODT150 are
given.
Similarly, for devices supporting different VCC voltages [Model selector] feature is used in the IBIS
model. For example, Texas instruments SN74LVC04A Hex Inverter supports 1.65-3.6V VCC. In
the IBIS model of SN74LVC04A provided by TI, three different voltages are supported: (i) 1.8V (ii)
2.5V and (iii) 3.3V as shown below:
|******************************************************************************
|
[Pin] signal_name model_name
R_pin
L_pin
C_pin
|

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1
1A
LVC04K_IN
2
1Y
LVC04K_OUT
3
2A
LVC04K_IN
4
2Y
LVC04K_OUT
................
..............(additional lines not shown)...

4.700e-02
5.100e-02
4.100e-02
3.900e-02

4.867e-09
4.083e-09
2.915e-09
2.561e-09

7.060e-13
5.920e-13
3.760e-13
2.880e-13.....

|******************************************************************************
| Model LVC04K_OUT
|******************************************************************************
|
[Model Selector]
LVC04K_OUT
|
LVC04K_OUT_18
1.8 volt Vcc
LVC04K_OUT_25
2.5 volt Vcc
LVC04K_OUT_33
3.3 volt Vcc
As shown above, Pins 1Y and 2Y has been assigned buffer type LVC04K_OUT which has [Model
selector] options LVC04K_OUT_18 , LVC04K_OUT_25, LVC04K_OUT_33 for 1.8V/2.5V/3.3V
VCC.
During the simulation by the SI analysis tool, one of these three models need to be selected for
SN74LVC04A. Newer versions of SI analysis tool usually allow selection of one of these models
through some menu. For example, In Cadence Specctraquest(i.e. Allegro SI 630) tool , this option
is available in the RefDesPins Tab in the signal model assignment menu. An example is shown in
the following diagram:

Figure 21: Selection of programmable buffer in specctraquest

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In case the SI analysis tool does not support [Model selector] feature, we need to edit the [Pin] list
of IBIS model to use the IBIS model we want. For example, if we are using 3.3V for the
74LVC04A buffer mentioned above, then we need to manually edit the IBIS model to change the
model_name of pins 2 and 4 from LVC04K_OUT to LVC04K_OUT_33.
Please refer to IBIS specification 4.0 for mode details about the model selector option.

2.1.5 TER Termination Strategy

2.1.5.1

[REC]

Termination strategy for different logic families may be followed as per the white
paper Interfacing different logic families

2.1.5.2

[REC]

Termination Strategy for Signal Integrity may be followed as per the white paper
Termination strategies for good Signal Integrity

Figure 22 illustrates the effect of termination on a particular signal.

Figure 22: Effect of terminations on a signal

The white paper Termination strategies for good signal integrity will give detailed explanations on the different
terminations

2.2 PRE Guidelines for Pre-Layout Analysis

2.2.1 REQ Test Requirements
2.2.1.1

[RULE]

One should arrive at an overview of topologies and the distances between various
devices

The Rough Placement of major components at the initial stages of Pre-Layout Analysis is helpful
from the point of deciding Net lengths for all interfaces. After the placement is over the Manhattan
distances between two interfacing devices may be used as the approximate trace length for nets
under simulation(Note: Manhattan distance means distance x +y where x is the horizontal distance
and y is the vertical distance between two points) . The validity of the Guidelines/Results generated

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by pre-layout analysis for the final board, depends on how closely the rough placement approaches
the actual placement on board. And depending on the trace lengths the termination component values
will differ. For more details about termination strategies [Termination Strategies for good Signal
Integrity] document may be referred.
Doing sample routing, one can arrive at the topologies and distances. Before waiting for the
routing of the entire board to complete, the SI engineer can get accurate information about the
topology, trace lengths and trace characteristics for all the critical interfaces. This is achieved by
completing the routing of one or two nets each in all the interfaces first. The information from this
routed sample nets can be used for an accurate simulation of all the critical interfaces.

There are basically three types of Topologies possible for the nets. Point-to-point topology,
Daisy Chain topology and star topology and a combination of star and daisy chain is also possible.
In a point-to-point topology, a diver is connected to a single receiver. This is the best topology that
a signal can have for good signal integrity.

Driver
1

Load
1

Driver
2

Load
2
Figure 23: Point to Point topology

When a number of receivers are connected to a single driver we may go for a daisy chain topology
In a daisy chain topology, the driver output is connected to 1st receiver, then from the 1st receiver pin
nd
rd
to the 2 receiver and from there to the 3 and so on. There will not be any stubs and if it is a critical
net, it is usually terminated at the end.

Load
1

Load
2

Load
3

Driver

Figure 24: Daisy Chain Topology

Though daisy chain is good in terms of signal quality in a point to multi-point topology, there will be
a skew between the signals reaching at different receivers. If this skew is not tolerable then a star
topology is preferred. In a star topology, a single driver will be driving multiple receivers and each
of the receivers will have a direct path to the receiver. Zero skew is achieved by having equal trace
lengths to all the receivers. The trace will be split at the driver and will be routed separately to each
of the receivers.

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Load
2
Load
1

Load
3

Driver

Figure 25:Star Topology

In some cases where the signal is not very critical, a combination of daisy chain and star may be used
for ease of routing. The following figure illustrates an example for mixed topology.

Load
2

Load
3

Load
4

Load
5

Driver
1
Load
1

Figure 26: Mixed Topology

The trace lengths constraints and termination strategy will differ for each topology. Also some
topologies are more critical from signal integrity point of view, like as Signals in star topology and daisy chain
topology will have more signal integrity issues compared to point to point interfaces. The details about
Topologies and recommended termination strategies are provided in the VSBU white paper Termination
strategies for good signal Integrity. Measure all points in daisy chain or star topology.

2.2.2 SIM Selection of Simulation Environment

2.2.2.1

[RULE]

Proper inputs on trace impedance, velocity and properties of PCB material should
be provided

The validity of simulation results greatly depends on the correctness of the simulation
environment. The parameters given under this should be accurate and closely match with the real
board characteristics based on the PCB stack-up . Following are the few parameters required for
setting the pre-layout simulation environment:

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Trace Impedance
The characteristic impedance of the trace is one of the most important parameter in SI
analysis. It is the input impedance of a infinitely long uniform transmission line. A uniform line
terminated in its characteristic impedance will have no standing waves, no reflections from the
end, and a constant ratio of voltage to current at a given frequency at every point on the line. For a
trace the characteristic impedance is a constant, which is a function of the geometry of the trace
and the PCB material used. Characteristic impedance typically used in printed circuit boards vary
from 50 to 75 ohms. The characteristic impedance can be easily calculated from the trace
geometry parameters using the softwares like ultra cad. Boards with controlled impedance will be
expensive compared to the non-controlled impedance boards. Hence proper judgment has to be
taken by the designer while selecting the controlled impedance.

Trace Signal velocity

Trace velocity is another important parameter, which will determine the simulation
accuracy. It is also a function of the trace geometry and the PCB material. It is proportional to the
series inductance and parallel capacitance of the trace per unit length.

PCB material
The properties of the PCB material like r, is a factor, which will decide the trace velocity and
trace impedance. So the accurate values of PCB parameters are critical in determining the accuracy
of the simulation.
2.2.2.2

[RULE] All the layer details and reference voltages should be properly verified and
confirmed.
While creating the SI Analysis Tool input from the Layout tool, it should be made sure that the stack
up details are properly taken by the tool. If not, it is to be manually edited to ensure the correct
simulation. Also, all the reference voltages should be verified in the database.

2.2.2.3

[REC]

Approximate number of vias on a net may be estimated and can be modeled in the
pre-lay out simulation.

Vias lower the desired impedances because of their inherent capacitance. The impedance mismatch from
the vias causes signal degradation due to reflections
Approximate number of vias that may be coming in a signal path can be estimated and can be included in
the pre-layout simulation. This will improve the accuracy of the simulation. Most of the present tools have
the option of generating via model based on theL stackup.
C

Figure 27: Equivalent model of a via.

The values of the parasitic capacitor & inductor of via can be calculated from the board parameters
like
D2 is diameter of Antipad,
D1 is diameter of the pad,
T is thickness of the board,
Er is the dielectric constant,
h is the length of the via,
d is the Via hole Diameter

The Via Capacitor and Inductor can be calculated as

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Cvia = 1.41*Er*T*D1 pF,

D2-D1

L= 5.08*h[ ln(4*h/d)+1] nH

From the topology of the net one can arrive at an approximate number of vias that will come on a net. For
example, for the nets running between two SMD components, at least two vias will be there unless the net
routed completely on top layer.
Note: To avoid this manual calculation of via capacitance/inductance during pre-layout simulation, a
recommended method would be to request the layout engineer to route one or two nets with a few vias (of
each diameter to be used in the final board) in the un-routed board. When this net will be extracted, the via
model will be automatically created by the tool. This model can be copied and reused for simulating other
nets during pre layout analysis..
2.2.2.4

[RULE]

In case of nets with multiple drivers, simulation should be done for all the cases
where each of the drivers is made to drive the bus.

When there are multiple drivers on a net, the signal quality at the receivers, should be ensured
when any of the drivers is driving the bus. The signals from different drivers may be different even if
they are of the same type by virtue of its position. For example, for a processor interface net shown in
Figure 28 , the simulation should be carried out for the cases when
1. D1 is driving
2. I/O1 is driving
3. I/O2 is driving
4. I/O3 is driving
5. And I/O4 is driving.
For all the cases, the signal quality at all the inputs (R1 and I/O1 to I/O4) should be monitored.

D1
I/O1

I/O3
I/O2

I/O4
R1

Figure 28: A net with multiple drivers.

2.2.2.5

[RULE]

All Power/GND nets should be identified and assigned with proper voltage

If we do not identify the Power/GND nets in the design, then SI analysis tool will consider the
Power/GND nets like any other nets and if we try to extract the topology of any net which has any
Pullup/Pulldown/Parallel termination to VCC/GND, then the tool will try to include the whole power net
with all the Decoupling capacitors and other components connected to that Power net! Hence, it is
very important that the Power nets are identified and assigned with proper DC voltages. Ground
should be assigned with 0 Volts. In Cadence Specctraquest(i.e. Allegro PCB SI),tool this is done
using the Menu Logic -> Identify DC nets.

2.2.3 FID Signal Fidelity Checks

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2.2.3.1

[RULE]

All AC Design Rule Checks should be carried out for both the Maximum and
minimum models of the chips.

Ringing

Figure 29: AC DRC parameters

This function is measurement of all the electrical parameters of a signal for good Signal Integrity. The
parameters for which the simulation results should be looked into are as follows:
Overshoot: Overshoot is that part of the signal that transitions above Vcc when measured at the
receiver pin.
Undershoot: Under shoot is the signal transition below Vss when measured at the receiver pin. It
should be ensured that at all the points, signal overshoots and undershoots are within the
tolerable limits of the receiving device. As a rule it should be ensured that the undershoot at no
receiver input goes below -0.5 V in case of ordinary devices. If the device ask for a tighter limit on
the undershoot, the data sheet specifications must be followed.
Ring-back: Ring-back is measured as that part of the signal that crosses Vcc in the negative
direction to its lowest value (for low to high transitions) and that part of the signal that crosses
Vss in the positive direction to its highest value (for high-to-low transitions). Care should be taken
to see that the ring back is not crossing the threshold.
Settling time: It is the time required by the signal to settle around a signal value. The settling
time will be different based on the percentage of the value to which the signal settles.
Rise time: The time required by the signal to rise from 10% to 90% of the signal value.
Fall time: The time taken by the signal to fall from 90% to 10% of the signal value.
Delay: The time measured between the same signal at the source and at the receiver at their
50% crossing points.
Duty cycle: It is the ratio of high level width to total period multiplied by 100.

These parameters should be checked at the point near the receiver pins. For the most critical
nets, varying one or more of the following parameters, one should do a sensitivity analysis:

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Stub length
Trace Impedance

Dielectric constant (r)

Termination resistor
Driver strength (fast/slow)

For example, incase of daisy chain topology with multiple loads above parameters should be
checked near each receiver along the chain. As the terminating components will always have some
finite tolerance, the simulation should be done for the values of these components varied over a
range. The simulation results should suggest the maximum tolerances the devices can have
preserving the signal quality. The signal integrity should be checked for both minimum and
maximum conditions of the IBIS model

2.2.4 GEN Generation of Component Selection, Placement and Routing Guidelines

2.2.4.1

[RULE]

The tolerances of the passive components used in the interfaces should be decided

This is to stress on the tolerance requirements of the components selected for the termination.
We dont need very high tolerance i.e better than 10% for these components. Proper selection of
tolerances should be done accordingly.

2.2.4.2

[RULE]

The placement of the termination components should be identified. Termination

placement at non-ideal positions should be simulated and margin for placement
should be provided.

During simulation of a net the placement of the terminating components is usually considered to
be in ideal position. For example, series termination kept right at the driver output pin.
But in actual board placement, it may not be always possible to keep these components at their
ideal locations due to various space constraints. Placing the termination far away from the ideal
position may kill the signal quality. But some margin can be allowed for the placement. The following
figure shows a comparison on signal quality between the signals with termination placed at ideal and
non- ideal positions.

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Figure 30: Source termination at ideal and non-ideal positions.

This can be considered at pre-layout simulation itself. Simulation should be carried out; over a set of
non-ideal placements of these terminating devices and a margin should be provided as a placement
constraint for these terminating components. For example, for series terminating resistor the
constraint can be like maximum distance from the driver pin.
Another example can be end termination placed right at the end of the trace, near the receiver pin.
In case of end termination, if it cannot be placed at the receiver pin, it should be placed after the
receiver pin so that no stubs are there in the signal path. Figure 31 Shows the signal quality when the
end termination was placed before and after the last receiver on the net.

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Figure 31: Signal on end terminated line for ideal and non-ideal termination placements.

2.2.4.3

[RULE]

The placement guidelines should be generated based on the approximate

placement and results of simulation

After the Simulation of various interfaces based on the trace lengths derived from Rough
Placement, placement constraints can be generated for Final Placement of all the devices. These
suggestions should be based on the results achieved after the pre-layout analysis
2.2.4.4

[RULE]

The trace constraints should be given for all the critical nets which include min/max
trace lengths, trace impedance, trace spacing, trace width

For routing of the board, trace constraints should be given for all the nets which were identified as
the critical nets and which have been simulated for ensuring signal quality. The constraints should be
as follows:
Min-Max trace length.
Trace impedance
Trace spacing (Differential nets and Cross talk)
Trace widths (based on the current drive requirements)

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2.3 POS Guidelines for Post-Layout Analysis

In PostLayout Analysis, the SI Analysis tool input is obtained from the routed board through the
interface provided in the tool itself. The time of creation of the database depends on the size of the
layout. The factors to be taken into account in Post-Layout Analysis are as given below:

2.3.1 REQ Test Requirements

2.3.1.1

[RULE]

2.3.1.2

[RULE] All the layer details and reference voltages should be properly verified and
confirmed.

One should arrive at an overview of topologies and the distances between various
devices, if pre-layout simulation was not done.
Please refer to section 2.2.1.1 for explanation

While creating the SI Analysis Tool input from the Layout tool, it should be made sure that the stacks
up details are properly taken by the tool. If not, it is to be manually edited to ensure the correct
simulation. Also, all the reference voltages should be verified in the database.

2.3.2 FID Signal Fidelity Checks

2.3.2.1

[RULE]

All AC Design Rule Checks should be carried out for minimum and maximum
conditions of the IBIS model.

Refer to section 2.2.3.1 for explanation.

2.3.2.2

[REC]

All AC Design Rule Checks may be carried out in parallel with layout for the finished
critical interfaces for improving productivity

The AC design rule checks should be carried out for the routed critical interfaces while the Board
Routing Process is going on. This will enable SI group to give feedback well early in the process,
instead of waiting for completion of board routing fully. This will save considerable amount of time and
rework otherwise would have required.
2.3.2.3

[REC]

All AC Design Rule Checks for the full board may be carried out in batch mode and
all the critical/problematic nets may be identified.

When routing is fully complete, the simulation may be carried out over the full board for all the
interfaces in Batch Mode. Batch mode is used primarily to generate a report file containing delay,
cross talk, and illegal digital effects flags for more than one net at a time. From the results of batch
mode analysis, critical interfaces showing poor signal quality may be identified. The critical nets
should be individually analyzed in interactive mode, and suggestions should be arrived at for
improving the signal quality. To detect the signals, which are just meeting the SI cases, the report
thresholds can be derated by a known amount. This derating will include the marginal cases also in
the critical nets list and in interactive simulation thereby judging the severity.
A typical report file generated by Quad XNS is given below.
ERROR CODES:
T
M
D
S
O
B
Vgb
Vcb

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Threshold Error (did not cross a logical voltage threshold)

Multi crossing error (signal crossed a threshold multiple times)
Delay Error (delay longer than default delay error threshold)
Signal Quality Error (undershoot or overshoot threshold error)
Oscillation error (signal was not monotonic (see manual))
Ground or Supply Bounce threshold error (drivers only)
Ground bounce
Supply bounce

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VM: The specified VM numbers are the unloaded measurement time for the indicated
driver. This time should be added to the reported delay time to match the graphic
waveform. VM times are relative to start of RISING/FALLING cycle.

Delay Rise(ns)
Delay Fall(ns)
Overshoot(V) Osc(V) ERROR
min
max
min
max
Low
High
MAX
=============================================================================
CLKPCA
TX 4448
VM (lh) 2.52
VM (hl) 2.49
Vgb
0.00
0.00
Vcb
0.00
0.00
TX 4447
0.52
1.42
1.04
2.45 -0.63 -1.81
0.00
D
TX 4448
-0.75
-0.08
-0.30
0.75 -0.56 -1.75
0.00
D
TX 4447
VM (lh) 2.52
VM (hl) 2.49
Vgb
0.00
0.00
Vcb
0.00
0.00
TX 4447
-0.75
-0.08
-0.30
0.75 -0.56 -1.75
0.00
D
TX 4448
0.52
1.42
1.04
2.45 -0.63 -1.81
0.00
D
CLKPCA
-0.75
1.42
-0.30
2.45 -0.56 -1.75
0.00
D
-----------------------------------------------------------------------------=============================================================================
DQ29
U3 V4
VM (lh) 1.40
VM (hl) 1.09
Vgb
0.00
0.00
Vcb
0.00
0.00
U2 50
3.27
3.60*
-1.09*
3.63* -0.74 -2.46
0.26
TMD O
U3 V4
-0.43
-0.02
-0.35
-0.05 -0.02 -0.07
0.00
D
U2 50
VM (lh) 0.50
VM (hl) 0.69
Vgb
0.00
0.00
Vcb
0.00
0.00
U2 50
-0.40
-0.27
-0.55
-0.40
0.24 0.77
0.00
DS
U3 V4
1.21
4.50*
0.25*
4.31* -0.82 -1.49
0.22
TMD O
DQ29
-0.43
4.50*
-1.09*
4.31* 0.24 0.77
0.26
TMDSO
-----------------------------------------------------------------------------From the above report, it is clear that DQ29 is a critical net with lot of violations. So it should
analyzed interactively and corrective measures should be implemented.
2.3.2.4

[RULE]

All identified critical/problematic nets should be simulated in interactive mode and

Signal integrity improvements should be incorporated in the design.

Interactive mode allows the user to analyze a single net in real time, see the results of the
simulation immediately in the log file, and view a voltage versus time waveform for each of the nodes
on the analyzed net. Once the results of batch mode simulation are available, critical nets can be
identified and interactive simulation can be performed on these nets. Suggestions for improving signal
integrity can be given after analyzing the results of interactive simulation. The simulation should be
carried out over the tolerance range of the terminating component values.
2.3.2.5

[RULE]

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All identified critical/problematic nets and the neighboring nets should be re

simulated again to verify the correctness of changes made in the layout.

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2.4 Simulation of Multi Gigabit Signals (A Step Further)

During the last few years, serial interconnect technologies has matured to enable high speed switched
architectures with excellent performance and scalability, as well as low pin counts and cost. Clock
speeds do jump from 33-133 MHz in the parallel connectivity world, to 2-10 GHz in the serial
connectivity world.
As rise times have decreased and clock frequencies increased, new signal integrity problems have
arisen as weve reached new bandwidth regimes. For many high speed serial links (PCI-Express, XAUI
etc), we are now entering the regime where the losses from the transmission lines begin to affect signal
quality. If these effects are not anticipated and the design optimized to minimize these effects, the
product may not work.

2.4.1 Gigabit design challenges

1.
2.
3.
4.

Signal Loss dominates the design process

Pre-route stackup planning is required
Enhanced IC, IC packaging, connector, and via models are required
Transmission lines at Gigabit rates have much greater loss than at Megabit rates

2.4.2 Losses at Gigabit rates

When a high speed signal travels through a long PCB trace, the signal will be degraded due to
electrical properties of traces. The higher the frequency and longer the trace, higher the degradation is.
This is caused by the bandwidth limitation of the PCB trace. Figure 32 shows the simulated received
signal on a typical backplane trace ignoring and including the lossy effects.

Figure 32: 100 psec rise time, 2 GHz clock signal at the end of a 36 inch backplane trace, 4
mils wide in FR4, modeled as an ideal lossless line and as an ideal lossy line.
These frequency dependent losses are caused primarily because of the following losses:
1. Conductor losses

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With the increase of data rate, the currents tend to flow on the surface of wire. The higher the data rate
narrower is current path. Therefore higher is the resistance of trace. This is known as skin effect. The
skin depth is inversely proportional to the square root of frequency, making effective series resistance
of the line proportional to square root of frequency. At higher frequencies, series resistance will
increase and there will be more resistive heating thus causing losses.
2. Dielectric losses
The second important loss mechanism is the shunt leakage current through the dielectric material. All
insulators have some residual dipoles that can re-orient in an external electric field. As these dipole
move back and forth in the AC field of a signal, they create an AC leakage current. If they can respond
as fast as the field changes, the higher frequency components of the changing field will move the
dipoles back and forth faster and the shunt AC leakage current through the material will increase.
The amount of leakage current, which converts the dipole motion into heating up the dielectric, depends
on the number of dipoles in the material, the size of the dipoles and how far they can move in the field.
This intrinsic, bulk material property is described by the dissipation factor of the material. The larger
the dissipation factor, the more dipoles and the greater the amount of shunt leakage current.
Even with a constant dissipation factor, the amount of leakage current will increase with higher
frequency. This means the shunt leakage resistance will decrease and the AC power consumption in
the dielectric will increase with frequency. We usually refer to the conductance of the dielectric, which is
the inverse of the resistance. The power absorbed in the dielectric, which contributes to the attenuation
of the signal, is directly proportional to the conductance through the dielectric. As a direct consequence
of higher frequencies being absorbed more than low frequencies, the bandwidth of transmitted signals
is decreased and the rise time of the transmitted signal is increased.
These two sources of loss contribute to attenuation that is frequency dependent. The contributions from
each term and the total expected attenuation are shown in Figure 33. It is clear that for a 4 mil wide
trace, dielectric loss dominates at sine wave frequencies higher than about 2 GHz.

Figure 33: Total attenuation in the 36 inch long backplane trace from conductor loss, dielectric loss and the
combination

2.4.3 Impact of losses

When the rise time of the signal is comparable with the rise time degradation, the lossy effects will
distort the received signal. Initially, this rise time degradation will affect timing. As the rise time is further
increased and is comparable to the bit period, the voltage waveform of the received bits will depend on

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the previous pattern of bits. Thus precise shape of the received waveform will depend on the prior bit
pattern. This effect is called intersymbol interference or ISI.
Dielectric loss increases with frequency more strongly than resistive loss. Dielectric loss grows roughly
linearly with frequency, and skin effect grows only as the square root of frequency. As a result, dielectric
loss at some point begins to dominate resistive loss.

2.4.4 Gigabit Simulations

2.4.4.1

[REC]

For Gigabit Simulations, Spice Models may be used as they offer very high degree
of accuracy

2.4.4.2

[RULE]

Proper tool should be selected for simulating Gigabit Signals

The validity of simulation results depends on the correctness of simulation environment. Following
features must be supported by GHz simulation tools:
1. Lossy coupled transmission lines
When designing at multi-gigabit speeds, analysis must account for lossy effects. "Loss" refers to the
phenomenon in which PCB-trace resistance and the heating of dielectric materials (like FR-4) cause
signals to lose amplitude (i.e., attenuate) and suffer shape distortion (disperse), particularly at higher
frequencies. For example, these effects are hardly noticed at the frequencies present in a 2-ns driver
edge, but for the frequencies that make up a 200-ps edge, they can be quite severe. A simulator that
does not take into account the frequency dependence of the losses is worthless in predicting the most
important property of lossy lines; rise time degradation.
2.
3.
4.
5.
6.
7.
2.4.4.3

Advanced via model

Multi-board simulations
Connector modeling
Support for SPICE models as provided by vendors
Stimulus with arbitrary waveforms, with the ability to include jitter
Eye-diagram displays

[RULE]

One should arrive at correct topology for simulation

The topology used in simulation should have lossy transmission line models. Apart from this, any via
model and connector model (if used) should also be included in the topology. In the trace models all the
parameters like dielectric constant, loss tangent, width of the trace etc should be defined correctly.
2.4.4.4

[RULE]

Eye Diagrams should be analyzed carefully

Very-high-speed SERDES-style designs are usually examined in the time domain in a different way
by the use of eye diagrams. An eye diagram takes the results of a simulation driven by a long, multicycle bit sequence, superimposes each bit period over the top of all otherslike a time-exposure
photographand presents waveforms that look something like a human eye. How "open" the middle of
the eye is at the receiver IC is a key factor in judging how likely the receiver is to recover each bit of
arriving data. The tendency of the bits in a complex stream to "wiggle" around each other (in voltage
and time) is called "jitter." A data channel with too much jitter will have a high bit error rate (BER) and
be unreliable.
Below given figure shows the eye diagram observed at the receiver (PCI Express Interface) for total
transmission line length of 16inches. If the eye height and the eye width falls under the specification of
the receiver, then it can be considered that the reliable data will reach at receiver.

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Figure 34: Eye Diagram

2.4.4.5

[RULE]

Multi-Bit Stimulus should be used to generate an eye diagram as this simulates all
possible data patterns

The most common type of stimulus used in eye-diagram generation is the "PRBS" or "pseudo-random
bit sequence." This type of pattern creates a randomized (though repeatable) sequence of bits that
emulates the randomness of real-world data patterns, and as efficiently as possible exercises the
characteristics of a data path. The key characteristics of PRBS stimulus is the time length of each bit in
the sequence (the "bit interval"), the number of bits in the sequence (after which it repeatsthe "bit
order"), and whether the sequence starts from a high or low state.

2.4.5 Opening Eye Diagram

Following steps could be taken to open the eye diagram :
2.4.5.1

[REC]

Use Signal Conditioning Techniques

Most of the devices today supporting gigabit signals come with option of pre-emphasis and
equalization.
Pre-emphasis is a unique signal improving technique that opens the eye pattern at the far end of the
cable for point-to-point applications. The reason it is unique is that it does not utilize or burn any bit
time, so the bus is still 100% efficient for data transfer. Every bit sent is valid information. Pre-emphasis
adds additional output current during the transition time of the bit. This tends to speed up the edge rate
and also provides a bit of over-shoot to the signal at the driver output. This modified waveshape is still
loaded by the interconnect, but the end effect is now much different and improved.
Equalization may also be used to further open the eye. Equalization can be an analog technique to
reverse the low pass effect of the cable with a high pass filter to recover and restore the original signal.
2.4.5.2

[REC]

Increase Line Width

The line width of a trace will affect the series resistance loss, which will increase with the square root of
frequency. Obviously, a wider line will have less resistive loss and help open the eye. Unfortunately, to
increase the line width and maintain the same target impedance also requires an increase in the
dielectric thickness. Increasing the line width would mean a thicker board.
2.4.5.3

[RULE]

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Skew should be minimized

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Any difference in the length of P & N trace will add jitter the eye and hence will close the eye diagram.
Thus Skew in a differential trace should be minimized.

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3 APPENDICES
3.1 Appendix A. Verification Of Rules
No.
2.1.1.1
2.1.1.2
2.1.1.3
2.1.1.4
2.1.1.5
2.1.1.6
2.1.2.1
2.1.2.2
2.1.2.3
2.1.2.4
2.1.2.6
2.1.2.7
2.1.2.8
2.1.3.1
2.1.3.2
2.1.3.3
2.1.3.4
2.1.3.5
2.1.3.6
2.1.3.7
2.1.4.1
2.1.4.2
2.1.5.1
2.1.5.2
2.2.1.1
2.2.2.1
2.2.2.3
2.2.2.4
2.2.3.1
2.2.4.1
2.2.4.2
2.2.4.3
2.2.4.4
2.3.1.1
2.3.2.1
2.3.2.2
2.3.2.3

Verification
PARSER/IBISCHK TOOL
PARSER/IBISCHK TOOL
PARSER/IBISCHK TOOL
PARSER/IBISCHK TOOL
PARSER/IBISCHK TOOL
PARSER/IBISCHK TOOL
PARSER/IBISCHK TOOL
PARSER/IBISCHK TOOL
PARSER/IBISCHK TOOL
PARSER/IBISCHK TOOL
PARSER/IBISCHK TOOL
PARSER/IBISCHK TOOL
PARSER/IBISCHK TOOL
MANUAL
MANUAL
MANUAL
MANUAL
MANUAL
MANUAL
MANUAL
MANUAL
SI TOOL
WHITE PAPER
WHITE PAPER
SI TOOL
SCRIPT
SCRIPT
SI TOOL
SI TOOL
SI TOOL
SI TOOL
MANUAL
MANUAL
SI TOOL
SI TOOL
SI TOOL
SI TOOL/SCRIPT

2.3.2.4

SI TOOL/SCRIPT

Wipro Confidential

Details

Cross ref

Page 46 of 47

Signal Integrity Analysis Guidelines

BRD.GL.SI.2.0

3.2 Appendix B. References

No.
Title
Ref-1. Signal integrity, Dr. Eric Bogatin
Ref-2. 2000-HPSDC, Effective SI analysis using IBIS
model, Shug@cisco.com
Ref-3. EDN Access : Solving SI problem in High Speed
Digital design
Ref-4. IBIS Version Document
Ref-5. Texas Instruments white papers
Ref-6. National Semiconductors white papers
Ref-7. The Jump to Light Speed (Megabit to
Gigabit),Kellee Crisafulli, Mentor Graphics
Corporation & Ron Gordon, Xilinx
Ref-8. White Paper on Transmit Pre-Emphasis and
Receive Equalization
Ref-9. What you lose from a Lossy Line, Dr. Eric Bogatin

Comments

4 GLOSSARY
POS
SSN
PCI
UTOPIA
I/O
IBIS
SERDES
ISI
XAUI
PRBS
BER

Wipro Confidential

Packet Over SONET

Simultaneously Switching Noise
Peripheral Connect Interface
Universal Test and Operation for Physical Interface for ATM
Input/Output
I/O Buffer Information Specification
SERializer/DESerializer
Inter Symbol Interference
10 Gigabit Attachment Unit Interface
Pseudo-random bit sequence
Bit Error Rate

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