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Clocks Basics in 10 Minutes or Less: Edgar Pineda Field Applications Engineer Arrow Components Mexico

This presentation provides an overview of clocks, including: - Clocks generate periodic signals for timing and are needed anywhere digital signals are processed, including data converters and interfaces. They provide frequency inputs to allow devices to perform their functions. - Common clock components include crystals, oscillators, fanout buffers for distributing clocks, and PLLs for cleaning jitter and adjusting phase/frequency. - Key clock parameters include signaling level, jitter, propagation delay, output skew, number of outputs/frequencies, and input voltage/frequency. - Common applications for clocks include communications, consumer electronics, and computers where requirements include low jitter, multiple frequencies, power efficiency, and standards compliance.

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171 views20 pages

Clocks Basics in 10 Minutes or Less: Edgar Pineda Field Applications Engineer Arrow Components Mexico

This presentation provides an overview of clocks, including: - Clocks generate periodic signals for timing and are needed anywhere digital signals are processed, including data converters and interfaces. They provide frequency inputs to allow devices to perform their functions. - Common clock components include crystals, oscillators, fanout buffers for distributing clocks, and PLLs for cleaning jitter and adjusting phase/frequency. - Key clock parameters include signaling level, jitter, propagation delay, output skew, number of outputs/frequencies, and input voltage/frequency. - Common applications for clocks include communications, consumer electronics, and computers where requirements include low jitter, multiple frequencies, power efficiency, and standards compliance.

Uploaded by

shyamsubbu
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Clocks Basics

in 10 Minutes or Less
Edgar Pineda
Field Applications Engineer
Arrow Components Mexico

Presentation Overview

Introduction to Clocks
Clock Functions
Clock Parameters
Common Applications
Summary

Clocks in the Signal Chain


The Real
World

Signal
Conditioning

Temperature

Analog
Signal
Conversion
to Digital

Pressure
Position
Speed
Flow

Power
Management

DSP/FPGA/ASIC

Clocks

Humidity
Sound
Light

Signal
Conditioning

Digital
Signal
Conversion
to Analog

Interface

Introduction to Clocks
What is a Clock?
A device that generates periodic signals for timing.

What types of systems require a clock?


Any system that requires a reference to time for synchronization,
command execution, and data transfer.

How does the clock fit into the signal chain?


Clocks are connected to anything that processes a signal in the
digital domain. Therefore, clocks are needed to connect the
DSP/FPGA/ASIC, Data Converters, and Interface
components.

What role does the clock play in the system?


The clocking network provides the frequency inputs to the various
devices within a system allowing them to perform their intended
function.

Crystal

CrystalA crystal is the disk of quartz and the packaging around it. It is a
passive circuit element which requires an oscillation circuit to produce a
useful signal.
XIN

XOUT

Oscillator
Gain
Stage

Typical Connection
6

Oscillator

Gain Stage
+
Buffer

OscillatorAn oscillator includes the crystal and the oscillation circuit which
Provides a signal with a logic level output. An oscillator is an independent
clock source.
Enable

CLKIN
Termination
Resistor

Typical Connection

How Does a Basic Clock Work?

A clock receives an input frequency from a


source and either distributes that frequency
or generates new frequencies to send as
outputs to other devices within the system.
This can either be done using Phases
Locked Loop (PLL) or non-PLL based
circuitry.
Non-PLL clocks are used when the time
delay between source and output, known as
a propagation delay, is not important to the
system.
PLL Clocks are used when the system
needs to minimize the propagation delay. It
is able to do this by acting as a phase
detector to keep an input clock in phase with
an incoming frequency through the use of a
feedback loop.

PLLs allow a clock to:

Eliminate propagation delay


Allows Phase Adjustments
Perform Integer or Fractional Multiplication
Make Duty Cycle Corrections
Remove noise from the reference clock with
jitter cleaning.

P1

PLL Design

Input
M

Phase/Freq
Detector
(PFD)

Loop Filter

VCO

P2

Clk1
Clk2

N
Pm

Clkm

Clock Functions
Fanout Buffers

Clock

PLL

Feedback

Multipliers/Dividers
/M
/N

Synthesizers

PLL

/P

PLL1
Osc
PLL2

/P1
/P2
/P3
/P4

Jitter Cleaners
9

Fanout Buffers
Fanout Buffers are the most basic type of clock and they are used to distribute an input frequency
to multiple outputs at the same frequency. These are typically used in low phase-noise clock
distributions. Fanout Buffers can be either PLL or Non-PLL Based, depending on the system
requirements.

Reference clock:

Reference clock:

PLL
FanOut

NonNon-PLL
FanOut

Reference
clock:
Output 1:
Output 2:
Output 3:
Output 4:

Disadvantages:
Non-PLL Buffer adds a
Propagation Delay time
Process and Part to Part
Skew might be an issue

Reference clock:
Output 1:
Output 2:
Output 3:
Output 4:
Output 5:

Clock

PLL

Feedback

10

Multiplier/Divider
Multiplier / Divider: A Clock which is able to translate an input clock
into an output clock with a higher (multiplier) or lower frequency
(divider). A Divider Clock can be either PLL or Non-PLL based.

Reference clock (fclock):

Clock
Multiplying /
Dividing

CDC
V304

/M
/N

PLL

/P

* fclock
2 * fclock

11

Synthesizer
Synthesizer: A special kind of circuit that contains one or more PLLs. It
receives a stimulus, usually a low frequency signal from a crystal, and
generates multiple outputs with different (integer or fractional) frequencies.

Reference clock

Clock
Synthesizers

CDC
V304

Crystal

/P1
PLL1
/P2

Osc

/P3
PLL2

fclock1
fclock2
fclock3

/P4

12

Jitter Cleaner
Jitter Cleaner: Any PLL-based clock that cleans the noises from the reference
clock and provides a clean and synchronized signal for the receivers using an
external VCO (VCXO) or internal VCO.

Ideal Input clock:


Real Input clock with Jitter:

Jitter Cleaning
using a VCXO

CDC
V304

LPF
VCXO

Ideal Input clock:


Clean Clock:
13

Clock Parameters
What are the key characteristics of a clock?
Signaling Level (Pre-Defined by the Receivers in the System)
Single-Ended:
Differential:

LVCMOS,TTL, LVTTL Up to ~250 MHz


LVDS, LVPECL, CML, PCI Express (HCSL),
SSTL, HSTL - Up to 10+ GHz

Performance
Jitter:
Propagation Delay:
Output Skew:

# of Outputs:
# of Frequencies:
Input Voltage:
Input Frequency
Output Frequencies

Common Range of <200 fs 100 ps


Common Value of ~3 ns
Common Range of 100 500 ps
Common Range of 1-24 Channels
Can be equal to # of channels
Common Range of 1.2 5 V

14

Jitter

Jitter is the most commonly used measure of the performance of a clock. It is defined as any signal
edge deviation from ideal. There are three main types of jitter that are commonly considered. These are
period, phase, and cycle-to-cycle. Common Jitter performance can range from < 200 fs to 100 ps.

Period

Yx, FBOUT
Yx, FBOUT

The deviation in cycle time of a signal


with respect to ideal period over a
random sample of cycles. This is also
referred to as short-term jitter.

tcycle n

Period Jitter

Cycle-to-Cycle

the variation in cycle time of a signal


between consecutive cycles, over a
random sample of successive cycle
pairs. Also known as adjacent cycle
jitter.

tjit(per) = tcycle n

1
fO

Cycle-to-Cycle
Yx, FBOUT
Yx, FBOUT

tcycle n

tcycle n+1

tjit(cc) = tcycle n - tcycle n+1

Phase

The integrated value from phase noise plot in


time over a specific band of frequencies. This
is long term jitter.
15

Propagation Delay
Propagation delay time, tpd: The time between the specified reference
points on the input and output voltage waveforms with the output
changing from one defined level (High or Low) to the other defined
level. It is common to have a propagation delay of ~3 ns.

tpd = tPHL or tPLH


OUTPUT 1

C L K IN P U T

tP H L 1

tP H L 1

OUTPUT 2

CLKOUT1

C L K IN P U T

OUTPUT 3

OUTPUT n

CLKO UT2

CLKOUTn
t

tP L H n

P r o p a g a tio n

d e la y s

, t PLH

and

PHLn

t PH L

16

Output Skew
Output Skew, tsk(o): The difference between any two propagation delay
times when input switching causes multiple outputs switching. Common
output skew can range anywhere from 100 ps to 500 ps.

17

Common Applications

Communications

Very Low Jitter


High Performance Requirements
Generally differential inputs to support higher speeds

Consumer

Frequency Accuracy (0 PPM translation Error)


Low Power
Different/Multiple Clock Frequencies
Medium Jitter Performance
Frequency Synchronization
Low Cost
Market on Time

PC/Memory

Wireless
Basestations

HDTV

Video
Surveillance

Servers

JEDEC Standards
Medium Jitter Performance
Timing Performance
Support DDR/DDR2/DDR3 requirements.

18

Presentation Summary

Introduction to Clocks
Clock Functions
Clock Parameters
Common Applications

To Learn More About Texas Instruments Clocking Solutions


Visit clocks.ti.com
For Specific End Equipment Solutions
Visit www.ti.com/applications
19

Recursos de soporte TI en espaol


Pgina en Internet

www.ti.com/mx
Lnea de soporte tcnico en espaol

01 800 670 75 44
Acceso a soporte por e-mail

http://www.ti.com/ww/mx/contact.html
20

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