STV8172A

Vertical Deflection Booster

for 3-APPTV/Monitor Applications with 70-V Flyback Generator
DATASHEET

Main Features
Power Amplifier

HEPTAWATT
(Plastic Package)
ORDER CODE: STV8172A

Flyback Generator
Stand-by Control
Output Current up to 3 App
Thermal Protection

Description

This device, supplied with up to 35 V, provides up to

3 App output current to drive the vertical deflection
yoke.
The internal flyback generator delivers flyback
voltages up to 75 V.

Input (Non Inverting)

Output Stage Supply
Output
Ground Or Negative Supply
Flyback Generator
Supply Voltage
Input (Inverting)

7
6
5
4
3
2
1

The STV8172A is a vertical deflection booster

designed for TV and monitor applications.

Tab connected
to pin 4

In double-supply applications, a stand-by state will

be reached by stopping the (+) supply alone.

Non-Inverting
Input

Output Stage
Supply

Flyback
Generator

Flyback
Generator
7

+
Power
Amplifier

Inverting
Input

Thermal
Protection

STV8172A

Ground or Negative Supply

June 2004

Supply
Voltage

Revision 1.3

Output

Absolute Maximum Ratings

STV8172A

Absolute Maximum Ratings

Symbol

Parameter

Value

Unit

Supply Voltage (pin 2) - Note 1 and Note 2

40

Flyback Peak Voltage - Note 2

75

-0.4 to (VS + 3)

- 0.4 to (VS + 2) or +40

Voltage
VS
V5, V 6
V3
V1, V 7

Voltage at Pin 3 - Note 2, Note 3 and Note 6

Amplifier Input Voltage - Note 2, Note 6 and Note 7

Current
I0 (1)

Output Peak Current at f = 50 to 200 Hz, t 10s - Note 4

I0 (2)

Output Peak Current non-repetitive - Note 5

Sink Current, t<1ms - Note 3

Source Current, t < 1ms

Flyback pulse current at f=50 to 200 Hz, t10s - Note 4

ESD1

Human body model (100 pF discharged through 1.5 k)

kV

ESD2

EIAJ Standard (200 pF discharged through 0 )

300

I3 Sink
I3 Source
I3
ESD Susceptibility

Temperature
Ts

Storage Temperature

-40 to 150

Tj

Junction Temperature

+150

Note:1. Usually the flyback voltage is slightly more than 2 x V S. This must be taken into consideration when
setting VS.
2. Versus pin 4
3. V3 is higher than V S during the first half of the flyback pulse.
4. Such repetitive output peak currents are usually observed just before and after the flyback pulse.
5. This non-repetitive output peak current can be observed, for example, during the Switch-On/SwitchOff phases. This peak current is acceptable providing the SOA is respected (Figure 8 and Figure 9).
6. All pins have a reverse diode towards pin 4, these diodes should never be forward-biased.
7. Input voltages must not exceed the lower value of either VS + 2 or 40 volts.

Thermal Data
Symbol
RthJC

2/14

Parameter
Junction-to-Case Thermal Resistance

Value

Unit

C/W

TT

Temperature for Thermal Shutdown

150

TJ

Recommended Max. Junction Temperature

120

STV8172A

Electrical Characteristics

Electrical Characteristics
(V S = 34 V, TAMB = 25C, unless otherwise specified)

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

Fig.

35

20

mA

19

50

mA

Supply
VS

Operating Supply Voltage Range (V2-V4)

Note 8

10

I2

Pin 2 Quiescent Current

I3 = 0, I5 = 0

I6

Pin 6 Quiescent Current

I3 = 0, I5 = 0, V6 =35v

I1

Input Bias Current

V1 = 1 V, V7 = 2.2 V

- 0.6

-1.5

I7

Input Bias Current

V1 = 2.2 V, V7 = 1 V

- 0.6

-1.5

VS - 2

Input

VIR

Operating Input Voltage Range

VI0

Offset Voltage

mV

Offset Drift versus Temperature

10

V/C

VI0/dt

Output
Operating Peak Output Current

0o<Tcase<125oC

V5L

Output Saturation Voltage to pin 4

I5 = 1.5 A

V5H

Output Saturation Voltage to pin 6

I5 = -1.5 A

Output Voltage in Stand-by

V1 = V7 = VS = 0
See Note 9

I0

1.5

1.7

1.8

2.3

Stand-by
V5STBY

VS - 2

80

dB

Miscellaneous
G

Voltage Gain

VD5-6

Diode Forward Voltage Between pins 5-6

I5 = 1.5 A

1.8

2.3

VD3-2

Diode Forward Voltage between pins 3-2

I3 = 1.5 A

1.6

2.2

V3SL

Saturation Voltage on pin 3

I3 = 20 mA

0.4

V3SH

Saturation Voltage to pin 2 (2nd part of flyback)

I3 = -1.5 A

2.1

2.8

8. In normal applications, the peak flyback voltage is slightly greater than 2 x (VS - V 4). Therefore, (VS
- V 4) = 35 V is not allowed without special circuitry.
9. Refer to Figure 4, Stand-by condition.

3/14

Electrical Characteristics

STV8172A

Figure 1: Measurement of I 1, I2 and I6

+Vs
I2

I6
6

2.2V

39k

STV8172A

(a)

S
1

(b)

I1

(a): I2 and I6 measurement

5.6k

1V

(b): I1 measurement

Figure 2: Measurement of V5H

+Vs

V5H

2.2V

STV8172A
1

- I5

1V

Figure 3: Measurement of V3L and V5L

+Vs
I3 or I5

(b)

(a)

1V

STV8172A
5
1
2.2V

V3L
4

(a): V5L measurement

(b): V 3L measurement

4/14

V5L

STV8172A

Application Hints

Application Hints
The yoke can be coupled either in AC or DC.

4.1

DC-coupled Application
When DC coupled (see Figure 4), the display vertical position can be adjusted with input bias. On
the other hand, 2 supply sources (VS and -VEE ) are required.
A Stand-by state will be reached by switching OFF the positive supply alone. In this state, where
both inputs are the same voltage as pin 2 or higher, the output will sink negligible current from the
deviation coil.
Figure 4: DC-coupled Application

+Vs

0 0 0 0 0 0 0 0 0 00.1F

Vertical Position
Adjustment

00000 00000

Output
Current

Flyback
Generator

Ip

Power
Amplifier
7

+
5

1
VM

R3

Thermal
Safety

1.5

Vm
-VEE

470F

(*) recommended:

4.1.1

Rd(*)

Yoke
Ly

0.22F

Vref

Output
Voltage

CF (47 to 100F)

470F

00 00 00 00 00 00 00 00 00 0.1F

Ly
Ly
------------- < Rd < ------------20s
50s

R2

00 00 00 00 00

R1

Application Hints
For calculations, treat the IC as an op-amp, where the feedback loop maintains V 1 = V7.

5/14

Application Hints

STV8172A

4.1.1.1 Centering
Display will be centered (null mean current in yoke) when voltage on pin 7 is (R1 is negligible):
VM + Vm R 2
V 7 = ------------------------ ----------------------
2
R 2 + R 3

4.1.1.2 Peak Current

( VM Vm )
R2
I P = ----------------------------- ------------------R 1 xR 3
2

Example: for V m = 2 V, VM = 5 V and IP = 1 A

Choose R1 in the1 range, for instance R1=1
2 IP R1 2
- = --------- = ---------------------------3
R
V V
3
M
m
R2

From equation of peak current:

Then choose R2 or R3. For instance, if R2 = 10 k, then R3 = 15 k

Finally, the bias voltage on pin 7 should be:
V +V
7 1
M
m
1
V 7 = ------------------------ ----------------- = ---- -------- = 1.4V
2 2.5
R
2
3
1 + ------R2

4.1.2

Ripple Rejection
When both ramp signal and bias are provided by the same driver IC, you can gain natural rejection
of any ripple caused by a voltage drop in the ground (see Figure 5), if you manage to apply the
same fraction of ripple voltage to both booster inputs. For that purpose, arrange an intermediate
point in the bias resistor bridge, such that (R8 / R7) = (R3 / R2), and connect the bias filtering
capacitor between the intermediate point and the local driver ground. Of course, R7 should be
connected to the booster reference point, which is the ground side of R1.
Figure 5: Ripple Rejection

2
Flyback
Generator

Reference
Voltage

Power
Amplifier
7

R9

R8

0000
0000

+
5

R7
1

Thermal
Safety

Rd

4
Ramp
Signal

Driver
Ground

6/14

R3

Source of Ripple

00 00

R2

R1

0000

Yoke
Ly

STV8172A

4.2

Application Hints

AC-Coupled Applications
In AC-coupled applications (See Figure 6), only one supply (VS ) is needed. The vertical position of
the scanning cannot be adjusted with input bias (for that purpose, usually some current is injected
or sunk with a resistor in the low side of the yoke).
Figure 6: AC-coupled Application

00000 00000

470F

+Vs

CF (47 to 100F)

0.1F
6

Output
Voltage

Output
Current

Flyback
Generator

Ip

Power
Amplifier

5
1

R3

VM
Vm

Thermal
Safety

1.5

00000

00000
4

R5

(*) recommended:

4.2.1

0000 C

Rd(*)

Yoke
Ly

0.22F

00000

R4

CL

R2

Ly
Ly
------------- < Rd < ------------50s
20s

00000

R1

Application Hints
Gain is defined as in the previous case:
I

R2
VM Vm
=
---------------------- ---------------------p
2
R R
1

Choose R1 then either R2 or R3. For good output centering, V 7 must fulfill the following equation:
VS
VM + Vm
-------- V
V ------------------------ V
7
7
7
2
2
---------------------- = -------------------------------------- + ------R +R
R
R
4
5
3
2

or
V M + V m
VS

1
1
1
V ------- + ------- + ---------------------- = ------------------------------ + ------------------------
7 R

R2 R + R
2 R3
2 (R 4 + R5 )
3
4
5

7/14

Application Hints

STV8172A

CS performs an integration of the parabolic signal on CL, therefore the amount of S correction is set
by the combination of CL and Cs.

4.3

Application with Differential-output Drivers

Certain driver ICs provide the ramp signal in differential form, as two current sources i + and i with
opposite variations.
Figure 7: Using a Differential-output Driver

+Vs

00000 00000

470F

Output
Voltage

CF (47 to 100F)

0.1F
6

Output
Current

Flyback
Generator

Differential output
driver IC

Ip

Power
Amplifier
ip
icm

+
5

R7

-ip

icm

Thermal
Safety

1.5

-VEE

470F

(*) recommended:

Rd(*)

0.22F

00000

00 00 00 00 00 00 00 00 00 00

Yoke
Ly

0.1F
R2

00 00 00 00 00

Ly
Ly
-------------- < Rd < -------------20 s
50s

R1

Let us set some definitions:

1
i cm = --- ( i + + i - )
2

icm is the common-mode current:

at peak of signal, i+ = icm + ip and i = icm - ip, therefore the peak differential signal is ip - (ip) = 2 ip, and the peak-peak differential signal, 4ip.

The application is described in Figure 7 with DC yoke coupling. The calculations still rely on the fact
that V1 remains equal to V7.

8/14

STV8172A
4.3.1

Application Hints

Centring
When idle, both driver outputs provide icm and the yoke current should be null (R1 is negligible),
hence:
i cm R 7 = i cm R 2 therefore R 7 = R 2

4.3.2

Peak Current
Scanning current should be IP when positive and negative driver outputs provide respectively
icm - ip and icm + ip, therefore
(i

cm

i ) R 7 = I p R 1 + ( i cm + i ) R 2 and since R7 = R2:

2R 7
Ip
----- = ----------R1
i

Choose R1 in the 1 range, the value of R2 = R7 follows. Remember that i is one-quarter of driver
peak-peak differential signal! Also check that the voltages on the driver outputs remain inside
allowed range.

Example: for icm = 0.4mA, i = 0.2mA (corresponding to 0.8mA of peak-peak differential

current), Ip = 1A
Choose R1 = 0.75, it follows R2 = R7 = 1.875k.

4.3.3

Ripple Rejection
Make sure to connect R7 directly to the ground side of R1.

4.3.4

Secondary Breakdown Diagrams

Figure 8: Output Transistor Safe Operating Area (SOA) for Secondary Breakdown

The diagram has been arbitrarily limited to max I0 (2 A).

9/14

Mounting Instructions

STV8172A

Figure 9: Secondary Breakdown Temperature Derating Curve (ISB = Secondary Breakdown Current)

Mounting Instructions
The power dissipated in the circuit is removed by adding an external heatsink. With the
HEPTAWATT package, the heatsink is simply attached with a screw or a compression spring
(clip).
A layer of silicon grease inserted between heatsink and package optimizes thermal contact. In DCcoupled applications we recommend to use a silicone tape between the device tab and the heatsink
to electrically isolate the tab.
Figure 10: Mounting Examples

10/14

STV8172A

Pin Configuration

Pin Configuration
Figure 11: Pins 1 and 7

Figure 12: Pin 3 & Pins 5 and 6

5
3

11/14

Package Mechanical Data

STV8172A

Package Mechanical Data

Figure 13: 7-pin Heptawatt Package

L
E
L1
M1
A

C
D1

H2

L2
L5

L3

F
E

E1

V4

L9

H3

G1

G2

Dia.

F
L10

H2

L4
L11
L7
L6

Table 1: Heptawatt Package

mm

inches

Dim.
Min.

Typ.

Min.

Typ.

Max.

4.8

0.189

1.37

0.054

2.40

2.80

0.094

0.110

D1

1.20

1.35

0.047

0.053

0.35

0.55

0.014

0.022

E1

0.70

0.97

0.028

0.038

0.60

0.80

0.024

0.031

2.34

2.54

2.74

0.095

0.100

0.105

G1

4.88

5.08

5.28

0.193

0.200

0.205

G2

7.42

7.62

7.82

0.295

0.300

0.307

H2

12/14

Max.

10.40

H3

10.05

16.70

16.90

0.409

10.40

0.396

17.10

0.657

0.409
0.668

0.673

STV8172A

Package Mechanical Data

Table 1: Heptawatt Package (Continued)
mm

inches

Dim.
Min.

Typ.

Max.

Min.

Typ.

L2

21.24

21.54

21.84

0.386

0.848

0.860

L3

22.27

22.52

22.77

0.877

0.891

0.896

L5

2.60

2.80

3.00

0.102

0.110

0.118

L6

15.10

15.50

15.80

0.594

0.610

0.622

L7

6.00

6.35

6.60

0.0236

0.250

0.260

L1

14.92

L4

0.587

1.29

L9

Max.

0.051

0.20

0.008

L10

2.10

2.70

0.082

0.106

L11

4.30

4.80

0.169

0.190

2.55

2.80

3.05

0.100

0.110

0.120

M1

4.83

5.08

5.33

0.190

0.200

0.210

V4
Dia.

40 (Typ.)
3.65

3.85

0.144

0.152

13/14

Revision History

STV8172A

Revision History
Table 2: Summary of Modifications
Version

Date

Description

1.0

August 2003

1.1

November 2003

Datasheet status changed to preliminary data.

1.2

December 2003

Modification to Figure 11.

1.3

June 2004

First Issue.

Datasheet status changed to datasheet.

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14/14