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    Gujarat Technological University: Instructions

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    Pritesh Saxena
    This document is an exam for a Digital VLSI Design course, consisting of 5 questions testing various concepts: 1. Question 1 has short answer questions about crosstalk, static vs dynamic circuits, CMOS equations and advantages, non-overlapping clocks, and pseudo gates. 2. Question 2 involves MOS transistor diagrams, gate capacitance calculation, and deriving the MOSFET drain current equation. 3. Question 3 covers photoresist types in lithography, constructing a pi-model for a wire, and estimating propagation delay using the Elmore delay model. 4. Question 4 derives CMOS inverter ratios and compares adder circuits, asking about noise margins and D latch/flip

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    Gujarat Technological University: Instructions

    Uploaded by

    Pritesh Saxena
    48 views2 pages
    This document is an exam for a Digital VLSI Design course, consisting of 5 questions testing various concepts: 1. Question 1 has short answer questions about crosstalk, static vs dynamic circuits, CMOS equations and advantages, non-overlapping clocks, and pseudo gates. 2. Question 2 involves MOS transistor diagrams, gate capacitance calculation, and deriving the MOSFET drain current equation. 3. Question 3 covers photoresist types in lithography, constructing a pi-model for a wire, and estimating propagation delay using the Elmore delay model. 4. Question 4 derives CMOS inverter ratios and compares adder circuits, asking about noise margins and D latch/flip

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    1710412

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    This document is an exam for a Digital VLSI Design course, consisting of 5 questions testing various concepts: 1. Question 1 has short answer questions about crosstalk, static vs dynamic circuits, CMOS equations and advantages, non-overlapping clocks, and pseudo gates. 2. Question 2 involves MOS transistor diagrams, gate capacitance calculation, and deriving the MOSFET drain current equation. 3. Question 3 covers photoresist types in lithography, constructing a pi-model for a wire, and estimating propagation delay using the Elmore delay model. 4. Question 4 derives CMOS inverter ratios and compares adder circuits, asking about noise margins and D latch/flip

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    48 views2 pages

    Gujarat Technological University: Instructions

    Uploaded by

    Pritesh Saxena
    This document is an exam for a Digital VLSI Design course, consisting of 5 questions testing various concepts: 1. Question 1 has short answer questions about crosstalk, static vs dynamic circuits, CMOS equations and advantages, non-overlapping clocks, and pseudo gates. 2. Question 2 involves MOS transistor diagrams, gate capacitance calculation, and deriving the MOSFET drain current equation. 3. Question 3 covers photoresist types in lithography, constructing a pi-model for a wire, and estimating propagation delay using the Elmore delay model. 4. Question 4 derives CMOS inverter ratios and compares adder circuits, asking about noise margins and D latch/flip

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    You are on page 1of 2

    Seat No.

    : ________

    Enrolment No.______________

    GUJARAT TECHNOLOGICAL UNIVERSITY


    M. E. - SEMESTER II EXAMINATION SUMMER 2014

    Subject code: 1710412


    Subject Name: Digital VLSI Design
    Time: 02:30 pm - 05:00 pm

    Date: 23-06-2014
    Total Marks: 70

    Instructions:
    1. Attempt all questions.
    2. Make suitable assumptions wherever necessary.
    3. Figures to the right indicate full marks.
    Q.1
    (a)
    (b)
    (c)
    (d)
    (e)
    (f)
    (g)

    Q.2

    (a)
    (b)
    (b)

    Q.3

    (a)
    (b)

    Q.3

    (a)

    Answer the following questions (Two marks each)


    Discuss crosstalk and its implications.
    Compare static and dynamic circuit for size, power dissipation and speed of
    operation.
    Write equation for CMOS channel charge.
    Why CMOS is preferred compared to BJT in Digital VLSI design?
    Why CMOS flip-flops prefer non-overlapping clocks?
    What do you mean by Pseudo gate?
    For Circuit shown in figure below, find path logical effort and Path Electrical
    effort.

    14

    Show internal diagram of MOS transistor and explain calculation of gate


    capacitance. With diagram show variation of the gate capacitances as functions
    of gate-to-source voltage VGS
    Derive the drain current equation for MOSFET using Gradual Channel
    Approximation (GCA).
    OR
    State importance of Power-Delay Product and explain with necessary
    equations.

    07

    With appropriate diagram discuss types of photoresists and their usage in


    lithography process.
    Consider 5mm long, 0.32m wide metal2 wire in 180nm process. The sheet
    resistance is 0.05W/ and the capacitance is 0.2fF/m. Estimate resistance and
    capacitance of the wire and construct a 3-segment p-model for the wire. A 10x
    unit-sized inverter drives a 2x inverter at the end of the 5mm wire. The gate
    capacitance is C = 2fF/m and the effective resistance is R = 2.5KW m for
    NMOS transistors. Neglect diffusion capacitance. Estimate the propagation
    delay using Elmore delay model.
    OR
    With appropriate diagram explain how CMOS inverter is fabricated on plain
    substrate.

    07

    07
    07

    07

    07

    Q.4

    (b)

    Sketch 2 input NOR gate with transistor widths chosen to achieve effective rise
    and fall resistance equal to a unit inverter. Compute the rising and falling
    propagation delays in terms of R and C of the NOR gate driving h identical
    NOR gates using Elmore delay model. If C = 2fF/m and R = 2.5KW m in a
    180nm process, what is the delay of fanout-of-4 NOR gate?

    07

    (a)

    Derive critical voltages for CMOS inverter and find ratio of W/L for
    symmetrical inverter.
    Draw and compare 1-bit full adder circuit using CMOS compound gate and
    CMOS transmission gate. Illustrate which mechanism will use less number of
    transistors.

    07

    (b)

    07

    OR

    Q.4

    (a)
    (b)

    Q.5

    (a)
    (b)

    Q.5

    (a)
    (b)

    For depletion load inverter circuit, discuss noise margin with transfer
    characteristic.
    Draw MOS transistor level schematic and explain operation of D Latch as well
    D Flip-flop with waveforms.

    07

    Explain concept of precharge and evaluate for dynamic logic circuit.


    What is feature size and l? Explain Layout design rules in terms of l.
    OR
    Write short note on NORA CMOS logic.
    Draw Circuit diagram and stick diagram for following boolean function

    07
    07

    07

    07
    07

    (i) Y = AB + C
    (ii) Y = ABC
    *************

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