QorIQ Qonverge Platform

Next-Generation Wireless Network

Bandwidth and Capacity
Enabled by Heterogeneous and
Distributed Networks

freescale.com

QorIQ Qonverge Platform

Preface
The increased use of smartphones and other mobile devices utilizing Internet applications, video calls and email are driving an unprecedented
increase in worldwide wireless network traffic. From a network operators perspective, the key factors in driving wireless network topologies are their
ability to meet demand for bandwidth, user capacities, users quality of service (QoS) and network costs.
As the world moved from 2G to 3G and now to the 4G LTE standard and LTE-Advanced in the future, demand for bandwidth capacity is increasing
exponentially. According to Cisco,the Mobile Network in 2015 global mobile data traffic will increase 26-fold between 2010 and 2015. Mobile data
traffic will grow at a compound annual growth rate (CAGR) of 92 percent from 2010 to 2015, reaching 6.3 exabytes per month by 2015. (Source:
Cisco Visual Networking Index Global IP Traffic Forecast, 2010-2015).
To achieve the required capacities, QoS and lower costs is contingent upon multiple factors like proximity of the users relative to the base station or
the transceivers, the number of users in a cell, data throughputs and patterns, core network capabilities, base station costs and operating costs.
Traditional macro sites are installed on rooftops or at designated cell sites that typically have the baseband units in a cabinet enclosure while the
transceivers, RF power amplifiers and antenna reside on a tower mast. The cabinet is then connected using a coaxial cable to the radio head on the
antenna mast, which is the most common cell site approach for building mobile networks.
Moving to LTE, this type of architecture is being transformed with the introduction of remote radio heads (RRH) connected to a base station cabinet
via fiber optic cables that can be distributed over 10 Km or more or smaller cells, both ways bring the users closer to the base station. A distributed
antenna system employs a macro or micro base station, the same as a traditional cellular site, but instead of the tall antenna mast, fiber-optic cables
are used to distribute the base stations signals to a group of antennas placed remotely in outdoor or indoor locations where required.
Subscribers are demanding faster data speeds, but due to limited coverage in dense urban areas and inside buildings, the wireless networks built
of only traditional macro base stations spaced 10 Km or more, handling hundreds of users with high power amplifiers no longer will be sufficient.
Instead, new types of overlay network deployments will be required for 4G data services and the types of base stations at the forefront of these
new deployments will be the small base stations called Enterprise-Femtocells, Picocells, Metrocells and distributed antenna systems. These base
stations typically handle single sectors covering a relatively small radius up to 5 Km with fewer users and lower power amplifiers installed outdoors in
metro areas such as building walls, street lampposts, poles, rooftops, campuses, enterprises, bus and train stations, as well as indoor deployments
covering a radius of up to 500m. Having these base stations installed and operated by mobile operators will ensure the right equipment form factor
for the right situation to meet the ever-growing need for greater capacity.
Wireless networks will evolve; however, the transition to 4G technology wont happen in one day. Keeping the base stations as compact as possible
while having them on a single baseband card results in the need to support 3G and 4G users simultaneously and a single baseband processor is
key to enable that.
Key elements of any base station design are its digital baseband processing elements that define its users capacity, data throughputs, scalability and
impact on equipment and operational costs. A high degree of integration and sophistication is key especially for compact base station design, as it is
lowering the cost and power consumption of the digital processing elements while maintaining the high throughputs and capacities.
This paper outlines Freescales solutions that enable the creation of these new types of base stations.

QorIQ Qonverge Platform

About ranges, data rates, antenna

configurations and bandwidth in
LTE

Small Cell Deployments

of energy from a limited source over multiple

frequencies. A wider carrier bandwidth results

Range

on the effective range due to the distribution

Data Rates

Carrier bandwidth has a significant impact

in shorter range for a given data rate or in lower

data rates for a given range.
The charts above depict small cell deployments
that can provide advantages by having

1.4 MHz

many small self-contained boxes mounted

500m

Carrier Bandwidth

at convenient locations closer to the users,

maximizing the throughputs over a larger

20 MHz

10 KM

20 KM

Cell Radius

Source: Airwalk

service area. As LTE deployments proceed it is

expected that wireless networks in dense urban areas, where multi-paths affects intensify, obstructions block the transmission or other interferences
exist, will consist of large numbers of small cells and/or larger cells with distributed radio heads.
Another option to increase data rates and ranges is to use sophisticated MiMO techniques requiring higher number of antennas. However, the
implementation of such configurations may result in higher overhead cost for indoor deployments where cell radius, installation space and base
station enclosure dimensions are confined.
System throughputs in areas with high concentration of user equipment can be maintained over smaller cell radius or by bringing the RF transceiver
closer with lower power RF amplifiers than used in traditional macro base station configurations. This allows operators to support maximum
throughput and capacity in a given area.

Digital baseband processing elements in LTE

eNodeB (eNB) base station
Digital baseband processing in LTE base station (eNB) is divided into several layers. Typically the processing elements include a general purpose
processor (GPP) device handling the MAC, RLC, RRC and PDCP layers; a digital signal processor (DSP) device handling the PHY layer; and digital
radio front-end logic typically in an ASIC, FPGA or off-the-shelf transceiver to prepare the signal to be sent to the RF amplifier.
The diagram below describes the different layers of LTE processing in eNodeB/eNB (LTE basestation)
In typical macro and micro base stations, the
baseband channel card is composed of single
GPP device and multiple DSP devices due to
the need for handling scalable and variable
number of sectors, number of users and

Digital
Baseband Processing Elements in LTE eNodeB (eNB) Base Station
Digital Baseband Processing Elements in LTE eNodeB (eNB) Base Station
eNB
Inter Cell RRM
RB Control

throughputs based on the specific deployment

Connection Mobility Cont.

requirements. Alternately, Picocell and

Radio Admission Control

Metrocell base stations typically handle single

eNB Measurement
Configuration and Provision

sector and a given number of users and data

Dynamic Resource
Allocation (Scheduler)

throughputs. The traditional single GPP device

and single DSP discrete device paradigm is
changing to a single unified System-on-Chip
(SoC).

MME
NAS Security
Idle State Mobility
Handling
EPS Bearer Control

RRC
PDCP

S-GW

RLC
MAC
PHY
E-UTRAN

S1

P-GW

Mobililty
Anchoring

UE IP Address
Allocation
Packet Filtering

Internet

EPC

Source: 3GPP TS 36.300 V8.12.0

QorIQ Qonverge Platform

L2 and L3 layers
The charts below depict the different functions in building L2 and L3 layers in an LTE base station. These typically are implemented by the GPP. The
three sub-layers are: Medium access Control (MAC), Radio Link Control (RLC) and Packet Data Convergence Protocol (PDCP).
Downlink andand
UplinkUplink
Chains inChains
LTE Base Stations
Downlink
in LTE Base Stations
SAE
Bearers

SAE
Bearers
ROHC

ROHC

ROHC

ROHC

Security

Security

Security

Security

ROHC

ROHC

Security

Security

PDCP

PDCP

Radio
Bearers

Radio
Bearers
RLC

Segm.
ARQ

Segm.
ARQ

Segm.
ARQ

Segm.
ARQ

RLC
BCCH BCCH

Segm.
ARQ

Segm.
ARQ
Logical
Channels

Logical
Channels
Scheduling/Priority Handling
MAC

Multiplexing UE1

Multiplexing UEn

HARQ

HARQ

Scheduling/Priority Handling
MAC

Multiplexing

HARQ
Transport Channels

Transport Channels

Downlink Chain

RACH

Uplink Chain

PHY (L1) physical layer

The charts below depict the chain of functions building the PHY (L1) layer in an LTE base station; typically implemented by the DSP cores and
baseband accelerators.
PHY (L1)
Physical
Layer Layer
PHY
(L1)
Physical
PHY Layer Downlink Processing Functions

MAC Layer

CRC
Attach

Turbo
Encoding

Rate
Matching

Scrambling
and
Modulation

Layer
Mapping
Pre-Coding
and Resource
Mapping

IFFT

MAC Layer
PHY Layer Uplink Processing Functions

FFT

MIMO
Channel
IDFT
Estimation Equalizer

Freq.
De-Modulation
Offset
De-Interleaving
Descrambling
Compensation

RateDematching, Transport
CRC
HARQ
Block
Check
Combining,
CRC
Turbo Decoding

Challenges in evolving networks

As wireless networks evolve, support for LTE and WCDMA standards and multimode operation with both technologies running simultaneously are
becoming requisite. Given the inherent differences between these wireless standards, a number of technical challenges have to be solved on various
levels of the processing stacks.
On the L1 physical layer, the 3GPP standards for third-generation WCDMA and next-generation LTE have taken different approaches to modulate
and map the data onto the physical medium. As the name indicates, WCDMA is based on code division multiple access and typically requires
processing resources to efficiently perform spreading/despreading, scrambling/descrambling and combining operations. These are the main functions
needed in the RAKE receiver approach typically used in WCDMA. The L1 operations in WCDMA are a mix of streaming and batch type operations,
which baseband architecture must process efficiently.
4

QorIQ Qonverge Platform

In contrast, LTE uses a mix of OFDMA for downlink and SC-FDMA modulation for uplink. This multicarrier approach follows the principle of
modulation for orthogonal subcarriers to maximize the spectrum density. The predominant operations in OFDMA/SC-FDMA are the Discrete Fourier
Transforms in the form of FFT or DFT and Multiply-Accumulate operations.
The nature of data organization and subframe structure in LTE allows the L1 processing steps to be scheduled sequentially according to the available
subframe user and allocation information. The key challenge is meeting the tight latency budgets of the physical layer processing to maximize the
available time budget in the MAC layer scheduler.

Baseband acceleration and addressing the multimode challenges

With Freescales devices, the physical layer (PHY) on the DSP is implemented using a mix of Starcore SC3850 high performance DSP cores and a
baseband accelerator platform called MAPLE (Multi Accelerators Platform). The MAPLE accelerators provide highly efficient hardware implementation
of the standardized building blocks for each of the air interface standards in single mode and in multimode operations, handling:
Fourier transform processing element: Used primarily in LTE for FFT and DFT Fourier transforms operations as well as RACH operations. It also
can be used in WCDMA for frequency domain search and RACH operations. The ability to perform additional vector post and pre-multiplier
operations makes this unit also very suitable for correlation and filtering operations.
Turbo/Viterbi decoding processing element: Used for Forward Error Correction (FEC) deploying Turbo and Viterbi decoding algorithms in both in
LTE/LTE-A and WCDMA. Other functions like CRC calculation, rate de-matching operations and HARQ combining are also covered.
Downlink encoding processing element: Used for FEC deploying Turbo encoding algorithms for both in LTE/LTE-A and WCDMA and rate
matching operations.
Chip rate processing element: Used to accelerate DL (Downlink) and UL (Uplink) spreading/despreading and scrambling/descrambling
operations for both data and control channels. This block is used exclusively for WCDMA and CDMA2K/EV-DO standards.
Equalization processing element: Performs the MiMO equalization operations based on MMSE (Minimum Mean Square Error), IRC (Interference
Rejection Combining), SIC (Successive Interference Cancellation) or ML (Maximum Likelihood) approaches, while its internal algorithms
and outputs are done and generated in floating point mathematics. A number of configurable operation modes allow the adaptation of the
equalization process to the user characteristics and channel conditions. These equalization algorithms are quite complex and require lots of
computation resources. Hence, Freescale has selected to implement the algorithms in hardware acceleration, which is adaptable to different
nuances and at the same time frees them from the DSP cores, leaving these for other tasks in the processing chain.
Physical Downlink Processing Element: Performs an encoding of the PDSCH (Physical Downlink Shared Channel) starting from the user
information bits up to the CP (cyclic prefix) insertion and antenna interface handshake. Including DL-MiMO precoding and layer mapping
operation.
Physical Uplink Processing Element: Performs decoding of PUSCH (Physical Uplink Shared Channel) resulting in decoded information bits.
As mentioned previously, there is a need to support multiple standards concurrently as users slowly migrate to LTE. It is especially important that
small cells that cover a given and relatively limited cell radius and number of users continue to support multimode while providing an upgrade path for
handling more advanced technologies.
In order to handle multimode operation, the DSP cores are fully programmable and can implement any standard. The MAPLE hardware block was
designed in such a way to enable multimode operation such as Turbo and Viterbi decoding, Turbo encoding and FFT/DFT can operate concurrently
on both standards in term of the algorithms processing and capacity.
The Layer 2 and Layer 3 algorithms use a mix of Power Architecture general purpose high performance cores and security acceleration. Most of
this processing is done on programmable cores where any standard including multimode operation can be implemented efficiently. The commonality
between WCDMA and LTE is the requirement for secure backhaul processing. The bulk of this is Ethernet, QoS, IPSec and WCDMA Frame Protocol
processing, which is offloaded to hardware acceleration and leaves software flexibility for the actual L2 stacks of both standards.
In terms of capacities, Freescale dimensioned its devices multiple cores and accelerators in such a way as to enable operation on both standards
simultaneously.
Freescale devices support multimode operation for the different base station sizes from Femtocell to Macrocell.

QorIQ Qonverge Platform

Meeting latency budget

To ensure continued competitiveness to 3G technology, the 3GPP standard body based LTE on OFDM (Orthogonal Frequency Division Multiplexing)
and MiMO (Multiple Inputs, Multiple Outputs) antenna techniques. The major performance goals addressed are significantly increasing data rates,
reducing latencies and improving spectrum efficiencies.
Latency is a key network metric and has a major influence on users experience both in voice calls and data transactions such as video and Internet
applications. The key challenge is meeting the tight latency budgets of the physical layer processing to maximize the available time budget for the
rest of the PHY processing and MAC layer scheduler tasks. The LTE defines the end-user roundtrip latency as less than 5mS, which requires the
latency within the basestation to be significantly lower (less than 0.5mS in DL and less than 1mS in UL).
MiMO equalization/detection and FEC (Forward Error Correction) are heavily used in newer, high bit-rate wireless communication standards such as
LTE and WiMAX. The MiMO Equalizer and Turbo coding error correction algorithms both in Uplink and Downlink are the major influencers on base
station throughput and latency. Freescale has developed a set of hardware accelerators that meet the low latencies by designing them for 3 to 5
times higher throughputs than the defined throughput. This is expected to result in completing these tasks ahead of time and leave more room for
the other algorithms in the processing chain.

About intellectual properties ownership

Unlike some competitors, Freescales ownership of the key intellectual properties (IP), coupled with deep engagement with leading OEMs (original
equipment manufacturers) in the wireless access market, puts Freescale in a position to define architectures and drive integration that provide
performance, power and cost benefits. Being relatively independent from external IP providers next-generation technologies and timelines enables
Freescale to drive a roadmap of devices that helps meet OEM targets for performance and timelines for next-generation wireless technologies.
The key processing elements in any device for mobile wireless infrastructures are the programmable cores, hardware accelerators, internal
interconnects and high speed interfaces. Freescale has long been an embedded processing leader. The market-proven Power Architecture core
is at the heart of Freescales strength and has been used by leading wireless OEMs worldwide for many years. While significantly enhanced from
generation to generation, it comes with a very rich ecosystem to provide customers with a seamless migration from their current products to higher
performance products. The Starcore DSP core has been enhanced by Freescale from generation to generation for more than a decade and is known
for its high performance and programmability. The SC3850 is used today in DSP devices deployed by many of the wireless manufacturers in LTE,
WCDMA and WiMAX deployments and has earned leading results from top benchmarking firms.
Other important components are the internal fabric and accelerator throughputs and standard compliance. The internal fabric is a component that
connects all processing elements and memories within the device; it must enable high throughputs and low latencies for data movement throughout
the SoC as well as not stalling any of the elements attached to it for processing its data. Both the internal fabric and the accelerators were proven to
be highly efficient and were field deployed by Freescale customers.

Device architectures
and capacities
Freescale has developed powerful and
innovative multicore processor, DSP and SoC

Data
Data
Rates
MHz
Carrier Bandwidth
Rates
for 20for
MHz20
Carrier
Bandwidth
Category
Peak Rate Mbps

devices. Some of these devices are in full

DL

10

50

100

150

300

UL

25

50

50

75

Capability for Physical Functionalities

production today and deployed in the field

utilizing some of the industrys most advanced

RF Bandwidth

silicon technology. These devices that are

Modulation

already being used in commercial and trial

20 MHz
QPSK, 16QAM, 64QAM

DL
UL

manufacturers to develop new technologies like

Multi-Antenna

LTE while increasing performance and reducing

costs for existing wireless technology such as

2 Rx Diversity

WCDMA.

2x2 MIMO

The 3GPP standard body defined in Release

4x4 MIMO

8 several levels of data rates for FDD 20 MHz

carrier bandwidth depicted in the table below.

QPSK,
16QAM,
64QAM

QPSK, 16QAM

networks were designed to allow base station

Source: 3GPP

Assumed in Performance Requirements

Not
Supported

Mandatory
Not
Supported

Mandatory

QorIQ Qonverge Platform

Freescale has created a family of products that scales with LTE throughputs ranging from 100Mbps to 300Mbps in the Downlink and from 50Mbps
to 150Mbps in the Uplink.
By leveraging the high-performance programmable architectures, Freescale can offer a family of software-compatible devices that scale from
Femtocells to Macrocells. The following sections describe Freescale solutions addressing the different types of base stations designs.

PSC9132 Enterprise-Femtocell/Picocell solutions

PSC9132 SoC (System-on-Chip) device is targeted at Enterprise-Femto/Picocell base station deployments:
Standards: FDD/TDD LTE (Rel. 8/9) and WCDMA (Rel. 99/6/7/8/9)
LTE Bandwidth: 20 MHz single sector or 2 sectors 10 MHz
WCDMA-HSPA+ Bandwidth: 2x 5 MHz
LTE throughputs: 150 Mbps DL/75 Mbps UL with 2x4 antenna MiMO
HSPA+ throughputs: Dual Cell84 Mbps
DL/23 Mbps UL

QorIQ
QorIQ
Qonverge
PSC9132
Qonverge
PSC9132
Processor Processor

Active Users in Single Mode

LTE100 users
AMR/HSPA+96/64 users respectively

e500 Core
Built on
Power Architecture

StarCore SC3850
DSP Core

32 KB L1 32 KB L1
I-Cache D-Cache

32 KB L1 32 KB L1
I-Cache D-Cache

512 KB

512 KB

Coherency Module

L2 Cache

L2 Cache

512 KB L2 Cache

Active Users in Dual mode

64 LTE users and 32 HSPA users

e500 Core
Built on
Power Architecture

StarCore SC3850
DSP Core

32 KB
Shared
M3 Memory

32 KB L1 32 KB L1
I-Cache D-Cache

32 KB L1
I-Cache

32 KB L1
D-Cache

32-bit
DDR3/3L
Memory
Controller
32-bit
DDR3/3L
Memory
Controller

simultaneously

PSC9132 device features

Dual Power Architecture e500 core at up to
1.2GHz
Dual Starcore SC3850 DSP at up to
1.2GHz
MAPLE-B2P Baseband Accelerators

Multicore Fabric
2x SPI
2x DUART
2x I2C
GPIO
USIM
IFC
eSDHC
Clocks/Reset

Platform

Ethernet
DMA

Security
Engine
V4.4

USB
2.0

IEEE 1588
1x GE
SGMII

1x GE
SGMII

PCI
Express

x2

CPRI

MAPLE-B2P
Baseband
JESD207/ADI
Accelerator
LTE/UMTS/WiMAX

x2

x4

4-lane 6 GHz SerDes

Security acceleration engine handling IPSec, Kasumi, Snow-3G

DMA engine
Dual DDR3/3L, 32bit wide, 1.333GHz, with ECC
IEEE1588 v2, NTP and interface to GPS sync. support
2G/3G Sniffing Support
Secured Boot support
Interfaces
4 SerDes lanes combining: 2x Ethernet 1G SGMII, 2x CPRI v4.1 @ 6.144G antenna interface, 2x PCIe at 5Gbps
Quad JESD207/ADI RF transceiver interfaces, USB 2.0, NAND/NOR flash controller, eSDHC, USIM, UART, I2C, eSPI

QorIQ Qonverge Platform

Different antenna configurations

Antenna
AntennaConfigurations
Configurations

Combining the digital baseband devices

Picocell Using RRH via Fiber-Optic Cable

together with the transceivers and the power

amplifiers in the same enclosure forms a

Picocell with Local Antenna

PSC9132

compact base station that can be mounted

PSC9132

Ethernet

almost anywhere outdoors and inside buildings

DDR3

DDR1

PHY

1000BaseT Debug

PHY

1000BaseT Back
Haul

IEEE 1588

by connecting the JESD207 standard antenna

interfaces to the local transceivers covering

DDR3

PCIe

DDR2

Ethernet
DDR3

DDR1

DDR3

remote antenna can be mounted on the top of

1000BaseT Back
Haul

DDR2

PCIe
USB

JESD207/
ADI

EEPROM

other hand if larger cell coverage is required, a

1000BaseT Debug

PHY
IEEE 1588

USB

a few hundred meters of cell radius. On the

PHY

EEPROM

CPRI

JESD207/
ADI
CPRI

the mast or in a remote location and connected

Antenna

to the baseband unit through the CPRI optical

RF IC

CPRI

interface. The below charts depict the different

options.

The combination of the four JESD207 interfaces or the two CPRI interfaces enables the PSC9132 to support dual mode of WCDMA and LTE with
different antenna configurations, for example 2x2 for WCDMA 5 MHz and 2x4 for LTE 20 MHz simultaneously.

PSC9131 SMB/home Femtocell solution

The PSC9131 SoC (System-on-Chip) device is targeted at Small-Medium-Business/Home base station deployments, the solution standards and
capacities include:
Standards: FDD/TDD LTE (Rel. 8/9), WCDMA (Rel. 99/6/7/8) and CDMA2K/EV-DO
LTE Bandwidth: 20 MHz single sector
WCDMA/HSPA+ Bandwidth: 5 MHz
LTE throughputs: 100Mbps DL/50Mbps UL with 2x2 antenna MiMO
HSPA throughputs: Single Cell
42 Mbps DL/11 Mbps UL

QorIQ
QorIQ
Qonverge
PSC9130
and
PSC9131 Processors
Qonverge
PSC9130
and PSC9131
Processors

Active Users in Single Mode

LTE16 users, or
HSPA16 users
Active Users in Dual mode

StarCore SC3850
DSP Core
32 KB L1
I-Cache

32 KB L1
D-Cache

512 KB
L2 Cache

8 LTE users and 8 HSPA users

e500 Core
Built on
Power Architecture
32 KB
I-Cache

32 KB
D-Cache

Coherency
Module

256 KB
L2 Cache

32-bit
DDR3/3L
Memory
Controller

MAPLE-B2F
Baseband
Accelerator
LTE/UMTS/CDMA2K

RF Interface
(JESD207/ADI)
and MaxPHY

simultaneously
Multicore Fabric

PSC9131 device features

Power Architecture e500 core at up to
1GHz
Starcore SC3850 DSP at up to 1GHz
MAPLE-B2F Baseband Accelerators
Platform

4x eSPI
2x DUART

Ethernet

2x I2C
GPIO
USIM

DMA

Security
Engine
v4.4

USB
2.0

IEEE 1588
1x GE

1x GE

IFC
eSDHC
2x PWM
Clocks/Reset

DMA engine
Security acceleration engine handling IPSec, Kasumi, Snow-3G
DDR3/3L, 32bit wide, 800 MHz, with ECC
IEEE1588 v2, NTP and interface to GPS sync. support
2G/3G Sniffing Support
Secured Boot support
Interfaces2x Ethernet 1G RGMII, 3x JESD207/ADI RF transceiver interfaces, USB 2.0, NAND/NOR flash controller, UART, eSDHC, USIM,
I2C, eSPI
8

QorIQ Qonverge Platform

Macrocell solutionP4080
processor and 3x MSC8157 DSP

eNodeB
eNodeB
Channel Card
Channel Card

P4080 Power Architecture processor and 3x

Remote Radio Heads

Layer 1

MSC8157 DSPs discrete solution is targeted

Layer 2/3

SRIO

at Macrocell base station deployments, this

MSC8157 DSP

CPRI 6 GHz

solution supporting standards and capacities

1x GE

include:
CPRI

Standards: FDD/TDD LTE (Rel. 8/9/10) and

P4080
Processor

SRIO

6 GHz

1x GE

WCDMA (Rel. 99/6/7/8/9)

LTE Bandwidth: 20 MHz up to 6 sectors

MSC8157 DSP

CPRI 6 GHz

LTE-Advanced Bandwidth: 60 MHz single

CPRI

sector

SRIO

6 GHz

WCDMA-HSPA+ Bandwidth: Up to 9 cells

of 5 MHz

MSC8157 DSP

CPRI 6 GHz

LTE aggregated throughputs: 900Mbps DL/

450Mbps UL with 4x4 or 8x8 antenna
MiMO
Active Users
LTE900 users, or
HSPA+/AMR384/900 active users respectively
The above macro base station channel card architecture is capable of delivering the highest throughputs allowed by the LTE standard for 20 MHz
and enable connecting to remote radio heads (RRH) via fiber optic cables using the CPRI (Common Radio Public Interface) protocol that can spread
over 10Km or more.

QorIQ
QorIQ
P4080 Communication Processor
P4080 Communication Processor
Power Architecture
e500-mc Core

128 KB
Backside
L2 Cache

32 KB
D-Cache

32 KB
I-Cache

eOpenPIC

1024 KB
Frontside CoreNet
Platform Cache

64-bit
DDR2/3
Memory Controller

1024 KB
Frontside CoreNet
Platform Cache

64-bit
DDR2/3
Memory Controller

CoreNet Coherency Fabric

PreBoot Loader

PAMU

PAMU

PAMU

PAMU

PAMU

Frame Manager

Frame Manager

Parse, Classify,
Distribute
Buffer

Parse, Classify,
Distribute
Buffer

Peripheral Access
Management Unit

Security Monitor
Internal BootROM
Power Mgmt
SD/MMC

eLBC

Security
4.0

Queue
Mgr.

Test
Port/
SAP

Pattern
Match
Engine
2.0

Buffer
Mgr.

SPI
4x I2C
2x USB 2.0/ULPI
Clocks/Reset

10 GE

1 GE

1 GE

1 GE

1 GE

10 GE

1 GE

1 GE

1 GE

1 GE

GPIO

Real-Time Debug

RapidIO
Message
Unit

PCIe

PCIe

2x DMA

PCIe

SRIO

SRIO

Watchpoint
Cross
Trigger
Perf. CoreNet
Monitor Trace
Aurora

18-Lane 5 GHz SerDes

CCSR

Core Complex (CPU, L2 and Frontside CoreNet Platform Cache)

Accelerators and Memory Control

Basic Peripherals and Interconnect

Networking Elements

QorIQ P4080 processor

Device features
Eight high-performance e500mc cores up to 1.5 GHz
Three level cache-hierarchy: 32 KB I/D L1; 128 KB private L2 per core; 2MB shared L3
Dual 64-bit (with ECC) DDR2/3 memory controllers up to 1.333 GHz data rate
Datapath Acceleration Architecture incorporating acceleration for the following functions: Packet parsing, classification and distribution
Queue management for scheduling, packet sequencing and congestion management
Hardware Buffer Management for buffer allocation and de-allocation
9

QorIQ Qonverge Platform

Security Engine
Pattern Matching
Ethernet interfaces:
Two 10 GBps Ethernet (XAUI) controllers
Eight 1 GBps Ethernet (SGMII) controllers
iEEE 1588v2
High-speed peripheral interfaces:
Three PCI Express v2.0 controllers/ports running at up to 5GHz
Dual Serial RapidIO 4x/2x/1x ports running at up to 3.125 GHz
Hardware hypervisor for safe partitioning of operating systems between cores
Secured boot capability
SD/MMC, 2x DUART, 4x I2C, 2x USB 2.0 with integrated PHY
Other peripheral interfaces: Two USB controllers with ULPI interface to external PHY, enhanced local bus controller, SD/MMC, SPI controller,
four I2C controllers, two dual UARTs, two 4-channel DMA engines

MSC8157 DSP
Device features

MSC8157
MSC8157
DSP DSP

6x SC3850 DSP cores subsystems each

with:

StarCore SC3850
DSP Core

SC3850 core at up to 1.2GHz

512 KB unified L2 cache/M2 memory

32 KB L1

32 KB L1

I-Cache

D-Cache

32 KB I-cache, 32KB D-cache, Writeback-buffer (WBB), Write through Buffer

(WTB), Memory Management Unit (MMU),
Programmable Interrupt Controller (PIC)
Internal/External Memories/Caches

64-bit
DDR3
Memory
Controller
1.33 GHz

3 MB
Shared
M3 Memory

512 KB
L2 Cache
SPI
I2C

CLASS Multicore Fabric

UART
Clocks/Reset
GPIO

3 MB M3 shared memory (SRAM)

Ethernet
DMA

1x GE

1x GE

DDR3 64-bit SDRAM interface at up to

1.333 GHz, with ECC

SGMII/
RGMII

Total 6 MB internal memory

SGMII/
RGMII

eMSG

DMA

SRIO

SRIO

x4

PCIe
x4

CPRI
4.1

x4

10-lane 6 GHz SerDes

CLASSChip-Level Arbitration and

Switching Fabric
Non-Blocking, fully pipelined and low latency
MAPLE-BBaseband Acceleration Platform
Turbo/Viterbi Decoder supporting: LTE, LTE-Advanced, 802.16e and m, WCDMA Chiprate and TD-SCDMA standards
FFT/DFT accelerator
Downlink accelerator for Turbo Encoding and Rate matching
MIMO acceleration support for MMSE, SIC, ML schemes and Matrix inversions
Chip rate despreading/spreading and descrambling/scrambling
CRC insertion and check
10 SERDES lanes high speed Interconnects
Two 4x/2x/1x Serial RapidIO v2.0 at up to 5G, daisy-chain capable
Six lanes CPRI v4.1 up to 6.144G, daisy-chain capable
PCI-e v2.0 4x/2x/1x at 5Gb
Two SGMII/RGMII Gigabit Ethernet ports
DMA Engine 32 channels
Other Peripheral Interfaces: SPI, UART, I2C, GPIOs, JTAG 1149.6
10

x6

MAPLE-B
Baseband
Accelerator

QorIQ Qonverge Platform

MSC8157
MSC8157
DSPPHY
DSPPHY
Downlink Downlink
Uplink Chain Uplink Chain
MAC Layer
MSC8157 DSPPHY Downlink Chain

CRC
attach

Turbo
Encoding

Vendors IP

Scrambling
and
Modulation

Rate
Matching

Close Loops
Within MAPLE

Layer
Mapping
Pre-Coding
and Resource
Mapping

Simple Software Implementation/

Low Core Load
MAC Layer

MSC8157 DSPPHY Uplink Chain

Channel
Est.
CE-DFT

FFT

IFFT

Freq.
MIMO
De-Modulation
Offset
IDFT
De-Interleaving
Descrambling
CE-Interp. Equalizer
Compensation
Matrix
Inversion
Very Low Latency Floating Point/
Excellent BLER
Very Flexible LTE-A Support (4x8)

SC3850 DSP Cores

RateDematching, Transport
CRC
HARQ
Block
Check
Combining,
CRC
Turbo decoding

Simple Software
Implementation and
Adaptable for LTE-A Changes

MAPLE-B

Microcell SolutionP3041 or
P2040 processor and
MSC8157 DSP

Microcell Channel Card

Microcell Channel Card

Built based on the P3041 or P2040 processor

Layer 1

Layer 2/3

and the MSC8157 DSP, targeted at Microcell

basestation deployments, its standards and
capacities support:
Standards: FDD/TDD LTE (Rel. 8/9/10) and

CPRI 6 GHz

MSC8157 DSP

SRIO

1x GE

P2040/P3041
Processor

1x GE

WCDMA (Rel. 99/6/7/8/9)

LTE Bandwidth: 20 MHz up to 2 sectors
LTE-Advanced Bandwidth: 20 MHz single
sector
WCDMA-HSPA+ Bandwidth: Up to 3 cells
of 5 MHz
LTE throughputs: 300 Mbps DL/150 Mbps UL with 4Tx and 4Rx antenna MiMO
Active Users
o LTE300 users, or
o HSPA+/AMR128/300 active users respectively

11

QorIQ Qonverge Platform

Software migration
Many leading OEMs are deploying the QorIQ family and the MSC8156/7 DSP devices in their Macro base station designs. The family of devices for
small cells brings an unprecedented high level of software reuse from the macro cells by reusing the same basic elements. The DSP and processor
cores are software backward compatible and MAPLE processing elements keeps the same API calls moving from Macro, Micro devices to Small Cell
SoCs and vice versa. This kind of reuse means much faster development time from the OEMs, resulting in lower engineering costs and faster time to
market.

Software offering and mapping

for PSC913X
Freescale provides not only the silicon but also
a comprehensive software solution for small

Software Offering and Mapping for PSC913X

Software Offering and Mapping for PSC913X

Applications
Layer API

software engagement model where Freescale

delivers L1 modem software for LTE, WCDMA
and dual-mode while its partners deliver the L2
and L3 software protocol stacks.

RISC Core
(Linux OS, RTP)

Operation and Maintenance

cells and the ability to run it in simultaneous

dual-mode. The chart below depicts the

Application Software

Additional Services

Payload

Can Mix and Match Software

Modules from Internal Sources,
Freescale/VortiQa and
Third-Party Ecosystem

RRC

PDCP
RLC

Freescale L1 API
Aligns with Femto
Forum FAPI

RISC Cores
(Linux OS)

IPv4/v6

MAC

IPSEC

L1 Control

Ethernet Control

Operator/OEM Supplied

MAC/RLC/PDCP/O&M
Software

RTP/GTP Signaling/
STCP
UDP

L1 Modem with
Hardware
Accelerators

LTE and WCDMA Modems

Software

Software Partner Supplied

Freescale Supplied

Software mapping on PSC9132

The stacks diagram below provides an example
on the functional mapping of the LTE software

Software
Software
Mapping
on PSC9132
Mapping
on PSC9132
e500v2 Core

e500v2 Core
RRM

components on the PSC9132 device.

OAM

GTP-U

The physical layer (L1) processing is handled

PDCP

entirely by the StarCore core subsystems with

DL, UL Scheduler

the support of the MAPLE-B accelerator. This

DL + UL RLC

functional split allows the encapsulation and

control of the modem part under the Femto
API (FAPI) as proposed by the Femto Forum.
This API provides the guidelines for the logical
interface between the L1 and L2 that the
industry has widely adopted.

12

NBAP

DL + UL MAC
LTE L1-L2 API

IKEv2

S1-AP, X2-AP
ROHC

FP

WCDMA MAC-(e)hs/e/i

MAC-B

Infra
Services

LTE L1-L2 API

eGTP-U

SCTP

UDP

DL, UL Scheduler

SEC

IP (IP sec)
Infra
Services

Ethernet
(Backhaul QoS)

veTSEC

Linux SMP, RT Patch, Core Affinity

MAPLE
Accelerators
eFTPE
eTVPE
EQPE
PUPE
PDPE
DEPE

SC3850

SC3850

LTE L1-L2 FAPI

LTE L1-L2 FAPI

PHY Controller
Sec 0
DL Control Ch.

(Estimations, PUCCH,
SRS, RACH)

UL Processing

PHY Controller
Sec 1
DL Control Ch.

(Estimations, PUCCH,
SRS, RACH)

Infra Services

SDOS

Infra Services

SDOS

UL Processing

QorIQ Qonverge Platform

Summary
Major changes are happening in the Radio Access Network including multimode and multi-standard base stations, and small/compact base
stations such as Picocells, Metrocells, Microcells, Femtocells and Macrocells with distributed and more flexible antenna systems for 3G and 4G. The
standards evolution and all the above create new commercial and technical challenges for OEMs and wireless operators. Shorter time to market and
a broader, more complex range of developments creates an urgent need for scalability and reuse in both hardware and software. With the wealth
of products that meet different base station capacities, and by leveraging the high performance processor and DSP cores together with baseband
accelerators optimal for both LTE and WCDMA processing, designers can improve base stations spectral efficiency and costs.
Freescale products address the key business needs of the OEMs and wireless operators by enhancing and optimizing to the future wireless network
in multiple key areas of Macrocells, Microcells and small cells. To achieve these enhancements, Freescale uses an array of in-house core technology
innovations in baseband processing that are all designed in flexible and software upgradeable manners. Moreover, easy software migration between
cores, technologies and different wireless standards delivered with commercial layer 1 software stacks for the small cells, enable fast time to market
and continuous optimization for throughputs, power and costs when moving from one generation to another. Freescale is using more advanced IP
and process technologies as demand for higher performance increases and as the network evolves to smaller cells and distributed antenna systems
that change dynamically with the ever-changing standards and services needs.

13

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Document Number: QORIQQONVERGEWP/REV 0