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CS M151B / EE M116C: Computer Systems Architecture

This document provides notes for a lecture on ALU design. It discusses: - Updating homework assignments and exam dates - Binary number representation including two's complement for positive and negative numbers - Binary arithmetic including addition, subtraction, and overflow detection - Floating point number representation and arithmetic - Design of a basic one-bit ALU and how to extend it to a multi-bit ALU - Additional ALU operations like AND, OR, subtraction, zero detection, and set on less than - Optimization techniques for faster addition like carry lookahead adders

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56 views

CS M151B / EE M116C: Computer Systems Architecture

This document provides notes for a lecture on ALU design. It discusses: - Updating homework assignments and exam dates - Binary number representation including two's complement for positive and negative numbers - Binary arithmetic including addition, subtraction, and overflow detection - Floating point number representation and arithmetic - Design of a basic one-bit ALU and how to extend it to a multi-bit ALU - Additional ALU operations like AND, OR, subtraction, zero detection, and set on less than - Optimization techniques for faster addition like carry lookahead adders

Uploaded by

tinhtrilac
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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You are on page 1/ 33

CS M151B / EE M116C

Computer Systems Architecture

ALU Design Part 1

Instructor: Prof. Lei He


<LHE@ee.ucla.edu>

Some notes adopted from Glenn Reinman

misc

Hw2 has been updated (due Jan 24)


Hw3 will be the sample midterm1 (due Jan 31)
Account for auditing (bruin, gobruin)
This lecture: ALU I
Next lecture (Jan 24): finish ALU
(by guest lecturer)

Jan 26 (Thursday) TA for review (no review session


next week)
Midterm I (Feb. 4th, Thursday)

Binary Numbers

Consider a 4-bit binary number


Decimal
0
1
2
3

Binary
0000
0001
0010
0011

Decimal
4
5
6
7

Binary
0100
0101
0110
0111

Examples of binary arithmetic:


3+2=5
+

3+3=6

Two s Complement Representation

Positive numbers: normal binary representation


Negative numbers: flip bits (0 !"1) , then add 1
Decimal
-8
-7
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
7

Two s Complement Binary


1000
1001
Smallest 4-bit
1010
number: -8
1011
1100
1101
1110
1111
0000
0001
0010
0011
Biggest 4-bit
0100
0101
number: 7
0110
0111

Two s Complement Arithmetic

Uses simple adder for + and - numbers


7 + (- 6) = 1
1

Decimal
0
1
2
3
4

2 s Complement Binary
0000
0001
0010
0011
0100

3 + (- 5) = -2
+

Decimal
-1
-2
-3
-4
-5

2 s Complement Binary
1111
1110
1101
1100
1011

0101

-6

1010

6
7

0110
0111

-7
-8

1001
1000

Details of Two s Complement Notation

Negation

flip bits and add 1. (Magic! Works for + and -)


Might cause overflow

Extend sign when loading into large register


+3 => 0011, 00000011, 0000000000000011
-3 => 1101, 11111101, 1111111111111101

Overflow detection (need to raise exception


when answer can t be represented)
0101 5
+ 0110 6
1011 -5 ??!!!

Overflow Detection

7
3

-6

So how do we detect overflow?

-4

-2

-6

-4
-5

Floating Point (FP)

Binary fractions:
10112 = 1x23 + 0x22 + 1x21 + 1x20

AND:
101.012 = 1x22 + 0x21 + 1x20 + 0x2-1 + 1x2-2

Example:
.75 = 3/4 = 1/2 + 1/4 = .112

Recall Scientific Notation

exponent

decimal point
sign

+6.02 x 10

Mantissa

23

radix (base)

Issues:
Arithmetic (+, -, *, / )
Representation, Normal form
Range and Precision
Rounding
Exceptions (e.g., divide by zero, overflow, underflow)
Errors
Properties ( negation, inversion, if A = B then A - B = 0 )

IEEE 754 FP Numbers

Single precision
representation of
(-1)S 2E-127 (1.M)

sign
bit

23

exponent:
excess 127
binary integer
(actual exponent
is e = E - 127)

mantissa:
sign + magnitude, normalized
binary significand with hidden
integer bit: 1.M

0 = 0 00000000 00 . . . 0
-1.5 = 1 01111111 10 . . . 0
325 = 101000101 = 1.01000101 x 28
= 0 10000111 01000101000000000000000
.02 = .0011001101100... = 1.1001101100... x 2-3
= 0 01111100 1001101100...

range of about 2 X 10-38 to 2 X 1038


always normalized (so always leading 1, never shown)
special representation of 0 (E = 00000000)
can do integer compare for greater-than, sign

Double Precision FP (IEEE 754)

sign

11

20

32

exponent:
excess 1023
binary integer
actual exponent is e = E - 1023

N = (-1)S 2 E-1023(1.M)

52 (+1) bit mantissa


range of about 2 X 10-308 to 2 X 10308

mantissa:
sign + magnitude, normalized
binary significand with hidden
integer bit: 1.M

Arithmetic Logic Unit Design

Instruction
Fetch

ALU operation

Instruction
Decode
Operand
Fetch

a
ALU

Execute
Result
Store
Next
Instruction

b
CarryOut

Zero
Result
Overflow

One Bit ALU

Performs AND, OR, and ADD


on 1-bit operands
components:

Operation
Operation
Operation
CarryIn

CarryIn

CarryIn
CarryIn

a
AND gate

0
00

aa

OR gate

1
11

1-bit adder
b

2
22

bb

Operation

Result
Result
Result

Operation
CarryIn

Multiplexor
b

CarryOut
0
CarryOut
CarryOut
1

Result

CarryOut

Result

One Bit Full Adder

Also known as a (3,2) adder


Half Adder

CarryIn

no CarryIn

Sum
b

Inputs

Outputs
Sum

Comments

0+0+0=00

0+0+1=01

0+1+0=01

0+1+1=10

1+0+0=01

1+0+1=10

1+0+1=10

1+1+1=11

CarryIn CarryOut

CarryOut

CarryOut Logic Equation

CarryOut = (!a & b & CarryIn) | (a & !b & CarryIn)


| (a & b & !CarryIn) | (a & b & CarryIn)
CarryOut = (b & CarryIn) | (a & CarryIn) | (a & b)
Inputs

Outputs
Sum

Comments

0+0+0=00

0+0+1=01

0+1+0=01

0+1+1=10

1+0+0=01

1+0+1=10

1+0+1=10

1+1+1=11

CarryIn CarryOut

Sum Logic Equation

Sum = (!a & !b & CarryIn) | (!a & b & !CarryIn)


| (a & !b & !CarryIn) | (a & b & CarryIn)

Inputs

Outputs
Sum

Comments

0+0+0=00

0+0+1=01

0+1+0=01

0+1+1=10

1+0+0=01

1+0+1=10

1+0+1=10

1+1+1=11

CarryIn CarryOut

32-bit ALU

Ripple Carry ALU


a0

Operation

b0

CarryIn
a

CarryIn

Operation

CarryIn
ALU0

Result0

CarryOut

a1

b1

CarryIn
ALU1

Result1

CarryOut

Result

a2
b2

CarryOut

1-bit ALU

ALU2

Result2

CarryOut

CarryIn

a31
b31

CarryIn
ALU31

Result31

32-bit ALU

Subtraction?

Expand our 1-bit ALU to include an inverter


2 s complement: take inverse of every bit and add 1
Binvert

Operation
CarryIn

0
1

CarryOut

Result

Overflow

For N-bit ALU

Overflow = CarryIn[N-1] XOR CarryOut[N-1]


Binvert

Operation
CarryIn

0
1

Result

XOR

CarryOut

Most significant (N-1) bit ALU

Overflow

Zero Detection

Conditional Branches
One big NOR gate
Zero = (ResultN-1+ResultN-2+....
Result1+Result0)
Any non-zero result will cause zero detection
output to be zero

Set-On-Less-Than (SLT)

SLT produces a 1 if rs < rt, and 0 otherwise


all but least significant bit will be 0
how do we set the least significant bit?
can we use subtraction?
rs - rt < 0

set the least significant bit to the sign-bit of (rs - rt)

New input: LESS


New output: SET

SLT Implementation

a.

CarryOut

Binvert

Binvert

Operation
CarryIn

Operation
CarryIn

1
Result

1
b

Result
b

2
Less

3
Set

Less

3
Overflow
detection

CarryOut

All but MSB

b.

Most Significant Bit

Overflow

Binvert

CarryIn

a0
b0

CarryIn
ALU0
Less
CarryOut

a1
b1
0

CarryIn
ALU1
Less
CarryOut

a2
b2
0

CarryIn
ALU2
Less
CarryOut

SLT Implementation

Operation

Result0

Result1

Result2

CarryIn

a31
b31
0

CarryIn
ALU31
Less

Result31
Set
Overflow

Set of MSB is connected


to Less of LSB!

Final Full Adder

You should feel


comfortable
identifying what
signals
accomplish:
add
sub
and
or
beq
slt

Bnegate

Operation

a0
b0

CarryIn
ALU0
Less
CarryOut

Result0

a1
b1
0

CarryIn
ALU1
Less
CarryOut

Result1

a2
b2
0

CarryIn
ALU2
Less
CarryOut

Result2

a31
b31
0

CarryIn
ALU31
Less

Zero

Result31
Set
Overflow

Can We Make a Faster Adder?

Worst case delay for N-bit Ripple Carry Adder


2N gate delays
2 gates per CarryOut
N CarryOuts

CarryIn

b
CarryOut

We will explore the Carry Lookahead Adder


Generate - Bit i creates new Carry
gi = Ai & Bi

Propagate - Bit i continues a Carry


pi = Ai | Bi

Carry Lookahead Adder (CLA)

Generate - Bit i creates new Carry


gi = Ai & Bi

Propagate - Bit i continues a Carry


pi = Ai | Bi

Now:
Cin1 = g0 | (p0 & Cin0)
Cin2 = g1 | (p1 & g0) | (p1 & p0 & Cin0)
Cin3 = g2 | (p2 & g1) | (p2 & p1 & g0) | (p2 & p1 & p0 &
Cin0)

This can get expensive if we try a full carry


lookahead adder!

Partial Carry Lookahead Adder

Connect several N-bit Lookahead Adders


together
Four 8-bit carry lookahead adders can form a
32-bit partial carry lookahead adder

Hierarchical CLA

CarryIn

a0
b0
a1
b1
a2
b2
a3
b3

CarryIn
Result0--3
ALU0
P0
G0

pi
gi
Car ry-lookahead unit
C1

a4
b4
a5
b5
a6
b6
a7
b7

a8
b8
a9
b9
a10
b10
a11
b11

a12
b12
a13
b13
a14
b14
a15
b15

ci + 1

CarryIn
Result4--7
ALU1
P1
G1

pi + 1
gi + 1
C2

ci + 2

CarryIn
Result8--11
ALU2
P2
G2

pi + 2
gi + 2
C3

ci + 3

CarryIn
Result12--15
ALU3
P3
G3

pi + 3
gi + 3
C4

CarryOut

ci + 4

Multiplication

Quick example
Multiplicand
Multiplier

1000
x
1001
1000
0000
0000
1000
Product 1001000

m bits x n bits = m+n bits


More complex than addition
more area and delay

Multiply Version 1

Start

Multiplier0 = 1

Multiplicand

1. Test
Multiplier0

Multiplier0 = 0

1a. Add multiplicand to product and


place the result in Product register

Shift left
64 bits

Multiplier
Shift right

64-bit ALU

32 bits
Product
Write

2. Shift the Multiplicand register left 1 bit

Control test

3. Shift the Multiplier register right 1 bit

64 bits

32nd repetition?

No: < 32 repetitions

Yes: 32 repetitions
Done

Multiply Version 2

Start

Multiplier0 = 1

Multiplicand

1. Test
Multiplier0

Multiplier0 = 0

1a. Add multiplicand to the left half of


the product and place the result in
the left half of the Product register

32 bits

Multiplier
Shift right

32-bit ALU

32 bits
Product
64 bits

Shift right
Write

2. Shift the Product register right 1 bit

Control test

3. Shift the Multiplier register right 1 bit

32nd repetition?

No: < 32 repetitions

Yes: 32 repetitions
Done

Multiply Version 3

Start

Product0 = 1

1. Test
Product0

Product0 = 0

Multiplicand
32 bits

1a. Add multiplicand to the left half of


the product and place the result in
the left half of the Product register

32-bit ALU

Product

Shift right
Write

Control
te s t

2. Shift the Product register right 1 bit

64 bits

32nd repetition?

No: < 32 repetitions

Yes: 32 repetitions
Done

Key Points

Two s complement is standard +/- numbers.


ISA drives ALU design
ALU performance, CPU clock speed driven by
adder delay
Multiply is expensive

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