Tcc89xx Chip Spec

CHIP
SPECIFICATION
TCC8900
High Performance and Low-Power Processor

For Digital Media Applications
Rev. 1.01
Aug 18, 2009
TCC8900
TCC8900_CHIP_SPEC
High Performance and Low-Power Processor for Digital Media Applications
Aug 18, 2009

REVISION HISTORY
Revision History
Date
2008-12-05
Revision
0.00
2008-12-11
0.01
2008-12-29
0.02
2009-01-22
0.03
2009-02-05
2009-03-10
0.04
0.05
2009-06-05
0.06
2009-08-07
1.00
2009-08-18
1.01
Description
* Initial Release
* Swapping of EDIXD0 and EDIXD8 in the Pin Description
* The ball maps of H1, J1, K1, L1, M1, N1, P1, T1, U1, V1, W1, Y1, L2, M2, N2, P2,
R2, U2, V2, W2, Y2, N3, P3, R3, T3, U3, V3, W3, Y3, P4, R4, T4, U4, V4, W4, Y4,
R5, T5, U5, V5, W5, Y5, P6, R6, V6, W6, Y6, P7, T7, U7, V7, Y7, T8, U8, V8, W8,
Y8, P9, R9, V9, W9, Y9, P10, R10, W10, Y10, T13, T14, N17, N18, M20, N20, P20
were changed.
The ball description on the Table 3.9 has been changed.
GPIOB[26] G6
GPIOB[27] C11
GPIOB[28] G7
GPIOB[29] D10
* The recommended operating frequency for each block was added.
* The resolution of the ADC(TSADC) was changed from 10 bits to 12 bits.
* The order of the TCO3 ~ TCO0 is changed to TCO0 ~ TCO3.
* The initial states of the GPIO were changed.
* Changing AC SPEC DAI(I2S)
* The initial states of the GPIOs have been changed.
* The ball map or pin description has been changed.
* The value of Ccard for SDMMC has been changed from 50pF to 30pF.
* Updating Timing Parameters for Each Symbol
TCC8900
TCC8900_CHIP_SPEC
Aug 18, 2009

TABLE OF CONTENTS
TABLE OF CONTENTS
Contents
1 Introduction ........................................................................................................................................................................ 1-1
1.1 TCC8900 Features................................................................................................................................................... 1-2
1.2 Applications .............................................................................................................................................................. 1-5
1.3 Block Diagram.......................................................................................................................................................... 1-6
2 Hardware Features............................................................................................................................................................. 2-7
3 PIN Description ................................................................................................................................................................ 3-15
3.1 TCC8900 Pin Description....................................................................................................................................... 3-15
3.2 TCC8900 I/O Type ................................................................................................................................................. 3-25
4 Package Information ........................................................................................................................................................ 4-27
4.1 Dimension .............................................................................................................................................................. 4-27
4.2 Ball Map ................................................................................................................................................................. 4-28
5 Electrical Specification...................................................................................................................................................... 5-29
5.1 Absolute Maximum Ratings.................................................................................................................................... 5-29
5.2 Recommended Operating Conditions .................................................................................................................... 5-30
5.3 Recommended Operating Frequency .................................................................................................................... 5-31
5.4 Electrical Characteristics for Power Supply............................................................................................................ 5-32
5.5 Electrical Characteristics for General I/O ............................................................................................................... 5-33
5.6 Electrical Characteristics for PLL ........................................................................................................................... 5-34
5.7 Electrical Characteristics for Video DAC ................................................................................................................ 5-35
5.8 Electrical Characteristics for ADC(for Touch Screen) ............................................................................................. 5-36
5.9 Electrical Characteristics for HDMI PHY ................................................................................................................ 5-37
5.10 Electrical Characteristics for LVDS....................................................................................................................... 5-38
5.11 Electrical Characteristics for SATA ....................................................................................................................... 5-39
5.12 Electrical Characteristics for LCD Interface.......................................................................................................... 5-40
5.13 Electrical Characteristics for Camera Interface .................................................................................................... 5-42
5.14 Electrical Characteristics for External Host Interface (EHI) .................................................................................. 5-44
5.15 Electrical Characteristics for SD/MMC Controller................................................................................................. 5-45
5.16 Electrical Characteristics for I2C Controller.......................................................................................................... 5-46
5.17 Electrical Characteristics for SPDI/F Transmitter ................................................................................................. 5-46
5.18 Electrical Characteristics for DAI(I2S) .................................................................................................................. 5-47
5.19 Electrical Characteristics for Nand Flash Controller ............................................................................................. 5-49
5.20 Electrical Characteristics for UART Controller...................................................................................................... 5-52
Figures
Figure 1.1 TCC8900 Functional Block Diagram...................................................................................................... 1-6
Figure 2.1 Memory Organization............................................................................................................................. 2-7
Figure 4.1 TCC8900 Package Dimension............................................................................................................. 4-27
Figure 4.2 TCC8900 Ball Map............................................................................................................................... 4-28
Figure 5.1 LVDS Transmit Timing Diagram ........................................................................................................... 5-38
Figure 5.2 Timing Diagram for LCD Controller ...................................................................................................... 5-40
Figure 5.3 Timing Diagram Data Output Referenced to PXCLK ........................................................................... 5-40
Figure 5.4 Timing Diagram Data Output Referenced to LCDSI............................................................................. 5-41
Figure 5.5 Timing Diagram for Camera Interface .................................................................................................. 5-42
Figure 5.6 Timing Diagram Data Output Referenced to CCLK.............................................................................. 5-42
Figure 5.7 EHI Timing Diagram............................................................................................................................. 5-44
Figure 5.8 Timing Diagram for SD/MMC Controller............................................................................................... 5-45
Figure 5.9 Timing Diagram for I2C Controller........................................................................................................ 5-46
Figure 5.10 Timing Diagram for SPDI/F Transmitter ............................................................................................. 5-46
Figure 5.11 Timing Diagram for DAI (receiver)...................................................................................................... 5-47
Figure 5.12 Timing Diagram for DAI Transmitter................................................................................................... 5-48
Figure 5.13 Timing Diagram for Command Latch Enable Cycle ........................................................................... 5-49
Figure 5.14 Timing Diagram for Single Address Latch Cycle ................................................................................ 5-49
Figure 5.15 Timing Diagram for Linear Address Latch Cycle ................................................................................ 5-49
Figure 5.16 Timing Diagram for Single Data Write Cycle ...................................................................................... 5-49
Figure 5.17 Timing Diagram for Linear Data Write Cycle ...................................................................................... 5-50
Figure 5.18 Timing Diagram for Single Data Read Cycle...................................................................................... 5-50
Figure 5.19 Timing Diagram for Linear Data Read Cycle...................................................................................... 5-50
Figure 5.20 Timing Diagram for TXD..................................................................................................................... 5-52
Figure 5.21 Timing Diagram for RXD .................................................................................................................... 5-52
Figure 5.22 Timing Diagram for TX Operation with H/W Flow Control .................................................................. 5-53
Figure 5.23 Timing Diagram for nCTS Timing Diagram ........................................................................................ 5-53
Figure 5.24 Timing Diagram for RX Operation with H/W Flow Control.................................................................. 5-54
Figure 5.25 Timing Diagram for nRTS Timing Diagram......................................................................................... 5-54
Aug 18, 2009

TABLE OF CONTENTS
TCC8900
TCC8900_CHIP_SPEC
Tables
Table 1.1 TCC8900 Features .................................................................................................................................. 1-2
Table 2.1 ARM1176JZFS Processor........................................................................................................................ 2-7
Table 2.2 Video Controller ....................................................................................................................................... 2-8
Table 2.3 Camera Interface ..................................................................................................................................... 2-8
Table 2.4 Video Output Interface ............................................................................................................................. 2-9
Table 2.5 DAI/CDIF Controller............................................................................................................................... 2-10
Table 2.6 SPDIF Controller.................................................................................................................................... 2-10
Table 2.7 External Device Interface....................................................................................................................... 2-10
Table 2.8 USB 1.1 Host ......................................................................................................................................... 2-10
Table 2.9 USB 2.0 OTG(On-The-GO) ................................................................................................................... 2-10
Table 2.10 nano PHY for USB2.0 OTG and USB1.1 Host..................................................................................... 2-11
Table 2.11 External Host Interface......................................................................................................................... 2-11
Table 2.12 SD/MMC Controller.............................................................................................................................. 2-11
Table 2.13 Memory Stick Controller....................................................................................................................... 2-11
Table 2.14 Nand Flash Controller.......................................................................................................................... 2-12
Table 2.15 IDE interface ........................................................................................................................................ 2-12
Table 2.16 UART Interface .................................................................................................................................... 2-12
Table 2.17 GPSB Interface.................................................................................................................................... 2-13
Table 2.18 General DMA Controller....................................................................................................................... 2-13
Table 2.19 Vectored Interrupt Controller................................................................................................................ 2-13
Table 2.20 Timer.................................................................................................................................................... 2-13
Table 2.21 ADC ..................................................................................................................................................... 2-14
Table 2.22 Real Time Clock................................................................................................................................... 2-14
Table 3.1 Power/Ground Information..................................................................................................................... 3-15
Table 3.2 PWRGPIOC Group I/O Pin Description ................................................................................................. 3-16
Table 3.3 PWRGPIOF Group I/O Pin Description ................................................................................................. 3-17
Table 3.4 PWRGPIOE Group I/O Pin Description ................................................................................................. 3-18
Table 3.5 PWRGPIOA Group I/O Pin Description ................................................................................................. 3-19
Table 3.6 PWRADC Group I/O Pin Description ..................................................................................................... 3-20
Table 3.7 PWRETC Group I/O Pin Description ..................................................................................................... 3-20
Table 3.8 PWRGPIOD Group I/O Pin Description ................................................................................................. 3-21
Table 3.9 PWRGPIOB Group I/O Pin Description ................................................................................................. 3-22
Table 3.10 PWRMEMQ Group I/O Pin Description ............................................................................................... 3-23
Table 3.11 PWROSC Group I/O Pin Description ................................................................................................... 3-24
Table 3.12 PWRUSB33 Group I/O Pin Description ............................................................................................... 3-24
Table 3.13 PWRUSBH Group I/O Pin Description................................................................................................. 3-24
Table 3.14 PWRRTC Group I/O Pin Description ................................................................................................... 3-24
Table 3.15 PWRSATAOSC Group I/O Pin Description .......................................................................................... 3-24
Table 3.16 PWRSATA Group I/O Pin Description .................................................................................................. 3-24
Table 3.17 PWRHDMIOSC Group I/O Pin Description.......................................................................................... 3-24
Table 3.18 PWRHDMI Group I/O Pin Description ................................................................................................. 3-24
Table 3.19 PWRLVDS Group I/O Pin Description.................................................................................................. 3-24
Table 3.20 PWRDAC Group I/O Pin Description ................................................................................................... 3-24
Table 3.21 TCC8900 I/O Type ............................................................................................................................... 3-25
Table 5.1 Recommended Operating Conditions.................................................................................................... 5-30
Table 5.2 Recommended Operating Frequency.................................................................................................... 5-31
Table 5.3 Peak Power Consumption ..................................................................................................................... 5-32
Table 5.4 DC Electrical Specification for General I/O ............................................................................................ 5-33
Table 5.5 DC Electrical Characteristics for PLL0................................................................................................... 5-34
Table 5.6 AC Electrical Characteristics for PLL0 ................................................................................................... 5-34
Table 5.7 DC Electrical Characteristics for PLL1/2/3 ............................................................................................. 5-34
Table 5.8 AC Electrical Characteristics for PLL1/2/3 ............................................................................................. 5-34
Table 5.9 DC Electrical Characteristics for DAC.................................................................................................... 5-35
Table 5.10 DC Electrical Characteristics for ADC.................................................................................................. 5-36
Table 5.11 AC Electrical Characteristics for ADC................................................................................................... 5-36
Table 5.12 DC Electrical Characteristics for HDMI PHY........................................................................................ 5-37
Table 5.13 AC Electrical Characteristics for HDMI Oscillator................................................................................. 5-37
Table 5.14 DC Electrical Characteristics for LVDS ................................................................................................ 5-38
Table 5.15 AC Electrical Characteristics for LVDS................................................................................................. 5-38
Table 5.16 DC Electrical Characteristics for SATA ................................................................................................ 5-39
Table 5.17 AC Electrical Characteristics for SATA Oscillator ................................................................................. 5-39
Table 5.18 AC Electrical Characteristics for SATA TX/RX...................................................................................... 5-39
Table 5.19 Timing Parameters for Each Symbol ................................................................................................... 5-40
Table 5.20 I/O Function Name for Corresponding Signal Name............................................................................ 5-40
Table 5.21 Timing Parameters for Each Symbols.................................................................................................. 5-41
6
TCC8900
TCC8900_CHIP_SPEC
Aug 18, 2009

TABLE OF CONTENTS
Table 5.23 I/O Function Name for Corresponding Signal Name ........................................................................... 5-43
Table 5.27 Timing for DAI (receiver)...................................................................................................................... 5-47
Table 5.28 Timing Parameters for Each Symbols ................................................................................................. 5-48
Table 5.30 I/O Function Name for Corresponding Signal Name ........................................................................... 5-51
Table 5.34 Timing Parameters for Each Symbols ................................................................................................. 5-54
TCC8900
TCC8900_CHIP_SPEC
Aug 18, 2009

INTRODUCTION
1 Introduction
The TCC8900 is the system LSI for digital multimedia applications which based on ARM1176JZF-S, ARMs proprietary RISC
CPU core. It can decode and encode various types of video and audio standards by software and dedicated hardware
accelerators JPEG / MPEG1 / MPEG2 / MPEG4-SP/ASP / H.264 / VC-1 / RV and other types of video standard and MP3 /
AAC / MPEG4-AAC / MPEG4-BSAC and other types of standard for audio
The on-chip high speed USB2.0 device controller enables the data transmission between a personal computer and storage
device such as NAND flash, HDD, CD, SD, MMC and Memory Stick etc, which can be controlled by the TCC8900.
1-1
Aug 18, 2009

INTRODUCTION
TCC8900
TCC8900_CHIP_SPEC
1.1 TCC8900 Features

Table 1.1 TCC8900 Features
Category
Description
TM
* TrustZone security extensions
* High-speed AMBA AXI Bus Interface
* High performance integer processor
* 8 stage pipelines
* Separate load-store and arithmetic pipelines
* Branch prediction with return stack
* Instruction and Data MMU(Memory Management Units)
PROCESSORS
* Micro TLB structures backed by a unified Main TLB.
(ARM1176JZF-S)
* Virtually indexed and physically addressed caches
* Level one TCM(Tightly-Coupled Memory)
* 16KBs ITCM and 16KBs DTCM
* 16KBs Instruction/Data Caches
* Including a non-blocking data cache with Hit-Under-Miss(HUM)
* Vector-Floating-Point(VFP) coprocessor support
* ARM Jazelle technology for efficient embedded Java execution
* JTAG interface for code debugging
* Internal(On-Chip) Memory
* 16KB Boot-ROM (EHI, NAND, USB Boot with security and etc.)
* 16KB Internal SRAM (Shared by Hardware)
* External(Off-Chip) Memory
MEMORY ORGANIZATION 1 * SDRAM
: up to 200MHz
* mDDR SDRAM : up to 200MHz(400Mbps)
* DDR SDRAM
: up to 200MHz(400Mbps)
* DDR2 SDRAM : up to 400MHz(800Mbps)
* 32bits Data Bus
2
* Decompressor (Decoder) up to 30fps @ Full-HD (1920x1080)
* H.263
: up to 40Mbps
* MPEG 1/2
* Up to Main Profile @ High Level
* Max. bitrate : up to 40Mbps
* MPEG4-ASP
* Up to Advanced Simple Profile Including DivX3.x
* MPEG4-AVC(H.264)
* Up to High Profile @ Level 5.1 3
VIDEO CODEC
* VC-1
* Up to Advanced Profile @ Level 3.0
* RV
* Real Video 10 ( Backward Compatible for RV8.9)
* JPEG
: up to 12Mpixels
* Compressor 4 (Encoder) up to 30fps or 24fps @HD(1280x720)
* H.263 : up to 30fps @ HD(1280x720p)
* MPEG4-ASP : up to 30fps @ HD(1280x720p)
* H.264 : up to 24fps @ HD(1280x720p)
* JPEG : up to 12Mpixels
* 2D/3D Graphic
* High Geometry and Pixel Processing
* Up to 7M polygon 5
* Full OpenVG v1.1 Support
GRAPHIC ENGINE
* Lines, Squares, Triangles, Points
* Vector Graphics
* ROP 3/4
* Arbitrary Rotation / Scaling
* Alpha Blending
1
2
3
4
5
The maximum operation frequency can be limited by the system configuration.

The performance of the video decoding can be limited by the system configuration.
Up to 1920x1080 30fps 25Mbps : Ref.Frame : 96Mbyte for VPU Memory in case of 32 Ref frame
The performance of the video encoding can be varied by the system configuration.
The maximum performance for this can be varied by the system configuration.
1-2
TCC8900
TCC8900_CHIP_SPEC
IMAGE ENHANCEMENT
VIDEO IN/OUT
Aug 18, 2009

INTRODUCTION
* Multitexture BItBLT
* Full OpenGL ES v2.0, v1.x Support
* 4X /16X FSAA
* Flat/Gouraud Shading
* Perspective Correct Texturing
* Point Sampling/Bilinear/Trilinear Filtering
* Mipmapping
* Multi Texturing
* Dot3 Bump Mapping
* Alpha Blending
* Stencil Buffering (4-bit)
* JSR 184
* Point Sprites
* 2 bit per pixel Texture Compressing (FLXTC)
* 4 bit per pixel Texture Compressing (ETC)
* Overlay Mixer
* 8bpp (RGB332)
* RGB (444, 454, 555, 565, 666, 888)
* Alpha-RGB (444, 454, 555, 666, 888)
* Sequential YUV (444, 422)
* Separated YUV (444, 440, 422, 420, 411, 410)
* Interleaved YUV (422, 420)
* BitBLT (16 Raster Operations)
* 3 Channel Source Mirror/Flip/90, 180, 270 Rotate
* 1 Channel Destination Mirror/Flip/90, 180, 270 Rotate
* 3 Channel Arithmetic Operation
* 3 Channel YCbCr-to-RGB Color Space Converting
* Overlay and Alphablending (2 overlay, 256-level alphablending)
* Color LUT
* Dithering
* Histogram Measurement
* Analyze the Luminance Components
* Multi-frames Average Mode
* User-defined Pixel Segments Support
* Contrast Enhancement
* User-defined Scaling Segments
* Multi-frames Average Mode
* De-Interlacer
* Motion-adaptive and Pixel-based Processing
* Film-mode Detection
* Simple Edge-oriented Mode
* Advanced Spatial-Temporal Mode
* Noise Reduction
* Directional-Smoothing Filter
* Temporal-Recursive Filter
* Noise Estimation
* Sharpness
* Spatial High-pass Filter
* Video Output
* 2 Display Controllers
* Controller 0 has single image channel
* Controller 1 has 3 image channels
* Progressive or Interlaced Digital Video Output
* Supported Functions
* 3 Channel Overlay / Chroma-Keying / Alpha-blending Only for Controller 1
* Gamma Correction
* Look-up table for Indexed or RGB Color
* Contrast, Brightness, Hue Function Supported.
* Supported Output Media
* TFT-LCD Supported
* HDMI Output Supported : up to 1920x1080p
* LVDS Output Supported : up to 1280x720p
* Composite TV-Out ( NTSC/PAL )
* Dual-Display Supported 1
* Two types of supported media
* CPU Type Main/Sub LCD : Time Shared
The maximum resolution and combination of image channels can be determined by the system configuration
1-3
Aug 18, 2009

INTRODUCTION
TCC8900_CHIP_SPEC
* Video Input
* CCIR-601/656 Interface
* Camera Input Supported
* 1 Channel Overlay / Chroma-Keying
* Input Image Scaler Output resolution is up to 4080x4080
SPECIAL HARDWARE
AUDIO
STORAGE INTERFACE
HOST INTERFACE
STREAMING
INTERFACE
* DVB-H MPE-FEC
* ECC Controller
* Touch Screen Interface
* 10/12 bits 8CH ADC
* I2S Master & Slave Interface
* 7.1 Channel Supported
* SPDIF Transmitter/Receiver
* 5.1 Channel Supported
* CD I/F
* I2S Slave Interface
* USB 2 Channel Interface
* 1 Channel for USB 2.0 OTG
* 1 Channel for USB1.1 Host
* UDMA 33/66, PIO Mode
* NAND Flash Interface
* 8 Bits / 16 Bits
* 4 CS Supported
* SD/MMC Controller : SD, MMC, SDIO, Ce-ATA
* Memory Stick Pro/Pro-HG Supported
* S-ATA Host
* Generation 1 : 1.5Gbps
* Generation 2 : 3.0Gbps
* EHI(External Host Interface)
* 8, 16bits, 18bits
* 2 Channels
* Bypass to LCD Port (CPU Type)
* TS Interface
* 2 Channel TS serial interfaces shared by GPSB
* 2 Channel TS parallel interfaces
* UART up to 6 Channels
* I2C ( 2 Master and 1 Slave ) 2 Channels
* GPSB(General Purpose Serial-Bus Master/Slave) 6 Channels
* Serial TS Interface Supported (Receiver Only) for 2 channels
* CAN Protocol 2.0 Supported

* Infra-Red Remote Receiver
PERIPHERALS
PMU
PROCESS
1-4
TCC8900
* Timers
* Four 16-bit timers with PWM output/counters
* Two 20-bit timers
* One 32-bit timer
* DMA - 12 Channels
* ADC
* 8-Channel General purpose 12-bit
* Shared by Touch Screen Controller
* RTC : Power-Down Mode & Auto-wakeup
* Internal power island for saving the current consumption.
* 65nm CMOS
TCC8900
TCC8900_CHIP_SPEC
Aug 18, 2009

INTRODUCTION
1.2 Applications
Category
Mobile Application Processor
Mobile
Co-processor
Portable
Devices
Portable
Navigation
CAR
Description
* Smart-Phone Application
* Support of all the Mobile / Digital broadcasting services
* T-DMB/S-DMB/DVB-H/ CMMB / ATSC-MH
* DVB-T / DTTB
* Support of Touch Screen Controller
* Low-power consumption for power-down mode
* Mobile-TV Solution
* Mobile Multimedia Co-Processor
* High quality Multimedia Player
* Low cost PDA application
* Multimedia Host Player
* 2D/3D Navigation
* Navigation with A/V System and D-TV
* Car Navigator
- Multimedia Play
* Multimedia Host Player
- USB1.1 Host
1-5
Aug 18, 2009

INTRODUCTION
TCC8900
TCC8900_CHIP_SPEC
1.3 Block Diagram
VIDEO PROCESSING UNITS
ARM1176JZFS
ARM1176 CORE
ITCM
(16KB)
DTCM
(16KB)
I/D-CACHE WITH MMU

(16KB/16KB)
STILL IMAGE
PROCESSING
MOVING PICTURE
DECODER
MOVING PICTURE
ENCODER
* H.264
* MPEG1/2/4
* REAL VIDEO
* VC-1(WMV9)
* DIVX
* H.264
* MPEG4
- JPEG ENCODER
- JPEG DECODER
VFP
(VECTOR FLOATING POINT)
GRAPHIC PROCESSING UNITS
BUS INTERFACE
IMAGE OVERLAY MIXER
2D/3D GRAPHIC PROCESSOR
SYSTEM MANAGEMENT UNITS

CLOCK
CONTROLLER
VECTORED INTERRUPT
CONTROLLER
(64 CHANNELS)
MISC. HARDWARES
PMU
HOST INTERFACE
(X8, X16, X18)
TIMERS
- POWER-DOWN MODE
- DEEP POWER-DOWN MODE
- NORMAL MODE
NAND FLASH CONTROLLER (ECC)
VIDEO IN/OUT PROCESSOR

SD/MMC CONTROLLER
(2 CHANNELS, SD/MMC/SDIO/CE-ATA)
DISPLAY CONTROLLER
* RGB OUTPUT
* COMPOSITE OUTPUT
* HDMI OUTPUT
* LVDS OUTPUT
MEMORY STICK HOST CONTROLLER

(PRO/PRO-HG)
USB2.0 OTG
USB1.1 HOST
CAMERA INTERFACE
MEMORY-TO-MEMORY SCALER
VIDEO IMAGE ENHANCER
GDMA
(12CH)
SERIAL-ATA, PARALLEL-ATA
* DE-NOISE
* DE-INTERLACER
I2S 7.1 CHANNEL

SPDIF TX/RX
MEMORY INTERFACE
I2C
2 MASTER, 1 SLAVE
DYNAMIC MEMORY ONLY

- X32 DATA BUS
RTC
(BATTERY POWER)
- SDRAM
- MDDR(MOBILE DDR)
- DDR
- DDR2
TOUCH SCREEN CONTROLLER

(8 CHANNEL)
ETC
Figure 1.1 TCC8900 Functional Block Diagram
1-6
TCC8900
TCC8900_CHIP_SPEC
Aug 18, 2009

HARDWARE FEATURES
2 Hardware Features
Table 2.1 ARM1176JZFS Processor
ARM1176JZFS
Cache Organizations
Tightly Coupled Memory
Debug Interface
Memory Map
0x00000000
0x10000000
0x20000000
0x40000000 ~
0x80000000
0xE0000000
0xF0000000
Key Features
* 16KBs/16KBs I/D Caches
* I/D MMU Supported
* Java Accelerator
* 16KB Instruction TCM
* 16KB Data TCM
* JTAG Synchronized Ports with RTCK
Description
Remapped Area
* REMAP = 00b : Boot-ROM
* REMAP = 01b : Internal SRAM
* REMAP = 10b : External SDRAM
* REMAP = 11b : No-Remap
Internal SRAM
* 16KBs Size
Reserved for TLB for virtual MMU Table
* Do not use this area
External SDRAM
* Up to 1GBs 2
Boot-ROM
* 16KBs size
Special Function Registers
* Hardware Control Registers
Figure 2.1 Memory Organization
1
2
If more detailed information is required, refer to the ARM1176JZFS Technical Reference Manual on ARM site.
The maximum size for external SDRAM is determined by the system configuration and the size of external SDRAM.
2-7
Aug 18, 2009

HARDWARE FEATURES
TCC8900_CHIP_SPEC
TCC8900
Table 2.2 Video Controller

Video Codec
Encoder
Decoder
Key Features
* H.264 Encoding
- 24fps @ HD Resolution (1280x720p)
* MPEG-4-ASP Encoding
* H.263 Encoding
* H.264 Decoding
- 30fps @ Full-HD Resolution
* MPEG4-ASP Decoding
* H.263 Decoding
* VC-1 Decoding
* RV Decoding
Table 2.3 Camera Interface

CAMERA I/F
Various Input Formats
Hardware Format Converter
Maximum Resolutions
1
2
Key Features
* CCIR601/656 4:2:2
* Down Scaling for Preview Display : 1/2, 1/4, 1/8
* Change the Image size and windowing.
* Support the master clock for camera module.
* Reconfigurable Packing the Pixel Data
* Dispatching the Pixel Data into Y/Cb/Cr
* Horizontal and Vertical Window Clipping
* Overlaying the Background Frame for Still or Moving Pictures
Chroma-Keying
Alpha-blending (0%, 25%, 50%, 75%, 100%, XOR)
* Support the Master Clock for Camera Module w/o External Oscillator
* up to 120MHz 1 for Still Image 2
The maximum frequency can be limited by the timing specification of the camera sensor or external device.
The maximum resolution can be limited by the system configuration.
2-8
TCC8900
TCC8900_CHIP_SPEC
Aug 18, 2009

HARDWARE FEATURES
Table 2.4 Video Output Interface

Video Output Interface
Color TFT LCD
Mono/Color STN LCD

NTSC/PAL Encoder Interface
NTSC/PAL composite output
HDMI Output 1
LVDS Output
Image Processing
Key Features
* Various type image sources
RGB565, RGB555, RGB666, RGB24, YCbCr4:2:0, YCbCr4:2:2
* Various type YCbCr4:2:0 and YCbCr4:2:2 to RGB converter
* Parallel 24bits and 18bits pixel data output
* 6(R):6(G):6(B)bits and 8(R):8(G):8(B)bits pixel data output
* Mono: 1, 2, 4bpp image source
* Color: 8(332), 12(444), 555, 565 bpp image source
* 4 and 8-bit pixel data interface
* CCIR601/656 interlace/non-interlace
* RGB to YCbCr4:2:2 converter
* Supports all NTSC and PAL formats
(NTSC-M/4.43, PAL-B/D/G/H/I/M/N/Combination N)
* The supported formats are
- 1920x1080p @ 60Hz
- 1920x1080i @ 30Hz
- 1280x720p @ 30Hz
- 720x480i @ 60Hz
- 720x480p @ 60Hz
- etc.
* 5 Differential Data Lanes
* Each data in each lane can be mapped to any pixel data and sync signals.
* OSD/Overlay: can mix up to 3 image sources.
- Channel 0 cant mix up for only 1 image channel
- Channel 1 has the 3 overlay channels.
- Chroma-keying
- 256 level Alpha-blending
- Contrast/Brightness/Hue Control
- Simple Gamma Correction Supported
- LUT for each image channels
* Virtual Window: Panning / Sliding the Window
* Subsampling: 1/2, 1/3, 1/4, 1/8
* Duplication: x2, x3, x4, x8
The maximum resolution can be limited by the system configuration.

2-9
Aug 18, 2009

HARDWARE FEATURES
TCC8900
TCC8900_CHIP_SPEC
Table 2.5 DAI/CDIF Controller

I2S (DAI/CDIF)
DAI (Digital Audio Interface)
CDIF (CD Interface)
Key Features
* System clock: 256fs, 384fs, 512fs.
* Maximum 7.1 channel supported
* Support of Master/Slave Mode with Reconfigurable Clock Polarity
* Wide Range of Sampling Frequency in Audio application
: 8kHz, 16kHz, 11.05kHz, 24kHz, 32kHz 44.1kHz, 48kHz
* Supports the I2S (MSB Justified Mode )
* Controls the Digital Audio Volume over the range 0dB to -90dB
* Using 2 Double Buffers for Audio I/O Data
* CD Interface for Feasible Implementation of CD Application
* Slave Mode
* I2S (LSB Justified Mode)
Table 2.6 SPDIF Controller

SPDIF
General Features
Maximum Operating Frequency
Key Features
* Transmitter/Receiver Included
* Bit Rate is 64 times the sampling frequency
* Configurable 16/24 Bits Mode
* 24MHz Output Data-Rate
SPDIF Clock = 12.288MHz, Ratio = 1
3.072Mbps / 48kHz (Data Rate)
Table 2.7 External Device Interface

External Device Interface
Static Memory Controller
Key Features
* Support of 4 Types Static Memory (NAND/IDE/ROM/SRAM)
* Controllable Setup / Pulse Width / Hold Time
* 8/16 Bits Width
Table 2.8 USB 1.1 Host

USB 1.1 Host
General Features
PHY Interface
Key Features
* USB1.1 Host Compatible
* OHCI 1.0 Compliant
* 2 Down Stream Port
- 1 for Dedicated USB1.1 Host Port
- 1 for nanoPHY for USB 2.0 OTG Port
* On-Chip UTMI PHY Serial Interface
* 48MHz
Table 2.9 USB 2.0 OTG(On-The-GO)

USB 2.0 OTG
General Feature
USB DMA
PHY Interface
2-10
Key Features
* Compliant USB2.0 Specification
* Support Interrupt, Bulk Transfer
* Support FS/HS dual mode operation
* 16bit interface
* FIFO size configuration
* 3 Channel DMA (EP1,EP2,EP3)
* Support 16/32bit MCU interface
* Single / Fly mode
* 4x32 FIFO for Each Endpoint
* On-Chip UTMI PHY Parallel Interface
* 12 External Oscillator (Main Oscillator)
* 30MHz with 16bits parallel interface
TCC8900
TCC8900_CHIP_SPEC
Aug 18, 2009

HARDWARE FEATURES
Table 2.10 nano PHY for USB2.0 OTG and USB1.1 Host
UTMI PHY
Supported Specification
General Features
System Features
Key Features
* Compliant with USB 2.0 Transceiver Macrocell Interface Spec. Ver-1.04
* 480Mbps High Speed / 12Mbps Full Speed, FS Only, 1.5Mbps Low Speed
* Separate 8/16 bit Unidirectional Parallel Interface
* Dual-Mode Device Support (HS/FS)
* Data and Clock Recovery from Serial Data on the USB Connector
* SYNC/End-Of-Packet Generation and Checking
* Bit Stuffing and unstuffing, Bit-stuffing Error Detection
* NRZI Encoding/Decoding
* Support of Suspend, Resume, Remote Wakeup Operations
* Integrated HS and FS Termination and Signaling Switching
* On-Chip PLL for 480Mbps
* Low Power Dissipation while Active, Idle, or on Standby
* 45-Ohm Termination / 1.5k Pull-up 15k Pull-down Integrated
* Minimal External Components Single Resistor
* up to 480MHz
Table 2.11 External Host Interface

EHI
SRAM Type Interface
Host Booting Procedure

Peak Access Bandwidth
Key Features
* 68/80 Series Interface with 8/16 Bit Width
* Burst Transfer and Address Auto-Increment
* Internal Interrupt Generation by an External Host Device
* Semaphore Register for Improving Data Transfer Efficiency
* READY can be Checked via Status Register and Pin.
* LOCK MODE: External Host Device can Occupy System bus without any
Handover.
* Configures 8/16 Bits Host Booting Mode
* Host Downloads the Program into On-Chip SRAM or Off-Chip Memory
* Restarts with Downloaded Program Code
* 8 Bits Configuration : 20MB/s
* 16 Bits Configuration : 40MB/s
Table 2.12 SD/MMC Controller

SD/MMC
Key Features
* SD ver.2.0
* SDIO ver.2.0
* MMC ver.4.3
* Ce-ATA Digital Protocol rev1.1
General Features
Maximum Frequency
* Automatic CRC Generation & Checking the Data/Command

* Data transmit/receive FIFO (32bits x 8)
* Supported SD/MMC Mode
1 Bit Serial or 4 Bit Parallel SD
1 Bit Serial for MMC
4/8 Bits Parallel Transfer
* External DMA Handshaking for Burst & Fast Transfer
* up to 50MHz 1
* Clock generation block Inside
Table 2.13 Memory Stick Controller

Memory Stick
Supported Specifications
General Features
Key Features
* Memory Stick Ver.1.x
* Memory Stick Pro
* Memory Stick Pro-HG
* Data transmit/receive FIFO (64bits x 4)
* External DMA Handshaking for Burst & Fast Transfer
* Memory Stick serial clock (Serial : 20MHz, Parallel : 40MHz)
The maximum operating frequency for storage devices can be limited by the system configuration and corresponding
interface ports.
2-11
Aug 18, 2009

HARDWARE FEATURES
TCC8900
TCC8900_CHIP_SPEC
Table 2.14 Nand Flash Controller

NAND I/F
NAND I/F
External Configuration
SLC
MLC
Key Features
* Automatic Detection of External READY Signal
* Configurable Cycle Times based-on Bus Frequency
* 8bit, 16bit, 32bit Interface to Buffer Memory
* 8x32Bits FIFO Included
* External DMA Handshaking for Burst and Fast Transfer
* 1 NAND - Single 8 bit NAND / Single 16bit NAND
* 2 NAND - Double Series 8 bit NAND / Double Series 16 Bit NAND
* 4 NAND - Double Parallel & Series 8 Bit NAND
* 2 Bit Error Detection & 1 Bit Error Correction per 256 bytes.
* Configurable Memory Regions for ECC Calculations
* 4/8/12/14/16 Bit Error Detection/Correction Based on BCH Algorithm
* 8x32 FIFO
Table 2.15 IDE interface

HDD (UDMA)
General Features
Key Features
* It Supports for the following mode.
- maximum theoretical bandwidths for various operating mode
UDMA
PIO MODE SPEED
SPEED
MODE
PIO MODE 3.3
MODE 0
16.67
0
MBps
MBps
PIO MODE 5.22
MODE 1
25
1
MBps
MBps
PIO MODE 8.33
MODE 2
33.33
2
MBps
MBps
PIO MODE 11.11
MODE 3
44.44
3
MBps
MBps
PIO MODE 16.67
MODE 4
66.67
4
MBps
MBps
* It has a 16x32 bit FIFO that supports internal DMA operation.
TBD
Table 2.16 UART Interface

UART
General Features
Key Features
* 16 bytes TX/RX FIFO
* Support of Hardware Flow Control ( CTS/RTS )
* 16 bits clock divider
* 16C550 Compatible Core
* Smart Card Interface

2-12
* Baud Rate Clock ( 3MHz 48MHz / 16 )
TCC8900
TCC8900_CHIP_SPEC
Aug 18, 2009

HARDWARE FEATURES
Table 2.17 GPSB Interface

GPSB
Key Features
General Feature
* MSB / LSB Selection mode

* Support Variable transfer (1~16bit)
* Clock frequency/ Polarity selection mode
* Support configurable Frame signal mode
* 60MHz for slave only
* 30MHz for master mode
Table 2.18 General DMA Controller

General DMA
General Features
DMA Request/Acknowledge
Inter-channel Arbitration
Key Features
* 12-Channel DMA
* Dedicated Bus Interface for Various Storage Interface Controllers
* Support of Byte/Half-word/Word Transfer
* Support of Circular Buffer Interface
Masking of the Source/Destination Address Bits
* 1/2/4/8 Burst Transfers
* Byte Swapping Function
* Support of Single/Continuous/Burst Mode
* 8x32bits FIFO Included
* External DMA Request/Acknowledge
* Interfacing the On-chip Storage Controllers
* Configurable Priority for Each Channel
* Round-robin Arbitration / Fixed Priority Arbitration
Table 2.19 Vectored Interrupt Controller

VPIC
General Features
Vectored Interrupt Handler
Key Features
* 64 Individual Interrupt Sources
* FIQ/IRQ Configurable
* Priority Reconfigurable for Each Interrupt Sources
* Polarity Controllable
* Edge/Level Sensitivity Controllable
* Dual/Single Edge Controllable when Edge Sensitivity Selected
* Vector ID Returned for Fast Handling
* Vector ID is one of 0 ~ 63
* 64x32 Vector Table Needed for Vector Handler on On-Chip Memory
Table 2.20 Timer

TIMER & WDT
Timer Counters
Watchdog Timers
Key Features
* Four 16-bit timers with PWM output/counters, two 20-bit timers, and one 32-bit timer
* External Event Counter
* Stop Mode / Free Running Mode
* Various Clock Sources ( PLL outputs ~ Divided Sub-Clock )
* PWM Functions TREFn, TMREFn
* Watchdog Timer Interrupt / Reset
2-13
Aug 18, 2009

HARDWARE FEATURES
TCC8900
TCC8900_CHIP_SPEC
Table 2.21 ADC

TSADC
General Features
Operating Frequency
Touch Screen
Key Features
* 12bit Resolution
* 0 ~ 3.3V Input Range ( In case of 3.3V AVDD)
* 1MSPS / 5MHz
* X/Y Position
* Up/Down Wake-up
Table 2.22 Real Time Clock

RTC
General Features
Interrupt & Round Reset

Wakeup Function
2-14
Key Features
* Sub Oscillator Included
* Clock and Calendar Function (BCD Display)
Sec/Min/Hour/Date/Day-of-Week/Month/Year
* Leap Year Generation
* Wakeup Signal Generation from the Deep Power-down Mode
* Alarm Interrupt in Normal Operation Mode
* Cyclic interrupts 1/256, 1/64, 1/16, 1/4, 1/2, 1 second interrupts
* Round-reset function 30-, 40-, 50- second
* Dedicated Wake-up Port
TCC8900
TCC8900_CHIP_SPEC
Aug 18, 2009

PIN DESCRIPTION
3 PIN Description
3.1 TCC8900 Pin Description
Table 3.1 Power/Ground Information
Group
# of Balls
GNDCORE
17
PWRCORE
15
GNDIO
PWRGPIOA
PWRGPIOB
PWRGPIOC
PWRGPIOD
PWRGPIOE
1
2
2
2
2
Ball#
F4, J5, F7, L7, T9, E10, E12,
U12, K13, M13, N13, R13, K14,
J15, P15, R15, K16
H4, J4, F6, R8, G9, G11, G12,
P13, W13, H14, J14, L15, N15,
T15, M4
P4, H5, F8, E11, T11, V11, F12,
E14, F15
V13
F11, F9
E6, E9
F13, F14
V10, V12
PWRGPIOF
G4, P5
PWRETC
PWRMEMQ
1
6
G14
J13, L14, M14, M15, N14, P14
PWRMEMZQ
J12
GNDMEMZQ
PWROSC
GNDOSC
PWRUSB12
PWRUSB33
GNDUSB
PWRUSBH
GNDUSBH
PWRLVDS33A
GNDLVDS33A
PWRSATA1
PWRSATA2
GNDSATA
PWRSATAOSC
GNDSATAOSC
PWRSATAPLL
GNDSATAPLL
PWRHDMI
GNDHDMI
PWRHDMIPLL1
PWRHDMIPLL2
GNDHDMIPLL
PWRHDMIOSC
GNDHDMIOSC
PWRADC
GNDADC
PWRDAC
GNDDAC
PWRPLL
GNDPLL
PWRRTC
1
1
1
1
1
1
1
1
2
3
1
1
2
1
1
1
1
1
3
1
1
1
1
1
1
1
1
2
1
1
1
H12
L6
M6
L4
L5
K1
B11
B10
P7, R7
T6, W5, Y5
R4
P3
M1, R1
U2
V1
P2
R2
T5
V2, V3, U6
R5
T4
R6
U5
V5
T13
T14
U9
T8, U7
N5
M3
N4
MIN(V)
TYP(V)
MAX(V)
1.14
1.20
1.26
TBD
TBD
TBD
1.8
2.5
3.3
1.89
2.62
3.46
1.8
1.71
2.38
3.14
2.7
1.14
3.0
-
1.8
2.5
3.3
3.0
1.20
3.3
-
3.6
1.89
2.62
3.46
3.3
1.26
3.6
-
1.14
1.14
1.20
1.20
1.26
1.26
3.0
3.3
3.6
1.14
1.20
1.26
1.14
1.20
1.26
1.14
1.14
1.20
1.20
1.26
1.26
3.0
3.3
3.6
2.7 1
2.7
1.14
1.5
3.3
3.0
1.20
3.0
3.6
3.3
1.26
3.3
1.71
2.38
3.14
Description
Internal Core Ground
Digital Internal Core Power
@ FCPU 500MHz
@ FCPU 600MHz
I/O Ground
GPIOA Group I/O Power
GPIOB Group I/O Power
GPIOC Group I/O Power
GPIOD Group I/O Power
GPIOE Group I/O Power
GPIOF Group I/O Power
ETC Group I/O Power
SDR/DDR/mDDR I/O Power
DDR2 ZQ Calibration Power
SDR/DDR/mDDR/DDR2 I/F Ground
Oscillator Power
Oscillator Ground
UTMI Digital Core Power
UTMI Analog Core Power
UTMI Ground
USB 1.1 Host Transceiver Power
USB 1.1 Host Transceiver Ground
LVDS Transmitter Power
LVDS Transmitter Ground
SATA Core Power 1
SATA Core Power 2
SATA Core Ground
SATA Oscillator Power
SATA Oscillator Ground
SATA PLL Power
SATA PLL Ground
HDMI Core Power
HDMI Core Ground
HDMI PLL Power 1
HDMI PLL Power 2
HDMI PLL Ground
HDMI Oscillator Power
HDMI Oscillator Ground
ADC Power
ADC Ground
DAC Power
DAC Ground
PLL Power
PLL Ground
RTC Core & I/O Power
PWRADC : When PWRADC is 2.7~3.0V, note that ADC error rate is increased.
3-15
Aug 18, 2009

PIN DESCRIPTION
TCC8900
TCC8900_CHIP_SPEC
Table 3.2 PWRGPIOC Group I/O Pin Description

NAME
BALL
GPIOC[0]
GPIOC[1]
GPIOC[2]
GPIOC[3]
GPIOC[4]
GPIOC[5]
GPIOC[6]
GPIOC[7]
GPIOC[8]
GPIOC[9]
GPIOC[10]
GPIOC[11]
GPIOC[12]
GPIOC[13]
GPIOC[14]
GPIOC[15]
GPIOC[16]
GPIOC[17]
GPIOC[18]
GPIOC[19]
GPIOC[20]
GPIOC[21]
GPIOC[22]
GPIOC[23]
GPIOC[24]
GPIOC[25]
GPIOC[26]
GPIOC[27]
GPIOC[28]
GPIOC[29]
GPIOC[30]
GPIOC[31]
A9
A8
B9
C9
B8
D9
E8
A7
C8
D8
B7
A6
C7
D7
E7
C6
B6
A5
A4
B5
D6
C5
B4
A3
D5
C4
B3
E5
A2
C3
D4
B2
I/O
1
INIT 2
FUNC0
FUNC1
FUNC2
FUNC3
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
IU
IU
IU
IU
IU
IU
IU
IU
I
I
I
I
I
I
I
I
I
I
IU
IU
IU
IU
I
I
IU
IU
I
IU
IU
I
I
I
GPIOC[0]
GPIOC[1]
GPIOC[2]
GPIOC[3]
GPIOC[4]
GPIOC[5]
GPIOC[6]
GPIOC[7]
GPIOC[8]
GPIOC[9]
GPIOC[10]
GPIOC[11]
GPIOC[12]
GPIOC[13]
GPIOC[14]
GPIOC[15]
GPIOC[16]
GPIOC[17]
GPIOC[18]
GPIOC[19]
GPIOC[20]
GPIOC[21]
GPIOC[22]
GPIOC[23]
GPIOC[24]
GPIOC[25]
GPIOC[26]
GPIOC[27]
GPIOC[28]
GPIOC[29]
GPIOC[30]
GPIOC[31]
LXD[0]
LXD[1]
LXD[2]
LXD[3]
LXD[4]
LXD[5]
LXD[6]
LXD[7]
LXD[8]
LXD[9]
LXD[10]
LXD[11]
LXD[12]
LXD[13]
LXD[14]
LXD[15]
LXD[16]
LXD[17]
LXD[18]
LXD[19]
LXD[20]
LXD[21]
LXD[22]
LXD[23]
LWEN
LOEN
LXA[0]
LCSN0
LCSN1
L0_LPD[0]
L0_LPD[1]
L0_LPD[2]
L0_LPD[3]
L0_LPD[4]
L0_LPD[5]
L0_LPD[6]
L0_LPD[7]
L0_LPD[8]
L0_LPD[9]
L0_LPD[10]
L0_LPD[11]
L0_LPD[12]
L0_LPD[13]
L0_LPD[14]
L0_LPD[15]
L0_LPD[16]
L0_LPD[17]
L0_LPD[18]
L0_LPD[19]
L0_LPD[20]
L0_LPD[21]
L0_LPD[22]
L0_LPD[23]
L0_LDE
L0_LCK
L0_LHS
L0_LVS
SDO(10)
SDI(10)
SCLK(10)
SFRM(10)
TSD5(3)
TSD6(3)
TSD7(3)
EXTLVS0(0)
EXTLVS1(0)
SDO(3)
SDI(3)
SCLK(3)
SFRM(3)
SDO(2)
SDI(2)
SCLK(2)
SFRM(2)
SD_D7(0)
SD_D6(0)
SD_D5(0)
SD_D4(0)
SD_D3(0)
SD_D2(0)
SD_D1(0)
SD_D0(0)
SD_CLK(0)
SD_CMD(0)
TSD4(3)
TSD3(3)
TSD2(3)
TSD1(3)
TSVALID(3)
TSCLK(3)
TSD0(3)
TSSYNC(3)
FUNC4
MS_D7(0)
MS_D6(0)
MS_D5(0)
MS_D4(0)
MS_D3(0)
MS_D2(0)
MS_D1(0)
MS_D0(0)
MS_CLK(0)
MS_BUS(0)
FUNC5
FUNC6
L1_LPD[0]
L1_LPD[1]
L1_LPD[2]
L1_LPD[3]
L1_LPD[4]
L1_LPD[5]
L1_LPD[6]
L1_LPD[7]
L1_LPD[8]
L1_LPD[9]
L1_LPD[10]
L1_LPD[11]
L1_LPD[12]
L1_LPD[13]
L1_LPD[14]
L1_LPD[15]
L1_LPD[16]
L1_LPD[17]
L1_LPD[18]
L1_LPD[19]
L1_LPD[20]
L1_LPD[21]
L1_LPD[22]
L1_LPD[23]
L1_LDE
L1_LCK
L1_LHS
L1_LVS
GPIOF[0]
GPIOF[1]
GPIOF[2]
GPIOF[3]
GPIOF[4]
GPIOF[5]
GPIOF[6]
GPIOF[7]
GPIOF[8]
GPIOF[9]
GPIOF[10]
GPIOF[11]
GPIOF[12]
GPIOF[13]
GPIOF[14]
GPIOF[15]
GPIOF[16]
GPIOF[17]
I/O type. B = bi-direction, I = Input, O = Output

INIT column represents the corresponding I/O state while the reset signal is asserted.
OL = output low, OH =output high, O=output unknown, IU = input/pull-up, ID = input /pull-down, I = input floating
2
3-16
GPIOF[19]
GPIOF[18]
GPIOF[22]
GPIOF[20]
GPIOF[21]
TCC8900
TCC8900_CHIP_SPEC
Aug 18, 2009

PIN DESCRIPTION
Table 3.3 PWRGPIOF Group I/O Pin Description

NAME
BPEN
GPIOF[0]
GPIOF[1]
GPIOF[2]
GPIOF[3]
GPIOF[4]
GPIOF[5]
GPIOF[6]
GPIOF[7]
GPIOF[8]
GPIOF[9]
GPIOF[10]
GPIOF[11]
GPIOF[12]
GPIOF[13]
GPIOF[14]
GPIOF[15]
GPIOF[16]
GPIOF[17]
GPIOF[18]
GPIOF[19]
GPIOF[20]
GPIOF[21]
GPIOF[22]
GPIOF[23]
GPIOF[24]
GPIOF[25]
GPIOF[26]
GPIOF[27]
BALL
F5
A1
D3
B1
E4
C2
C1
D2
E3
E2
F3
F2
D1
E1
G3
F1
G2
G1
H2
H3
J2
J3
J6
K7
K2
K4
K3
K6
K5
I/O
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
INIT
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
FUNC0
BPEN
GPIOF[0]
GPIOF[1]
GPIOF[2]
GPIOF[3]
GPIOF[4]
GPIOF[5]
GPIOF[6]
GPIOF[7]
GPIOF[8]
GPIOF[9]
GPIOF[10]
GPIOF[11]
GPIOF[12]
GPIOF[13]
GPIOF[14]
GPIOF[15]
GPIOF[16]
GPIOF[17]
GPIOF[18]
GPIOF[19]
GPIOF[20]
GPIOF[21]
GPIOF[22]
GPIOF[23]
GPIOF[24]
GPIOF[25]
GPIOF[26]
GPIOF[27]
FUNC1
BPEN
HPXD[0]
HPXD[1]
HPXD[2]
HPXD[3]
HPXD[4]
HPXD[5]
HPXD[6]
HPXD[7]
HPXD[8]
HPXD[9]
HPXD[10]
HPXD[11]
HPXD[12]
HPXD[13]
HPXD[14]
HPXD[15]
HPXD[16]
HPXD[17]
HPRDN
HPWRN
HPCSN0
HPCSN1
HPXA
HPINT0
HPINT1
EXTLVS1(1)
EXTLVS0(1)
FUNC2
BPEN
SD_D0(3)
SD_D1(3)
SD_D2(3)
SD_D3(3)
SD_D4(3)
SD_D5(3)
SD_D6(3)
SD_D7(3)
SD_CMD(3)
SD_CLK(3)
SDO(7)
SDI(7)
SCLK(7)
SFRM(7)
SDO(8)
SDI(8)
SCLK(8)
SFRM(8)
SD_D3(1)
SD_D2(1)
SD_D1(1)
SD_D0(1)
SD_CMD(1)
SD_CLK(1)
SDO(9)
SDI(9)
SCLK(9)
SFRM(9)
FUNC3
BPEN
HDDXD0
HDDXD1
HDDXD2
HDDXD3
HDDXD4
HDDXD5
HDDXD6
HDDXD7
HDDXD8
HDDXD9
HDDXD10
HDDXD11
HDDXD12
HDDXD13
HDDXD14
HDDXD15
HDDXA0
HDDXA1
HDDXA2
HDDCSN1
HDDRDY
HDDCSN0
HDDAK
HDDRQ
HDDIOW
HDDIOR
CAN_RX
CAN_TX
FUNC4
BPEN
TSD0(0)
TSD1(0)
TSD2(0)
TSD3(0)
TSD4(0)
TSD5(0)
TSD6(0)
TSD7(0)
TSVALID(0)
TSCLK(0)
TSSYNC(0)
FUNC5
BPEN
MS_D0(3)
MS_D1(3)
MS_D2(3)
MS_D3(3)
MS_D4(3)
MS_D5(3)
MS_D6(3)
MS_D7(3)
MS_BUS(3)
MS_CLK(3)
FUNC6
BPEN
EDIXA[3]
EDIXA[4]
EDIXA[5]
EDIXA[6]
EDIXA[7]
EDIXA[8]
EDIXA[9]
EDIXA[10]
EDIXA[11]
EDIXA[12]
EDIXA[13]
EDIXA[14]
EDIXA[15]
EDIXA[16]
EDIXA[17]
EDIXA[18]
MS_D3(1)
MS_D2(1)
MS_D1(1)
MS_D0(1)
MS_BUS(1)
MS_CLK(1)
3-17
Aug 18, 2009

PIN DESCRIPTION
TCC8900
TCC8900_CHIP_SPEC
Table 3.4 PWRGPIOE Group I/O Pin Description

NAME
GPIOE[0]
GPIOE[1]
GPIOE[2]
GPIOE[3]
GPIOE[4]
GPIOE[5]
GPIOE[6]
GPIOE[7]
GPIOE[8]
GPIOE[9]
GPIOE[10]
GPIOE[11]
GPIOE[12]
GPIOE[13]
GPIOE[14]
GPIOE[15]
GPIOE[16]
GPIOE[17]
GPIOE[18]
GPIOE[19]
GPIOE[20]
GPIOE[21]
GPIOE[22]
GPIOE[23]
3-18
BALL
N7
P8
U10
M7
L8
N8
R9
U11
W11
Y11
Y12
T10
Y13
P9
Y14
M8
Y15
L9
W12
R10
Y16
P10
Y17
R11
I/O
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
INIT
IU
IU
IU
IU
IU
IU
IU
IU
I
I
I
I
I
I
I
I
IU
IU
IU
IU
IU
IU
IU
IU
FUNC0
GPIOE[0]
GPIOE[1]
GPIOE[2]
GPIOE[3]
GPIOE[4]
GPIOE[5]
GPIOE[6]
GPIOE[7]
GPIOE[8]
GPIOE[9]
GPIOE[10]
GPIOE[11]
GPIOE[12]
GPIOE[13]
GPIOE[14]
GPIOE[15]
GPIOE[16]
GPIOE[17]
GPIOE[18]
GPIOE[19]
GPIOE[20]
GPIOE[21]
GPIOE[22]
GPIOE[23]
FUNC1
UTXD(0)
URXD(0)
UCTS(0)
URTS(0)
UTXD(1)
URXD(1)
UCTS(1)
URTS(1)
UTXD(2)
URXD(2)
UTXD(3)
URXD(3)
CPD[0]
CPD[1]
CPD[2]
CPD[3]
CPD[4]
CPD[5]
CPD[6]
CPD[7]
CCKI
CVS
CHS
CCKO
FUNC2
FUNC3
FUNC4
SD_CLK(4)
SD_CMD(4)
SD_D0(4)
SD_D1(4)
SD_D2(4)
SD_D3(4)
TSD0(1)
TSD1(1)
TSD2(1)
TSD3(1)
TSD4(1)
TSD5(1)
TSD6(1)
TSD7(1)
TSCLK(1)
TSSYNC(1)
TSVALID(1)
MS_CLK(4)
MS_BUS(4)
MS_D0(4)
MS_D1(4)
MS_D2(4)
MS_D3(4)
MS_D0(2)
MS_D1(2)
MS_D2(2)
MS_D3(2)
MS_D4(2)
MS_D5(2)
MS_D6(2)
MS_D7(2)
MS_CLK(2)
MS_BUS(2)
SFRM(5)
SCLK(5)
SDI(5)
SDO(5)
SFRM(4)
SCLK(4)
SDI(4)
SDO(4)
SD_D0(2)
SD_D1(2)
SD_D2(2)
SD_D3(2)
SD_D4(2)
SD_D5(2)
SD_D6(2)
SD_D7(2)
SD_CLK(2)
SD_CMD(2)
CFIELD
FUNC5
FUNC6
TCC8900
TCC8900_CHIP_SPEC
Aug 18, 2009

PIN DESCRIPTION
Table 3.5 PWRGPIOA Group I/O Pin Description

NAME
GPIOA[0]
GPIOA[1]
GPIOA[2]
GPIOA[3]
GPIOA[4]
GPIOA[5]
GPIOA[6]
GPIOA[7]
GPIOA[8]
GPIOA[9]
GPIOA[10]
GPIOA[11]
GPIOA[12]
GPIOA[13]
GPIOA[14]
GPIOA[15]
BALL
Y18
T12
W14
N9
W15
M9
W16
N10
V15
M10
U14
U13
V14
P11
N11
R12
I/O
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
INIT
IU
IU
I
I
IU
IU
IU
IU
IU
IU
I
I
I
I
I
I
FUNC0
GPIOA[0]
GPIOA[1]
GPIOA[2]
GPIOA[3]
GPIOA[4]
GPIOA[5]
GPIOA[6]
GPIOA[7]
GPIOA[8]
GPIOA[9]
GPIOA[10]
GPIOA[11]
GPIOA[12]
GPIOA[13]
GPIOA[14]
GPIOA[15]
FUNC1
SCL0
SDA0
CLK_OUT0
CLK_OUT1
WDTRSTO
IRDI
HDMI_CECO
HDMI_CECI
SCL1
SDA1
CBCLK(0)
CLRCK(0)
CDATA(0)
EXTCLKI
HDMI_HPD
UTM_DRVVBUS
FUNC2
TCO0
TCO1
TCO2
TCO3
FUNC3
FUNC4
FUNC5
FUNC6
EDIXA[19]
EDIXA[20]
CBCLK(1)
CLRCK(1)
CDATA(1)
TCO4
TCO5
3-19
Aug 18, 2009

PIN DESCRIPTION
TCC8900
TCC8900_CHIP_SPEC
Table 3.6 PWRADC Group I/O Pin Description

NAME
AIN[0]
AIN[1]
AIN[2]
AIN[3]
AIN[4]
AIN[5]
AIN[6]
AIN[7]
BALL
V16
U15
W17
W18
Y19
V17
U16
R14
I/O
B
B
B
B
B
B
B
B
INIT
I
I
I
I
I
I
I
I
FUNC0
GPIOE[24]
GPIOE[25]
GPIOE[26]
GPIOE[27]
GPIOE[28]
GPIOE[29]
GPIOE[30]
GPIOE[31]
FUNC1
AIN[0]
AIN[1]
AIN[2]
AIN[3]
TSC_YM
TSC_YP
TSC_XM
TSC_XP
FUNC2
FUNC3
SD_CMD(7)
SD_CLK(7)
SD_D0(7)
SD_D1(7)
SD_D2(7)
SD_D3(7)
MS_BUS(7)
MS_CLK(7)
MS_D0(7)
MS_D1(7)
MS_D2(7)
MS_D3(7)
NAME
BM[0]
BM[1]
BM[2]
TDO
TEST
RSTN
NTRST
TMS
TCK
TDI
RTCK
BALL
H16
G15
C20
B20
B19
C19
E17
D17
F16
E16
E15
I/O
I
I
I
O
I
I
I
I
I
I
O
INIT
I
I
I
O
I
I
I
I
I
I
O
FUNC0
BM[0]
BM[1]
BM[2]
TDO
TEST
RSTN
NTRST
TMS
TCK
TDI
RTCK
FUNC1
FUNC2
FUNC4
FUNC5
FUNC6
Table 3.7 PWRETC Group I/O Pin Description
3-20
FUNC3
FUNC4
FUNC5
FUNC6
TCC8900
TCC8900_CHIP_SPEC
Aug 18, 2009

PIN DESCRIPTION
Table 3.8 PWRGPIOD Group I/O Pin Description

NAME
GPIOD[0]
GPIOD[1]
GPIOD[2]
GPIOD[3]
GPIOD[4]
GPIOD[5]
GPIOD[6]
GPIOD[7]
GPIOD[8]
GPIOD[9]
GPIOD[10]
GPIOD[11]
GPIOD[12]
GPIOD[13]
GPIOD[14]
GPIOD[15]
GPIOD[16]
GPIOD[17]
GPIOD[18]
GPIOD[19]
GPIOD[20]
GPIOD[21]
GPIOD[22]
GPIOD[23]
GPIOD[24]
GPIOD[25]
BALL
A20
D16
A19
C17
C18
A18
B18
A17
G13
D15
H13
C16
L11
B17
L10
C15
K11
D14
J11
B16
K10
A16
K8
C14
K9
D13
I/O
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
INIT
IU
IU
IU
IU
IU
IU
IU
IU
I
I
I
I
I
I
I
I
IU
IU
IU
IU
IU
IU
IU
IU
I
I
FUNC0
GPIOD[0]
GPIOD[1]
GPIOD[2]
GPIOD[3]
GPIOD[4]
GPIOD[5]
GPIOD[6]
GPIOD[7]
GPIOD[8]
GPIOD[9]
GPIOD[10]
GPIOD[11]
GPIOD[12]
GPIOD[13]
GPIOD[14]
GPIOD[15]
GPIOD[16]
GPIOD[17]
GPIOD[18]
GPIOD[19]
GPIOD[20]
GPIOD[21]
GPIOD[22]
GPIOD[23]
GPIOD[24]
GPIOD[25]
FUNC1
BCLK(1)
LRCK(1)
MCLK(1)
DAO0(1)
DAI0(1)
DAO1(1)
DAI1(1)
DAO2(1)
DAI2(1)
DAO3(1)
DAI3(1)
SPD_TX(1)
SPD_RX(1)
UTXD(4)
URXD(4)
UCTS(4)
URTS(4)
UTXD(5)
URXD(5)
UCTS(5)
URTS(5)
FUNC2
BCLK(0)
LRCK(0)
MCLK(0)
DAO0(0)
DAI0(0)
SFRM(11)
SCLK(11)
SDI(11)
SDO(11)
SFRM(6)
SCLK(6)
SDI(6)
SDO(6)
SFRM(12)
SCLK(12)
SDI(12)
SDO(12)
FUNC3
FUNC4
FUNC5
FUNC6
TSD7(2)
TSD6(2)
SPD_TX(0)
TSSYNC(2)
TSD5(2)
TSD4(2)
TSVALID(2)
TSCLK(2)
TSD3(2)
TSD2(2)
TSD1(2)
TSD0(2)
3-21
Aug 18, 2009

PIN DESCRIPTION
TCC8900
TCC8900_CHIP_SPEC
Table 3.9 PWRGPIOB Group I/O Pin Description

NAME
GPIOB[0]
GPIOB[1]
GPIOB[2]
GPIOB[3]
GPIOB[4]
GPIOB[5]
GPIOB[6]
GPIOB[7]
GPIOB[8]
GPIOB[9]
GPIOB[10]
GPIOB[11]
GPIOB[12]
GPIOB[13]
GPIOB[14]
GPIOB[15]
GPIOB[16]
GPIOB[17]
GPIOB[18]
GPIOB[19]
GPIOB[20]
GPIOB[21]
GPIOB[22]
GPIOB[23]
GPIOB[24]
GPIOB[25]
GPIOB[26]
GPIOB[27]
GPIOB[28]
GPIOB[29]
GPIOB[30]
GPIOB[31]
BALL
J7
B15
J10
E13
J8
B14
J9
C13
H11
A15
H10
D12
H6
B13
F10
A14
G10
A13
H7
A12
H9
D11
H8
C12
G5
B12
G6
C11
G7
D10
G8
C10
I/O
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
INIT
IU
IU
IU
IU
IU
IU
IU
IU
I
I
I
I
I
I
I
I
I
I
I
I
I
I
IU
IU
IU
IU
IU
IU
I
I
IU
IU
FUNC0
GPIOB[0]
GPIOB[1]
GPIOB[2]
GPIOB[3]
GPIOB[4]
GPIOB[5]
GPIOB[6]
GPIOB[7]
GPIOB[8]
GPIOB[9]
GPIOB[10]
GPIOB[11]
GPIOB[12]
GPIOB[13]
GPIOB[14]
GPIOB[15]
GPIOB[16]
GPIOB[17]
GPIOB[18]
GPIOB[19]
GPIOB[20]
GPIOB[21]
GPIOB[22]
GPIOB[23]
GPIOB[24]
GPIOB[25]
GPIOB[26]
GPIOB[27]
GPIOB[28]
GPIOB[29]
GPIOB[30]
GPIOB[31]6
FUNC1
EDIXD8
EDIXD9
EDIXD10
EDIXD11
EDIXD4
EDIXD5
EDIXD6
EDIXD7
EDIXD0
EDIXD1
EDIXD2
EDIXD3
EDIXD12
EDIXD13
EDIXD14
EDIXD15
EDIWEN0
EDIWEN1 1
EDIOEN0
EDIOEN1 2
EDIXA[0] 3
EDIXA[1] 4
EDIXA[2]
EDICSN0 5
EDICSN1
EDICSN2
EDICSN3
EDICSN4
EDIRDY0 6
EDIRDY1
EDICSN5
EDICSN6
FUNC2
SD_D0(5)
SD_D1(5)
SD_D2(5)
SD_D3(5)
SD_D4(5)
SD_D5(5)
SD_D6(5)
SD_D7(5)
FUNC3
MS_D0(5)
MS_D1(5)
MS_D2(5)
MS_D3(5)
MS_D4(5)
MS_D5(5)
MS_D6(5)
MS_D7(5)
FUNC4
FUNC5
FUNC6
SFRM(1)
SCLK(1)
SDI(1)
SDO(1)
SD_CMD(5)
SD_CLK(5)
MS_BUS(5)
MS_CLK(5)
SFRM(0)
SCLK(0)
SD_D4(6)
SD_D5(6)
SD_D6(6)
SD_D7(6)
SD_D0(6)
SD_D1(6)
SD_D2(6)
SD_D3(6)
SD_CMD(6)
SD_CLK(6)
MS_D4(6)
MS_D5(6)
MS_D6(6)
MS_D7(6)
MS_D0(6)
MS_D1(6)
MS_D2(6)
MS_D3(6)
MS_BUS(6)
MS_CLK(6)
EDIXA[23]
SDI(0)
SDO(0)
EDIXA[22]
EDIXA[21]
Dedicated to NAND WEN signal for NAND booting

Dedicated to NAND OEN signal for NAND booting
3
Dedicated to NAND CLE signal for NAND booting
4
Dedicated to NAND ALE signal for NAND booting
5
Dedicated to NAND CSN0 signal for NAND booting
6
Dedicated to NAND Ready signal for NAND booting, Either EDIRDY0 or GPIOB[31] can be used for NAND ready signal
as described in the BOOT PROCEDURE in datasheet.
2
3-22
TCC8900
TCC8900_CHIP_SPEC
Aug 18, 2009

PIN DESCRIPTION
Table 3.10 PWRMEMQ Group I/O Pin Description

NAME
BALL
DRAM_XD28
DRAM_XD27
DRAM_XD25
DRAM_XD30
DRAM_DQM3
DRAM_DQS3
DRAM_DQSB3
DRAM_XD31
DRAM_XD24
DRAM_XD26
DRAM_XD29
DRAM_XD20
DRAM_XD19
DRAM_XD17
DRAM_XD22
DRAM_DQM2
DRAM_DQS2
DRAM_DQSB2
DRAM_XD23
DRAM_XD16
DRAM_XD18
DRAM_XD21
DRAM_CLKB
DRAM_CLK
DRAM_XA6
DRAM_XA12
DRAM_XA11
DRAM_RASN
DRAM_XA0
DRAM_XA5
DRAM_XA10
DRAM_CASN
DRAM_CSN1
DRAM_XA2
DRAM_ODT0
DRAM_CSN0
DRAM_BA0
DRAM_BA2
DRAM_XA3
DRAM_BA1
DRAM_XA1
DRAM_XA4
DRAM_XA7
DRAM_ODT1
DRAM_XA9
DRAM_CKE
DRAM_XA8
DRAM_WEN
DRAM_XD12
DRAM_XD11
DRAM_XD9
DRAM_XD14
DRAM_DQM1
DRAM_DQS1
DRAM_DQSB1
DRAM_XD15
DRAM_XD8
DRAM_XD10
DRAM_XD13
DRAM_XD4
DRAM_XD3
DRAM_XD1
DRAM_XD6
DRAM_DQM0
DRAM_DQS0
DRAM_DQSB0
DRAM_XD7
DRAM_XD0
DRAM_XD2
DRAM_XD5
DRAM_VREF0
DRAM_VREF1
DRAM_VREF2
DRAM_VREF3
DRAM_GATEI
DRAM_GATEO
DRAM_ZQ
W19
U17
T17
Y20
V18
U18
T18
U19
V19
W20
V20
R16
T19
U20
T20
R17
R18
P18
R19
R20
P17
P19
P20
N20
M20
P12
N19
N18
N12
N17
N16
M11
M17
M18
M12
M19
L19
L18
M16
L17
L13
L16
K19
L12
J20
K18
K12
K17
H20
G20
F20
H19
J19
J18
J17
G19
J16
H17
H18
E20
F19
D20
E19
F18
G18
G17
D19
D18
E18
F17
H15
K15
P16
T16
L20
K20
G16
I/O
INIT
FUNC0
(DDR2-2CS)
XD28
XD27
XD25
XD30
DQM3
DQS3
DQSB3
XD31
XD24
XD26
XD29
XD20
XD19
XD17
XD22
DQM2
DQS2
DQSB2
XD23
XD16
XD18
XD21
CLKB
CLK
XA6
XA12
XA11
RASN
XA0
XA5
XA10
CASN
CSN1
XA2
ODT0
CSN0
BA0
BA2
XA3
BA1
XA1
XA4
XA7
ODT1
XA9
CKE
XA8
WEN
XD12
XD11
XD9
XD14
DQM1
DQS1
DQSB1
XD15
XD8
XD10
XD13
XD4
XD3
XD1
XD6
DQM0
DQS0
DQSB0
XD7
XD0
XD2
XD5
VREF0
VREF1
VREF2
VREF3
GATEI
GATEO
ZQ
FUNC1
(DDR2-1CS)
XD28
XD27
XD25
XD30
DQM3
DQS3
DQSB3
XD31
XD24
XD26
XD29
XD20
XD19
XD17
XD22
DQM2
DQS2
DQSB2
XD23
XD16
XD18
XD21
CLKB
CLK
XA6
XA12
XA11
RASN
XA0
XA5
XA10
CASN
XA13
XA2
ODT0
CSN0
BA0
BA2
XA3
BA1
XA1
XA4
XA7
XA14
XA9
CKE
XA8
WEN
XD12
XD11
XD9
XD14
DQM1
DQS1
DQSB1
XD15
XD8
XD10
XD13
XD4
XD3
XD1
XD6
DQM0
DQS0
DQSB0
XD7
XD0
XD2
XD5
VREF0
VREF1
VREF2
VREF3
GATEI
GATEO
ZQ
FUNC2
(DDR/mDDR)
XD28
XD27
XD25
XD30
DQM3
DQS3
XD31
XD24
XD26
XD29
XD20
XD19
XD17
XD22
DQM2
DQS2
XD23
XD16
XD18
XD21
CLKB
CLK
XA6
XA12
XA11
RASN
XA0
XA5
XA10
CASN
CSN1
XA2
CSN0
BA0
XA13
XA3
BA1
XA1
XA4
XA7
CKE1
XA9
CKE0
XA8
WEN
XD12
XD11
XD9
XD14
DQM1
DQS1
XD15
XD8
XD10
XD13
XD4
XD3
XD1
XD6
DQM0
DQS0
XD7
XD0
XD2
XD5
FUNC3
(SDR)
XD28
XD27
XD25
XD30
DQM3
FUNC4
FUNC5
FUNC6
XD31
XD24
XD26
XD29
XD20
XD19
XD17
XD22
DQM2
XD23
XD16
XD18
XD21
CLK
XA6
XA12
XA11
RASN
XA0
XA5
XA10
CASn
CSN1
XA2
XA14
CSN0
BA0
XA13
XA3
BA1
XA1
XA4
XA7
CKE1
XA9
CKE0
XA8
WEN
XD12
XD11
XD9
XD14
DQM1
XD15
XD8
XD10
XD13
XD4
XD3
XD1
XD6
DQM0
XD7
XD0
XD2
XD5
GATEI
GATEO
ZQ
3-23
Aug 18, 2009

PIN DESCRIPTION
TCC8900
TCC8900_CHIP_SPEC
Table 3.11 PWROSC Group I/O Pin Description

NAME
XI
XO
BALL
L2
L1
I/O
I
O
INIT
FUNC0
XI
XO
FUNC1
FUNC2
NAME
OTG_VBUS
OTG_DP
OTG_DM
OTG_REXT
BALL
L3
H1
J1
M2
I/O
INIT
FUNC0
OTG_VBUS
OTG_DP
OTG_DM
OTG_REXT
FUNC1
FUNC2
NAME
UBH_DP
UBH_DM
BALL
A11
A10
I/O
INIT
FUNC0
UBH_DP
UBH_DM
FUNC1
FUNC2
FUNC0
RTC_XTI
RTC_XTO
RTC_PMWKUP
RTC_RSTN
FUNC3
FUNC4
FUNC5
FUNC6
Table 3.12 PWRUSB33 Group I/O Pin Description

FUNC3
FUNC4
FUNC5
FUNC6
Table 3.13 PWRUSBH Group I/O Pin Description

FUNC3
FUNC4
FUNC5
FUNC6
Table 3.14 PWRRTC Group I/O Pin Description

NAME
RTC_XTI
RTC_XTO
RTC_PMWKUP
RTC_RSTN
BALL
N3
N2
M5
N6
I/O
I
O
O
I
INIT
NAME
SATA_XI
SATA_XO
BALL
R3
T3
I/O
I
O
INIT
FUNC0
SATA_XI
SATA_XO
NAME
SATA_REXT
SATA_TXP
SATA_TXN
SATA_RXP
SATA_RXN
BALL
T2
U1
T1
N1
P1
I/O
INIT
FUNC0
SATA_REXT
SATA_TXP
SATA_TXN
SATA_RXP
SATA_RXN
NAME
HDMI_XI
HDMI_XO
BALL
U4
U3
I/O
INIT
FUNC0
HDMI_XI
HDMI_XO
NAME
HDMI_TXCP
HDMI_TXCN
HDMI_TX0P
HDMI_TX0N
HDMI_TX1P
HDMI_TX1N
HDMI_TX2P
HDMI_TX2N
HDMI_REXT
BALL
Y1
W1
Y2
W2
Y3
W3
Y4
W4
V4
I/O
INIT
FUNC0
HDMI_TXCP
HDMI_TXCN
HDMI_TX0P
HDMI_TX0N
HDMI_TX1P
HDMI_TX1N
HDMI_TX2P
HDMI_TX2N
HDMI_REXT
NAME
LVDS_TCLKP
LVDS_TCLKN
LVDS_TEP
LVDS_TEN
LVDS_ROUT
LVDS_TDP
LVDS_TDN
LVDS_TCP
LVDS_TCN
LVDS_TBP
LVDS_TBN
LVDS_TAP
LVDS_TAN
BALL
V6
V7
Y6
W6
P6
Y7
W7
Y8
W8
Y9
W9
Y10
W10
I/O
INIT
FUNC0
LVDS_TCLKP
LVDS_TCLKN
LVDS_TEP
LVDS_TEN
LVDS_ROUT
LVDS_TDP
LVDS_TDN
LVDS_TCP
LVDS_TCN
LVDS_TBP
LVDS_TBN
LVDS_TAP
LVDS_TAN
INIT
FUNC0
DAC_OUT
DAC_COMP
DAC_IREF
DAC_VREF
OH
IL
Table 3.15 PWRSATAOSC Group I/O Pin Description
Table 3.16 PWRSATA Group I/O Pin Description
Table 3.17 PWRHDMIOSC Group I/O Pin Description
Table 3.18 PWRHDMI Group I/O Pin Description
Table 3.19 PWRLVDS Group I/O Pin Description
Table 3.20 PWRDAC Group I/O Pin Description

NAME
DAC_OUT
DAC_COMP
DAC_IREF
DAC_VREF
3-24
BALL
U8
T7
V8
V9
I/O
TCC8900
TCC8900_CHIP_SPEC
Aug 18, 2009

PIN DESCRIPTION
3.2 TCC8900 I/O Type

Table 3.21 TCC8900 I/O Type
TYPE
Diagram
DESCRIPTION
PAD Name
TDO
RTCK
PMWKUP
cmos input with controllable pullup/down and output PAD
analog and digital mixed PAD
AIN[0]~AIN[7]
cmos input, bypass input and output

PAD
GPIOF Group
cmos input with controllable pullup/down, output, and bypass output

PAD
GPIOC Group
schmitt trigger input with controllable

pull-up/down and output PAD
GPIOA Group
GPIOB Group
GPIOD Group
GPIOE Group
schmitt trigger input
BPEN
RSTN
BM[2]~BM[0]
TEST
Real Time Clock Oscillator
XTIN,XTOUT
DRV[1:0]
Clock output
3-25
Aug 18, 2009

PIN DESCRIPTION
3-26
TCC8900
TCC8900_CHIP_SPEC
oscillator for XIN/XOUT
XIN,XOUT
TCC8900
TCC8900_CHIP_SPEC
Aug 18, 2009

PACKAGE INFORMATION
4 Package Information
4.1 Dimension
Figure 4.1 TCC8900 Package Dimension
4-27
4-28
Figure 4.2 TCC8900 Ball Map
GNDUSB
XO
GNDSATA
SATA_RXP
SATA_RXN PWRSATAPLL PWRSATA2
GNDSATA
SATA_TXN
SATA_TXP PWRSATAOSC
OTG_DM
BGA1
OTG_DP
HDMI_TXCP
GPIOF[16]
GPIOF[14]
HDMI_TXCN
GPIOF[12]
GPIOF[11]
GNDSATAOSC
GPIOF[5]
GPIOF[2]
HDMI_TX1P
HDMI_TX1N
GNDHDMI
HDMI_XO
SATA_XO
SATA_XI
RTC_XTI
GNDPLL
OTG_VBUS
GPIOF[25]
GPIOF[20]
GPIOF[18]
GPIOF[13]
GPIOF[9]
GPIOF[7]
GPIOF[1]
GPIOC[29]
GPIOC[26]
PWRUSB33
GPIOF[27]
GNDCORE
GNDIO
GPIOB[24]
BPEN
GPIOC[27]
GPIOC[24]
GPIOC[21]
GPIOC[19]
GPIOC[17]
PWRGPIOF
PWRPLL
GPIOE[0]
GPIOE[3]
GNDCORE
GPIOF[22]
GPIOB[0]
GPIOB[18]
GPIOB[28]
GNDCORE
GPIOC[14]
GPIOC[13]
GPIOC[12]
GPIOC[10]
GPIOC[7]
LVDS_ROUT PWRLVDS33A
RTC_RSTN
GNDOSC
PWROSC
GPIOF[26]
GPIOF[21]
GPIOB[12]
GPIOB[26]
PWRCORE
PWRGPIOC
GPIOC[20]
GPIOC[15]
GPIOC[16]
GPIOC[11]
PWRHDMIOSC
PWRHDMI
GNDHDMI
GNDDAC
GNDLVDS33A DAC_COMP
HDMI_TX2P GNDLVDS33A
HDMI_TX2N GNDLVDS33A
LVDS_TEP
LVDS_TEN
LVDS_TDP
LVDS_TDN
HDMI_REXT GNDHDMIOSC LVDS_TCLKP LVDS_TCLKN
HDMI_XI
PWRHDMIPLL2
PWRSATA1 PWRHDMIPLL1 GNDHDMIPLL PWRLVDS33A
GNDIO
PWRRTC
PWRCORE RTC_PMWKUP
PWRUSB12
GPIOF[24]
PWRCORE
PWRCORE
PWRGPIOF
GNDCORE
GPIOF[3]
GPIOC[30]
GPIOC[25]
GPIOC[22]
GPIOC[18]
LVDS_TCP
LVDS_TCN
DAC_IREF
DAC_OUT
GNDDAC
PWRCORE
GPIOE[1]
GPIOE[5]
GPIOE[15]
GPIOE[4]
GPIOD[22]
GPIOB[4]
GPIOB[22]
GPIOB[30]
GNDIO
GPIOC[6]
GPIOC[9]
GPIOC[8]
GPIOC[4]
GPIOC[1]
LVDS_TBP
LVDS_TBN
DAC_VREF
PWRDAC
GNDCORE
GPIOE[6]
GPIOE[13]
GPIOA[3]
GPIOA[5]
GPIOE[17]
GPIOD[24]
GPIOB[6]
GPIOB[20]
PWRCORE
PWRGPIOB
PWRGPIOC
GPIOC[5]
GPIOC[3]
GPIOC[2]
GPIOC[0]
10
LVDS_TAP
LVDS_TAN
PWRGPIOE
GPIOE[2]
GPIOE[11]
GPIOE[19]
GPIOE[21]
GPIOA[7]
GPIOA[9]
GPIOD[14]
GPIOD[20]
GPIOB[2]
GPIOB[10]
GPIOB[16]
GPIOB[14]
GNDCORE
GPIOB[29]
GPIOB[31]
GNDUSBH
UBH_DM
10
DRAM_ODT1
DRAM_XA8
PWRMEMZQ
GNDMEMZQ
PWRCORE
GNDIO
GNDCORE
GPIOB[11]
GPIOB[23]
GPIOB[25]
GPIOB[19]
12
11
GPIOE[9]
GPIOE[8]
GNDIO
GPIOE[7]
GNDIO
GPIOE[23]
GPIOA[13]
GPIOA[14]
12
GPIOE[10]
GPIOE[18]
PWRGPIOE
GNDCORE
GPIOA[1]
GPIOA[15]
DRAM_XA12
DRAM_XA0
DRAM_CASN DRAM_ODT0
GPIOD[12]
GPIOD[16]
GPIOD[18]
GPIOB[8]
PWRCORE
PWRGPIOB
GNDIO
GPIOB[21]
GPIOB[27]
PWRUSBH
UBH_DP
11
13
GPIOE[12]
PWRCORE
PWRGPIOA
GPIOA[11]
PWRADC
GNDCORE
PWRCORE
GNDCORE
GNDCORE
DRAM_XA1
GNDCORE
PWRMEMQ
GPIOD[10]
GPIOD[8]
PWRGPIOD
GPIOB[3]
GPIOD[25]
GPIOB[7]
GPIOB[13]
GPIOB[17]
13
14
GPIOE[14]
GPIOA[2]
GPIOA[12]
GPIOA[10]
GNDADC
AIN[7]
PWRMEMQ
PWRMEMQ
PWRMEMQ
PWRMEMQ
GNDCORE
PWRCORE
PWRCORE
PWRETC
PWRGPIOD
GNDIO
GPIOD[17]
GPIOD[23]
GPIOB[5]
GPIOB[15]
14
15
GPIOE[16]
GPIOA[4]
GPIOA[8]
AIN[1]
PWRCORE
GNDCORE
GNDCORE
PWRCORE
PWRMEMQ
PWRCORE
DRAM_VREF1
GNDCORE
DRAM_VREF0
BM[1]
GNDIO
RTCK
GPIOD[9]
GPIOD[15]
GPIOB[1]
GPIOB[9]
15
DRAM_DQM0
DRAM_XD2
DRAM_XD0
GPIOD[4]
GPIOD[6]
GPIOD[5]
18
DRAM_XD3
DRAM_XD6
DRAM_XD7
RSTN
TEST
GPIOD[2]
19
DRAM_XA5
DRAM_CSN1
DRAM_BA1
DRAM_WEN
DRAM_CSN0
DRAM_CLK
DRAM_XA6
DRAM_BA0 DRAM_GATEI
DRAM_XA7 DRAM_GATEO
DRAM_RASN DRAM_XA11
DRAM_XA2
DRAM_BA2
DRAM_CKE
DRAM_XA9
DRAM_XD10 DRAM_XD13 DRAM_XD14 DRAM_XD12
16
GPIOE[20]
GPIOA[6]
AIN[0]
AIN[6]
17
GPIOE[22]
AIN[2]
AIN[5]
18
GPIOA[0]
AIN[3]
19
AIN[4]
20
DRAM_XD30
DRAM_XD28 DRAM_XD26
DRAM_DQM3 DRAM_XD24 DRAM_XD29
DRAM_XD27 DRAM_DQS3 DRAM_XD31 DRAM_XD17
DRAM_VREF3 DRAM_XD25 DRAM_DQSB3 DRAM_XD19 DRAM_XD22
DRAM_XD20 DRAM_DQM2 DRAM_DQS2 DRAM_XD23 DRAM_XD16
DRAM_VREF2 DRAM_XD18 DRAM_DQSB2 DRAM_XD21 DRAM_CLKB
DRAM_XA10
DRAM_XA3
DRAM_XA4
GNDCORE
DRAM_XD9
DRAM_XD4
DRAM_XD1
BM[2]
TDO
GPIOD[0]
20
DRAM_DQSB0 DRAM_DQS0 DRAM_XD15 DRAM_XD11
DRAM_XD5
NTRST
TMS
GPIOD[3]
GPIOD[13]
GPIOD[7]
17
DRAM_XD8 DRAM_DQSB1 DRAM_DQS1 DRAM_DQM1
BM[0]
DRAM_ZQ
TCK
TDI
GPIOD[1]
GPIOD[11]
GPIOD[19]
GPIOD[21]
16
BGA1
BGA1
TCC8900_CHIP_SPEC
HDMI_TX0P
HDMI_TX0N
GNDHDMI
SATA_REXT
GNDSATAPLL
RTC_XTO
OTG_REXT
XI
GPIOF[23]
GPIOF[19]
GPIOF[17]
GPIOF[15]
GPIOF[10]
GPIOF[8]
GPIOF[6]
GPIOF[4]
GPIOC[31]
GPIOC[23]
GPIOC[28]
GPIOF[0]
Aug 18, 2009

PACKAGE INFORMATION
TCC8900
4.2 Ball Map
TCC8900
TCC8900_CHIP_SPEC
Aug 18, 2009

ELECTRICAL SPECIFICATION
5 Electrical Specification
5.1 Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
DC Supply Voltage for I/O

(Various I/O power excepts for analog ADC, DAC, PLL, USB)
VDDIO
4.6
DC Supply Voltage for Internal Digital Logic (PWR12)
VDDI
1.8
DC Supply Voltage for Analog Part of ADC (PWRADC)
VDDADC
4.6
DC Supply Voltage for PLL (PWRPLL)
VDDPLL
1.8
DC Supply Voltage for USB2.0 (PWRUSB)
VDDUSB
4.6
DC Supply Voltage for RTC (PWRRTC)
VDDRTC
4.6
Digital Input Voltage for Input Buffer
VIN
4.6
Digital Output Voltage for Output Buffer
VOUT
4.6
V
mA
In/Out Current for Digital I/O
II/O
20
Analog Input Voltage for ADC
VIN_ADC
0 ~ VDDADC
Storage Temperature
TSTG
-55 to 150
V
o
Note:
Absolute maximum ratings specify the values beyond which the device may be damaged permanently. Exposure to absolute
maximum rating conditions for extended periods may affect reliability. Each condition value is applied with the other values
kept within the following operating conditions and functional operation under any of these conditions is not implied.
(1) All voltages are measured with respect to VSS unless otherwise specified.
(2) VDDI must always be less than VDDIO
(3) The voltage difference between analog and digital grounds must always be within 0.3V.
5-29
Aug 18, 2009

TCC8900
TCC8900_CHIP_SPEC
5.2 Recommended Operating Conditions

Table 5.1 Recommended Operating Conditions 1
Parameter
Symbol
MIN
TYP
MAX
Unit
Output Load Resistance for DAC [1% tolerance]
RLOAD
37.5
1.14
1.2
1.26
Core (PWRCORE) and PLL (PWRPLL) supply Voltage

@ FCPU 500MHz
Core (PWRCORE) and PLL (PWRPLL) supply Voltage
@FCPU 600MHz
Operating Temperature [Extended]
Operating Temperature [Industrial]
VDDI
VDDPLL
V
TBD
TOPER
TOPER
-30
-40
TBD
TBD
85
85
The recommended operating conditions for power/ground are described on the Power/Ground Information in the Pin
Descriptions.
5-30
C
C
TCC8900
TCC8900_CHIP_SPEC
Aug 18, 2009

5.3 Recommended Operating Frequency

Table 5.2 Recommended Operating Frequency
Parameter
Condition
Symbol
MIN
TYP
MAX
Unit
XIN Oscillator
XTIN Oscillator
@ 1.2V(TYP)
@ 1.2V(TYP)
FXIN
FXTIN
12
32.768
12
12
32.768*128
MHz
KHz
@ 1.2V(TYP)
@ 1.2V(TYP)
@ 1.2V(TYP)
@ 1.2V(TYP)
FBCLKGEN
FCPUGEN
FPLLDIVIN
FIOCLKGEN
910
500
830
500
MHz
MHz
MHz
MHz
@ 1.2V(TYP)
@ 1.2V(TYP)
@ 1.2V(TYP)
@ 1.2V(TYP)
@ 1.2V(TYP)
@ 1.2V(TYP)
@ 1.2V(TYP)
@ 1.2V(TYP)
FCPU
FBUS_DDI
FBUS_GRP
FBUS_IOB
FBUS_SMU
FBUS_VBUS
FBUS_VCODEC
FBUS_MEM
500
240
190
166
125
215
160
260
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
@ 1.2V(TYP)
@ 1.2V(TYP)
@ 1.2V(TYP)
@ 1.2V(TYP)
@ 1.2V(TYP)
@ 1.2V(TYP)
@ 1.2V(TYP)
@ 1.2V(TYP)
@ 1.2V(TYP)
@ 1.2V(TYP)
@ 1.2V(TYP)
@ 1.2V(TYP)
@ 1.2V(TYP)
@ 1.2V(TYP)
@ 1.2V(TYP)
FIO_CIF
F IO_EHI
F IO_GPSB
F IO_MSTICK
F IO_SDMMC
F IO_UART
F IO_LCD
F IO_PMU
F IO_TIMER
F IO_TSIF
F IO_SPDIF
F IO_AUDIO
F IO_CAN
F IO_I2C
F IO_USBH
200
166
166
100
100
166
166
12
125
80
100
166
50
16
48
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Input Clock of Bus Clock Generator (1 ~ 7)

24
Input Clock of CPU Clock Generator
Input Clock of PLL Divider
25
Input Clock of I/O Clock Generator
23
ARM1176JZF-S Core Clock

Bus Clock of DDI Bus
Bus Clock of Graphic Bus
Bus Clock of I/O Bus
Bus Clock of SMU Controller
Bus Clock of Video Bus
Core Clock of Video Codec
Bus Clock of Memory Interface
4
Operating Clock of Camera Interface

4
Operating Clock of EHI
26
Operating Clock of GPSB Controller
4
Operating Clock of Memory Stick Controller
4
Operating Clock of SD/MMC Controller
4
Operating Clock of UART Controller
4
Operating Clock of LCD Controller
Operating Clock of PMU
Operating Clock of Timer
Operating Clock of TSIF(Not GPSB)
4
Operating Clock of SPDIF Transmitter/Receiver
4
Operating Clock of Audio (ADMA/DAI/CDIF)
4
Operating Clock of CAN
4
Operating Clock of I2C
Operating Clock of USB 1.1 Host
12
12
48
48
The maximum operating frequency can be changed without any notice until approved for
mass production.
23
The related clocks are FBUS_DDI, FBUS_GRP, FBUS_MEM, FBUS_VBUS, FBUS_VCODEC,FBUS_SMU, FBUS_IOB.
The related clock is FCPU.
25
The prefix of related clocks is FIO_.
26
The operating frequencies of external interface are not same as this. More detailed information is described on the timing
characteristics of I/O interface. Refer to the corresponding timing information.
24
5-31
Aug 18, 2009

TCC8900
TCC8900_CHIP_SPEC
5.4 Electrical Characteristics for Power Supply

Table 5.3 Peak Power Consumption
Parameter
Power
Condition
Internal Core Power
PWRCORE
PWRGPIOn,
(n=A,B,C,D,E,F)
PWRETC
@ 1.2V
@ 1.8V
@ 2.7V
@ 3.3V
@ 1.8V
@ 2.5V
@ 3.3V
@ 3.3V
@ 1.2V
@ 3.3V
@ 3.3V
@ 2.7V
GPIO Power
Memory I/O Power
PWRMEMQ,
PWRMEMZQ
Oscillator Power (XI/XO)

USB 1.2 Power of nanoPHY
USB 3.3 Power of nanoPHY
USB 1.1 Host Tranceiver Power
RTC Power
PWROSC
PWRUSB12
PWRUSB33
PWRUSBH
PWRRTC
MIN
TYP
MAX
Unit
TBD
mA
TBD
mA
TBD
mA
TBD
TBD
TBD
TBD
TBD
mA
mA
mA
mA
mA
The rests of the power which are not described in the above table are shown in the
corresponding sub-section.
The value in the above table does not mean the average power. Refer to this at the
designing of the power circuit.
5-32
TCC8900
TCC8900_CHIP_SPEC
Aug 18, 2009

5.5 Electrical Characteristics for General I/O

Table 5.4 DC Electrical Specification for General I/O
Parameter
Symb
ol
High Level Input Voltage

Low Level Input Voltage
Hysteresis Voltage
VIH
VIL
V
High Level Input Current
IIH
Low Level Input Current
IIL
High Level Output Voltage

Low Level Output Voltage
Tri-state Output Leakage Current
Input capacitance
Output capacitance
VOH
VOL
IOZ
CIN
COUT
XI/XO Frequency
FOSC1
XTIN/XTOUT Frequency
FOSC2
Test Condition
VIN = VDDIO, pull-down disabled

VIN = VDDIO, pull-down enabled
VIN = VSSIO, pull-up disabled
VIN = VSSIO, pull-up enabled
IOH = -100uA
IOL = 100uA
VOUT = VSSIO or VDDIO
Any input and Bidirectional buffers
Any output buffer
MIN
TYP
0.7VDDIO
-0.3
0.1VDDIO
-10
TBD
-10
TBD
VDDIO0.2
Normal
High Drive = Normal * 128
MAX
VDDIO+0.3
0.3VDDIO
10
TBD
10
TBD
0.2
10
5
5
-10
12
32.768
4194.304
Un
it
V
V
V
A
A
A
A
V
V
A
pF
pF
MH
z
kHz
Ta = 25oC, VSS = 0.0V unless otherwise specified.

Note:
(1) 12MHz is recommended for XI/XO frequency.
(2) PLL Output Frequencies are determined by XI/XO frequency.
5-33
Aug 18, 2009

TCC8900
TCC8900_CHIP_SPEC
5.6 Electrical Characteristics for PLL

Table 5.5 DC Electrical Characteristics for PLL0
Parameter
Symbol
Test Condition
Power Down Current

Power Consumption
IPD
PDD
VDDPLL = 1.2V
VDDPLL = 1.2V
Parameter
Symbol
Test Condition
Input Frequency
VCO output frequency
Output Frequency
Locking Time
Fin
Fvco
Fout
TLT
VDDPLL = 1.2V
VDDPLL = 1.2V
VDDPLL = 1.2V
VDDPLL = 1.2V
Parameter
Symbol
Test Condition
Power Down Current

Power Consumption
IPD
PDD
VDDPLL = 1.2V
VDDPLL = 1.2V
Parameter
Symbol
Test Condition
Input Frequency
VCO output frequency
Output Frequency
Locking Time
Fin
Fvco
Fout
TLT
VDDPLL = 1.2V
VDDPLL = 1.2V
VDDPLL = 1.2V
VDDPLL = 1.2V
MIN
TYP
MAX
Unit
80
3.0
A
mW
Ta = 25oC unless otherwise specified.
Table 5.6 AC Electrical Characteristics for PLL0

MIN
800
40
TYP
12
-
MAX
Unit
1600
1600
300
MHz
MHz
MHz
us
Table 5.7 DC Electrical Characteristics for PLL1/2/3

MIN
TYP
MAX
Unit
80
1.5
A
mW
Table 5.8 AC Electrical Characteristics for PLL1/2/3
5-34
MIN
250
8
TYP
12
-
MAX
Unit
600
600
300
MHz
MHz
MHz
us
TCC8900
TCC8900_CHIP_SPEC
Aug 18, 2009

5.7 Electrical Characteristics for Video DAC

Table 5.9 DC Electrical Characteristics for DAC
Parameter
Symbol
Resolution
Conversion Rate
Differential Non-Linearity
Integral Non-Linearity
Full Scale Output Voltage
Output Load
External Reference Voltage
Bit
FCLK
DNL
INL
VO
RLOAD
VREF
Test Condition
MIN
TYP
MAX
Unit
1.17
1.3
37.5
1.26
10
27
1
2.5
1.43
bits
MHz
LSB
LSB
V
1% tolerance
-
(VDDDAC =3.0V, VSSDAC =0V, Power Down = OFF, Top=30C,

R(IREF) =1.2k, Load Resistance=37.5 unless otherwise specified.)
5-35
Aug 18, 2009

TCC8900
TCC8900_CHIP_SPEC
5.8 Electrical Characteristics for ADC(for Touch Screen)

Table 5.10 DC Electrical Characteristics for ADC
Parameter
Symbol
Resolution
Differential Non-Linearity
Integral Non-Linearity
Bit
DNL
INL
TOPOFF
BOTOFF
Offset Voltage
Test Condition
MIN
TYP
MAX
Unit
VREF=3.3V, GND=0V
VREF=3.3V, GND=0V
10(TBD)
1(TBD)
3(TBD)
bits
LSB
LSB
VREF=3.3V, GND=0V
10(TBD)
LSB
(Converter Specifications: VDDADC= 3.3V, VSSADC= 0V, Top=25C, VREF=3.3V, GND=0.0V unless otherwise specified)
Table 5.11 AC Electrical Characteristics for ADC

Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Maximum conversion rate

Standby supply current
fc
1
60(TBD)
MSPS
uA
Dynamic supply current
IVDD
3.0(TBD)
5(TBD)
mA
Reference current
IREF
THD
0.4(TBD)
60(TBD)
0.6(TBD)
56(TBD)
mA
Total harmonic distortion

Signal-to-noise & distortion ratio
SNDR
fCKIN = 5MHz
STBY = VDD
fCKIN = 5MHz
(without system load)
VREF = 3.3V
fCKIN = 5MHz
AINT = 50kHz
fCKIN = 5MHz
AINT = 50kHz
54(TBD)
dB
48(TBD)
dB
(Converter Specifications: VDDADC =3.3V, VSSADC=0V, Top=25C, VREF=3.3V, GND=0.0V unless otherwise specified)
VDDIO = 3.3V0.3V
5-36
TCC8900
TCC8900_CHIP_SPEC
Aug 18, 2009

5.9 Electrical Characteristics for HDMI PHY

Table 5.12 DC Electrical Characteristics for HDMI PHY
Parameter
Symbol
Test Condition
Internal Video PLL ON
Internal Video PLL OFF
-
MIN
-
TYP
72
42
TBD
Normal Mode Operating Power
PCC
Power-Down Mode Power
PPD
Parameter
Symbol
Test Condition
Min
Typ
HDMI Oscillator Frequency

Frequency Tolerance
Duty Cycle
FR
FTOL
DC
-100
40
27
Jitter
JCLKI
MAX
Unit
mW
mW
Table 5.13 AC Electrical Characteristics for HDMI Oscillator
Peak-to-Peak Jitter
RMS Jitter
Max
Unit
100
60
100
7
MHz
ppm
%
ps
ps
5-37
Aug 18, 2009

TCC8900
TCC8900_CHIP_SPEC
5.10 Electrical Characteristics for LVDS

Table 5.14 DC Electrical Characteristics for LVDS
Parameter
Symbol
Output differential voltage

Change in VOD between
complementary output states
Output offset voltage
Change in VOS between
complementary output states
Dynamic Current
Power Down Current
VOD
Test Condition
MIN
TYP
MAX
3.0
3.3
3.6
50
mV
1.375
DVOS
50
mV
IDD
IPD
70
100
mA
uA
DVOD
VOS
1.125
1.25
Unit
Typical values measured at PWRLVDS=3.3V and TA=25 oC
Table 5.15 AC Electrical Characteristics for LVDS

Parameter
Symbol
TXCLKIN Period
DLL Lock Time
Skew Between Channels
Duty Cycle
TTCP
TDLL
TSK
DC
Jitter
JCLKI
Test Condition
Min
10
-200
40
Peak-to-Peak Jitter
RMS Jitter
These values are measured at the typical condition.
Figure 5.1 LVDS Transmit Timing Diagram
5-38
Typ
Max
Unit
40
100
200
60
100
7
ns
us
ps
%
ps
ps
TCC8900
TCC8900_CHIP_SPEC
Aug 18, 2009

5.11 Electrical Characteristics for SATA

Table 5.16 DC Electrical Characteristics for SATA
Parameter
Symbol
TX serial data output voltage
DVTX
RX serial data input voltage
DVRX
Dynamic Current
IDD
Power Down Current
IPD
Test Condition
MIN
1.5Gbps
3.0Gbps
1.5Gbps
3.0Gbps
Normal Mode
Partial Mode
Slumber Mode
400
400
325
275
TYP
MAX
700
700
600
750
80
40
12
Unit
mVp-p
mVp-p
mW
mW
All values in the above table are measured at typical condition.
Table 5.17 AC Electrical Characteristics for SATA Oscillator

Parameter
Symbol
Test Condition
Min
Typ
25
100
Oscillator Frequency
FR
Frequency Tolerance
Duty Cycle
FTOL
DC
-100
40
Clock Transition Time
TCLKT
Jitter
JCLKI
Parameter
Symbol
Unit Interval
UI
Max
MHz
100
60
1.5
1.5
40
2.5
Rising
Falling
Peak-to-Peak Jitter
RMS Jitter
Unit
ppm
%
ns
ps
ps
Table 5.18 AC Electrical Characteristics for SATA TX/RX
TX Serial Output Rise Time

(20% 80%)
TX Serial Output Fall Time
(80% 20%)
TX Serial Data Output Voltage
(Differential Peak-to-Peak)
RX Serial Data Input Voltage
(Differential Peak-to-Peak)
TTX.RISE
DC
DVTX
TRJ
Test Condition
1.5Gbps
3.0Gbps
1.5Gbps
3.0Gbps
1.5Gbps
3.0Gbps
1.5Gbps
3.0Gbps
1.5Gbps
3.0Gbps
Min
Typ
666.67
333.33
100
67
100
67
400
400
325
275
Max
Unit
ps
273
136
273
136
700
700
600
750
ps
ps
mVp-p
mVp-p
5-39
Aug 18, 2009

TCC8900
TCC8900_CHIP_SPEC
5.12 Electrical Characteristics for LCD Interface

The following figure shows the timing diagram for TFT-LCD with RGB interface. All the timing parameters can be configured
by LHTIME1, LHTIME2, LVTIME1 ~ 4 registers.
FPW
FLC
FSWC
FEWC
VSYNC
HSYNC
line 1
PXDATA
line 2
......
line n-1
line n
ACBIAS
LPW
LSWC
LPC
LSWC
HSYNC
PXCLK
line 1
PXDATA
ACBIAS
Figure 5.2 Timing Diagram for LCD Controller

The LHS (HSYNC), LVS (VSYNC), LBIAS (ACBIAS, Data Enable) and LPD[17:0] (PXDATA[17:0]) signals are referenced by
LCK (PXCLK). Each min and max timing for the output delay are shown in the following figure.
Figure 5.3 Timing Diagram Data Output Referenced to PXCLK

Table 5.19 Timing Parameters for Each Symbol
Parameter
Symbol
Min
Max
Unit
Clock Cycle
TCYCLE
10
ns
Output Delay
TOD
ns
Remark
Table 5.20 I/O Function Name for Corresponding Signal Name

Signal Name
VSYNC
HSYNC
ACBIAS
PXDATA[23:0]
PXCLK
I/O Function Name

L0_LVS, L1_LVS
L0_LHS, L1_LHS
L0_LDE, L1_LDE
L0_LPD[23:0], L1_LPD[23:0]
L0_LCK, L1_LCK
The following figure shows the timing diagram of bus interface to CPU I/F LCD device. The reference clock is used internally
and the cycle time is defined as the register value written by software.
5-40
TCC8900
TCC8900_CHIP_SPEC
Aug 18, 2009

Figure 5.4 Timing Diagram Data Output Referenced to LCDSI

Table 5.21 Timing Parameters for Each Symbols
Parameter
LCLK Clock Period
( LCDSI Clock)
RD/WE Setup Time Referenced to LCLK
Symbol
Min
tCLK
18
T_rstp
0 * tCLK
7 * tCLK
ns
RD/WE Pulse Width Referenced to LCLK
T_rpw
1 * tCLK
256 * tCLK
ns
RD/WE Hold Time Referenced to LCLK
T_rhld
0 * tCLK
7 * tCLK
ns
Signal Name
#CS
#RS
#RD
#WE
Write Data[17:0]
Max
Unit
Remark
ns
I/O Function Name

LCSN0, LCSN1
LXA[0]
LOEN
LWEN
LXD[17:0]
5-41
Aug 18, 2009

TCC8900_CHIP_SPEC
5.13 Electrical Characteristics for Camera Interface
Figure 5.5 Timing Diagram for Camera Interface
Figure 5.6 Timing Diagram Data Output Referenced to CCLK
5-42
TCC8900
TCC8900
TCC8900_CHIP_SPEC
Aug 18, 2009


Parameter
Symbol
Clock Frequency
TCCK
Setup time for CVS(CAM_VSYNC)
Tvs_su
Min
2
Max
Unit
120
MHz
Remark
ns
Hold time for CVS(CAM_VSYNC)
Tvs_hld
ns
Setup time for CHS(CAM_HSYNC)
Ths_su
ns
Hold time for CHS(CAM_HSYNC)
Ths_hld
ns
Setup time for CPD[7:0](CAM_DATA)
Td_su
ns
Hold time for CPD[7:0](CAM_DATA)
Td_hld
ns

Signal Name
CCLK
CAM_VSYNC
CAM_HSYNC
CAM_DATA[7:0]
I/O Function Name

CCKI
CVS
CHS
CPD[7:0]
5-43
Aug 18, 2009

TCC8900
TCC8900_CHIP_SPEC
5.14 Electrical Characteristics for External Host Interface (EHI)

The EHI has two clock inputs; one is HCLK, which is for the on-chip system bus, the other is ECLK, which is for interface
with the external host device. Therefore, interface timing with the external host is only related with ECLK.
HPCSN
HPXA
Twlw
HPWRN
Twhw
Trlw
HPRDN
Twhw
Tds
Tdd
HPXD
Trdh
Twdh
HPWRN(E)
HPRDN(R/W)
Figure 5.7 EHI Timing Diagram

Symbol
Twlw
Twhw
Trlw
Trhw
Tds
Twdh
Tdd
Trdh
27
TP = ECLK period (ns)
5-44
Description
Write low width
Write high width
Read low width
Read high width
Data setup time
Write data hold
Data delay time
Read data hold
Min.
2TP 27
3TP
4TP
3TP
10
5
0
Max.
25ns
3TP +10ns
Unit
ns
ns
ns
ns
ns
ns
ns
TCC8900
TCC8900_CHIP_SPEC
Aug 18, 2009

5.15 Electrical Characteristics for SD/MMC Controller

The SD/MMC host controller is designed to supports high-speed mode (SD rev.1.10, up to 50 MHz Clock) as well as default
speed mode (SD rev.1.01, up to 25 MHz Clock). A user doesnt need to set differently our SD/MMC host controller for mode
change between default mode and high speed mode. If you want to change mode to high-speed mode from default mode
and vice versa, by using switch-function command (CMD6), the SD/MMC cards are set to such mode. The timing diagram
shows the input/output timing criterion referenced to SD/MMC clock.
Figure 5.8 Timing Diagram for SD/MMC Controller

Parameter
Symbol
Min
Max
Unit
Remark
Clock frequency Data Transfer Mode
fPP
50
MHz
Ccard 30pF
Clock low time
tWL
ns
Ccard 30pF
Clock high time
tWH
ns
Ccard 30pF
Clock rise time
tLH
ns
Ccard 30pF
Clock fall time
tHL
ns
Ccard 30pF
Input set-up time
tISU
ns
Ccard 30pF
Input hold time
tIH
2.5
ns
Ccard 30pF
Output delay time
tODLY
10
ns
Ccard 30pF
Output hold time
tOH
ns
Ccard 30pF
5-45
Aug 18, 2009

TCC8900
TCC8900_CHIP_SPEC
5.16 Electrical Characteristics for I2C Controller
Figure 5.9 Timing Diagram for I2C Controller

Parameter
Symbol
SCL clock frequency
Min
Max
Unit
400
KHz
Hold time(repeated) START condition
tSTA
0.95
Data hold time
tHD:DAT
0.9
Data setup time
tSU:DAT
0.4
us
HIGH period of the SCL clock
tHIGH
0.96
us
LOW period of the SCL clock
tLOW
1.4
us
Setup time for STOP condition
tSTO
1.0
us
Remark
us
us
5.17 Electrical Characteristics for SPDI/F Transmitter
Figure 5.10 Timing Diagram for SPDI/F Transmitter

5-46
Parameter
Symbol
Min
SPDIFclk Clock Cycle Time

SPDIFclk Data Output Time Referenced to
SPDIFclk
Tclkp
110
Tomin/Tomax
Max
Unit
Remark
ns
10
ns
CL = 50pF
TCC8900
TCC8900_CHIP_SPEC
Aug 18, 2009

5.18 Electrical Characteristics for DAI(I2S)
Figure 5.11 Timing Diagram for DAI (receiver)

Test Conditions
MODE = I2S, fs = 48KHz, MCLK = 256fs, BCLK = 64fs
Table 5.27 Timing for DAI (receiver)

Parameter
Symbol
MCLK cycle time
tMCY
19.40
81.40
ns
BCLK cycle time
tBCY
4 * tMCY
4 * tMCY
ns
BCLK pulse width high
tBCH
39
163
ns
BCLK pulse width low
tBCL
38
162
ns
MCLK to BCLK
tMB
0.18
0.18
ns
BCLK to LRCK
tBL
14.77
14.77
ns
DAI setup time to BCLK rising edge
tDIS
ns
DAI hold time from BCLK rising edge

DAO Output Timing Referenced to
BCLK
tDIH
ns
tDOPD
Min
Typ
Max
Unit
Remark
ns
5-47
Aug 18, 2009

TCC8900
TCC8900_CHIP_SPEC
Figure 5.12 Timing Diagram for DAI Transmitter

5-48
Parameter
Symbol
Min
MCLK cycle time
tMCY
36
Max
Unit
ns
BCLK cycle time
tBCY
16 * tMCY
ns
BCLK pulse width high
tBCH
8 * tMCY
ns
BCLK pulse width low
tBCL
8 * tMCY
ns
MCLK to BCLK
tMB
19
ns
BCLK to LRCK
tBL
13
ns
DAO Output Timing Referenced to BCLK
tDOPD
ns
Remark
TCC8900
TCC8900_CHIP_SPEC
Aug 18, 2009

5.19 Electrical Characteristics for Nand Flash Controller
Figure 5.13 Timing Diagram for Command Latch Enable Cycle
Figure 5.14 Timing Diagram for Single Address Latch Cycle
Figure 5.15 Timing Diagram for Linear Address Latch Cycle
Figure 5.16 Timing Diagram for Single Data Write Cycle
5-49
Aug 18, 2009

TCC8900_CHIP_SPEC
Figure 5.17 Timing Diagram for Linear Data Write Cycle
Figure 5.18 Timing Diagram for Single Data Read Cycle
Figure 5.19 Timing Diagram for Linear Data Read Cycle
5-50
TCC8900
TCC8900
TCC8900_CHIP_SPEC
Aug 18, 2009


Parameter
Clock Period
Symbol
tHCLK
Min
10
Max
Unit
ns
CLE Set-Up Time
tCLS
( STP + PW ) x tHCLK + 1.0
( STP + PW ) x tHCLK + 2
ns
CLE Hold Time
tCLH
HLD x tHCLK 2.0
HLD x tHCLK 1.0
ns
WEN Pulse Width
tWP
PW x tHCLK
PW x tHCLK
ns
WEN High Hold Time

Write Cycle Time
OEN Pulse Width
OEN High Hold Time
tWH
tWC
tRP
tREH
( STP + HLD ) x tHCLK

( STP + PW + HLD ) x tHCLK
PW x tHCLK

PW x tHCLK
ns
ns
ns
ns
Read Cycle Time
tRC
ns
ALE Set-Up Time

ALE Hold Time
tALS
tALH
( STP + PW ) x tHCLK 1.00

HLD x tHCLK 2.00
( STP + PW ) x tHCLK + 2.00

HLD x tHCLK + 1.00
ns
ns
Data Set-Up Time
tDS
ns
Data Hold Time
tDH
HLD x tHCLK 1.00
HLD x tHCLK + 1.00
ns
Data Set-Up Time in READ
tDSR
5.00
15.0
ns
Data Hold Time in READ
tDHR
ns

Signal Name
NFC_CSN
NFC_ALE
NFC_CLE
NFC_OEN
NFC_WEN
NFC_IO[15:0]
I/O Function Name

NAND_CSN0, NAND_CSN1
NAND_ALE
NAND_CLE
NAND_OEN
NAND_WEN
NANDXD[15:0]
5-51
Aug 18, 2009

TCC8900
TCC8900_CHIP_SPEC
5.20 Electrical Characteristics for UART Controller
Figure 5.20 Timing Diagram for TXD

Parameter
Symbol
Pulse duration of 1bit TXD
Ttxd_1
Pulse duration of nbit TXD
Ttxd_n
TXD output delay time
Ttxd_d
Min
BRCP
-15
N x BRCP
-15
0.5
Max
BRCP
+15
N x BRCP
+ 15
15
Unit
Remark
ns
3.3V
ns
3.3V
ns
3.3V
z BRC : Baud-Rate Clock

z BRCP : Baud-Rate Clock Period
z CL : 71pF
Figure 5.21 Timing Diagram for RXD

Parameter
Symbol
Min
Max
Unit
Remark
RXD Start to Rx FiFo.
Trxdf
10.5 x BRCP
11 x BRCP
ns
3.3V
z BRC : Baud-Rate Clock

z BRCP : Baud-Rate Clock Period
z CL : 71pF
5-52
TCC8900
TCC8900_CHIP_SPEC
Aug 18, 2009

Figure 5.22 Timing Diagram for TX Operation with H/W Flow Control
Figure 5.23 Timing Diagram for nCTS Timing Diagram

Parameter
Symbol
Min
Max
Unit
Remark
Deasserted nCTS to Tx Start

Deasserted nCTS to Tx Stop
:to stop next transmission(setup
time)
Tdcts
BRCP
ns
3.3V
Tacts
4 x BRCP/16
ns
3.3V
z BRC : Baud-Rate Clock , BRCP : Baud-Rate Clock Period , CL : 71pF
5-53
Aug 18, 2009

TCC8900
TCC8900_CHIP_SPEC
Figure 5.24 Timing Diagram for RX Operation with H/W Flow Control
Figure 5.25 Timing Diagram for nRTS Timing Diagram

Parameter
DTL(and RXD start condition) to
deasserted nRTS
ATL to asserted nRTS
5-54
Symbol
Min
Max
Unit
Remark
Tdrts
BRCP
ns
3.3V
Tarts
BRCP/16 + 8
ns
3.3V
BRC : Baud-Rate Clock , BRCP : Baud-Rate Clock Period , CL : 71pF

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CHIP

High Performance and Low-Power Processor

High Performance and Low-Power Processor for Digital Media Applications

Aug 18, 2009

High Performance and Low-Power Processor for Digital Media Applications

Aug 18, 2009

Aug 18, 2009

High Performance and Low-Power Processor for Digital Media Applications

Aug 18, 2009

High Performance and Low-Power Processor for Digital Media Applications

Aug 18, 2009

Aug 18, 2009

High Performance and Low-Power Processor for Digital Media Applications

1.1 TCC8900 Features

The maximum operation frequency can be limited by the system configuration.

High Performance and Low-Power Processor for Digital Media Applications

Aug 18, 2009

Aug 18, 2009

* CAN Protocol 2.0 Supported

High Performance and Low-Power Processor for Digital Media Applications

High Performance and Low-Power Processor for Digital Media Applications

Aug 18, 2009

Mobile Application Processor

Aug 18, 2009

High Performance and Low-Power Processor for Digital Media Applications

1.3 Block Diagram

VIDEO PROCESSING UNITS

I/D-CACHE WITH MMU

GRAPHIC PROCESSING UNITS

IMAGE OVERLAY MIXER

2D/3D GRAPHIC PROCESSOR

SYSTEM MANAGEMENT UNITS

NAND FLASH CONTROLLER (ECC)

VIDEO IN/OUT PROCESSOR

MEMORY STICK HOST CONTROLLER

I2S 7.1 CHANNEL

DYNAMIC MEMORY ONLY

TOUCH SCREEN CONTROLLER

Figure 1.1 TCC8900 Functional Block Diagram

Aug 18, 2009

High Performance and Low-Power Processor for Digital Media Applications

Figure 2.1 Memory Organization

Aug 18, 2009

High Performance and Low-Power Processor for Digital Media Applications

Table 2.2 Video Controller

Table 2.3 Camera Interface

Hardware Format Converter

Aug 18, 2009

High Performance and Low-Power Processor for Digital Media Applications

Table 2.4 Video Output Interface

Color TFT LCD

Mono/Color STN LCD

The maximum resolution can be limited by the system configuration.

Aug 18, 2009

High Performance and Low-Power Processor for Digital Media Applications

Table 2.5 DAI/CDIF Controller

DAI (Digital Audio Interface)

CDIF (CD Interface)

Table 2.6 SPDIF Controller