SP ST2221C A.004
SP ST2221C A.004
SP ST2221C A.004
Version
: A.004
Issue Date : 2002/06/14
File Name : SP-ST2221C-A.004.doc
Total Pages : 17
9 7 1
ST2221C
ST2221C
16-Bit Constant Current LED Drivers
General Description
The ST2221C is specifically designed for LED and LED DISPLAY constant current drivers.
The value of constant current can be varied using an external resistor (Iout = 5 ~90mA). The
devices include a 16-bit shift registers, latches, and constant current drivers on a single Silicon
CMOS chip.
Features
z
z
z
z
z
- 1 -
VersionA.004
ST2221C
GND
SERIAL-IN
1
2
24
VDD
23
R-EXT
CLOCK
LATCH
OUT0
3
4
22
21
SERIAL-OUT
OUT1
OUT2
OUT3
7
8
20
19
18
OUT4
OUT5
OUT6
10
11
12
OUT7
ENABLE
OUT15
OUT14
OUT13
17
16
OUT12
OUT11
15
14
OUT10
13
OUT8
OUT9
Block Diagram
R-EXT
OUT15
OUT1
OUT0
I-REG.
ENABLE
Q
ST D
ST D
ST D
LATCH
SERIAL-IN
D
CK
CK
D
CK
SERIAL-OUT
CK
CLOCK
- 2 -
VersionA.004
ST2221C
Timing Diagram
1
15
16
5V
CLOCK
0V
5V
SERIAL-IN
0V
5V
LATCH
0V
5V
ENABLE
0V
On
Off
OUT0
On
OUT1
Off
On
OUT2
Off
OUT15
On
Off
SERIAL-OUT
5V
0V
Pin Description
PIN No.
1
2
3
4
5~20
21
22
23
24
PIN NAME
GND
SERIAL-IN
CLOCK
LATCH
OUT0~15
ENABLE
SERIAL-OUT
R-EXT
VDD
FUNCTION
Ground terminal
Input terminal of a data shift register
Input terminal of a clock for shift register
Input terminal of data strobe
Output terminals
Input terminal of output enable (active low)
Output terminal of a data shift register
Input terminal of an external resistor
5V Supply voltage terminal
- 3 -
VersionA.004
ST2221C
2. LATCH terminal
VDD
RIN(up)
ENABLE
LATCH
RIN(DOWN)
GND
CLOCK,
GND
4. SERIAL-OUT terminal
VDD
SERIAL-OUT
SERIAL-IN
GND
GND
- 4 -
VersionA.004
ST2221C
SYMBOL
RATING
UNIT
VDD
VIN
IOUT
VOUT
fCLK
IGND
0 ~ 7.0
-0.4 ~ VDD+0.4
90
-0.5 ~ 9.5
25
1440
2.87 (DIP-24 : Ta=25C)
1.45 (SOP-24 : Ta=25C)
1.27 (SSOP-24 : Ta=25C)
40.0 (DIP-24)
79.2 (SOP-24)
90.2 (SSOP-24)
-55 ~ 150
V
V
mA
V
MHz
mA
Supply Voltage
Input Voltage
Output Current
Output Voltage
Clock Frequency
GND Terminal Current
Power Dissipation
PD
Thermal Resistance
Rth(j-a)
Storage Temperature
Tstg
C/W
C
Input Voltage
LATCH Pulse Width
CLOCK Pulse Width
Set-up Time for DATA
Hold Time for DATA
Set-up Time for LATCH
Clock Frequency
Power Dissipation
SYMBOL
VDD
VOUT
TOPR
IO
IOH
IOL
VIH
VIL
tw LAT
tw CLK
tsetup(D)
thold(D)
tsetup(L)
fCLK
PD
CONDITION
OUTn
SERIAL-OUT
SERIAL-OUT
MIN.
4.5
TYP.
5.0
-40
5
0.7VDD
-0.3
15
15
20
20
15
Cascade operation
Ta = 85C (DIP-24)
Ta = 85C (SOP-24)
Ta = 85C (SSOP-24)
- 5 -
MAX.
5.5
9
85
85
1.0
-1.0
VDD+0.3
0.3VDD
25
UNIT
V
V
mA
V
ns
ns
ns
ns
ns
MHz
1.37
0.69
0.61
VersionA.004
ST2221C
SYMBOL
CONDITION
MIN.
TYP.
MAX.
VIH
0.7VDD
VDD
VIL
GND
0.3VDD
IOH
VOH = 9.5 V
1.0
VOL
IOL = 1.0 mA
0.4
VOH
IOH = -1.0 mA
4.6
VOUT = 0.70.25V
IOL1
REXT = 910
VOUT = 0.70.25V
IOL2
REXT = 360
UNIT
V
uA
V
IOL3
10
IOL4
10
1.5
5.0
%/V
Pull-Up Resistor
RIN(up)
150
300
600
RIN(down)
Pull-Down Resistor
Supply Current OFF
Supply Current ON
100
200
400
0.3
0.6
3.9
5.5
7.7
7.2
10.1
14.1
3.9
5.5
7.7
7.2
10.1
14.1
mA
SYMBOL
SIN-OUTn
Propagation LATCH-OUTn
Delay Time
(L to H) ENABLE-OUTn
CLK-SOUT
SIN-OUTn
Propagation LATCH-OUTn
Delay Time
(H to L) ENABLE-OUTn
CLK-SOUT
Output Current Rise Time
Output Current Fall Time
tpLH
CONDITION
VDD=5.0V
VIH=VDD
VIL=GND
REXT=4701
VL=3.0V
RL=65
CL=13pF
tpHL
tor
tof
MIN.
TYP.
MAX.
450
550
UNIT
450
550
450
550
15
20
20
40
20
40
20
40
15
20
450
550
ns
20
40
ns
ns
ns
Delay time tpLH and Rise Time tor will both increase as the Rext value increased.
- 6 -
VersionA.004
ST2221C
Test Circuit
DC characteristic
IDD
VDD
OUT0
ENABLE
IOL
CLOCK
IIL ,IIH
LATCH
VIL ,VIH
OUT15
SERIAL-IN
R-EXT GND
SERIAL-OUT
I ref
AC characteristic
RL
VDD
VIL ,VIH
OUT0
ENABLE
CL
SW-
CLOCK
MATRIX
LATCH
RL
OUT15
SERIAL-IN
R-EXT GND
SERIAL-OUT
CL
CL
- 7 -
VL
VersionA.004
ST2221C
Timing Diagram
1. CLOCK-SERIAL-IN, SERIAL-OUT, OUTn
tr
tf
twCLK
CLOCK
SERIAL-IN
90%
50%
10%
tsetup
90%
50%
10%
twCLK
50%
50%
thold
50%
50%
tof
tor
90%
50%
10%
OUTn (current)
90%
50%
10%
tpLH
tpHL
50%
50%
SERIAL-OUT
tpHL
tpLH
2. CLOCK-LATCH
50%
CLOCK
SERIAL-IN
50%
50%
tsetup(L)
3. ENABLE-OUTn
ENABLE
50%
50%
tpHL
tpLH
50%
50%
OUTn
- 8 -
VersionA.004
ST2221C
Vo=0.45(V)
Vo=0.70(V)
Vo=0.95(V)
Iout (mA/bit)
Iout (mA/bit)
Vdd=5V
Tj=140C (Max)
16bit Active
Ta=25C
20
40
60
80
90
80
70
60
50
40
30
20
10
0
Vo=0.45(V)
Vo=0.70(V)
Vo=0.95(V)
Vdd=5V
Tj=140C (Max)
16bit Active
Ta=60C
100
20
40
Iout (mA/bit)
Iout (mA/bit)
Vo=0.45(V)
Vo=0.70(V)
Vo=0.95(V)
Vdd=5V
Tj=140C (Max)
16bit Active
Ta=85C
20
40
60
80
90
80
70
60
50
40
30
20
10
0
100
Vo=0.45(V)
Vo=0.70(V)
Vo=0.95(V)
Vdd=5V
Tj=140C (Max)
16bit Active
Ta=25C
20
Iout (mA/bit)
Iout (mA/bit)
Vo=0.95(V)
Vdd=5V
Tj=140C (Max)
16bit Active
Ta=60C
20
40
60
60
80
100
40
100
80
90
80
70
60
50
40
30
20
10
0
60
80
90
80
70
60
50
40
30
20
10
0
100
Vo=0.95(V)
Vdd=5V
Tj=140C (Max)
16bit Active
Ta=85C
Vo=0.45(V)
Vo=0.70(V)
20
40
60
80
100
- 9 -
VersionA.004
ST2221C
Vo=0.95(V)
Iout (mA/bit)
Iout (mA/bit)
Vdd=5V
Tj=140C (Max)
16bit Active
Ta=25C
20
40
60
80
90
80
70
60
50
40
30
20
10
0
100
Vo=0.45(V)
Vo=0.7(V)
Vo=0.95(V)
Vdd=5V
Tj=140C (Max)
16bit Active
Ta=60C
60
80
100
Iout-Rext
100
Iout={ Vref(V)/Rext(ohm) }*13.79
90
Vo=0.45(V)
80
70
Vo=0.7(V)
Vo=0.7(V)
Iout (mA)
Iout (mA/bit)
40
20
Vo=0.95(V)
60
50
40
30
20
Vdd=5V
Tj=140C (Max)
16bit Active
Ta=85C
10
0
20
40
60
80
100
100
1000
10000
Rext ()
- 10 -
VersionA.004
ST2221C
3.2
2.8
2.4
2
1.6
1.2
0.8
0.4
0
Imax - Ta (DIP)
DIP
Ta - Pd
SOP
SSOP
50
100
150
90
80
70
60
50
40
30
20
10
0
Vo=0.7(V)
Vo=1.0(V)
Vdd=5V
Tj=140C (Max)
16bit Active
Rext=470ohm
Ambient Temperature Ta
50
100
150
Ambient Temperature Ta
90
80
70
60
50
40
30
20
10
0
Imax - Ta (SOP)
Vo=0.7(V)
Imax - Ta (SOP)
Vo=1.0(V)
Vdd=5V
Tj=140C (Max)
16bit Active
Rext=470ohm
50
100
90
80
70
60
50
40
30
20
10
0
150
Vo=0.7(V)
Vo=1.0(V)
Vdd=5V
Tj=140C (Max)
16bit Active
Rext=470ohm
Ambient Temperature Ta
50
100
150
Ambient Temperature Ta
Note
As the power dissipation of a semiconductor chip is limited its package and ambient
temperature, this device requires a maximum output current be calculated for a given operating
condition. The maximum allowable power consumption (Pd (max)) of this device is
calculated as follows:
(Tj (junction temperature) (max) - Ta (ambient temperature) )(C )
Pd (max)(Watt ) =
Rth (C / Watt )
Based on the Pd (max), the maximum allowable current can be calculated as follows:
Iout = ( Pd VDDIDD) / ( # outputsVoDuty )
- 11 -
VersionA.004
ST2221C
R=
Vf
SCAN
OUT0
ENABLE
VCE
Vo
CLOCK
LATCH
SERIAL-IN
R-EXT GND
OUT15
SERIAL-OUT
CPU
OUT0
ENABLE
CLOCK
LATCH
SERIAL-IN
R-EXT GND
OUT15
SERIAL-OUT
Note
This device has only one ground pin shared by signal, output sink current, and power ground. It is
advisable to pattern the ground layout with minimized inductance such that the switching noise induced
by the input signals and the output sink current would not cause chip malfunction. To prevent the
drivers outputs from damage by overshoot stress, it is also advisable not to turn off the drivers and
scan transistors simultaneously.
- 12 -
VersionA.004
ST2221C
Package Outline
P-DIP 24
UNITINCH
1.250 0.03
0.355 0.02
0.300
0.258 0.005
=7 ~15
0.130 0.05
0.130 0.02
SEATING PLANE
0.210
0.100typ
0.018typ
0.060typ
- 13 -
VersionA.004
ST2221C
Package Outline
SOP24
0.020*45
0.406 0.013
0.295 0.004
UNITINCH
0.016typ
0.050typ
0.600 0.014
- 14 -
0.010
0.099 0.006
0.012max
0.004max
0.0350.015
=0~8
VersionA.004
ST2221C
Package Outline
SSOP24
0.020*45
0.236 0.008
0.154 0.004
UNITINCH
0.012typ
0.025typ
0.341 0.004
0.004max
0.01max
- 15 -
0.010
0.064 0.011
0.0250.025
=0~8
VersionA.004
ST2221C
The products listed herein are designed for ordinary electronic applications, such as
electrical appliances, audio-visual equipment, communications devices and so on. Hence,
it is advisable that the devices should not be used in medical instruments, surgical
implants, aerospace machinery, nuclear power control systems, disaster/crime-prevention
equipment and the like. Misusing those products may directly or indirectly endanger
human life, or cause injury and property loss.
Silicon Touch Technology, Inc. will not take any responsibilities regarding the misusage
of the products mentioned above. Anyone who purchases any products described herein
with the above-mentioned intention or with such misused applications should accept full
responsibility and indemnify. Silicon Touch Technology, Inc. and its distributors and all
their officers and employees shall defend jointly and severally against any and all claims
and litigation and all damages, cost and expenses associated with such intention and
manipulation.
- 16 -
VersionA.004