IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-Q, NO.

6, DECEMBER1974

347

[51 R. A. Stehlin and G. W. Niemann, Complementary transistor-transistor logic (CTzL)an approach to high-speed
micropower logic, IEEE J. Solid-State Circuits, vol. SC-7,

Stanley
F. Moyer was born in Hamburg,
Pa., on September 8, 1931. He graduated
from Capitol Radio Engineering Institute,
Washington, D.C. in 1956. He has also attended Albright College, Reading, Pa.j and
Lafayette College, Easton, Pa.
In 1956 he joined Bell Laboratories, Reading, Pa., where he has worked on the
development
of germanium diffused base
transistors,
silicon transistors,
and fieldeffect transistors. Since 1966, he has worked

pp. 153160, Apr. 1972.

Paul C. Davis

(S64)-M61) was born in

Glenville, W. Vs., on March 14, 1937. He
received the B.S.E E. degree from West
Virginia University, Morgantown,
in 1959,
the M.S. degree from Massachusetts Institute of Technology, Cambridge, in 1961, and
the Ph.D. degree in electrical engineering
from Lehigh University, Bethlehem, Pa., in
1968.
He has been a Teaching
Assistant at
M.I.T. and served two years as an army
officer in the Ordnance Guided Missile School, Huntsville, Ala.
In 1962 he became
tories,

Reading,

a Member
Pa.

He

has

of the Technical
been

engaged

Staff, Bell
in

Labora-

characterization

and modeling of transistors and in the design of linear and digital

integrated
circuitry.
Dr. Davis is a member of Eta KapDa Nu and Tau Beta Pi, and

an associate member of Sigma Xi.

on the

development

of silicon

monolithic

integrated

circuits.

Veikko R. Saari was born in Brooklyn, N.Y.,

on April 24, 1928. He received the B.S. and
M.S. degrees in physics from the University
of Minnesota,
Minneapolis,
in 1951 and
1956, respectively.
Since 1956 he has been working on the
design of solid-state circuits at Bell Laboratories, Holmdel, N.J.
Mr. Saari is a member of the American
Association of Physics Teachers.

Relationship Between Frequency Response and Settling

Time of Oper;tion~ Amplifiers
B. YESHWANT

KAMATH,

STUDENT MEMBER, IEEE, ROBERT

G. MEYER,
PAUL R. GRAY, MEMBER, IEEE

AbstracfThe
effects of pole-zero pairs (doublets) on the frequency response and settling time of operational amplifiers are
explored using analytical techniques and computer simulation. It
is shown that doublets which produce only minor changes in circuit
frequency response can produce major changes in settling time. The
importance of doublet spacing and frequency are examined. It is
shown that settling time always improves as doublet spacing is
reduced whereas the effect of. doublet frequency is different for
0.1 and 0.01 percent error bands. Finally it is shown that simple
analytical formulas can be used to estimate the influence of frequency doublets

on amplifier settling time.

I.

INTRODUCTION

MANY
applications
of operational
amplifiers, the
settling time is an important
parameter
[1]. The
I
settling time is the time taken for the output of the
amplifier to settle to within 0.1 or 0.01 percent after the
~

Manuscript
received May 13, 1974; revised August 8, 1974. This
work was supported
by the Joint Services Electronics
Program
under Contract
F44620-71-C-@187.
The authors are with the Department
of Electrical
Engineering
and Computer
Sciences and the Electronics
Research Laboratory,
IJniversity
of California,
Berkeley,
Calif. 9472Y3.

MEMBER, IEEE, AND

application
of an input step. This test is usually done in
a unity-gain
configuration
with a 1O-V step input and
thus the error bands on the output are 10 and 1 mV, respectively, for 0.1 and 0.01 percent accuracy. These tests
are important
in specifying the operational
amplifier for
use in such applications
as A/D and D/A converters.
The settling time of an amplifier is composed of two
distinct periods [1]. The first period is called the slew
time during which the amplifier output makes the transition from the original output voltage to the vicinity of
the new value. During this period the amplifier acts in a
grossly nonlinear
fashion and the length of this period
is generally determined by the current available to charge
the amplifier compensation
capacitance.
The second portion of the settling time is the period after slew limiting
when the amplifier output is near its final value and the
circuit acts in a quasi-linear
fashion. It has been shown
[2], [3] that this period is significantly
affected by the
presence of pole-zero pairs (called doublets) in the amplifier transfer function. In high-speed operational amplifiers, the slew time can be very short and this second

IEEE JOURNAL OF SOLID-STATECIRCUITS, DECEMBER1974

348

Fig. 1.

Operational

amplifier model for calculation

response.

of transient

period in the quasi-linear

region can dominate the settling time of the amplifier.
The circuit behavior
clescribed above is difficult to
evaluate in practice. Direct measurements
of these aspects of amplifier performance
are clifficult to perform
and the effects of different parameters
in the circuit are
difficult to isolate. In this paper the effect of cloublets on
the frequency response and settling time of a fast operational amplifier is investigated
using analytical
techniques and computer simulation.
II.

slew rate of the amplifier

through
the compensation
capacitor.
They can also have a very strong effect on
settling time if the phase margin is allowed to become
too small. However, in an optimum design, these poles
will produce only a slightly underdamped
response, and
this response will be short in duration compared to the
transients
introduced
by the doublet. A closely spaced
doublet is assmnecl and the doublet frequency is assumed
much less than the amplifier unity-gain
frequency.
The circuit of Fig. 1 is analyzed
in the Appendix
where it is shown that the response to a step input of
amplitude V is:

V..,(t) = V(l k, exp [co.ot] + k, exp [ (t/r,)]),

for t > T,

(2)
r2?

THEORY

Doublets in an amplifier transfer

function can arise
from a number of causes. For example, bypassing
one
side of an active loacl at high frequencies
[4] leads to
the introduction
of a pole-zero pair with an octave separation. The use of a feedforward
capacitor to bypass a
lateral p-n-p transistor
[2] can cause the creation of a
doublet with &30 percent mismatch
between pole and
zero frequencies.
Previous analyses of the effects of a doublet have assumed linear operation
of the circuit in question
[1]
[3]. However, the application of a 1O-V step to an operational amplifier results in quite nonlinear operation during the slewing period, and a linear analysis cannot be
justified for this case. A model which represents the situation in a practical amplifier is shown in Fig. 1. The amplifier is connected in a unity-gain
feedback loop. The
differential input stage is modeled as shown with maximum available
current 10 and a transfer
characteristic
slope of g,m for values of ]V~l less than (10/0,,, }. For
values of IV~I > (lO/g,~), the input stage limits at a current l.. This is the major source of nonlinearity
in the
circuit during the transient
response. A doublet is assumed present in the amplifier frequency
response together with the dominant pole produced by the compensation capacitor. These are shown schematically
in Fig. 1.
Since this portion of the circuit is assumed to act linearly,
the precise cletails of the circuit arrangement
are not
critical, However, to conform to the practical
example
considered later, a current II is assumed fed from the
input stage to the circuit producing the doublet, and a
current Iz is assumed fed from this circuit to the output.
The use of voltage variables does not change the results
of the analysis.
In this analysis, the higher frequency poles near ancl
beyond crossover have been neglected. These poles are
certainly important
since they limit the bandwidth
and

(1)

where

1
Q.

(3)

T, slewing period
W. doublet zero frequency
UP doublet pole frequency
COCOA X (amplifier
dominant
pole)
bandwidth
A
open-loop low frequency gain.

unity-gain

Equation
(1) indicates the presence of a slow settling
component in the output with a time constant (l/~,) and
a magnitude kzV. Equation
(2) indicates that for a given
fractional doublet spacing (for example, ~. = 1.3 Or) the
magnitude of the slow settling component is proportional
to the doublet frequency, and the magnitude of the input
step. However,
(3) indicates that the time constant of
the slow settling component is inversely proportional
to
the doublet frequency.
Thus lower frequency
doublets
will give a response which persists for a longer period
but with a smaller amplitude. Higher frequency doublets
will give a response which dies out faster but has a
larger amplitude. The relative importance of these trends
will depend on the particular
situation. If settling to 0.1
percent only is important, a lower frequency doublet may
give a slow-settling
component which is always within
the error band and thus does not degrade performance.
For settling to 0.01 percent the same doublet may cause
great increases
in settling
time. A higher frequency
doublet is likely to produce settling time degradation
in
all cases but its effect will die away much sooner [3].
III.

COMPUTER

SIMULATION

The analytical
expressions derived above use a greatly
simplified model of the operational
amplifier. In order
to check the validity
of these approximations
and to
further investigate
these effects, computer
simulations
were performed on the PA 772 operational
amplifier [2].
This amplifier was chosen because it is a high speed
amplifier with a fast settling time and the effects of

ICAMATH et

d :FREQUENCY RESPONSE AND

SETTLING

349

T1i%f10

artificially
introduced
doublets are easy to distinguish.
The amplifier itself has a doublet due to the use of feedforward but a doublet compression scheme which is an
integral part of the amplifier makes the effect of this
doublet undetectable.
In order to observe the effect of a
doublet on the response of the amplifier, one half of the
active load was bypassed with a capacitor in a similar
fashion to the LM 118 [4]. By varying the magnitude
of the capacitor and a resistor in series with it, doubleti
were introduced
at different frequencies
with different
pole-zero
separations.
The open-loop
unity-gain
frequency was kept constant in all cases at OJCO
= 6.1 MHz
by small adjustments
in the value of the compensation
capacitor. The compensation
capacitor used was larger
Lhan the one in the original ,pA 772 to allow for these
adjustments.
The program used was the SPICE program developed
at the University
of California,
Berkeley.
SPICE has a
general nonlinear transient analysis capability with comprehensive
large-signal
device models. The computed
open-loop gain and phase response for the basic amplifier are shown in Fig. 2(a) and (b) together with the
response when a doublet at 18 kHz is included. Even
with the addition of such a doublet with 32 percent mismatch between pole and zero frequencies, the change in
the frequency response is small. For a smaller doublet
(such as 8 percent pole-zero mismatch)
the effect on
frequency
response is indiscernible
on these scales. In
Fig. 2 (c) an expanded graph is shown of phase versus
frequency
for the amplifier with and without doublets.
The doublets used here were at 18 kHz with pole-zero
mismatches
of 32, 20, and 8 percent. It is apparent that
the 8 percent doublet has very little effect on the frequency response, but it will be shown to have a significant effect on the settling time.
In Fig. 3 (a) the computed transient response is shown
with a 1O-V input step ( 5 to +5 V) for the original
circuit in a unity-gain
voltage follower configuration.
On
this scale, the addition of doublets produces an almost
imperceptible
change in response. In Fig, 3 (b), this response is shown on an expanded scale to allow observation of 0.1 percent (10 mV) settling time. This is seen
to be about 0.43 ,ps for the case of no doublet, with about
0.2 ps of this being slewing time and the rest being
caused by overshoot. Because of the neglect of higher
frequency poles, this overshoot is not predicted by the
analysis in the Appendix.
Also shown in Fig. 3 (b) are response curves with doublets added to the amplifier.
It is apparent
that the
doublet at 180 kHz with 32 percent spacing produces the
worst degradation
of settling time with a value of 1.56 ps.
The 32 percent doublet at 18 kHz gives a settling time of
0.80 ~s, even though it persists much longer due to its
longer time constant. The much smaller initial value of
the slow settling component due to the 18 kHz doublet
results in its decaying below 10 mV sooner than is the
case for the 180 kHz doublet.

120Gain
(dB)

1.32 Doublet ot 18kHz

NO doublet

80-

40-

I
IkHz

IHz

1MHz

IO MHZ

I MHz

hlHz

Frequent y

(a)

,.
Ikiiz

I!iz

Frequency

(b)

No doublet

-90
1.08

Phase
(degree)

1.2
1

Doublet Ot 18kHz

-954

1.32
Ooublet spacing

-1oo
1
IH:

T
1

I MHz

I I(Hz

10idHz

Frequency
(c)

Fig. 2. Computed open-loop frequency response of the amplifier

with and without doublets. (a) Gain versus frequency. (b)
Phase versus frequency. (c) Expanded Pha* versus freWencY.

The graphs of Fig. 3(b) are shown even further expanded in Fig. 3(c) so that 0.01 percent (1 mV) settling
times can be determined.
In this case, for any given
fractional
doublet spacing, the lower frequency doublet
has by far the worst effect on settling time. This possibility was pointed out in Section II. Even though the
higher frequency doublets give larger initial amplitudes
of the slow settling component, the very slow decay for
the lower frequency
doublets makes them much more

significant for l-mV settling time, The worst case is for

the 32 percent doublet separation at a frequency of 18
kHz giving a l-mV settling time of 14.14 ps.
These results are illustrated in Fig. 4 where computed
settling times are shown as a function of doublet spacing

%5Q

IEEE JOURNAL OF SOLID-STATE CIRCUITS, DECEMBER1974

I
5.0L
0.0

1
\
0.5

1.32 Do,blel al 180 kHz

1.32 Doublet of 18kHz

%
No d~~bl~,

(
1,5

1.0
Time

(b)

(a)

No doublet

1,0

L
1.5

2.0

Time [pee}

(c)
Fig. 3. Computed unity-gain transient response of the ampIifier
to a 1O-V input step from 5 to +5 V, (a) Linear voltage
scale. (b) and (c) Expanded voltage scaJe.

Doublet
Settlhg

at 18 kHz

to
I mV

180 kHz

180 kHz
18 kHz

10 mV

1
1.3

r
1.2

1.1
Doublet

spacing

@z I Up

Fig. 4. Computed unity gain settling time versus doublet spacing

for two different doublet frequencies and settling accuracies,
Input step from 5 to +-5 V.

( ~sec )

(
2,0

KAMATH f?
~ Ctl.
:FREQUENCYRESPONSEAND SETTLINGTIME

351
TABLE I

Doublet
Spacing

Doublet at
18 kHz
Doublet at
180 kHz

1.08
1.2
1.32
1.08
1.2
1.32

ktv,
(mV)

(2)

10-mV Settling Time

(J&s)

computer

predicted

computer

predicted

computer

predicted

8.09
6.53
6.15
0.825
0.708
0.654

8.14
7.29
6.88
0.812
0.726
0.683

2.46
6.25
9.97
24.6
67.2
106

2.28
5.81
9.19
24.2
62.9
98.7

0.44
0.48
0.80
0.77
1.34
1,56
0.43

0,47
0.51
0.57
0.72
1.34
1.56

No Doublet

doublet frequencies (18 and 180 kHz).

This shows clearly that for 10-mV settling, the 180-kHz
doublet gives the worst degradation whereas for l-mV
settling the long time constant associated with the 18kHz doublet causes this to be the worst case. These tests
were repeated for negative steps from +5 to 5 V and
similar results were obtained.
The computed results are summarized in Table I. The
consistent trend towards smaller settling time is apparent as the doublet spacing is reduced. Also shown in
Table I are values of ., and k2V calculated from (2)
and (3) together with values determined from the computed responses. The values of ~z were simply determined from the tail of the exponential decay and the
values of k2V were determined by extrapolating back
from the region of the exponential decay. Quite close
agreement is seen in the values determined from the two
methods.
Finally, Table I shows calculated values of settling
time using (1). These show good agreement with the
computed values.
for two different

IV. CONCLUSIONS
It has been shown that frequency doublets in the
transfer function of an operational amplifier may cause
severe degradation of settling time while only causing
minor changes in the frequency response of the amplifier. The effect of the doublet depends both on its frequency and the pole-zero spacing. Reduction of the polezero spacing of the doublet reduces its effect, but
pole-zero frequency mismatches as small as 8 percent
can cause significant increases in settling time.
The effect of the doublet frequency on settling time is
more complex. For 0.01 percent settling, a lower frequency doublet can potentially cause the worst performance degradation because of its long time constant. However, for 0.1 percent settling, the smaller amplitude of a
lower frequency doublet may mean that it is always
within the error band and has little effect. In that case a
higher frequency doublet would cause more settling time
degradation because of its larger amplitude, even though
it decayed faster.

l-mV Settling Time

(W)
predicted

computer

6.7
12.8
15.2
2.59
3.01
3.14

7.3
12.0
14.2
2.62
3.01
3.05
0.56

Finally, it has been shown quite generally that the

simple formulas derived here can be used to predict the
influence of frequency doublets on operational amplifier
settling time.
APPENDIX
The circuit of Fig. 1 is to be analyzed for a step input
of magnitude V where in general
(4)

v > I,/g..

In this situation, the initial voltage Vd applied to the

differential input stage is sufficient to cause limiting and
a constant current 10 is supplied to the doublet and output stage. Computer simulation shows that in practice
this occurs. The period when the input stage is limiting
represents the slewing period of the amplifier and the
feedback loop is effectively open during this period.
When the output voltage Vo,,t approaches within Io/gm
of V, the differential stage enters its linear region and
the amplifier settles to its final value with the feedback
loop closed. Assumptions made are that the doublet is
closely spaced and the doublet frequency is much less
than the amplifier unity-gain frequency, i.e., ~. << tiCO.
Consider the slewing period where the input stage is
limiting. Then
(5)

(6)
A/gm
V..,(S) = 1 + (sA/coco) I,(s) .

(7)

Taking inverse Laplace transforms

(8)

Vout(t) = +

1 &$:fi)3

exp [-wJ]

+ 1 (C.JC,JACOJ
exp [ (UCJA) t] .
(cLLo/AoJ.)
1
At time T,, the output Vout reaches (V

(9)

(lo/g,.) and

IEEEJOURNALOF SOLID-STATE
CIRCUITS,
DECEMBER1974

352

the differential input stage enters its linear region. The

whole amplifier then begins settling as a linear feedback
loop with initial conditions determined as follows.
(lo)

11(7$) = 10
V.,(ZJ

(11)

= v :.

~, ~ (%/6)=) 1
2

1-

(JiJ

~, ~

N 1 ~~ T,,

w%)

1 (%/%)

(12)

(25)

(13)

It is interesting to note that (25) is the same result as

obtained in earlier work [1], [2] assuming completely
linear operation of the amplifier.
Using equation (21 ) and assuming w. << w~,, (25) can
be further simplified to

(14)

(2)

and
exp [(m../A)T,]

(24)

For typical component values wfiT. <<1. In extreme cases,

this term may be as large as 0.2 or 0.3. However, the
effect of this factor on calculated settling time is much
less because settling time is related to the logarithm of
kz. Thus

Using
exp [ oJ,z.]
= 1 COOT,

1 + T)

in (9) we have

From (21) it can be seen that

Using (14) and (12) in (8) gives

2(T8)
5+:4+)(

-:)

15)

With the amplifier operating linearly, the circuit equations are given by
A/g.
12(s)
V..,(S) = 1 + (A.s/Loco)

(16)

1 + (~/%) v
)
12(s) = gm
1 + (s/@p)( (S

~. .

Vot($)

(17)

~z~

if COz
<< LOCO.

(26)

REFERENCES

[11 P. R. Gray and R, G. Meyer, Recent advances in monolithic operational amplifier design, IEEE 7nzn.s. Circuits
Syst., vol. CAS-Z1, pp. 317-327, May 1974.
[21 R. J. Apfel and P. R. Gray, A monolithic fast-settling feedforward operational amplifier using doublet compression techniques, in ISSCC Dig. Tech. Papers, 1974, pp. 134135.
[31 F. D. Waldhauer, Analog integrated circuits of large bandwidth, in 1963 IEEE Conv. Rec., part 2, pp. 200-207.
[4] R. C. Dobkin, (LM 118 op amp slews 70 V/ys,J National
Semi-Conductor Linear Brief 17, Aug. 1971.

where initial conditions at t = Ts are given by (10),

(11), and (15). An analysis gives for t > T,
V.,(t) E V(l k, exp [co..(t T,)]
+ kz exp [u.(f

T,)])

(18)

B. Yeshwant Kamath (S72) was born in

Mangalore, India, on August 26, 1948. He
received the B .Tech. degree in electrical
engineering from the Indian Institute of
Technology, Madras, India, in 1969, and
the M.S.E.E. degree from Syracuse University, Syracuse, N .Y., in 1971. He is presently at the University of California,
Berkeley, studying towards the Ph.D degree
in electrical engineering.
His interests are in bioelectronics and in-

where
~ , ~ (%/(0=) 1
1
(OJJCI).) 1

[(

1 :

1 (C+Jco.)
2 [ 1 + (a.o/uJ 1

(21)

grated circuits.

Equation (18) can be written as

Vot(t) N V(l k, exp [co.ot]
+ kz exp [coct]),
for t > T,.
Since 0.<<

w.., the last term represents

(22)

the slow settling

Robert G. Meyer (S64M68), for a photograph and biography,

please see p. 166 of the August 1974 issue of this JOURNAL.

component and is the term of interest.

For typical values normally encountered, the term in
parentheses in (20) is approximately unity. Thus
?cZ =

i.e.,

?/2

exp

[w.T,],

(23)
Paul R. Gray (S65-M69), for a photograph and biography, please
see p. 313 of this issue.