1. Explain about ARM architecture and organization?

The ARM (Advanced RISC Machine) architecture consists of :

1. Load store architecture
2. Register bank
3. ALU
4. Multiply register
5. Data bus
6. Barrel shifter
7. Address register
8. Instruction decoder
9. Incrementer

1. Load store architecture

Since the arm processor is basically a RISC processor it uses a load store
architecture.This means ,it has two instruction types load and store for
transferring data in and out of the processor respectively.
LOAD : This instruction copies data from memory to registers in the
processor core.
STORE :This instruction copies data from registers in the processor core to
memory. The ARM processor instruction set does not include the
instructions that directly manipulate data in memory. The data processing is
carried out only in registers.
2. Register bank
This is a bank of 32 bit registers used for storing data items. It consists of 2
read ports, 1 write port + 1 read, 1 write port reserved for r15 (program
counter).
3. ALU ( Arthimetic Logical Unit)
It performs the arithmetic and logic functions required. The ALU performs
the operation and stores the computed result via internal bus in destination
register and then to the register bank.
4. Multiply register
5. Data bus
The data enters ARM core through the data bus. The data is either in the
form of an instruction opcode or a data item .Since Von Neumann
architecture is used , data items and instructions share the same bus. this is
contrast with Hardvard architecture of the ARM which uses two different
buses.
6. Barrel Shifter
The contents of registers are alternatively preprocessed in barrel shifter
before applying as input to ALU. A wide range of addresses and expressions
can be caluculated using barrel shifter and ALU.
7. Address Register
This holds the address generated by the load and store instructions and
places it on the address bus.
8. Instruction Decoder
This unit decodes the instruction opcode read from the memory and then the
instruction is executed.
9. Incrementer

For load and store instructions, the incrementer updates the contents of the
address register before the processor core reads or writes the next register
value from or to the consecutive memory location. The processor core
continues the execution instruction. Only when an exception or interrupt
occurs, the normal execution flow is changed.

2. Explain about ARM programming model? (or)

Explain about ARM Register organization?
ARM registers: It has 37 registers.

ARM7TDMI has a total of 37 registers31 general-purpose 32-bit registers

and six status registersbut these cannot all be seen at once. The processor state
and operating mode dictate which registers are available to the programmer.

15 general registers (R0 to R14), and one status registers and program counter are
visible at any time when you write user-level programs
R13 (SP)-Stack pointer
R14 (LR)- Link register
R15 (PC)- program counter
The ARM state register set:
In ARM state, 16 general registers and one or two status registers are visible at
any one time. In privileged (non-User) modes, mode-specific banked registers are
switched in. The above Figure (Register organization in ARM state) shows
which registers are available in each mode: the banked registers are marked with a
shaded triangle.
The ARM state register set contains 16 directly accessible registers: R0 to R15. All
of these except R15 are general-purpose, and may be used to hold either data or
address values. In addition to these, there is a seventeenth register used to store
status information.
Register 14 is used as the subroutine link register. This receives a copy of R15
when a Branch and Link (BL) instruction is executed. At all other times it may be
treated as a general-purpose register. The corresponding banked registers R14_svc,
R14_irq, R14_fiq, R14_abt and R14_und are similarly used to hold the return
values of R15 when interrupts and exceptions arise, or when Branch and Link
instructions are executed within interrupt or exception routines.
Register 15 holds the Program Counter (PC). In ARM state, bits [1:0] of R15 are
zero and bits [31:2] contain the PC. In THUMB state, bit [0] is zero and bits [31:1]
contain the PC.
Register 16 is the CPSR (Current Program Status Register). This contains
condition code flags and the current mode bits.
FIQ mode has seven banked registers mapped to R8q14 (R8_fiqR14_fiq). In
ARM state, many FIQ handlers do not need to save any registers. User, IRQ,
Supervisor, Abort and Undefined each have two banked registers mapped to R13
and R14, allowing each of these modes to have a private stack pointer and link
registers.

3. Explain about THUMB programming model? (or)

Explain about THUMB Register organization?

The THUMB state register set;

The THUMB state register set is a subset of the ARM state set. The
programmer has direct access to eight general registers, R0R7, as well as the
Program Counter (PC), a stack pointer register (SP), a link register (LR), and
the CPSR. There are banked Stack Pointers, Link Registers and Saved Process
Status Registers (SPSRs) for each privileged mode. This is shown in above
Figure ( Register organization in THUMB state).

4. Explain about the program status register of ARM?

The ARM contains a Current Program Status Register (CPSR), plus five
Saved Program Status Registers (SPSRs) for use by exception handlers.
These registers functions are:
Hold information about the most recently performed ALU operation.
Control the enabling and disabling of interrupts.
Set the processor operating mode

The N, Z, C and V are condition code flags

may be changed as a result of arithmetic and logical operations in the
processor
may be tested by all instructions to determine if the instruction is to be
executed
N : Negative. Z : Zero. C : Carry. V : Overflow
The I and F bits are the interrupt disable bits
The T bit is thumb bit
The M0, M1, M2, M3 and M4 bits are the mode bits

5. Explain about operating modes of ARM?

The ARM has seven basic operating modes:
User : unprivileged mode under which most tasks run
FIQ : entered when a high priority (fast) interrupt is raised
IRQ : entered when a low priority (normal) interrupt is raised
Supervisor : entered on reset and when a Software Interrupt
instruction is executed
Abort : used to handle memory access violations
Undef : used to handle undefined instructions
System : privileged mode using the same registers as user mode

6. Explain about ARM Memory organization?

In addition to the processor register state, an ARM system has
memory state. Memory may be viewed as a linear array of bytes numbered
from zero up to 232-l. Data items may be 8-bit bytes, 16-bit half-words or 32bit words. Words are always aligned on 4-byte boundaries (that is, the two
least significant address bits are zero) and half-words are aligned on even

byte boundaries. The memory organization is illustrated in below figure.

This shows a small area of memory where each byte location has a unique
number. A byte may occupy any of these locations, and a few examples are
shown in the figure. A word-sized data item must occupy a group of four
byte locations starting at a byte address which is a multiple of four, and
again the figure contains a couple of examples. Half-words occupy two byte
locations starting at an even byte address. This is the standard, 'little-endian',
memory organization used by the ARM.

Figure:'little-endian', memory organization

Memory Formats
ARM7TDMI-S views memory as a linear collection of bytes numbered upwards from zero. Bytes 0 to 3
hold the first stored word, bytes 4 to 7 the second and so on. ARM7TDMI-S can treat words in memory as
being stored either in Big-endian or Little-endian format.

The Memory Organization of a Flash Device is divided into Flash sectors. Flash
sectors are named blocks in RL-FlashFS. Typically, a blocks is a 64 KB memory
page. Blocks can be devided into memory cells, which are written sequencially.
The memory cell size depends on the device architecture and is 8- (byte), 16- (half
word) or 32-bit wide (word).
Each Block contains its own allocation information written to the file allocation
table located on top of memory. The file name and file content are stored in lower
memory regions. If the file size exceeds a single block, then the file is stored across
several blocks. Several smaller files are stored into a single block.

When the file content is modified, the old file content is invalidated and a new
memory block is allocated. The Flash Block is erased when all the data stored in
the Flash Block have been invalidated.
ARM and Thumb instruction set overview
ARM and Thumb instructions can be grouped by functional area.
All ARM instructions are 32 bits long. Almost all Thumb instructions were 16-bit.
The Thumb instruction set is a subset of the most commonly used 32-bit ARM
instructions. Thumb instructions are each 16 bits long, and have a corresponding
32-bit ARM instruction that has the same effect on the processor model. Thumb
instructions operate with the standard ARM register configuration, allowing
excellent interoperability between ARM and Thumb states.
On execution, 16-bit Thumb instructions are transparently decompressed to full 32bit ARM instructions in real time, without performance loss.
Thumb has all the advantages of a 32-bit core:
32-bit address space
32-bit registers
32-bit shifter, and Arithmetic Logic Unit (ALU)
32-bit memory transfer.
Thumb therefore offers a long branch range, powerful arithmetic operations, and a
large address space.
Together, the 32-bit and 16-bit Thumb instructions provide functionality that is
almost identical to that of the ARM instruction set.

The following table describes some of the functional groupings of the available
instructions:
Instruction
Group
Branch and
control

Description
These instructions do the following:

Branch to subroutines.

Branch backwards to form loops.

Branch forward in conditional structures.

Make following instructions conditional without

branching.

Change the processor between ARM state and Thumb state.

Data processing These instructions operate on the general-purpose registers. They

can perform operations such as addition, subtraction, or bitwise
logic on the contents of two registers and place the result in a third
register. They can also operate on the value in a single register, or
on a value in a register and an immediate value supplied within the
instruction.
Long multiply instructions give a 64-bit result in two registers.
Register load
and store

These instructions load or store the value of a single register from

or to memory. They can load or store a 32-bit word, a 16-bit
halfword, or an 8-bit unsigned byte. Byte and halfword loads can
either be sign extended or zero extended to fill the 32-bit register.
A few instructions are also defined that can load or store 64-bit
doubleword values into two 32-bit registers.

Multiple
register load
and store

These instructions load or store any subset of the general-purpose

registers from or to memory.

Status register
access

These instructions move the contents of a status register to or from

a general-purpose register.

Coprocessor

These instructions support a general way to extend the ARM

architecture. They also enable the control of the CP15 System
Control coprocessor registers.

7. Discuss about ARM features?

Large uniform register file: An ARM processor contains a large number of
like a RISC.
Load -store architecture: ARM processor uses a RISC architecture .It
contains a large number of registers. The instruction set contains separate
load and store instructions for transferring data between the register bank
and external memory. When data is to be operated it is stored in the register
and then processed. The memory accesses are separated from data

processing. So we can use data items stored in registers multiple items

without multiple memory access.
Uniform and fixed length (32bit ) instruction fields : ARM processor
instruction set contains reduced number of instructions. All instructions are
32 bits long. Most instructions execute in a single cycle. Every instruction
can be conditionally executed.
Three address instruction formats: Most instruction of RISC and ARM
processor have 3 address instruction formats, i.e. two source operands are
stored in two different address locations and third operand is stored in a
third address location.
ARM has 32-bit architecture but supports 16 bit or 8 bit data types also.
ARM is programmable as little endian or big endian data alignment in
memory.
ARM provides the advantage of using a CISC in terms of functionality,
along with the advantage of an RISC in terms of faster program
implementation as well as reduced code lengths.
ARM processor has an RISC core for processing
Combination of RISC and CISC features ARM supports to a complex
addressing modes based instruction set.