Q. 1 - Q. 25 Carry One Mark Each.: X A X AA
Q. 1 - Q. 25 Carry One Mark Each.: X A X AA
Q. 1 - Q. 25 Carry One Mark Each.: X A X AA
SET-3
1
tan x
, the determinant of AT A1 is
1
tan x
For A =
(B) cos 4x
(A) sec 2 x
Q.2
=2
If
=2
(B)
(C)
=4
with respect to
(D)
is equal to
=0
equals
(A) 2
Q.4
(D) 0
Q.3
(C) 1
(B) 0
(D) 2
(C)
Consider the function g (t ) = e t sin(2 t )u (t ) where u (t ) is the unit step function. The area under
g (t ) is _______.
Q.5
1
The value of n is ______.
n =0 2
Q.6
For the circuit shown in the figure, the Thevenin equivalent voltage (in Volts) across terminals a-b
is ________.
3
12 V
1A
Q.7
10
+
5A
VX
20
+
-
0.25 VX
EC
1/14
GATE 2015
Q.8
SET-3
At very high frequencies, the peak output voltage V0 (in Volts) is ________.
100 F
1 k
1 k
V0
100 F
1.0sin(t) V
1 k
1 k
100 F
Q.9
Which one of the following processes is preferred to form the gate dielectric (SiO2) of MOSFETs ?
(A) Sputtering
(C) Wet oxidation
Q.10
If the base width in a bipolar junction transistor is doubled, which one of the following statements
will be TRUE?
(A)
(B)
(C)
(D)
Q.11
In the circuit shown in the figure, the BJT has a current gain ( ) of 50. For an emitter-base
voltage
= 600 mV, the emitter-collector voltage
(in Volts) is _______.
3V
60 k
EC
500
2/14
GATE 2015
Q.12
SET-3
In the circuit shown using an ideal opamp, the 3-dB cut-off frequency (in Hz) is _______.
vi
10 k
10 k
+
0.1 F
10 k
Q.13
vo
10 k
In the circuit shown, assume that diodes D1 and D2 are ideal. In the steady state condition, the
average voltage Vab (in Volts) across the 0.5 F capacitor is _____.
1 F
50 sin (t)
D1
D2
b
0.5 F
Vab
Q.14
The circuit shown consists of J-K flip-flops, each with an active low asynchronous reset (R input).
The counter corresponding to this circuit is
EC
3/14
GATE 2015
Q.15
SET-3
In the circuit shown, diodes D1 , D2 and D3 are ideal, and the inputs E1 , E2 and E3 are 0 V for
logic 0 and 10 V for logic 1. What logic gate does the circuit represent?
E1
E2
E3
D1
D2
D3
V0
1 k
10V
(A)
(B)
(C)
(D)
Q.16
Q.17
3-input OR gate
3-input NOR gate
3-input AND gate
3-input XOR gate
Which one of the following 8085 microprocessor programs correctly calculates the product of two
8-bit numbers stored in registers B and C?
(A)
MVI A, 00H
JNZ LOOP
CMP C
LOOP DCR B
HLT
(B)
MVI A, 00H
CMP C
LOOP DCR B
JNZ LOOP
HLT
(C)
MVI A, 00H
LOOP ADD C
DCR B
JNZ LOOP
HLT
(D)
MVI A, 00H
ADD C
JNZ LOOP
LOOP INR B
HLT
Q.18
3
i =0
i x[n i ] .
The condition on the filter coefficients that results in a null at zero frequency is
EC
(A) 1 = 2 = 0; 0 = 3
(B) 1 = 2 = 1; 0 = 3
(C) 0 = 3 = 0; 1 = 2
(D) 1 = 2 = 0; 0 = 3
4/14
GATE 2015
Q.19
SET-3
Consider the Bode plot shown in the figure. Assume that all the poles and zeros are real-valued.
40 dB
40 dB/dec
40 dB/dec
0 dB
The value of
Q.20
Q.21
300
fL
900
Freq. (Hz)
fH
10
is _______.
s ( s + 10)
( + )
+
where , and are positive real numbers. The condition for this controller to act as a phase lead
compensator is
(A)
Q.22
<
(B)
>
(C)
<
(D)
>
The modulation scheme commonly used for transmission from GSM mobile terminals is
(A) 4-QAM
(B) 16-PSK
(C) Walsh-Hadamard orthogonal codes
(D) Gaussian Minimum Shift Keying (GMSK)
Q.23
A message signal m(t) = Am sin(2fmt) is used to modulate the phase of a carrier Ac cos(2fct) to get
the modulated signal y(t) = Ac cos(2fct + m(t)). The bandwidth of y(t)
(A) depends on Am but not on fm
(B) depends on fm but not on Am
(C) depends on both Am and fm
(D) does not depend on Am or fm
Q.24
The directivity of an antenna array can be increased by adding more antenna elements, as a larger
number of elements
(A)
(B)
(C)
(D)
EC
5/14
GATE 2015
Q.25
SET-3
A coaxial cable is made of two brass conductors. The spacing between the conductors is filled with
Teflon ( r' = 2.1, tan = 0) . Which one of the following circuits can represent the lumped
element model of a small piece of this cable having length ?
Rz / 2 Lz / 2
Rz / 2 Lz / 2
Rz / 2 Lz / 2
Gz
Cz
Cz
Lz / 2
Lz / 2
Gz
(C)
(B)
(A)
Rz / 2 Lz / 2
Rz
Lz
Gz
Cz
Cz
(D)
Q.26
The Newton-Raphson method is used to solve the equation f (x) = x3 5x2 + 6x 8 = 0. Taking the
initial guess as x = 5, the solution obtained at the end of the first iteration is __________.
Q.27
A fair die with faces {1, 2, 3, 4, 5, 6} is thrown repeatedly till 3 is observed for the first time. Let
X denote the number of times the die is thrown. The expected value of X is ____.
Q.28
+ 3
( )
+ 2 ( ) = 0.
Given x(0) = 20 and x(1) = 10/e, where e = 2.718, the value of x(2) is _________.
Q.29
EC
is _______.
6/14
GATE 2015
Q.30
SET-3
In the circuit shown, the current I flowing through the 50 resistor will be zero if the value of
capacitor C (in F) is ______.
1 mH
50
1 mH
5 sin(5000t)
1 mH
Q.31
Q.32
(A)
3.5 + 2
20.5
(C)
10
2+ 0
2+ 0
10
20.5
3.5 2
(B)
3.5 + 2
0.5
30.5
3.5 2
(D)
7+ 4
0.5
30.5 7 4
(A)
(C)
EC
)(
)(
( ) =
( )
( )
is
(B)
(D)
)(
)(
7/14
GATE 2015
Q.33
SET-3
The electric field profile in the depletion region of a p-n junction in equilibrium is shown in the
figure. Which one of the following statements is NOT TRUE?
E
(V/cm)
104
0.1 0
0.5
1.0
X (m)
(A) The left side of the junction is n-type and the right side is p-type
(B) Both the n-type and p-type depletion regions are uniformly doped
(C) The potential difference across the depletion region is 700 mV
(D) If the p-type region has a doping concentration of 1015 cm-3, then the doping concentration in
the n-type region will be 1016 cm-3
Q.34
The current in an enhancement mode NMOS transistor biased in saturation mode was measured to
be 1 mA at a drain-source voltage of 5 V. When the drain-source voltage was increased to 6 V
while keeping gate-source voltage same, the drain current increased to 1.02 mA. Assume that drain
to source saturation voltage is much smaller than the applied drain-source voltage. The channel
length modulation parameter (in
) is _______.
Q.35
An npn BJT having reverse saturation current I S = 10-15 A is biased in the forward active region
with VBE = 700 mV. The thermal voltage ( VT ) is 25 mV and the current gain ( ) may vary from
50 to 150 due to manufacturing variations. The maximum emitter current (in A) is ________.
Q.36
A three bit pseudo random number generator is shown. Initially the value of output
Y Y2 Y1 Y0 is set to 111. The value of output Y after three clock cycles is
(A) 000
EC
(B) 001
(C) 010
(D) 100
8/14
GATE 2015
Q.37
SET-3
A universal logic gate can implement any Boolean function by connecting sufficient number of
them appropriately. Three gates are shown.
Gate 1
Gate 2
Gate 3
An SR latch is implemented using TTL gates as shown in the figure. The set and reset pulse inputs
are provided using the push-button switches. It is observed that the circuit fails to work as desired.
The SR latch can be made functional by changing
Set
5V
Q
Reset
(A) NOR gates to NAND gates
(B) inverters to buffers
(C) NOR gates to NAND gates and inverters to buffers
(D) 5 V to ground
Q.39
In the circuit shown, assume that the opamp is ideal. If the gain (vo / vin) is 12, the value of
R (in k) is _____.
10 k
10 k
vin
10 k
v0
EC
9/14
GATE 2015
Q.40
SET-3
In the circuit shown, both the enhancement mode NMOS transistors have the following
( )=1
;
=
= 1 . Assume that the channel length
characteristics:
(in
modulation parameter is zero and body is shorted to source. The minimum supply voltage
volts) needed to ensure that transistor M1 operates in saturation mode of operation is _______.
VDD
M2
2V
Q.41
M1
In the circuit shown, assume that the diodes D1 and D2 are ideal. The average value of voltage Vab
(in Volts), across terminals a and b is _________.
D2
D1
6 sin(t)
a +
10 k
Q.42
10 k
Vab
b
20 k
EC
10/14
GATE 2015
Q.43
SET-3
A realization of a stable discrete time system is shown in the figure. If the system is excited by a
unit step sequence input x[n] , the response y[ n ] is
[ ]
5/3
2/9
5/3
Let [ ] = 1 + cos
ak =
Q.45
2
1
(B) 5 u[n] 3 u[n]
3
3
n
1
2
(C) 5 u[n] 5 u[n]
3
3
Q.44
[ ]
1
2
(A) 4 u[n] 5 u[n]
3
3
n
2
1
(D) 5 u[n] 5 u[n]
3
3
be a periodic signal with period 16. Its DFS coefficients are defined by
16 n =0
8
15
is _______.
( 2)
( 10 )
where denotes the convolution operation and t is in seconds. The Nyquist sampling rate (in
samples/sec) for ( ) is _____.
Q.46
The position control of a DC servo-motor is given in the figure. The values of the parameters are
is
Td(s)
Va(s)
KT
Ra+La s
1
J s+B
1
s
(s)
Kb
EC
11/14
GATE 2015
Q.47
SET-3
is _______.
Y(s)
s+3
s+2
Q.48
The characteristic equation of an LTI system is given by F(s) = s5 + 2s4 + 3s3 + 6s2 4s 8 = 0.
The number of roots that lie strictly in the left half s-plane is _________.
Q.49
Q.50
is _________.
[ ] = 0.5 [ ], where
is a
1.5 for = 0, 1
0
otherwise.
1
x
x e is
2
_______.
Q.51
sin( t / 5)
sin( t ) , centered
4
t / 5
1
Hz, is
2
sin( t / 5) j 4
e
t / 5
sin( t / 5) j 4
(C)
2
e
t / 5
(A)
EC
sin( t / 5) j 4
e
t / 5
sin( t / 5) j 4
(D)
2
e
t / 5
(B)
12/14
GATE 2015
Q.52
SET-3
Q.53
( )
equals ________.
Consider the 3 m long lossless air-filled transmission line shown in the figure. It has a characteristic
impedance of 120 , is terminated by a short circuit, and is excited with a frequency of 37.5 MHz.
What is the nature of the input impedance (Zin)?
ZL=0
Zin
(A) Open
Q.54
(B) Short
3m
(C) Inductive
(D) Capacitive
A 200 m long transmission line having parameters shown in the figure is terminated into a load .
through a switch, which is
The line is connected to a 400 V source having source resistance
closed at t = 0. The transient response of the circuit at the input of the line (z = 0) is also drawn in
the figure. The value of
(in ) is ________.
RS = 150
R0 = 50
r,eff = 2.25
RL
VS = 400 V
200 m
z=0
Q.55
EC
z=L
A coaxial capacitor of inner radius 1 mm and outer radius 5 mm has a capacitance per unit length of
172 pF/m. If the ratio of outer radius to inner radius is doubled, the capacitance per unit length
(in pF/m) is ________.
13/14
GATE 2015
SET-3
EC
14/14