User Manual

for
Krypton v1.1
Saurabh Agrawal
Abhishek Kamath
Kaushlesh Sharma
Debapratim Ghosh

Reconfigurable Hardware Design Team

Virtual Labs (e-Prayog) Wadhwani Electronics Lab
Indian Institute of Technology Bombay
September 2012

Board Synopsis

Krypton v1.1 (hereafter referred to as Krypton) is a 5M1270ZT144C5N CPLD-based board developed

at e-Prayog, WEL Lab, IIT Bombay under the Virtual Labs Project by the Ministry of Human
Resource and Development (MHRD), Government of India. This is a low-cost solution aimed to cater
to the needs of undergraduate and graduate electrical/electronics engineering students in a course in
digital design and thereafter, design of fairly complex digital systems.

Prerequisites for using Krypton

Before using Krypton, you are expected to have a basic familiarity/ working knowledge of:
Basic concepts of digital logic and digital systems- logic circuits, combinational and sequential
logic, and their applications in systems design
Familiarity with any Hardware Description Language (HDL), such as VHDL or Verilog
Not mandatory, but familiarity with various kinds of Programmable Logic Devices (PLDs)
On the e-Prayog webpage and in the support disk, there are introductory study material available
on programmable logic devices, digital electronics, as well as introduction to hardware description
languages.

Precautions for using Krypton

Do not touch the pins of any onboard IC directly, to avert the risk of damage by electrostatic
discharge.
When interfacing with large number of external peripherals, power the board through a single
+5V DC supply (tested).
The voltage at any I/O pin should not exceed 3.3V .
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Contents in the Support Disk/Webpage

Krypton user manual (obviously!)
Example applications with manual (labsheets)
Driver files for the host PC (CMD20817)
UrJTAG software for programming the CPLD
Installer executable for Altera Quartus II v12.0
Video tutorials for Krypton and using Quartus II and UrJTAG

Features and Specifications for Krypton

Figure 1 shows a top view of Krypton with detailed labels.

Figure 1: Krypton top-view with labeled features

Following are the features on Krypton.

A board centered around 5M1270ZT144C5N, a CPLD of Alteras MAX V family (980 macrocells/1270 logic elements)
USB programmable and powered, with provision for external DC supply
Preconfigured on-board I/Os- 8 switches, 8 LEDs and 4 push-buttons with hardware debounce
On-board clock of 1Hz and 50MHz, and provision for external clock source connection
Connectors provided on-board to interface standard peripherals directly (LCD/GLCD/PS2)
Large number of on-board I/Os (86) provided for various applications
Hot-socketing provided by detachability of the CPLD daughter card for compatibility with
of the MAX II family.

Configuring Krypton Before Programming

You will need to ensure that an appropriate power source is selected for the CPLD while programming
or running an application. To do this, an on-board jumper PWRSEL needs to be connected suitably.

PWRSEL Jumper Setting

1. Between pin 1 and center
2. Between pin 2 and center

Power Source for Krypton

Board powered through USB
(Bus-powered via host PC)
Board powered through external power supply header
EXTPWR

Table 1: Configuration for PWRSEL jumper

Getting Krypton working with your PC

1. Plug in the USB cable to the USB connector on the board, and the other end of the cable to a
USB port on your PC. Turn on the power switch. There are three power LEDs on the board,
which should glow.
2. You will need to install the drivers for Krypton the first time it is connected to your PC. The
procedure to do so varies slightly, depending on the operating system in use.

For Windows XP:

3. Once you connect Krypton to your PC and power it on, a Found New Hardware window will
open up. Select No, not this time and click Next. Now, select Install from a specific
list or location (Advanced), and click Next.
4. Now, click on the Browse button and provide the path to the folder CMD20817 (which is
available in the support disk). Click Next.
5. This installation should now begin. The Found New Hardware may open up more than once
(usually, not more than four times). In such cases, repeat steps 3-4.

6. At the end of the installation, you should see a desktop pop-up notification Your device is
now installed and ready to use.
For Windows 7:
3. Once you connect Krypton to your PC and power it on, Windows 7 automatically searches for
available drivers. If no drivers are available, a desktop notification showing Device driver was
NOT successfully installed will pop up. In such case, right click Computer Properties
Device Manager.
4. Inside Device Manager, under Other devices you will see 2 uninstalled devices named RS232-HS.
Right click on the first one and select Update driver. Now select Browse the computer for
driver software, and click Next. Now, provide the path to the folder CMD20817 (which is
available in the support disk). Click Next.
5. The installation should now begin. After this is complete, repeat step 4 for the second uninstalled
device RS232-HS. Krypton is now ready to be used.

Using Quartus II IDE to make Applications

Quartus II is the IDE provided by Altera for the user to write their HDL code (VHDL or Verilog)
to target a digital system designed to be implemented on a target PLD. The IDE allows for code
compilation, followed by generating a programming file for a specific target PLD (a CPLD or and
FPGA). Quartus II has a free subscription/web edition that can be used. Suppose we wish to design
and implement on Krypton, the simple logic circuit shown in Figure 2. This section provides a
step-by-step method for doing the same.

a
b

c
d
Figure 2: A simple logic circuit to be implemented on Krypton
1. Open Quartus II IDE. A pop-up will appear asking you to either create a new project or open
an existing one. Click on Create New Project. Alternatively, you may click on File New
Project Wizard.
2. An Introduction page opens up. Click on Next.
3. This opens up Page 1. Here, you need to specify a working directory for your project. Click
Browse (...) to create a new folder for this project. Next specify the project name and top
level design entity. Important: This is a very critical step in your design. Top level design
entity refers to the name of the entity in your HDL code (if you are using VHDL) or name
of the module (if you are using Verilog) which you wish to implement. By default the entity
name follows the same name as the project. It is preferred not to change this. Since we wish to
implement the circuit in Figure 2, name the project as myLogicCkt. The top level entity is also
named myLogicCkt by default. Click Next.
4. This opens up Page 2. This page allows you to include any existing VHDL/Verilog program
files as part of your project. You may skip this step as this is not mandatory. Click Next.
4

5. On Page 3, you are asked for the family and device settings, i.e. the target PLD on which you
wish to implement your design. Important: This is a very crucial step to select the correct
device, which is on Krypton.
6. Click on the Family drop-down list and select MAX V. The device window shows a long list of
devices available in the MAX V family.
7. On the right side of the window, you can filter out the device list by selecting Package as TQFP,
Pin Count as 144 and Speed Grade as 5. You will see that the list is now quite short! Select
the device 5M1270ZT144C5N and click Next.
8. In the Page 4 window, you will be asked to select a simulation tool. Again, this is not mandatory
and can be skipped. Click Next, and on Page 5 you will be shown a project summary. You
may use this to review your settings, and can go back to rectify any mistake. Once confirmed,
click Finish. The project is now created.
9. Now, go to File New. A window will open, asking you to select the HDL you will use. In
this case, select VHDL. A text editor window will open, where you can write your HDL code. For
our circuit, enter the following code.
library ieee;
use ieee.std logic 1164.all;
entity myLogicCkt is
port (a, b, c, d : in std_logic;
y : out std_logic);
end entity myLogicCkt;
architecture struct of myLogicCkt is
begin
y <= (a and b) or (c and d);
end
end architecture struct;
Notice that the entity name myLogicCkt is kept the same as we had specified while starting the
new project wizard.
10. Save this file (preferably in the same project directory) with any name e.g. circuit1.vhd. The
file name should have a .vhd extension.
11. Go to Processing Start Compilation. This starts the compilation process, and errors in
the code, if any, are shown on the post-compilation report.
12. You need to now assign the port pins of your design (a, b, c, d, y) to I/O pins on the CPLD
to verify the logic function working. For simplicity, we will assign the input lines to the on-board
switches and outputs to on-board LEDs.
13. Go to Assignments Pin Planner. A new window opens up, showing you the schematic
of the device selected (in this case, MAX V), and below, the signal lines that need to be pinassigned. Follow the information in Table 2 to do the pin assignment.Warning: Sometimes the
pin planner window may show the signals TDI, TDO, TMS, TCK. DO NOT assign these to any
pins.
14. Once the pin assignment is complete, compile the design again (i.e. repeat Step 11).

Switch
S1
S2
S3
S4
S5
S6
S7
S8

CPLD Pin No.

48
45
44
43
42
41
40
39

LED
LED1
LED2
LED3
LED4
LED5
LED6
LED7
LED8

CPLD Pin No.

58
57
55
53
52
51
50
49

Table 2: Pin mapping for on-board Switches and LEDs

15. Now go to Tools Programmer. A programmer window will open. You should see the project
output file myLogicCkt.pof in this window. If not, you may need to create a fresh project from
the start.
16. In the programmer window, go to File Generate (JAM, SVF...). A new window will open.
Select the programming file type as Serial Vector Format (SVF). Browse to the directory
where you wish to store the .svf file. Preferably, save it directly in C:\ drive. The filename
need not be the same as the project name. Let us give the name myLogic.svf. Click on
Generate. The programming file is now ready.

Using UrJTAG to program Krypton

UrJTAG is a free software to program devices using the JTAG protocol. UrJTAG uses a virtual JTAG
port on the PC which is usually accessed through the USB port, as in Krypton. Assume that you
have your programming file created from Quartus II, and saved in C:\ as myLogic.svf. Follow the
given instructions to program Krypton with this .svf file.
1. Copy the UrJTAG folder from the support disk to your PC desktop. Open the jtag.exe
executable in the folder. A terminal window with a jtag> prompt opens up.
2. Give the command cable ft2232 and hit enter. If the drivers have been installed, you should
see a message Connected to libftd2xx driver.
3. Now, give the command detect, an hit enter. It should now show you the CPLD (target device)
details as follows.
IR Length: 10
Chain Length: 1
Device ID: 0000001.............
Manufacturer: Altera
.
.
.
.
.
.
jtag>
4. The steps 2-3 need to be followed every time (a) Krypton is connected to your PC and (b) a
new jtag.exe window is opened.

5. The device can now be programmed. Give the command svf c:\myLogic.svf. The jtag>
prompt will disappear for around 40 seconds while the device is being programmed. Once the
prompt returns, it indicates that programming is complete. You may now verify the working of
your logic design on the board (using the switches/LEDs etc.).

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Using Krypton for More Applications

Apart from the on-board switches and LEDs, there are push-buttons and connectors/headers are
provided for connecting commonly used peripherals such as character LCD/graphics LCD/PS2 devices
and also for general-purpose I/O. This section details more about using these features.
1. Using the push-buttons: There are four on-board push-buttons, which are hardware debounced.
When pressed, they are connected to ground (GND), which can be read by the CPLD. The pin
mapping for these switches are in Table 3.
Push-button
UP
DOWN
LEFT
RIGHT

CPLD Pin No.

141
142
143
144

Table 3: Pin mapping for push-buttons

2. Clock sources for Krypton: Krypton has on-board 1Hz and 50MHz clock sources which can be
used independently. Also, you may connect an external clock source to the EXT_CLK header.
Refer Table 4 for the pin mapping.
Clock Source
On-board 1Hz
On-board 50MHz
External clock

CPLD Pin No.

18
20
91

Table 4: Pin mapping for clock sources

3. Using the 26-pin HEADER0, 40-pin HEADER1 and 26-pin HEADER2: Figure 3 shows the numbering
convention for the general purpose I/O headers HEADER0, HEADER1, HEADER2 and the LCD Connector. Tables 5-7 show the pin mapping for these using the same numbering convention and
pattern as in Figure 3.
4. Using the LCD Connector: Krypton has a 20 pin on-board LCD connector that can be used to
interface either a 16 2 character LCD module (most commonly, the JHD162A) or a Graphics
LCD (GLCD) module. Table 8 shows the pin mapping for this connector.
Important: 1. The pin 1 of the LCD/GLCD module should align with the pin 1 in the LCD
connector. Wrong connections may damage the LCD module! 2. Backlight facility is available
only for GLCD and not for character LCD.
5. Using the PS2 Connector: The on-board PS2 connector may be used for direct interfacing to
a PS2 device such as a keyboard or a mouse. PS2 has two communication lines- CLOCK and
DATA. Table 9 shows the pin mapping for the PS2 connector.

(a) HEADER0

(b) HEADER1 and LCD Connector

(c) HEADER2

Figure 3: Pin mapping for general purpose I/O headers

Odd No. Pin
(Pin 1) 1
3
5
7
13
15
21
23
27
29
31
37
GND

Even No. Pin

2
4
6
12
14
16
22
24
28
30
32
38
VDD (5V ) (Pin 26)

Table 5: Pin mapping for HEADER0

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1.

Frequently Asked Questions (FAQs)

From where can I download Quartus II?

Ans: You can visit the following URL to download a free web edition:
https://www.altera.com/download/software/quartus-ii-we
2.

Can I use UrJTAG directly from www.urjtag.org?

Ans: Yes you can, however, the distribution does not have support for MAX V devices. We at ePrayog have created the necessary libraries. Simply use the UrJTAG provided on the e-Prayog
webpage http://59.181.142.81/. UrJTAG allows you to create your own libraries for any
other PLD you wish to use.
3.

I wish to use the USB only for programming, after which I want Krypton to function as a
standalone unit. Is this possible?

Ans: Yes it is! You may use a standard power source such as a battery or a regulated DC power
supply, after the programming is complete. Follow the power settings explained in Section 6.
Take care not to use a supply of below 5V .
8

Even No. Pin

(Pin 40) VDD (5V )
108
107
106
104
102
98
96
94
88
86
84
80
76
74
72
70
68
66
62

Odd No. Pin

GND
105
103
101
97
95
93
89
87
85
81
79
77
75
73
71
69
67
63
59 (Pin 1)

Table 6: Pin mapping for HEADER1

Odd No. Pin
Even No. Pin

GND
5V (Pin 26)

133
139

131
138

129
134

127
132

125
130

123
124

121
122

119
120

117
118

113
114

111
112

109 (Pin 1)
110

Table 7: Pin mapping for HEADER2

4.

Suppose Krypton is currently configured to synthesize a particular logic function. Can this
setting be erased somehow?

Ans: No. There is no direct concept of erasing a CPLD. You will notice that even if Krypton is
powered off, it will run the last programmed configuration the next time it is powered on. This
continues for the rest of its life, unless you program it for some other logic function.
5.

Can I simulate my design before implementing it?

Ans: Yes. Quartus II supports the use of third-party simulators such as ModelSIM. If you wish to
simulate, specify the simulator while creating the project, in Page 4 as explained in Section
8. Once you compile your design, you can invoke the simulator by going to Tools Run
Simulation Tool Gate Level Simulation. Alteras ModelSIM web edition may be downloaded from https://www.altera.com/download/software/modelsim-starter
Use of a simulation tool is recommended for large and complex designs.
6.

What system requirements do I need to get my PC working with Krypton?

Ans: You need a minimum of Windows XP (Service Pack 2 or higher) with enough disk space to
install Quartus II.
7.

In the UrJTAG folder, the jtag.exe shows an error while opening/fails to open. What could be
the problem?

Ans: Use the UrJTAG provided on the e-Prayog webpage. This problem will not occur.

Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

CPLD Pin No.

GND
+5V

70
72
74
76
80
84
86
88
94
96
98
102
104
106

+5V
GND

GLCD Functional Pin

GND
VDD
V0
RS

R/W
EN
D0
D1
D2
D3
D4
D5
D6
D7
CS1
CS2
RESET
Vout
LED+
LED-

Table 8: Pin mapping for LCD Connector

PS2 Pin Name
CLOCK
DATA

CPLD Pin No.

139
140

Table 9: Pin mapping for PS2 Connector

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Help and Support

You are welcome to contact the Reconfigurable Hardware Design Team at e-Prayog, IIT Bombay to
report software bugs, hardware failures/ other issues, and help and information in application developments. Suggestions regarding mistakes in the manual and other documentation/ distributables are
welcome. Various queries and hate mail are also welcome.
Send an e-mail to cpld.wel@gmail.com
For administrative queries, e-mail to vlabs_wel@ee.iitb.ac.in

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