ure M.

PERII1, Aleksandar ORI1, Slobodan OBRADOVI1, Petar SPALEVI2

Slobomir P University-Bosnia and Herzegovina (1), University of Pritina-Serbia (2)

Application of Frequency Locked Loop in Consumption Peak

Load Control
Abstract. This article describes the application of the Frequency Locked Loop (FLL) in the Consumption Peak Load Control (PLC). The digital
content of FLL represents the main information for optimal control. Particular significance was given to the description of the extended FLL, which is
suitable for this application. Detailed solutions of FLL input module and FLL adjustments are given. The performances of the realized PLC System
are demonstrated by the graphics, which are recorded on the applied PLC System.
Streszczenie. W tym artykule opisano zastosowanie Frequency Locked Loop (FLL) do sterowania obcieniem szczytowym Peak Load Control
(PLC). Szczeglne znaczenie nadano opisowi rozszerzonego FLL, ktry jest odpowiedni dla tej aplikacji. Podano szczegowe rozwizania w
module FLL wejciowych i korekt FLL . PLC. (Zastosowanie Frequency Locked Loop w kontroli zuycia obcienia szczytowego).

Keywords: Frequency Locked Loop, Frequency Synthesizer, Electricity Peak Load, Consumption Control.
Sowa kluczowe: FLL ptla czstotliwociowa, synteza czstotliwoci,.

Introduction
Generally, Phase Locked Loop (PLL) and Frequency
Locked Loop (FLL) systems, if they are in the stable states,
generate the output signals whose frequencies are the
same to their input signal frequencies. However, there is the
difference between them. The PLL input and output signals
are, at the same time, in phase. That is not case with FLL
input and output signals. In many applications in the field of
control, measurement and telecommunication, the
frequency appears as the only signal parameter, which
carries information, so that it is not necessary to care about
the phase difference between input and output. In such
applications, in comparison with the PLL, the FLL is more
suitable for usage.
In this article, an application of the FLL for the
development of a consumption peak load control (PLC) is
described. This FLL, described in [2], possesses powerful
ability to average the periods of non uniform pulse rate, fed
at the input. This FLL is used for addition and/or subtraction
of unlimited number of non uniform pulse rate frequencies.
Any number of pulses per second might be add or subtract
at the inputs of FLL, to match synthesized frequency of the
output pulse rate. However, the FLL will still generate
uniform pulse rate at the output, no mater what level of
irregularities exists in the input signals periods.
The approach to Peak Load Control (PLC), based on
the FLL [2], offers the optimal, but simple and natural way of
peak load control for all kind of large consumers, regardless
of the consumption in a factory, the technological process,
organization of production, the variability of the used current
power, the size of the space and position of the factory and
regardless of the other parameters that might have
influence on the peak load control.
In practice, very large losses of electricity exist due to
excess of consumption, which appears as variable peak
load for large electricity customers and for citizens in wide
consumption. PLC systems for large electricity customers
was very complex in practice, because of the very wide
variety of large customers and a number of parameters that
might have influence. Therefore, the general solution, which
would be applicable in all cases, must be adaptable to all
kind of customers. Such a solution should provide a high
degree of flexibility in operation, so that an operator can,
using his experience and creativity, step by step, reprogram
factory settings in order to stabilize and minimize peak load,
but without to disturb technological process or work
productivity of that factory.

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The approach described in this paper is applied in the

project "Expert system for peak load control, within the
national projects of the Ministry of Science and Technology
of the Republic of Serbia.
The described algorithm was created through years of
experience and contributions in the field of rational energy
consumption and other results in the field of electronics and
control, as well as in the field of PLL and FLL applications.
Ref. [1-2] are used for the basic concept, ref. [3-4] are
closely related to this work. Ref. [5-8] are used in the
realization of interface between PC and electronic block, in
electronics implementation and software support.

Fig. 1 Organization of the extended FLL

Organization of the extended FLL

The FLL, described in [2], is extended, as shown in Fig.
1. It contains UP-DOWN counter (accumulator), then
electronic block with decoders of accumulator contents,
logics and control signal generators, which altogether are to
control processes P1 to PN, according to the requirements of
a system where the extended FLL (EFLL) is applied. The
affection of any process P1 to PN is added or subtracted and
convert to pulse rate, which is fed to input DOWN. The
frequency of this pulse rate carries information about
controlled or measured physical parameter. On the other
side, pulse rate from the reference function generator,
whose frequency might be any kind of function in time, is
fed to the input UP. The third input is parallel one, which
represents the initial value of accumulator ACC0. The initial
value ACC0 is to be entered to accumulator usually at the
beginning of the control process, but it may be entered at
any time, if it is necessary. In some applications, ACC0

PRZEGLD ELEKTROTECHNICZNY (Electrical Review), ISSN 0033-2097, R. 88 NR 1b/2012

might be used as very useful and powerful control

parameter.
The extended FLL, shown in Fig. 1, represents general
model, which is more suitable for wide range of applications
in comparison with FLL, described in [2]. The output pulse
rate of extended FLL is not generated at the output, like in
case of FLL, described in [2]. Instead of that, the current
accumulator content is continuously decoded, and
according to the content state, generated control signal are
used to affect to the processes at the input, leading so
control to the desired direction. Classical PLL and FLL, in
most of their applications, are to be in the transient mode as
short as possible. In comparison with them, the stable state
of extended FLL might be rather short, because it works in
transient mode all the time, while reducing the error to zero.
The extended FLL is in the stable state, providing that the
frequencies of pulse rates, which are fed to inputs DOWN

and UP, are equal. It should be noticed that the current

accumulator content, in the mathematical sense, represents
the time integral of the difference between two pulse rates
frequencies, added to ACC0.
The PLC system based on the extended FLL
It was emphasized that, in FLL and many electronic
applications, pulse rate frequency may carry information
about any physical parameter, which is to be controlled or
measured. In the extended FLL, which is applied in PLC
system, pulse rate frequency represents information about
the power consumption. Every pulse in the PLC system
corresponds, automatically, to the constant amount of
consumed electricity energy.
The organization of the PLC system, based on the
extended FLL, is shown in Fig. 2. The principles of the

Fig. 2. The PLC System: installation of photo sensor in MAX is under control of the laboratory of Electrical Distribution; checking
functions and verifications of extended MAX makes Republican Bureau for Measures.

extended FLL, Fig. 1, are completely incorporated into the

PLC system in Fig. 2. UP-DOWN counter (ACC) is
represented as a part of electronic block in Fig. 2.
Processes P1 to PN are consumers C1 to CN. Addition
of consumption C1 to CN, is realized by device MAX
(Maxigraf measures the average consumption power during
15 minutes and, at the same time, the all energy consumed
in the factory).
Two photo sensors are built in MAX to convert, in real
time, current power consumption to pulse rate frequency of
Sp.
The reference function generator from Fig. 1, is
changed by the binary programmable generator with crystal
oscillator frequency of 32 768 Hz, in Fig. 2.
The programmable generator generates pulse rate
Smin, whose frequency corresponds to the minimum
consumption power of a factory. This minimal power
consumption is achieved when all consumers are switched
off, whose short exclusion will not disrupt the process of
technological work. The consumption which corresponds to
frequency of Smin, will appear as the main criterion curve of
the factory on the graphics, later on, in Figs 6 and 7.
The next important parameter, which is used for
consumption control is the initial content off FLL
accumulator Eo. It appears physically as energy in Fig. 2,
instead of ACC0 in Fig.1. Device MAX is synchronized (this
is not shown in Fig.2) by pulse rate S15 form MTK receiver.
The period of S15 is 15 minutes. MTK receiver is device,
controlled from a distance center. All the system is

the

synchronized by signal S15, including electronic block, PC

computer and programmable generator.
The FLL accumulator content is entered to PC, using
communication interface between electronic block and PC
computer. PC computer serves in this PLC system for the
graphics presentations of current parameters and energy
states of the factory as well as for the prediction of the
consumption power (MAX value) at the end of the 15minutes time period. At any time, this is used for the
decision in electronic block, if action of switching is
necessary. The prediction makes software packet, which
will appear as Eprogres on the graphics, later on, in Fig. 7.
At last, PC computer is used as base of data, which enable
to show daily, monthly and yearly presentation of different
energy parameters.
Switching and sound line brings serial coded signals.
They are used for switching consumers C1 to CN and to
inform all the participants about energy state in the factory.
The input module of Extended FLL
The general scheme of the input module of extended
FLL, applied in PLC system, is shown in Fig. 2. The
accumulator, in Fig. 2, is 16 bit UP-DOWN counter,
consisting of four 4-bit binary UP-DOWN counter CD
40193. It is of practical interest to consider the solution for
the input module of extended FLL, because of two reasons.
The first one is the fact that UP-DOWN counters, as well as
the other integrated circuits with two counting inputs, are
not allowed to accept counting pulses in both inputs UP and
DOWN simultaneously. The second one is the need to
consider how to apply the extended FLL in some other

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265

applications. In such ones, it may be necessary to add or to

subtract more pulse rates, in case that they are not added
like in case of PLC system, where device MAX performs
this function. The addition of two or more pulse rates, can
not be performed by the logic circuits only. Actually, before
addition by the logic circuits, it is necessary to disable the
appearance of any two pulses simultaneously. At the same
time, these pulses carry information, and they must not be
lost. They should be only separated in time, i.e. desynchronized.
For the purpose of de-synchronization of any two
simultaneous pulses in pulse rates Sp and Smin, Fig. 2, desynchronizers D1 and D2 and clock pulse rates CL1 and
CL2 are used. The frequencies of pulse rates CL1 and CL2
are equal, i.e. 512 Hz, but they are phase-shifted by 180
degrees. It is very easy to get CL1 and CL2 by pulse rate
CL0 from the programmable generator, whose frequency is
1024 Hz. This solution is shown in Fig. 3. It consists of one
flip-flop, which acts as divider by two, and two AND logic
circuits. Time relation between CL0, CL1 and CL2 may be
seen in timing diagram, Fig.5.

Fig. 5. Timing diagram for the signals shown in Figs. 3 and 4

The scheme of the de-synchronizer D2 is completely the

same like that one shown in Fig.3. The only deference is
that module D2 serves to generate Smind instead of Smin
and that for this purpose uses CL2 instead of CL1. That
means every pulse in Smin will be changed in Smind with
the first next pulse in CL2. Due to this fact, pulses in Spd
and Smind can never occur simultaneously.
It is of interest to notice that, for some other applications,
the described approach might be extended to any number of
pulse rates, which are to be added. For this purpose, it
would be necessary to extract, as many phase-shifted clock
pulse rates as there are pulse rates for addition.

Fig. 3 Generation of clock pulse rates CL1 and CL2

Fig. 4. Detailed scheme of de-synchronizer D1

Detailed scheme of de-synchronizer D1 is shown in Fig.

4. Timing diagrams, for all signals shown in Fig. 4, are
presented in Fig. 5. The de-synchronizer D1, using clock
pulse rate CL1, generates pulse rate Spd instead of Sp.
Allpulses in Sp are shifted in time. Actually, pulse a from
CL1, is extracted instead of pulse number 1 in Sp, Fig. 5. In
the same way, pulse number 2 in Sp is changed by pulse
c from CL1. It should be noted that every pulse in Sp is
changed with the first next pulse in CL1. It is obvious, that
the frequency of pulse rate CL1 must be grater than the
maximum frequency of pulse rate Sp, which could appear in
one factory. In the practical solution of PLC system, the
frequency of CL1 is 512 Hz and that is much grater than the
maximum frequency of pulse rate Sp, which is in practice
about 3 Hz. This frequency depends on the resolution,
which one would use in measuring of the total power
consumption, but the frequency of 3 Hz, provides
acceptable resolution for the purpose of the consumption
peak load control.

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Fig. 6. The basic functioning principle of PLC System

Brief graphic presentation on the realized PLC System

The basic functioning principle of PLC System is
demonstrated in Fig. 6. This figure is generated on the PC
monitor. The main and the other criterion curves (altogether
nine) are fixed for one factory and they are drown using
manually entered data into PC, like E0 and the frequency of
Smin. Total consumption of a factory is drown in real time,
using data from the electronic block. The maximum
ofenergy which is not to be exceeded in the factory, during
15 min, is Emax. It depends on E0 and frequency of Smin.
Detection field is defined by criterion curves. Whenever total
consumption curve reaches any of the criterion curves,
providing that total consumption would exceed Emax at the
end of 15 min time, electronic block would switched of some
of consumers. At last, if the previous switching of is not
sufficient, the total consumption curve will reach the main
criterion curve and the rest of consumers will be switched of.

PRZEGLD ELEKTROTECHNICZNY (Electrical Review), ISSN 0033-2097, R. 88 NR 1b/2012

If all consumers, whose exclusion does not disrupt

production, are switched of, the total consumption curve will
follow the main criterion curve and the consumed energy of
a factory will be exactly at planed Emax, at the end of 15

min time. The distance between the criterion curves and E0,
may be chosen according to the control needs. The real
time graphic presentation on the realized PLC system is
shown in Fig. 7. In addition to the parameters

Fig. 7. The real time graphic presentation of the current MAX and total power consumption on the realized PLC System

shown in Fig. 6, the effect of software packet Eprogres may

be seen in Fig. 7. Eprogres shows that, providing total
consumption keeps intensity which has at the beginning, the
total consumption will exceed Emax at the end of 15 min
time. The current power consumption is shown on the left
side. It corresponds to the current total consumption.
Conclusion
The described extended FLL, due to decoding of digital
state inside of FLL and ability to control its content by many
outside pulse rates and by preset of the whole FLL content,
is suitable for development of many different applications in
the field of control, measurement and telecommunication.
The approach to PLC system, based on the extended
FLL, offers the optimal, but simple and natural way of peak
load control for all kind of consumers. It was successfully
applied in practice regardless of the amount of consumption,
the technological process, the organization of production,
the variability of the used current power, the size and
position of the factory and regardless of the other
parameters that might have influence on the peak load. It
enables change of priority of every consumer in the function
of the technological process, monthly or seasonal
reprogramming of the system, visual, sound, current and
long-term monitoring (daily, monthly, annual) of the factory
consumption and the other benefits.

REFERENCES
[1] Dj. M. Perisic, A new approach to discrete phase locked-loop
based on the digital measurement of time intervals, Electronics
Letters, vol. 15, 1979, P. 445-446.
[2] Dj. M. Perisic, Digital Frequency Subtractor and/or Adder
based on a version of a Hybrid Frequency-Locked Loop,
Electronics Letters, vol. 17, 1981, P. 28-29.
[3] A. M. Raievi, B. M. Popovi, PLL as the Frequency
Synthesizer with Continuous Phase Divider, Electronics and
Electrical Engineering, Kaunas: Technologija, 2009, No. 5(93),
P. 4750.
[4] Dj. M. Perisic, A. Zoric, S. Obradovic, Peak Control System for
Large Consumers, International Scientific Conference-Unitech
10, Gabrovo, ISSN 1313-230x, P. -45 -48.
[5] William F. Egan, Frequency Synthesis by Phase Lock, John
Wiley and Sons, Inc., 2002, P. 593.
[6] Roland E. Best, Phase Locked Loops, Mc Graw Hill, ISBN 007-141201-8, 2003, P. 421.
[7] A. Agarwal, J. Lang, Foundation of Analog and Digital
Elektronic Circuit, Denise E. M. Penrose, San Francisko, USA,
2005, P. 984.
[8] M. Contu, Delphi 2010, Handbook, Winteh Italia, Srl, Italy,
2010, P. 318.
Authors: prof. dr in. ure Perii, Faculty of Information
Technologies, str. Pavlovia put bb. 76300 Slobomir, Bosnia and
Herzegovina, E-mail: djurdje@beotel.rs ; prof. dr in. Aleksandar .
ori, Faculty of Information Technologies, str. Pavlovia put bb.
76300
Slobomir,
Bosnia
and
Herzegovina,
E-mail:
acazoric@yahoo.com; prof. dr in. Slobodan Obradovi, Faculty of
Information Technologies, str. Pavlovia put bb. 76300 Slobomir,
Bosnia and Herzegovina, E-mail: slobo.obradovic@gmail.com; prof.
dr in. Petar Spalevi, Faculty of Technical Sciences, str. Knjaza
Miloa
7,
38220
K.
Mitrovica,
Serbia,
E-mail:
petar.spalevic@yahoo.com;

PRZEGLD ELEKTROTECHNICZNY (Electrical Review), ISSN 0033-2097, R. 88 NR 1b/2012

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