DRV 8811

DRV8811
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SLVS865H SEPTEMBER 2008 REVISED NOVEMBER 2013
STEPPER MOTOR CONTROLLER IC

Check for Samples: DRV8811
FEATURES
Pulse Width Modulation (PWM) Microstepping

Motor Driver
Built-In Microstepping Indexer
Up to 1.9-A Current Per Winding
Three-Bit Winding Current Control Allows
up to Eight Current Levels
Low MOSFET On-Resistance
8-V to 38-V Operating Supply Voltage Range
Thermally Enhanced Surface Mount Package
APPLICATIONS
Printers
Scanners
Office Automation Machines
Gaming Machines
Factory Automation
Robotics
DESCRIPTION/ORDERING INFORMATION
The DRV8811 provides an integrated stepper motor driver solution for printers, scanners, and other automated
equipment applications. The device has two H-bridge drivers, as well as microstepping indexer logic to control a
stepper motor.
The output driver block for each consists of N-channel power MOSFETs configured as full H-bridges to drive the
motor windings.
A simple step/direction interface allows easy interfacing to controller circuits. Pins allow configuration of the
motor in full-step, half-step, quarter-step, or eighth-step modes. Decay mode and PWM off time are
programmable.
Internal shutdown functions are provided for over current protection, short circuit protection, under-voltage
lockout and overtemperature.
The DRV8811 is packaged in a PowerPAD 28-pin HTSSOP package with thermal pad (Eco-friendly: RoHS
and no Sb/Br).
ORDERING INFORMATION (1)
TA
40C to 85C
(1)
(2)
PACKAGE (2)
PowerPAD (HTSSOP) PWP
ORDERABLE PART NUMBER

Reel of 2000
Tube of 50
DRV8811PWPR
DRV8811PWP
TOP-SIDE MARKING
DRV8811
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright 20082013, Texas Instruments Incorporated
DRV8811
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FUNCTIONAL BLOCK DIAGRAM
VM
VCC
CP1
Internal VCC
VCC
0.22 F
Internal
VGD
Reference
Charge
CP2
Internal Ref
VM
Pump
and
VCC
LS Gate
Drive
Regulator
VCP
Thermal
0.22 F
Shut down
HS Gate
VM
Drive
VMA
VREF
ENABLEn
AOUT1
+
SLEEPn
STEP
Motor
Step
Driver A
Motor
AOUT2
DIR
Indexer /
USM0
ISENA
Control
Logic
USM1
VCC
RESETn
SRn
VM
VMB
HOMEn
DECAY
BOUT1
RCA
Motor
Driver B
RCB
BOUT2
ISENB
GND
GND
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Product Folder Links: DRV8811
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TERMINAL FUNCTIONS
NO.
I/O (1)
GND
7, 21
Device ground
VMA
28
Bridge A power supply
VMB
15
Bridge B power supply
VCC
10
Logic supply voltage
Connect to 3-V to 5-V logic supply. Bypass to GND with a 0.1-F

ceramic capacitor
CP1
23
IO
Charge pump flying capacitor
Connect a 0.22-F capacitor between CP1 and CP2
CP2
24
IO
Charge pump flying capacitor
Connect a 0.22-F capacitor between CP1 and CP2
VCP
22
IO
High-side gate drive voltage
Connect a 0.22-F ceramic capacitor to VM
VGD
20
IO
Low-side gate drive voltage
Bypass to GND with a 0.22-F ceramic capacitor
ENABLEn
26
Enable input
Logic high to disable device outputs, logic low to enable outputs
SLEEPn
27
Sleep mode input
Logic high to enable device, logic low to enter low-power sleep mode
DECAY
Decay mode select
Voltage applied sets decay mode - see motor driver description for
details. Bypass to GND with a 0.1-F ceramic capacitor
STEP
19
Step input
Rising edge causes the indexer to move one step
DIR
Direction input
Level sets the direction of stepping
USM0
13
Microstep mode 0
USM0 and USM1 set the step mode - full step, half step, quarter
step, or eight microsteps/step
USM1
12
Microstep mode 1
USM0 and USM1 set the step mode - full step, half step, quarter
step, or eight microsteps/step
RESETn
17
Reset input
Active-low reset input initializes the indexer logic and disables the Hbridge outputs
SRn
16
Sync. Rect. enable input
Active-low. When low, synchronous rectification is enabled. Weak

internal pulldown.
VREF
Current set reference input
Reference voltage for winding current set
RCA
Bridge A blanking and off time adjust
Connect a parallel resistor and capacitor to GND - see motor driver

description for details
RCB
Bridge B blanking and off time adjust
Connect a parallel resistor and capacitor to GND - see motor driver

description for details
ISENA
Bridge A ground / Isense
Connect to current sense resistor for bridge A
ISENB
14
Bridge B ground / Isense
NAME
DESCRIPTION
EXTERNAL COMPONENTS OR CONNECTIONS

POWER AND GROUND
Connect to motor supply (8 V to 38 V). Both VMA and VMB must be
connected to same supply.
CONTROL
Connect to current sense resistor for bridge B

OUTPUTS
AOUT1
Bridge A output 1
Connect to bipolar stepper motor winding A
AOUT2
25
Bridge A output 2
Positive current is AOUT1 AOUT2
BOUT1
11
Bridge B output 1
Connect to bipolar stepper motor winding B
BOUT2
18
Bridge B output 2
Positive current is BOUT1 BOUT2
HOMEn
Home position
Logic low when at home state of step table, logic high at other states
(1)
Directions: I = input, O = output, OZ = 3-state output, OD = open-drain output, IO = input/output
DRV8811
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PWP (HTSSOP) PACKAGE
ISENA
HOME
DIR
AOUT1
DECAY
RCA
GND
VREF
RCB
VCC
BOUT1
USM1
USM0
ISENB
ABSOLUTE MAXIMUM RATINGS (1)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
GND
(PPAD)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VMA
SLEEPn
ENABLEn
AOUT2
CP2
CP1
VCP
GND
VGD
STEP
BOUT2
RESETn
SRn
VMB
(2) (3)
over operating free-air temperature range (unless otherwise noted)

MIN
MAX
UNIT
VMX
Power supply voltage range
0.3
40
VCC
Power supply voltage range
0.3
Digital pin voltage range
0.5
0.3 V
VCC
0.3
0.5
VREF
Input voltage range

ISENSEx pin voltage range
IO(peak)
Peak motor drive output current, t < 1 s
PD
Continuous total power dissipation
TJ
Operating virtual junction temperature range
40
150
TA
Operating ambient temperature range
40
85
Tstg
Storage temperature range
60
150
(1)
(2)
(3)
Internally limited
See Dissipation Ratings table
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolutemaximumrated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
Power dissipation and thermal limits must be observed.
DISSIPATION RATINGS
BOARD
PACKAGE
R JA
DERATING
FACTOR
ABOVE TA = 25C
TA < 25C
TA = 70C
TA = 85C
Low-K (1)
PWP
67.5 C/W
14.8 mW/C
1.85 W
1.18 W
0.96 W
(2)
PWP
39.5 C/W
25.3 mW/C
3.16 W
2.02 W
1.64 W
High-K (3)
PWP
33.5 C/W
29.8 mW/C
3.73 W
2.38 W
1.94 W
High-K (4)
PWP
28 C/W
35.7 mW/C
4.46 W
2.85 W
2.32 W
Low-K
(1)
(2)
(3)
(4)
The JEDEC Low-K board used to derive this data was a 76 mm x 114 mm, 2-layer, 1.6 mm thick PCB with no backside copper.
The JEDEC Low-K board used to derive this data was a 76 mm x 114 mm, 2-layer, 1.6 mm thick PCB with 25 cm2 2-oz copper on
backside.
The JEDEC High-K board used to derive this data was a 76 mm x 114 mm, 4-layer, 1.6 mm thick PCB with no backside copper and
solid 1 oz. internal ground plane.
The JEDEC High-K board used to derive this data was a 76 mm x 114 mm, 4-layer, 1.6 mm thick PCB with 25 cm2 1-oz copper on
backside and solid 1 oz. internal ground plane.
DRV8811
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RECOMMENDED OPERATING CONDITIONS

MIN
VM
Motor power supply voltage range
VCC
Logic power supply voltage range
VREF
VREF input voltage
(1)
(1)
NOM
MAX
UNIT
38
5.5
VCC
All VM pins must be connected to the same supply voltage.
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ELECTRICAL CHARACTERISTICS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Power Supplies
IVM
VM operating supply current
VM = 35 V, fPWM < 50 KHz
4.5
mA
IVCC
VCC operating supply current
fPWM < 50 KHz
0.4
mA
IVMQ
VM sleep mode supply current
VM = 35 V
12
20
IVCCQ
VCC sleep mode supply current
20
VM undervoltage lockout voltage
VM rising
6.7
VCC undervoltage lockout voltage
VCC rising
2.71
2.95
VUVLO
VREF Input/Current Control Accuracy

IREF
VREF input current
ICHOP
Chopping current accuracy
VREF = 3.3 V
VREF = 2.0 V, 70% to 100% current
VREF = 2.0 V, 20% to 56% current
10
10
0.3 VCC
Logic-Level Inputs
VIL
Input low voltage
VIH
Input high voltage
IIL
Input low current
VIN = 0.3 VCC
20
20
IIH
Input high current
VIN = 0.3 VCC
20
20
RPU
Pullup resistance
ENABLEn, RESETn
RPD
Pulldown resistance
DIR, STEP, SLEEPn, USM1, USM0, SRn
0.7 VCC
V
A
A
HOMEn Output
VOL
Output low voltage
IO = 200 A
VOH
Output high voltage
IO = 200 A
0.3 VCC
0.7 VCC
V
V
Decay Input
VIL
Input low threshold voltage
For fast decay mode
VIH
Input high threshold voltage
For slow decay mode
0.21
VCC
0.6 VCC
H-Bridge FETS
Rds(on)
HS FET on resistance
Rds(on)
LS FET on resistance
VM = 24 V, IO = 2.5 A, TJ = 25C
0.50
VM = 24 V, IO = 2.5 A, TJ = 85C
0.60
VM = 24 V, IO = 2.5 A, TJ = 25C
0.50
VM = 24 V, IO = 2.5 A, TJ = 85C
0.60
IOFF
20
0.75
0.75
20
Motor Driver
tOFF
Off time
Rx = 56 k, Cx = 680 pF
30
38
46
tBLANK
Current sense blanking time
Rx = 56 k, Cx = 680 pF
700
950
1200
ns
SRn = 0
100
475
800
ns
2.5
4.5
6.5
150
160
180
tDT
Dead time
(1)
Protection Circuits
IOCP
tTSD
(1)
Overcurrent protection trip level

Thermal shutdown temperature
(1)
Die temperature
Not tested in production - guaranteed by design.
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TIMING REQUIREMENTS
PARAMETER
MIN MAX UNIT
fSTEP
Step frequency
tWH(STEP)
Pulse duration, STEP high
500
kHz
s
tWL(STEP)
Pulse duration, STEP low
tSU(STEP)
Setup time, command before STEP rising
200
ns
tH(STEP)
Hold time, command after STEP rising
200
tWAKE
Wakeup time, SLEEPn inactive high to STEP input accepted
ms
tSLEEP
Sleep time, SLEEPn active low to outputs disabled
tENABLE
Enable time, ENABLEn inactive high to outputs enabled
20
tDISABLE
Disable time, ENABLEn active low to outputs disabled
20
ns
10 tRESETR
Reset release time, RESETn inactive high to outputs enabled
11 tRESET
Reset time, RESETn active low to outputs disabled
1
2
STEP
DIR, USMx
6
SLEEPn, ENABLEn, RESETn
8
10
7
9
11
OUTPUT
DRV8811
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FUNCTIONAL DESCRIPTION
PWM H-Bridge Drivers
DRV8811 contains two H-bridge motor drivers with current-control PWM circuitry, and a microstepping indexer. A
block diagram of the motor control circuitry is shown below.
VM
OCP
VGD
VMA
VCP
AOUT1
+
RCA
Predrive
Step
Motor
AOUT2
PWM
OCP
ISENA
A=8
DAC
OCP
VGD
VCP
Control /
Indexer
Logic
VM
VMB
BOUT1
Predrive
BOUT2
PWM
OCP
ISENB
A=8
DAC
RCB
DECAY
VREF
Figure 1. Block Diagram
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Current Regulation
The PWM chopping current is set by a comparator, which compares the voltage across a current sense resistor,
multiplied by a factor of 8, with a reference voltage. The reference voltage is input from the VREF pin. The fullscale (100%) chopping current is calculated as follows:
ICHOP =
VREFX
8 RISENSE
(1)
Example:
If a 0.22- sense resistor is used and the VREFx pin is 3.3 V, the full-scale (100%) chopping current is
3.3 V/(8 * 0.22 ) = 1.875 A.
The reference voltage is also scaled by an internal DAC that allows torque control for fractional stepping of a
bipolar stepper motor, as described in the "Microstepping Indexer" section below.
When a winding is activated, the current through it rises until it reaches the chopping current threshold described
above, then the current is switched off for a fixed off time. The off time is determined by the values of a resistor
and capacitor connected to the RCA (for bridge A) and RCB (for bridge B) pins. The off time is approximated by:
tOFF = R C
(2)
To avoid falsely tripping on transient currents when the winding is first activated, a blanking period is used
immediately after turning on the FETs, during which the state of the current sense comparator is ignored. The
blanking time is determined by the value of the capacitor connected to the RCx pin and is approximated by:
tBLANK = 1400 C
(3)
Decay Mode
During PWM current chopping, the H-bridge is enabled to drive through the motor winding until the PWM current
chopping threshold is reached. This is shown in Figure 2, Item 1. The current flow direction shown indicates
positive current flow in the step table below.
Once the chopping current threshold is reached, the H-bridge can operate in two different states, fast decay or
slow decay.
In fast decay mode, once the PWM chopping current level has been reached, the H-bridge reverses state to
allow winding current to flow in a reverse direction. If synchronous rectification is enabled (SRn pin logic low), the
opposite FETs are turned on; as the winding current approaches zero, the bridge is disabled to prevent any
reverse current flow. If SRn is high, current is recirculated through the body diodes, or through external Schottky
diodes. Fast-decay mode is shown in Figure 2, Item 2.
In slow-decay mode, winding current is re-circulated by enabling both of the low-side FETs in the bridge. This is
shown in Figure 2, Item 3.
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VM
1 Drive current
1
xOUT2
xOUT1
3
Fast decay (reverse)
Slow decay (brake)
Figure 2. Decay Mode

The DRV8811 also supports a mixed decay mode. Mixed decay mode begins as fast decay, but after a period of
time switches to slow decay mode for the remainder of the fixed off time.
Fast and mixed decay modes are only active if the current through the winding is decreasing; if the current is
increasing, then slow decay is always used.
Which decay mode is used is selected by the voltage on the DECAY pin. If the voltage is greater than 0.6 x VCC,
slow decay mode is always used. If DECAY is less than 0.21 x VCC, the device operates in fast decay mode
when the current through the winding is decreasing. If the voltage is between these levels, mixed decay mode is
enabled.
In mixed decay mode, the voltage on the DECAY pin sets the point in the cycle that the change to slow decay
mode occurs. This time can be approximated by:
0.6 VCC
tFD = R C In
VDECAY
(4)
Operation of the blanking, fixed off time, and mixed decay mode is illustrated in Figure 3.
10
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PWM
ON
PWM
OFF
ON
ITRIP
ON
0.6 VCC
(tOFF)
PWM_ON
ITRIP
VBLANK
BLANK
RCx
Winding
Current
PWM
R
0.6
VBLANK
RCx
VCC
VCC
PWM_OFF
0.21 VCC
VDECAY
Voltage
0.21 VCC
FAST
BLANK
(tFD)
SLOW
FAST_DECAY
DECAY
DECAY
To other PWM
Figure 3. PWM
Microstepping Indexer
Built-in indexer logic in the DRV8811 allows a number of different stepping configurations. The USM1 and USM0
pins are used to configure the stepping format as shown in the table below:
USM1
USM0
Full step (2-phase excitation)
STEP MODE
1/2 step (1-2 phase excitation)
1/4 step (W1-2 phase excitation)
Eight microsteps/steps
The following table shows the relative current and step directions for different settings of USM1 and USM0. At
each rising edge of the STEP input, the indexer travels to the next state in the table. The direction is shown with
the DIR pin high; if the DIR pin is low the sequence is reversed. Positive current is defined as xOUT1 = positive
with respect to xOUT2.
Note that the home state is 45 degrees. This state is entered at power-up or device reset. The HOMEn output
pin is driven low in this state. In all other states it is driven logic high.
11
DRV8811
FULL STEP
USM = 00
1/4 STEP
USM = 10
1/8 STEP
USM = 11
100
98
20
11.325
92
38
22.5
83
56
33.75
71
71
45 (home state)
56
83
56.25
38
92
67.5
20
98
78.75
3
4
5
6
7
8
9
10
11
12
13
14
AOUTx
BOUTx
CURRENT
CURRENT
(% FULL-SCALE) (% FULL-SCALE)
1/2 STEP
USM = 01
2
1
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15
16
STEP ANGLE
(DEGREES)
100
90
10
20
98
101.25
11
38
92
112.5
12
56
83
123.75
13
71
71
135
14
83
56
146.25
15
92
38
157.5
16
98
20
168.75
17
100
180
18
98
20
191.25
19
92
38
202.5
20
83
56
213.75
21
71
71
225
22
56
83
236.25
23
38
92
247.5
24
20
98
258.75
25
100
270
26
20
98
281.25
27
38
92
292.5
28
56
83
303.75
29
71
71
315
30
83
56
326.25
31
92
38
337.5
32
98
20
348.75
RESETn, ENABLEn and SLEEPn Operation

The RESETn pin, when driven active low, resets the step table to the home position. It also disables the H-bridge
drivers. The STEP input is ignored while RESETn is active.
The ENABLEn pin is used to control the output drivers. When ENABLEn is low, the output H-bridges are
enabled. When ENABLEn is high, the H-bridges are disabled and the outputs are in a high-impedance state.
Note that when ENABLEn is high, the input pins and control logic, including the indexer (STEP and DIR pins) are
still functional.
The SLEEPn pin is used to put the device into a low power state. If SLEEPn is low, the H-bridges are disabled,
the gate drive charge pump is stopped, and all internal clocks are stopped. In this state all inputs are ignored
until the SLEEPn pin returns high.
12
DRV8811
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Protection Circuits
Overcurrent Protection (OCP)
If the current through any FET exceeds the preset overcurrent threshold, all FETs in the H-bridge will be disabled
until the ENABLEn pin has been brought inactive high and then back low, or power is removed and re-applied.
Overcurrent conditions are sensed in both directions; i.e., a short to ground, supply, or across the motor winding
will all result in an overcurrent shutdown.
Note that overcurrent protection does not use the current sense circuitry used for PWM current control and is
independent of the Isense resistor value or VREF voltage. Additionally, in the case of an overcurrent event, the
microstepping indexer will be reset to the home state.
Thermal Shutdown (TSD)
If the die temperature exceeds safe limits, all drivers in the device are shut down and the indexer is reset to the
home state. Once the die temperature has fallen to a safe level operation resumes.
Undervoltage Lockout (UVLO)
If at any time the voltage on the VM pins falls below the undervoltage lockout threshold voltage, all circuitry in the
device is disabled and the indexer is reset to the home state. Operation resumes when VM rises above the
UVLO threshold.
13
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THERMAL INFORMATION
Thermal Protection
The DRV8811 has thermal shutdown (TSD) as described above. If the die temperature exceeds approximately
150C, the device will be disabled until the temperature drops to a safe level.
Any tendency of the device to enter thermal shutdown is an indication of either excessive power dissipation,
insufficient heatsinking, or too high an ambient temperature.
Power Dissipation
Power dissipation in the DRV8811 is dominated by the power dissipated in the output FET resistance, or RDS(ON).
Average power dissipation when running a stepper motor can be roughly estimated by:
PTOT = 4 RDS(ON) (IOUT(RMS))
(5)
where PTOT is the total power dissipation, RDS(ON) is the resistance of each FET, and IOUT(RMS) is the RMS output
current being applied to each winding. IOUT(RMS) is equal to the approximately 0.7x the full-scale output current
setting. The factor of 4 comes from the fact that there are two motor windings, and at any instant two FETs are
conducting winding current for each winding (one high-side and one low-side).
The maximum amount of power that can be dissipated in the DRV8811 is dependent on ambient temperature
and heatsinking. Figure 4 and Figure 5 show how the maximum allowable power dissipation varies according to
temperature and PCB construction. Figure 4 shows data for a JEDEC low-K board, 2-layers with 2-oz. copper,
76 mm x 114 mm x 1.6 mm thick, with either no backside copper or a 24 cm2 copper area on the backside.
Similarly, Figure 5 shows data for a JEDEC high-K board, 4 layers with 1-oz. copper, 76 mm x 114 mm x 1.6 mm
thick, and a solid internal ground plane. In this case, the PowerPAD is tied to the ground plane using thermal
vias, and no additional outer layer copper.
Note that RDS(ON) increases with temperature, so as the device heats, the power dissipation increases. This must
be taken into consideration when sizing the heatsink. Refer to Figure 6.
Heatsinking
The PowerPAD package uses an exposed pad to remove heat from the device. For proper operation, this pad
must be thermally connected to copper on the PCB to dissipate heat. On a multi-layer PCB with a ground plane,
this can be accomplished by adding a number of vias to connect the thermal pad to the ground plane. On PCBs
without internal planes, copper area can be added on either side of the PCB to dissipate heat. If the copper area
is on the opposite side of the PCB from the device, thermal vias are used to transfer the heat between top and
bottom layers.
For details about how to design the PCB, refer to TI Application Report SLMA002, " PowerPAD Thermally
Enhanced Package" and TI Application Brief SLMA004, " PowerPAD Made Easy", available at www.ti.com.
In general, the more copper area that can be provided, the more power can be dissipated. Figure 7 shows
thermal resistance vs. copper plane area for a single-sided PCB with 2-oz. copper heatsink area. It can be seen
that the heatsink effectiveness increases rapidly to about 20 cm2, then levels off somewhat for larger areas.
14
DRV8811
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PD - Max Power Dissipation - Watts
POWER DISSIPATION
(2-LAYER)
POWER DISSIPATION
(4-LAYER)
TA - Ambien Temperature - C
Figure 4.
Figure 5.
TYPICAL RDS(ON)
vs
TEMPERATURE
THERMAL RESISTANCE
vs
COPPER AREA
RDS(ON) - m
JA
Temperature - C
Figure 6.
Figure 7.
15
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REVISION HISTORY
Changes from Revision G (May 2010) to Revision H
Page
Changed FEATURES bullet ................................................................................................................................................. 1
Changed IO(peak) and deleted IO in Absolute Maximum Ratings table ................................................................................... 4
Changed maximum digital pin voltage .................................................................................................................................. 4
Added parameters to Logic-Level Inputs section of the ELECTRICAL CHARACTERISTICS ............................................. 6
Changed TIMING REQUIRMENTS ...................................................................................................................................... 7
16
PACKAGE OPTION ADDENDUM
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8-Nov-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package

Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (C)
Device Marking
(4/5)
DRV8811PWP
ACTIVE
HTSSOP
PWP
28
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DRV8811
DRV8811PWPR
ACTIVE
HTSSOP
PWP
28
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DRV8811
(1)
The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
8-Nov-2013
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION

www.ti.com
8-Nov-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
DRV8811PWPR
Package Package Pins

Type Drawing
SPQ
HTSSOP
2000
PWP
28
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
330.0
16.4
Pack Materials-Page 1
6.9
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
10.2
1.8
12.0
16.0
Q1
PACKAGE MATERIALS INFORMATION

www.ti.com
8-Nov-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DRV8811PWPR
HTSSOP
PWP
28
2000
367.0
367.0
38.0
Pack Materials-Page 2
IMPORTANT NOTICE
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changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TIs terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
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TI assumes no liability for applications assistance or the design of Buyers products. Buyers are responsible for their products and
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DRV8811

SLVS865H SEPTEMBER 2008 REVISED NOVEMBER 2013

STEPPER MOTOR CONTROLLER IC

Pulse Width Modulation (PWM) Microstepping

ORDERABLE PART NUMBER

PRODUCTION DATA information is current as of publication date.

Copyright 20082013, Texas Instruments Incorporated

FUNCTIONAL BLOCK DIAGRAM

Submit Documentation Feedback

Copyright 20082013, Texas Instruments Incorporated

Product Folder Links: DRV8811

SLVS865H SEPTEMBER 2008 REVISED NOVEMBER 2013

Bridge A power supply

Bridge B power supply

Logic supply voltage

Connect to 3-V to 5-V logic supply. Bypass to GND with a 0.1-F

Charge pump flying capacitor

Connect a 0.22-F capacitor between CP1 and CP2

Charge pump flying capacitor

Connect a 0.22-F capacitor between CP1 and CP2

High-side gate drive voltage

Connect a 0.22-F ceramic capacitor to VM

Low-side gate drive voltage

Bypass to GND with a 0.22-F ceramic capacitor

Logic high to disable device outputs, logic low to enable outputs

Sleep mode input

Decay mode select

Rising edge causes the indexer to move one step

Level sets the direction of stepping

Sync. Rect. enable input

Active-low. When low, synchronous rectification is enabled. Weak

Current set reference input

Reference voltage for winding current set

Bridge A blanking and off time adjust

Connect a parallel resistor and capacitor to GND - see motor driver

Bridge B blanking and off time adjust

Connect a parallel resistor and capacitor to GND - see motor driver

Bridge A ground / Isense

Connect to current sense resistor for bridge A

Bridge B ground / Isense

EXTERNAL COMPONENTS OR CONNECTIONS

Connect to current sense resistor for bridge B

Connect to bipolar stepper motor winding A

Positive current is AOUT1 AOUT2

Connect to bipolar stepper motor winding B

Positive current is BOUT1 BOUT2

Directions: I = input, O = output, OZ = 3-state output, OD = open-drain output, IO = input/output

Submit Documentation Feedback

Copyright 20082013, Texas Instruments Incorporated

Product Folder Links: DRV8811

PWP (HTSSOP) PACKAGE

ABSOLUTE MAXIMUM RATINGS (1)

over operating free-air temperature range (unless otherwise noted)

Power supply voltage range

Power supply voltage range

Digital pin voltage range

Input voltage range

Peak motor drive output current, t < 1 s

Continuous total power dissipation